CXG1172UR JPHEMT High Power DPDT Switch with Logic Control Description The CXG1172UR can be used in wireless communication systems, for example, CDMA handsets, W-CDMA handsets. The IC has on-chip logic for operation with 1 CMOS control input. The Sony JPHEMT process is used for low insertion loss and on-chip logic circuit. 12 pin UQFN (Plastic) Features • Low insertion loss: 0.3dB@900MHz, 0.45dB@2GHz • 1 CMOS compatible control line • Small package size: 12-pin UQFN Applications Antenna switch for cellular handsets W-CDMA, CDMA Structure GaAs JPHEMT MMIC Absolute Maximum Ratings (Ta = 25°C) • Bias voltage VDD 7 V • Control voltage Vctl 5 V • Operating temperature Topr –35 to +85 °C • Storage temperature Tstg –65 to +150 °C GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E04522-PS CXG1172UR Block Diagram and Recommended Circuit RF3 RF2 GND CRF 6 5 7 GND CRF 4 3 F2 F3 GND F1 CRF CRF RF4 8 GND RF1 2 F4 9 1 10 11 GND 12 Cbypass (100pF) Cbypass (100pF) VDD Rctl (1kΩ) GND CTL When using this IC, the following external components should be used. Rctl: This resistor is used to improve ESD performance. 1kΩ is recommended. CRF: This capacitor is used for RF decoupling and must be used for all applications. Cbypass: This capacitor is used for DC line filtering. 100pF is recommended. Truth Table CTL ON state OFF state F1 F2 F3 F4 L RF1 – RF2, RF3 – RF4 RF2 – RF3, RF4 – RF1 ON OFF ON OFF H RF2 – RF3, RF4 – RF1 RF1 – RF2, RF3 – RF4 OFF ON OFF ON –2– CXG1172UR DC Bias Condition Item (Ta = 25°C) Min. Typ. Max. Unit Vctl (H) 2.0 2.85 3.6 V Vctl (L) 0 — 0.4 V 2.5 2.85 3.6 V VDD Electrical Characteristics Item Insertion loss Isolation (Ta = 25°C) Symbol IL ISO. VSWR VSWR Switching speed TSW Condition Typ. Max. Unit 900MHz 0.30 0.50 dB 1500MHz 0.35 0.55 dB 2000MHz 0.45 0.65 dB Min. 900MHz 14 22 dB 1500MHz 10 18 dB 2000MHz 8 16 dB 50Ω 1.2 1.5 µs 8 1dB compression input power P1dB ∗1, ∗2 Input IP3 IIP3 ∗3 33 50 — dBm dBm 60 ACLR2 ∗1, ±5MHz ∗1, ±10MHz 2fo ∗1 –75 –55 dBc 3fo ∗1 –75 –55 dBc 2fo ∗2 –75 –60 dBc 3fo ∗2 –75 –60 dBc Bias current IDD VDD = 2.85V 25 50 µA Control current Ictl Vctl (H) = 2.85V 15 25 µA ACLR Harmonics ACLR1 –60 –50 dBc –60 –55 dBc ∗1 Pin = 25dBm, 0/2.85V control, VDD = 2.85V, 1920 to 1980MHz ∗2 Pin = 25dBm, 0/2.85V control, VDD = 2.85V, 900MHz ∗3 Pin = 25dBm (900MHz) + 25dBm (901MHz), 0/2.85V control, VDD = 2.85V –3– CXG1172UR Pin Description Pin No. Symbol Description 2 RF1 RF input/output. Connect capacitor (recommended value: 100pF) in use 4 RF2 RF input/output. Connect capacitor (recommended value: 100pF) in use 6 RF3 RF input/output. Connect capacitor (recommended value: 100pF) in use 8 RF4 RF input/output. Connect capacitor (recommended value: 100pF) in use 10 VDD DC power supply 12 CTL Logic control 1, 3, 5, 7, 9, 11 GND GND –4– CXG1172UR Package Outline Unit: mm 12PIN UQFN (PLASTIC) x4 0.1 2.0 9 S A-B C 0.4 ± 0.1 0.55 ± 0.05 0.6 4-R0.2 C 7 6 12 4 B 2.0 10 A 1 0. 0.14 26 3 0.4 0.18 PIN 1 INDEX 0.07 0.25 0.05 M S C A-B S 0.05 MAX0.02 S Solder Plating + 0.09 0.25 – 0.03 + 0.09 0.14 – 0.03 S TERMINAL SECTION PACKAGE STRUCTURE Note:Cutting burr of lead are 0.05mm MAX. PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.01g SONY CODE UQFN-12P-01 LEAD PLATING SPECIFICATIONS ITEM SPEC. LEAD MATERIAL COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18µm –5– Sony Corporation