CXG1176UR High Power DPDT Switch with Logic Control Description This IC can be used in wireless communication systems, for example, W-CDMA handsets. The IC has on-chip logic for operation with 2 CMOS control inputs. The Sony JPHEMT process is used for low insertion loss and on-chip logic circuit. 12 pin UQFN (Plastic) Features • Low insertion loss • 2 CMOS compatible control line • Small package size: 12-pin UQFN Applications • Antenna switch for cellular handsets • Dual-Band W-CDMA Structure GaAs JPHEMT MMIC Absolute Maximum Ratings (Ta = 25°C) • Bias voltage VDD 7 V • Control voltage Vctl 5 V • Operating temperature Topr –35 to +85 °C • Storage temperature Tstg –65 to +150 °C GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E04910-PS CXG1176UR Block Diagram and Recommended Circuit RF3 RF2 GND CRF CRF 6 5 4 F3 GND F4 7 F1 F5 F2 F6 CRF RF1 GND GND 3 CRF 8 2 9 1 10 11 12 CTLA CTLB RF4 GND Cbypass (100pF) VDD When using this IC, the following external components should be used: CRF: This capacitor is used for RF decoupling and must be used for all applications. Cbypass: This capacitor is used for DC line filtering. 100pF is recommended. Truth Table State CTLA CTLB ON State F1 F2 1 L L RF4 – RF3 OFF OFF 2 L H RF4 – RF2 3 H L 4 H H F3 F4 F5 F6 OFF OFF ON OFF OFF OFF ON OFF RF1 – RF3 OFF ON OFF OFF OFF RF1 – RF2 ON OFF OFF ON ON ON –2– ON OFF OFF CXG1176UR DC Bias Conditions Item (Ta = 25°C) Min. Typ. Max. Unit Vctl (H) 2.0 2.85 3.6 V Vctl (L) 0 — 0.4 V 2.5 2.85 3.6 V VDD Electrical Characteristics Item Symbol Insertion loss IL Isolation ISO. VSWR VSWR Switching speed TSW (Ta = 25°C) State Typ. Max. Unit 830 to 885MHz 0.25 0.45 dB 1920 to 2170MHz 0.35 0.55 dB Condition Min. 830 to 885MHz 20 25 dB 1920 to 2170MHz 15 20 dB 50Ω 1.2 1.5 — 5 10 µs –60 –50 dBc ACLR1 ±5MHz ∗1 ACLR2 ±10MHz ∗1 –65 –55 dBc 2fo ∗1 –75 –60 dBc 3fo ∗1 –75 –60 dBc Bias current IDD VDD = 2.85V 80 150 µA Control current Ictl Vctl (H) = 2.85V 15 25 µA ACLR Harmonics ∗1 Pin = 25dBm, 0/2.85V control, VDD = 2.85V, 830 to 840MHz, 1920 to 1980MHz Measurement system noise level: ACLR (±5MHz) < –60dBc, (±10MHz) < –65dBc, 2nd Harmonics < –90dBc, 3rd Harmonics < –90dBc –3– CXG1176UR Package Outline Unit: mm 12PIN UQFN (PLASTIC) x4 0.1 2.0 9 S A-B C 0.4 ± 0.1 0.55 ± 0.05 0.6 4-R0.2 C 7 6 12 4 A B 2.0 10 1 0. 0.14 26 3 0.4 0.18 PIN 1 INDEX 0.07 0.25 0.05 M S C A-B 0.05 S MAX0.02 S Solder Plating + 0.09 0.25 – 0.03 + 0.09 0.14 – 0.03 S TERMINAL SECTION PACKAGE STRUCTURE Note:Cutting burr of lead are 0.05mm MAX. PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.01g SONY CODE UQFN-12P-01 LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SPEC. COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18µm –4– Sony Corporation