CXG7003FN Power Amplifier/Antenna Switch + Low Noise Down Conversion Mixer for PHS Description The CXG7003FN is a MMIC consisting of the power amplifier, diversity antenna supported switch and low noise down conversion mixer. This IC is designed using the Sony’s GaAs J-FET process featuring a single positive power supply operation. Features • Operates at a single positive power supply: VDD = 3V • Diversity antenna supported switch • Small mold package: 26-pin HSOF <Power amplifier/antenna switch transmitter block > • Low current consumption: IDD = 150mA (POUT = 20.2dBm, f = 1.9GHz) • High power gain: Gp = 40dB Typ. (POUT = 20.2dBm, f = 1.9GHz) <Antenna switch receiver block/ low noise down conversion mixer> • Low current consumption: IDD = 5.5mA Typ. (When no signal) • High conversion gain: Gc = 19.5dB Typ. (f = 1.9GHz) • Low distortion: Input IP3 = –12dBm Typ. (f = 1.9GHz) • High image suppression ratio: IMR = 40dBc Typ. (f = 1.9GHz) • High 1/2 IF suppression ratio: 1/2IFR = 47dBc Typ. (f = 1.9GHz) Applications Digital cordless telephones (PHS) 26 pin HSOF (Plastic) Absolute Maximum Ratings <Power amplifier block> • Supply voltage VDD • Voltage between gate and source VGSO • Drain current IDD • Allowable power dissipation PD 6 V 1.5 550 V mA 3 W <Switch block> • Control voltage VCTL 6 V <Front-end block> • Supply voltage • Input power VDD PRF 6 10 V dBm <Common to each block> • Channel temperature Tch • Operating temperature Topr • Storage temperature Tstg 150 –35 to +85 –65 to +150 °C °C °C Recommended Operating Conditions <Common to each block> • Supply voltage VDD Structure GaAs J-FET MMIC <Switch block> • Control voltage (H) • Control voltage (L) 2.7 to 3.3 V VCTL (H) 2.9 to 3.3 VCTL (L) 0 to 0.2 V V Notes on Handling GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E04401-PS CXG7003FN Block Diagram and External Circuit 2.2nH PIN 14 13 15 12 16 11 VGG 100pF 2.2nH VDD1 1nF 18nH 1nF 18nH 10nF 1.8nH VDD2 VDD3 (POUT) 1nF 1pF 17 (TX) 10 30pF 30pF 18 VCTL1 9 100pF 19 ANT2 8 30pF ANT1 7 20 (RX) 30pF 30pF VCTL2 21 6 22 5 23 4 100pF (RFIN) 10nH 10pF 3.9nH 6.8nH 13pF 13pF 24 3 25 2 100nF VDD (IF AMP, MIX) 18pF 26 1 82nH 1nF 5pF IFOUT Pin Configuration PIN 14 13 VGG GND 15 12 CAP VDD1 16 11 POUT VDD2 17 10 TX VDD3 18 9 VCTL1 GND 19 8 ANT2 RX 20 7 ANT1 VCTL2 21 6 GND RFIN 22 5 GND CAP 23 4 VDD (RF AMP) GND 24 3 GND CAP 25 2 VDD (LO AMP) IFOUT/VDD (IF AMP, MIX) 26 1 LOIN –2– 1nF 1nF VDD (RF AMP) VDD (LO AMP) LOIN CXG7003FN Pin Description Pin No. Description Symbol 1 LOIN Local signal input pin 2 VDD (LO AMP) VDD pin of local amplifier 3 GND 4 VDD (RF AMP) VDD pin of RF amplifier 5 GND GND pin 6 GND GND pin 7 ANT1 Antenna switch pin. This pin is ANT1-Tx or ANT1-Rx by setting of VCTL1 and VCTL2. 8 ANT2 Antenna switch pin. This pin is ANT2-Tx or ANT2-Rx by setting of VCTL1 and VCTL2. 9 VCTL1 Antenna switch control 1 pin 10 TX Tx pin. Signal is input to antenna switch during ANT-Tx. 11 POUT Power amplifier output pin 12 CAP Connection pin of external capacitor (for noise elimination) 13 VGG Gate voltage adjustment pin of power amplifier (first stage, middle stage, rear-end FET) 14 PIN Signal input pin to power amplifier 15 GND GND pin 16 VDD1 VDD1 pin of power amplifier (first stage FET) 17 VDD2 VDD2 pin of power amplifier (middle stage FET) 18 VDD3 VDD3 pin of power amplifier (rear-end FET) 19 GND GND pin 20 RX Rx pin. ANT input signal is output to this pin during ANT1-Rx or ANT2-Rx. 21 VCTL2 Antenna switch control 2 pin 22 RFIN RF signal input pin 23 CAP External capacitor connection pin. This pin is connected to LNA FET source. RF amplifier characteristic is optimized during 1.9GHz by the capacitor of 13pF (Typ.). 24 GND GND pin 25 CAP External capacitor connection pin. IF amplifier distortion is improved by this capacitor. 26 IFOUT/VDD (IF AMP, MIX) IF output and IF AMP, MIX VDD GND pin –3– CXG7003FN Electrical Characteristics These specifications are when the Sony's recommended evaluation board shown on page 8 is used. 1. Control Pin Logic for Antenna Switch Conditions of control pins ANT1 – TX ANT2 – RX ANT2 – TX ANT1 – RX VCTL1 = 3V, VCTL2 = 0V ON OFF VCTL1 = 0V, VCTL2 = 3V OFF ON 2. Power Amplifier Block + Antenna Switch Transmitter Block These specifications are common to the ANT1 transmission and ANT2 transmission. Unless otherwise specified: VDD = 3V, IDD = 150mA, POUT = 20.2dBm, f = 1.9GHz When ANT1 transmission: VCTL1 = 3V, VCTL2 = 0V When ANT2 transmission: VCTL1 = 0V, VCTL2 = 3V (Ta = 25°C) Item Symbol Current consumption IDD Gate voltage adjustment value VGG Output power POUT Power gain GP Adjacent channel leak power ratio (600 ± 100kHz) ACPR600kHz Adjacent channel leak power ratio (900 ± 100kHz) Occupied bandwidth Measurement conditions Min. Typ. Max. Unit 150 0.6 0.04 Measured with the ANT pin mA 20.2 V dBm 40 dB Measured with the ANT pin –63 –55 dBc ACPR900kHz Measured with the ANT pin –70 –60 dBc OBW Measured with the ANT pin 250 275 kHz 36 2nd-order harmonic level — Measured with the ANT pin –25 dBc 3rd-order harmonic level — Measured with the ANT pin –25 dBc –4– CXG7003FN 3. Antenna Switch Receiver Block + Low Noise Down Conversion Mixer Block These specifications are common to the ANT1 reception and ANT2 reception. Unless otherwise specified: VDD = 3V, RF1 = 1.90GHz/–35dBm, LO = 1.66GHz/–15dBm When ANT1 reception: VCTL1 = 0V, VCTL2 = 3V When ANT2 reception: VCTL1 = 3V, VCTL2 = 0V (Ta = 25°C) Item Symbol Measurement conditions Min. Typ. Max. Unit 5.5 7.5 Current consumption IDD When no signal Conversion gain GC When a small signal Noise figure NF Input IP3 IIP3 When a small signal ∗1 –17 –12 dBm Image suppression ratio IMR RF2 = 1.42GHz/–35dBm 25 40 dBc 1/2 IF suppression ratio 1/2IFR RF2 = 1.78GHz/–35dBm 41 47 dBc 17 19.5 4.4 mA dB 5.5 dB 2 × LO–IF suppression ratio — RF2 = 3.08GHz/–35dBm 39 45 dBc 2 × LO+IF suppression ratio — RF2 = 3.56GHz/–35dBm 34 65 dBc –50 –40 dBm LO to ANT leak PLK ∗1 Conversion from IM3 suppression ratio during RF1 = 1.9000GHz/–35dBm and RF2 = 1.9006GHz/–35dBm input. –5– CXG7003FN Example of Representative Characteristics 1. Power Amplifier + Antenna Switch Transmitter Block (f = 1.9GHz, Ta = 25°C) –45 POUT 15 –50 10 –55 ACPR600kHz 5 –60 0 –65 –5 –40 –35 –30 –25 –20 –15 –70 –10 22 POUT – Output power [dBm] POUT – Output power [dBm] 20 VDD = var., VGG = const., IDD = 150mA (@VDD = 3V, POUT = 20.2dBm), PIN = –19.7dBm When ANT1 transmission: VCTL1 = 3V, VCTL2 = 0V When ANT2 transmission: VCTL1 = 0V, VCTL2 = 3V The data shown below is common to ANT1 and ANT2. 23 –40 ACPR600kHz – Adjacent channel leak power ratio [dBc] VDD = 3V, VGG = const., IDD = 150mA (@POUT = 20.2dBm), PIN = var. When ANT1 transmission: VCTL1 = 3V, VCTL2 = 0V When ANT2 transmission: VCTL1 = 0V, VCTL2 = 3V The data shown below is common to ANT1 and ANT2. 25 –40 Gp – Power gain [dB] GP 40 –50 39 –55 ACPR600kHz 38 –60 37 –65 180 200 –70 220 ACPR600kHz – Adjacent channel leak power ratio [dBc] –45 41 160 20 –55 19 –60 ACPR600kHz 2.5 3.0 3.5 4.0 VDD – Supply voltage [V] VDD = 3V, VGG = var., IDD = var., PIN = var., POUT = 20.2dBm When ANT1 transmission: VCTL1 = 3V, VCTL2 = 0V When ANT2 transmission: VCTL1 = 0V, VCTL2 = 3V The data shown below is common to ANT1 and ANT2. –40 42 140 –50 17 2.0 Gp, ACPR600kHz vs. IDD 120 POUT 21 18 PIN – Input power [dBm] 36 100 –45 IDD – Current consumption [mA] –6– 4.5 –65 –70 5.0 ACPR600kHz – Adjacent channel leak power ratio [dBc] POUT, ACPR600kHz vs. VDD POUT, ACPR600kHz vs. PIN CXG7003FN 2. Antenna Switch Receiver Block + Low Noise Down Conversion Mixer (Ta = 25°C) GC, NF vs. PLO POUT, PIM3 vs. PIN VDD = 3V, RF1 = 1.90GHz/small signal, LO = 1.66GHz When ANT1 reception: VCTL1 = 0V, VCTL2 = 3V When ANT2 reception: VCTL1 = 3V, VCTL2 = 0V VDD = 3V, RF1 = 1.9000GHz, RF2 = 1.9006GHz, LO = 1.66GHz/–15dBm When ANT1 reception: VCTL1 = 0V, VCTL2 = 3V When ANT2 reception: VCTL1 = 3V, VCTL2 = 0V The data shown below is common to ANT1 and ANT2. 22 5.50 20 5.00 19 4.75 18 4.50 NF 17 4.25 16 –25 4.00 –20 –15 –10 –5 0 PLO – Local input [dBm] VDD = 3V, RF = 1.90GHz/–35dBm, LO = 1.66GHz When ANT1 reception: VCTL1 = 0V, VCTL2 = 3V When ANT2 reception: VCTL1 = 3V, VCTL2 = 0V Input IP3 is common to ANT1 and ANT2. –10 Input IP3 [dBm] Input IP3 –12 –35 –14 –40 –16 –45 ANT1 –18 –50 –20 –55 PLK – LO to ANT leak level [dBm] –30 ANT2 –60 –20 –15 –10 0 POUT –20 –40 PIM3 –60 –80 Input IP3 –100 –50 –40 –30 –20 –10 PIN – RF input power [dBm] Input IP3, PLK vs. PLO –22 –25 POUT – IF output power, PIM3 – 3rd-order intermodulation power [dBm] 5.25 GC NF – Noise figure [dB] GC – Conversion gain [dB] 21 The data shown below is common to ANT1 and ANT2. 20 –5 0 PLO – Local input [dBm] –7– 0 CXG7003FN Recommended Evaluation Board CXG7003FN Via Hole PAIN ANT2 VGG VDD_PA VCTL1 ANT1 VCTL2 VDD_LNA VDD_LO IFOUT LOIN VDD_IF Via Hole Glass fabric-base epoxy board (4 layers) Thickness between layers 1 and 2: 0.2mm Dimensions: 50mm × 50mm VCTL2 VDD (PA) VDD (LO) VDD (IF) VCTL1 VDD (LNA) VGG (Open) Enlarged Diagram of External Circuit Block C8 C8 L2 C7 L6 C1 L2 C8 C6 L6 C6 C9 C7 L1 C6 C6 C6 C7 L5 L4 C3 C4 C10 C4 L3 C2 C5 C8 L7 C8 –8– C8 L1 = 1.8nH L2 = 2.2nH L3 = 3.9nH L4 = 6.8nH L5 = 10nH L6 = 18nH L7 = 82nH C1 = 1pF C2 = 5pF C3 = 10pF C4 = 13pF C5 = 18pF C6 = 30pF C7 = 100pF C8 = 1nF C9 = 10nF C10 = 100nF CXG7003FN Package Outline Unit: mm HSOF 26PIN (PLASTIC) 0.08 ∗5.6 ± 0.05 0.45 ± 0.15 0.9 ± 0.1 S 5.5 4.2 A 0.4 0.5 (1.5) (0.7) 4.4 ± 0.1 (1.75) 14 3.8 ± 0.05 26 13 1 0.4 S 4.4 0.2 0.2 0.07 M S A (0.2) 0.2 ± 0.05 + 0.05 0.2 0 Solder Plating B + 0.05 0.14 – 0.03 DETAIL B NOTE: Dimension “ ∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.06g SONY CODE HSOF-26P-01 LEAD PLATING SPECIFICATIONS ITEM –9– SPEC. LEAD MATERIAL COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18µm Sony Corporation