SSM25G45EM N-CHANNEL INSULATED-GATE BIPOLAR TRANSISTOR High input impedance C High peak current capability C VCE 450V ICP 150A C C 4.5V gate drive C G SO-8 E E G E E Absolute Maximum Ratings Parameter Rating Units VCE Symbol Collector-Emitter Voltage 450 V VGE Gate-Emitter Voltage ±6 V VGEP Pulsed Gate-Emitter Voltage ±8 V Pulsed Collector Current 150 A Maximum Power Dissipation 2.5 W TSTG Storage Temperature Range -55 to 150 °C TJ Operating Junction Temperature Range -55 to 150 °C ICP PD @ TC=25°C 1 Electrical Characteristics @ Tj=25oC (unless otherwise specified) Parameter Symbol Min. Typ. Max. Units - - 10 µA IGES Gate-Emitter Leakage Current Test Conditions VGE=± 6V, VCE=0V ICES Collector-Emitter Leakage Current (Tj=25°C) VCE=450V, VGE=0V - - 10 µA VCE(sat) Collector-Emitter Saturation Voltage VGE=4.5V, ICP=150A (Pulsed) - 6 8 V VGE(th) Gate Threshold Voltage VCE=VGE, IC=250uA 0.35 - 1.2 V Qg Total Gate Charge IC=50A - 64.5 - nC Qge Gate-Emitter Charge VCE=360V - 7 - nC Qgc Gate-Collector Charge VGE=5V - 30 - nC td(on) Turn-on Delay Time VCC=225V - 11.5 - ns tr Rise Time IC=50A - 24.5 - ns td(off) Turn-off Delay Time RG=25Ω - 150 - ns tf Fall Time VGE=5V - 3.3 - µs Cies Input Capacitance VGE=0V - 2227 - pF Coes Output Capacitance VCE=25V - 200 - pF Reverse Transfer Capacitance f=1.0MHz - 79 - pF - - 50 °C/W Cres RthJA 1 Thermal Resistance Junction-Ambient Notes: 1.Surface mounted on 1 in2 copper pad of FR4 board ; 125°C/W when mounted on min. copper pad. 9/21/2004 Rev.2.01 www.SiliconStandard.com 1 of 4 SSM25G45EM 140 180 T A =25 o C ID , Drain Current (A) 140 120 3.0V 100 80 60 2.0V 40 5.0V 4.5V 4.0V T A =150 o C 120 IC , Collector Current (A) 160 5.0V 4.5V 4.0V 100 3.0V 80 60 2.0V 40 20 20 VG=1.0V VG=1.0V 0 0 0 2 4 6 8 0 10 2 Fig 1. Typical Output Characteristics 8 10 12 10 V GE =4.5V VCE(sat),Saturation Voltage(V) V CE =4.5V 25°C 70°C 125°C T A =150°C 120 80 40 I C =130A 8 6 I C =100A 4 I C =50A 2 0 0 0 1 2 3 4 5 0 6 20 40 60 Fig 3. Collector Current vs. Gate-Emitter Voltage 100 120 140 160 Fig 4. Collector- Emitter Saturation Voltage vs. Junction Temperature 200 ICP, Peak Collector Current (A) 1.5 1.2 0.9 0.6 0.3 0 160 120 80 40 0 -50 0 50 Junction Temperature ( 100 o C) Fig 5. Gate Threshold Voltage vs. Junction Temperature 9/21/2004 Rev.2.01 80 Junction Temperature ( o C) V GE , Cate-Emitter Voltage (V) VGE(th) (V) 6 Fig 2. Typical Output Characteristics 160 IC , Collector Current(A) 4 V CE , Collector-Emitter Voltage (V) V CE , Collector-Emitter Voltage (V) 150 0 1 2 3 4 5 6 7 V GE , Gate-to-Emitter Voltage (V) Fig 6. Minimum Gate Drive Area www.SiliconStandard.com 2 of 4 SSM25G45EM f=1.0MHz 10000 12 VGE , Gate -Emitter Voltage (V) 11 Capacitance (pF) Cies 1000 Coes 100 Cres I CP =50A V CC =360V 10 9 8 7 6 5 4 3 2 1 0 10 1 5 9 13 17 21 25 29 0 30 60 90 120 150 Q G , Gate Charge (nC) VCE, Collector-Emitter Voltage (V) Fig 7. Typical Capacitance Characterisitics Fig 8. Gate Charge Waveform VCE RC 90% TO THE OSCILLOSCOPE C VCE G RG 225 V 10% E VGE + - 5V VGE td(on) tr Fig 9. Switching Time Test Circuit td(off) tf Fig 10. Switching Time Waveform VCE TO THE OSCILLOSCOPE C Flasher Vtrig G 300V E CM RG V GE + _ VCM IGBT + - 1~3mA IG VG IC VCM = 300V CM =100uF Fig 11. Gate Charge Test Circuit 9/21/2004 Rev.2.01 ICP = 150A VG =5V Fig 12. Application Test Circuit www.SiliconStandard.com 3 of 4 SSM25G45EM Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 9/21/2004 Rev.2.01 www.SiliconStandard.com 4 of 4