SSM9510GM
N- and P-channel Enhancement-mode Power MOSFETs
Simple drive requirement
N-CH BV DSS
D2
D2
D1 D2
D1 D1
D1
Lower gate charge
Fast switching characteristics
Pb-free; RoHS compliant.
SO-8
30V
28mΩ
R DS(ON)
ID
G2
G2
S2
G1 S2
S1 G1
S1
6.9A
P-CH BVDSS
-30V
RDS(ON)
DESCRIPTION
55mΩ
ID
-5.3A
Advanced Power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching, ruggedized
device design, low on-resistance and cost-effectiveness.
D2
D1
G2
G1
The SSM9510GM is in the SO-8 package, which is widely preferred for
commercial and industrial surface mount applications. It is well suited
for low voltage applications requiring complementary N and P MOSFETs.
S1
S2
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Rating
VDS
Drain-Source Voltage
VGS
Gate-Source Voltage
ID @ TA=25°C
ID @ TA=70°C
Units
N-channel
P-channel
30
-30
V
±20
±20
V
3
6.9
-5.3
A
3
5.5
-4.2
A
30
-30
A
Continuous Drain Current
Continuous Drain Current
1
IDM
Pulsed Drain Current
PD @ TA=25°C
Total Power Dissipation
2.0
Linear Derating Factor
0.016
W
W/°C
TSTG
Storage Temperature Range
-55 to 150
°C
TJ
Operating Junction Temperature Range
-55 to 150
°C
THERMAL DATA
Symbol
Rthj-a
2/10/2005 Rev.2.01
Parameter
Thermal Resistance Junction-ambient
3
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Max.
Value
Unit
62.5
°C/W
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SSM9510GM
N-channel Electrical Characteristics @ Tj=25oC (unless otherwise specified)
Symbol
Parameter
Test Conditions
BVDSS
Drain-Source Breakdown Voltage
∆ BV DSS/ ∆ Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA
RDS(ON)
Static Drain-Source On-Resistance
VGS=0V, ID=250uA
2
Min.
Typ. Max. Units
30
-
-
V
-
0.02
-
V/°C
VGS=10V, ID=5A
-
-
28
mΩ
VGS=4.5V, ID=3A
-
-
40
mΩ
VGS(th)
Gate Threshold Voltage
VDS=VGS, ID=250uA
1
-
3
V
gfs
Forward Transconductance
VDS=10V, ID=5A
-
4.6
-
S
IDSS
Drain-Source Leakage Current (Tj=25oC)
VDS=30V, VGS=0V
-
-
1
uA
Drain-Source Leakage Current (Tj=70 C)
VDS=24V, VGS=0V
-
-
25
uA
Gate-Source Leakage
VGS=±20V
-
-
±100
nA
ID=6.9A
-
10
16
nC
o
IGSS
2
Qg
Total Gate Charge
Qgs
Gate-Source Charge
VDS=24V
-
2
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=4.5V
-
6
-
nC
VDS=15V
-
8
-
ns
2
td(on)
Turn-on Delay Time
tr
Rise Time
ID=1A
-
7
-
ns
td(off)
Turn-off Delay Time
RG=3.3Ω , VGS=10V
-
20
-
ns
tf
Fall Time
RD=15Ω
-
6
-
ns
Ciss
Input Capacitance
VGS=0V
-
540
870
pF
Coss
Output Capacitance
VDS=25V
-
160
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
120
-
pF
Source-Drain Diode
Symbol
Parameter
2
Test Conditions
Min.
Typ. Max. Units
VSD
Forward On Voltage
IS=1.7A, VGS=0V
-
-
1.2
V
trr
Reverse Recovery Time
IS=6.9A, VGS=0V
-
20
-
ns
Qrr
Reverse Recovery Charge
dI/dt=100A/µs
-
11
-
nC
2/10/2005 Rev.2.01
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2 of 8
SSM9510GM
P-channel Electrical Characteristics @ T j=25oC (unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
-30
-
-
V
-
-0.023
-
V/°C
VGS=-10V, ID=-5A
-
-
55
mΩ
VGS=-4.5V, ID=-3A
-
-
90
mΩ
VDS=VGS, ID=-250uA
-1
-
-3
V
BVDSS
Drain-Source Breakdown Voltage
∆BV DSS/∆ Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=-1mA
RDS(ON)
2
Static Drain-Source On-Resistance
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
IDSS
IGSS
VGS=0V, ID=-250uA
Max. Units
VDS=-10V, ID=-5A
-
4.9
-
S
o
VDS=-30V, VGS=0V
-
-
-1
uA
o
Drain-Source Leakage Current (Tj=70 C)
VDS=-24V, VGS=0V
-
-
-25
uA
Gate-Source Leakage
VGS= ± 20V
-
-
±100
nA
Drain-Source Leakage Current (Tj=25 C)
2
Qg
Total Gate Charge
ID=-5.3A
-
9
15
nC
Qgs
Gate-Source Charge
VDS=-24V
-
2
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=-4.5V
-
6
-
nC
VDS=-15V
-
10
-
ns
2
td(on)
Turn-on Delay Time
tr
Rise Time
ID=-1A
-
8
-
ns
td(off)
Turn-off Delay Time
RG=3.3Ω ,VGS=-10V
-
25
-
ns
tf
Fall Time
RD=10Ω
-
13
-
ns
Ciss
Input Capacitance
VGS=0V
-
580
930
pF
Coss
Output Capacitance
VDS=-25V
-
180
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
120
-
pF
Source-Drain Diode
Min.
Typ.
VSD
Symbol
Forward On Voltage2
Parameter
IS=-1.7A, VGS=0V
Test Conditions
-
-
Max. Units
-1.2
V
trr
Reverse Recovery Time
IS=-5.3A, VGS=0V
-
21
-
ns
Qrr
Reverse Recovery Charge
dI/dt=-100A/µs
-
17
-
nC
Notes:
1.Pulse width limited by maximum junction temperature.
2.Pulse width <300us , duty cycle <2%.
3.Surface mounted on 1 in2 copper pad of FR4 board; 135°C/W when mounted on minimum copper pad.
2/10/2005 Rev.2.01
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3 of 8
SSM9510GM
N-channel
70
90
T A =25 o C
80
10V
ID , Drain Current (A)
10V
70
ID , Drain Current (A)
T A =150 o C
60
8.0V
60
50
6.0V
40
30
4.5V
8.0V
50
40
6.0V
30
4.5V
20
20
10
10
V G =3.0V
V G =3.0V
0
0
0
1
2
3
4
5
6
0
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
2
3
4
5
Fig 2. Typical Output Characteristics
1.8
40
ID=5A
T A =25 o C
I D =5A
V G =10V
1.6
Normalized RDS(ON)
36
RDS(ON) (mΩ )
1
V DS , Drain-to-Source Voltage (V)
32
28
1.4
1.2
1.0
24
0.8
0.6
20
3
4
5
6
7
8
9
10
-50
11
0
50
100
150
o
V GS , Gate-to-Source Voltage (V)
T j , Junction Temperature ( C)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
5
2
1.8
4
1.6
T j =150 o C
1.4
T j =25 o C
IS(A)
VGS(th) (V)
3
2
1.2
1
0.8
0.6
1
0.4
0.2
0
0
0
0.2
0.4
0.6
0.8
1
1.2
V SD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
2/10/2005 Rev.2.01
1.4
-50
0
50
100
T j ,Junction Temperature (
o
150
C)
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
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4 of 8
SSM9510GM
N-channel
f=1.0MHz
14
10000
I D =5.7A
V DS =16V
10
1000
8
Ciss
C (pF)
VGS , Gate to Source Voltage (V)
12
6
Coss
Crss
100
4
2
0
10
0
4
8
12
16
20
1
5
9
Fig 7. Gate Charge Characteristics
17
21
25
29
Fig 8. Typical Capacitance Characteristics
1
10
1ms
1
10ms
100ms
0.1
1s
10s
DC
T A =25 o C
Single Pulse
Normalized Thermal Response (Rthja)
100
ID (A)
13
V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Duty factor=0.5
0.2
0.1
0.1
0.05
0.02
0.01
PDM
Single Pulse
0.01
t
T
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Rthja=135°C/W
0.001
0.01
0.1
1
10
100
0.0001
0.001
0.01
V DS , Drain-to-Source Voltage (V)
Fig 9. Maximum Safe Operating Area
VDS
0.1
1
10
100
1000
t , Pulse Width (s)
Fig 10. Effective Transient Thermal Impedance
VG
90%
QG
4.5V
QGS
QGD
10%
VGS
td(on) tr
td(off) tf
Fig 11. Switching Time Waveform
2/10/2005 Rev.2.01
Charge
Q
Fig 12. Gate Charge Waveform
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5 of 8
SSM9510GM
P-channel
70
60
o
T A =150 C
o
T A =25 C
60
-10V
-8.0V
50
-ID , Drain Current (A)
-ID , Drain Current (A)
50
40
-6.0V
30
20
-4.5V
10
-10V
-8.0V
40
-6.0V
30
20
-4.5V
10
V G =-3.0V
V G =-3.0V
0
0
0
1
2
3
4
5
6
0
-V DS , Drain-to-Source Voltage (V)
2
3
4
5
6
-V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1.8
100
I D = -5 A
V G = -10 V
I D = -5A
90
1.6
o
Normalized R DS(ON)
T A =25 C
80
RDS(ON) (mΩ )
1
70
60
1.4
1.2
1
0.8
50
0.6
40
3
4
5
6
7
8
9
10
-50
11
-V GS ,Gate-to-Source Voltage (V)
0
50
100
150
o
T j , Junction Temperature ( C)
Fig 3. On-Resistance v.s. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
5
3
2.8
4
2.6
2.4
T j =25 o C
-VGS(th) (V)
T j =150 o C
-IS(A)
3
2.2
2
1.8
2
1.6
1.4
1
1.2
1
0
0
0.2
0.4
0.6
0.8
1
1.2
-V SD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
2/10/2005 Rev.2.01
1.4
-50
0
50
100
150
o
T j , Junction Temperature ( C)
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
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6 of 8
SSM9510GM
P-channel
f=1.0MHz
10000
I D =-5.3A
V DS =-24V
10
1000
8
Ciss
C (pF)
-VGS , Gate to Source Voltage (V)
12
6
Coss
Crss
100
4
2
10
0
0
2
4
6
8
10
12
14
1
16
5
Q G , Total Gate Charge (nC)
9
13
17
21
25
29
-V DS , Drain-to-Source Voltage (V)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
100
1
Normalized Thermal Response (Rthja)
Duty factor=0.5
10
-ID (A)
1ms
1
10ms
100ms
1s
10s
DC
0.1
T A =25 o C
Single Pulse
0.01
0.2
0.1
0.1
0.05
0.02
0.01
PDM
t
Single Pulse
0.01
T
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Rthja=135°C/W
0.001
0.1
1
10
100
0.0001
0.001
0.01
-V DS , Drain-to-Source Voltage (V)
Fig 9. Maximum Safe Operating Area
VDS
0.1
1
10
100
1000
t , Pulse Width (s)
Fig 10. Effective Transient Thermal Impedance
VG
90%
QG
-4.5V
QGS
QGD
10%
VGS
td(on) tr
td(off) tf
Fig 11. Switching Time Waveform
2/10/2005 Rev.2.01
Charge
Q
Fig 12. Gate Charge Waveform
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7 of 8
SSM9510GM
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
2/10/2005 Rev.2.01
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