SSM9930M
DUAL N- AND DUAL P-CHANNEL ENHANCEMENT-MODE
POWER MOSFETS
Simple drive requirement
Low on-resistance
Full-bridge applications, such as
N-CH
P2G
N2D/P2D
P1S/P2S
P1G
LCD monitor inverter
N1D/P1D
SO-8
30V
R DS(ON)
33mΩ
6.3A
ID
N2G
N1S/N2S
BV DSS
P-CH
N1G
Description
Advanced Power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching, ruggedized
device design, low on-resistance and cost-effectiveness.
BV DSS
-30V
RDS(ON)
55mΩ
ID
-5.1A
P1S
P2S
P1G
P2G
The SSM9930M is in the SO-8 package, which is widely preferred for
commercial and industrial surface mount applications, and is well suited
for applications such as low-voltage inverters and motor drives.
P2N2D
P1N1D
N2G
N1G
Symbol
Parameter
Rating
N-channel
VDS
Drain-Source Voltage
VGS
Gate-Source Voltage
ID @ TA=25°C
ID @ TA=70°C
N2S
N1S
Absolute Maximum Ratings
Units
P-channel
30
-30
V
± 25
±25
V
3
6.3
-5.1
A
3
4.2
-3.4
A
20
-20
A
Continuous Drain Current
Continuous Drain Current
1
IDM
Pulsed Drain Current
PD @ TA=25°C
Total Power Dissipation
2.0
Linear Derating Factor
0.016
W
W/°C
TSTG
Storage Temperature Range
-55 to 150
°C
TJ
Operating Junction Temperature Range
-55 to 150
°C
Thermal Data
Symbol
Rthj-amb
10/21/2004 Rev.1.01
Parameter
Thermal Resistance Junction-ambient
3
Max.
www.SiliconStandard.com
Value
Unit
62.5
°C/W
1 of 8
SSM9930M
N-channel Electrical Characteristics @ Tj=25oC (unless otherwise specified)
Symbol
Parameter
Test Conditions
BVDSS
Drain-Source Breakdown Voltage
∆ BV DSS/ ∆ Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA
RDS(ON)
Static Drain-Source On-Resistance
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
IDSS
2
Typ. Max. Units
30
-
-
V
-
0.037
-
V/°C
VGS=10V, ID=5A
-
-
33
mΩ
VGS=4.5V, ID=3A
-
-
60
mΩ
VDS=VGS, ID=250uA
1
-
3
V
VDS=10V, ID=5A
-
5.2
-
S
o
VDS=30V, VGS=0V
-
-
1
uA
o
Drain-Source Leakage Current (Tj=70 C)
VDS=24V, VGS=0V
-
-
25
uA
Gate-Source Leakage
VGS=±25V
-
-
±100
nA
ID=5A
-
7.1
-
nC
Drain-Source Leakage Current (Tj=25 C)
IGSS
VGS=0V, ID=250uA
Min.
2
Qg
Total Gate Charge
Qgs
Gate-Source Charge
VDS=15V
-
2.3
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=4.5V
-
3.8
-
nC
VDS=15V
-
7.2
-
ns
2
td(on)
Turn-on Delay Time
tr
Rise Time
ID=1A
-
10.4
-
ns
td(off)
Turn-off Delay Time
RG=6Ω ,VGS =10V
-
18
-
ns
tf
Fall Time
RD=15Ω
-
7.8
-
ns
Ciss
Input Capacitance
VGS=0V
-
600
-
pF
Coss
Output Capacitance
VDS=25V
-
230
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
94
-
pF
Source-Drain Diode
Symbol
Parameter
2
Test Conditions
Min.
Typ. Max. Units
VSD
Forward On Voltage
IS=1.7A, VGS=0V
-
-
1.2
V
trr
Reverse Recovery Time
IS=1.7A, VGS=0V
-
21.4
-
ns
Qrr
Reverse Recovery Charge
dI/dt=100A/µs
-
16
-
nC
10/21/2004 Rev.1.01
www.SiliconStandard.com
2 of 8
SSM9930M
P-channel Electrical Characteristics @ T j=25oC (unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
-30
-
-
V
-
-0.037
-
V/°C
VGS=-10V, ID=-5A
-
-
55
mΩ
VGS=-4.5V, ID=-3A
-
-
100
mΩ
VDS=VGS, ID=-250uA
-1
-
-3
V
VDS=-10V, ID=-5A
-
4.8
-
S
-1
uA
BVDSS
Drain-Source Breakdown Voltage
∆ BVDSS/∆ Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C,ID=-1mA
RDS(ON)
2
Static Drain-Source On-Resistance
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
IDSS
VGS=0V, ID=250uA
o
VDS=-30V, VGS=0V
o
VDS=-24V, VGS=0V
Drain-Source Leakage Current (Tj=25 C)
Drain-Source Leakage Current (Tj=70 C)
IGSS
Gate-Source Leakage
2
-
Max. Units
-
-
-
-25
uA
VGS= ± 25V
-
-
±100
nA
Qg
Total Gate Charge
ID=-5A
-
7.3
-
nC
Qgs
Gate-Source Charge
VDS=-15V
-
2.5
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=-4.5V
-
3.8
-
nC
VDS=-15V
-
10.8
-
ns
2
td(on)
Turn-on Delay Time
tr
Rise Time
ID=-1A
-
7.6
-
ns
td(off)
Turn-off Delay Time
RG=6Ω ,VGS =-10V
-
19.6
-
ns
tf
Fall Time
RD=15Ω
-
17.5
-
ns
Ciss
Input Capacitance
VGS=0V
-
486
-
pF
Coss
Output Capacitance
VDS=-25V
-
185.5
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
133.8
-
pF
Source-Drain Diode
Min.
Typ.
VSD
Symbol
Forward On Voltage2
Parameter
IS=-1.7A, VGS=0V
Test Conditions
-
-
Max. Units
-1.2
V
trr
Reverse Recovery Time
IS=-1.7A, VGS=0V
-
21
-
ns
Qrr
Reverse Recovery Charge
dI/dt=-100A/µs
-
15
-
nC
Notes:
1.Pulse width limited by max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
3.Surface mounted on 1 in2 copper pad of FR4 board ; 135°C/W when mounted on min. copper pad.
10/21/2004 Rev.1.01
www.SiliconStandard.com
3 of 8
SSM9930M
N-channel
25
25
10V
8.0V
T A =25 o C
ID , Drain Current (A)
20
T A =150 o C
6.0V
8.0V
6.0V
ID , Drain Current (A)
4.0V
15
10
V G =3.0V
5
4.0V
15
10
V G =3.0V
5
0
0
0
1
2
3
4
5
6
0
V DS , Drain-to-Source Voltage (V)
1
2
3
4
5
6
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1.8
45
I D =5A
I D =5A
T A =25°C
1.6
Normalized RDS(ON)
40
RDS(ON) (mΩ )
10V
20
35
30
V G =10V
1.4
1.2
1.0
25
0.8
20
0.6
3
4
5
6
7
8
9
10
-50
11
0
50
100
150
o
V GS , Gate-to-Source Voltage (V)
T j , Junction Temperature ( C)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
2
10.00
1.8
T j =150 o C
T j =25 o C
IS(A)
VGS(th) (V)
1.00
1.6
1.4
0.10
1.2
1
0.01
0.1
0.3
0.5
0.7
0.9
1.1
1.3
V SD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
10/21/2004 Rev.1.01
1.5
-50
0
50
T j ,Junction Temperature (
100
o
150
C)
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
www.SiliconStandard.com
4 of 8
SSM9930M
N-channel
f=1.0MHz
1000
Ciss
10
I D =4.5A
V DS =15V
Coss
8
C (pF)
VGS , Gate to Source Voltage (V)
12
6
Crss
100
4
2
10
0
0
2
4
6
8
10
12
14
1
5
9
13
17
21
25
29
Q G , Total Gate Charge (nC)
V DS , Drain-to-Source Voltage (V)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
1
100
10
ID (A)
1ms
10ms
1
100ms
1s
0.1
T A =25 o C
Single Pulse
DC
Normalized Thermal Response (Rthja)
DUTY=0.5
0.2
0.1
0.1
0.05
PDM
0.02
t
0.01
T
0.01
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Rthja = 135°C/W
Single Pulse
0.001
0.01
0.1
1
10
100
0.0001
0.001
0.01
V DS , Drain-to-Source Voltage (V)
Fig 9. Maximum Safe Operating Area
VDS
0.1
1
10
100
1000
t , Pulse Width (s)
Fig 10. Effective Transient Thermal Impedance
VG
90%
QG
4.5V
QGS
QGD
10%
VGS
td(on) tr
td(off) tf
Fig 11. Switching Time Waveform
10/21/2004 Rev.1.01
Charge
Q
Fig 12. Gate Charge Waveform
www.SiliconStandard.com
5 of 8
SSM9930M
P-channel
25
25
T A =25 o C
-8.0V
20
-10V
-8.0V
-6.0V
20
-6.0V
-ID , Drain Current (A)
-ID , Drain Current (A)
T A =150 o C
-10V
15
-4.0V
10
5
15
-4.0V
10
5
V G =-3.0V
V G =-3.0V
0
0
0
1
2
3
4
5
0
6
-V DS , Drain-to-Source Voltage (V)
1
2
3
4
5
6
-V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1.8
100
I D =-5A
T A =2\5°C
90
I D =-5A
V G = -10V
1.6
Normalized RDS(ON)
RDS(ON) (mΩ )
80
70
60
50
1.4
1.2
1
0.8
40
30
0.6
3
4
5
6
7
8
9
10
11
-50
-V GS , Gate-to-Source Voltage (V)
0
50
100
150
o
T j , Junction Temperature ( C)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
10.00
3
2.5
T j =150 o C
T j =25 o C
-IS(A)
-VGS(th) (V)
1.00
2
0.10
1.5
0.01
1
0.1
0.3
0.5
0.7
0.9
1.1
1.3
-V SD ,Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
10/21/2004 Rev.1.01
1.5
-50
0
50
T j ,Junction Temperature (
100
o
150
C)
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
www.SiliconStandard.com
6 of 8
SSM9930M
P-channel
I D =-5A
V DS =-15V
12
10
1000
C (pF)
-VGS , Gate to Source Voltage (V)
f=1.0MHz
10000
14
8
Ciss
Coss
Crss
6
100
4
2
0
10
0
2
4
6
8
10
12
14
1
5
Q G , Total Gate Charge (nC)
9
13
17
21
25
29
-V DS , Drain-to-Source Voltage (V)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
1
100
Normalized Thermal Response (Rthja)
DUTY=0.5
10
1ms
-ID (A)
10ms
1
100ms
1s
0.1
DC
T A =25 o C
Single Pulse
0.2
0.1
0.1
0.05
PDM
0.02
t
T
0.01
0.01
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Single Pulse
Rthja = 135°C/W
0.001
0.01
0.1
1
10
100
0.0001
0.001
0.01
-V DS , Drain-to-Source Voltage (V)
Fig 9. Maximum Safe Operating Area
VDS
0.1
1
10
100
1000
t , Pulse Width (s)
Fig 10. Effective Transient Thermal Impedance
VG
90%
QG
4.5V
QGS
QGD
10%
VGS
td(on) tr
td(off) tf
Fig 11. Switching Time Waveform
10/21/2004 Rev.1.01
Charge
Q
Fig 12. Gate Charge Waveform
www.SiliconStandard.com
7 of 8
SSM9930M
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
10/21/2004 Rev.1.01
www.SiliconStandard.com
8 of 8