SST SST39WF1601-70-4I-B3KE

16 Mbit (x16) Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
SST39WF160x2.7V 16Mb (x16) MPF+ memories
Data Sheet
FEATURES:
• Organized as 1M x16
• Single Voltage Read and Write Operations
– 1.65-1.95V
• Superior Reliability
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 5 µA (typical)
– Auto Low Power Mode: 5 µA (typical)
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 32 KWord)
for SST39WF1602
– Bottom Block-Protection (bottom 32 KWord)
for SST39WF1601
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Security-ID Feature
– SST: 128 bits; User: 128 bits
• Fast Read Access Time:
– 70 ns
• Latched Address and Data
• Fast Erase and Word-Program:
– Sector-Erase Time: 36 ms (typical)
– Block-Erase Time: 36 ms (typical)
– Chip-Erase Time: 140 ms (typical)
– Word-Program Time: 28 µs (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pin Assignments and
Command Sets
• Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (5mm x 6mm)
– 48-ball WFBGA (4mm x 6mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST39WF1601/1602 devices are 1M x16 CMOS
Multi-Purpose Flash Plus (MPF+) manufactured with
SST’s proprietary, high-performance CMOS SuperFlash
technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability
compared with alternate approaches. The SST39WF1601/
1602 write (Program or Erase) with a 1.65-1.95V power
supply. These devices conform to JEDEC standard pin
assignments for x16 memories.
Featuring high performance Word-Program, the
SST39WF1601/1602 devices provide a typical Word-Program time of 28 µsec. These devices use Toggle Bit or
Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip
hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed
typical endurance of 100,000 cycles. Data retention is rated
at greater than 100 years.
The SST39WF1601/1602 devices are suited for applications that require convenient and economical updating of
©2009 Silicon Storage Technology, Inc.
S71297-05-000
11/09
1
program, configuration, or data memory. For all system
applications, they significantly improve performance and
reliability, while lowering power consumption. They inherently use less energy during Erase and Program than
alternative flash technologies. The total energy consumed
is a function of the applied voltage, current, and time of
application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a
shorter erase time, the total energy consumed during any
Erase or Program operation is less than alternative flash
technologies. These devices also improve flexibility while
lowering the cost for program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
Word-Program Operation
To meet high density, surface mount requirements, the
SST39WF1601/1602 are offered in both 48-ball TFBGA
and 48-ball WFBGA packages. See Figures 2 and 3 for
pin assignments.
The SST39WF1601/1602 are programmed on a word-byword basis. Before programming, the sector where the
word exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last.
The data is latched on the rising edge of either CE# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 40
µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 20 for flowcharts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks.
Any commands issued during the internal Program operation are ignored. During the command sequence, WP#
should be statically held high or low.
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written to the device
using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
The SST39WF1601/1602 also have the Auto Low Power
mode which puts the device in a near standby mode after
data has been accessed with a valid Read operation. This
reduces the IDD active read current from typically 9 mA to
typically 5 µA. The Auto Low Power mode reduces the typical IDD active read current to the range of 2 mA/MHz of
Read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition
used to initiate another Read cycle, with no access time
penalty. Note that the device does not enter Auto-Low
Power mode after power-up with CE# held steadily low,
until the first address transition or CE# is driven high.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-byblock) basis. The SST39WF1601/1602 offer both SectorErase and Block-Erase modes. The sector architecture is
based on uniform sector size of 2 KWord. The Block-Erase
mode is based on uniform block size of 32 KWord. The
Sector-Erase operation is initiated by executing a six-byte
command sequence with Sector-Erase command (30H)
and sector address (SA) in the last bus cycle. The BlockErase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and
block address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-ofErase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 10 and 11 for
timing waveforms and Figure 24 for the flowchart. Any
commands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt to Sector(Block-) Erase the protected block will be ignored. During
the command sequence, WP# should be statically held
high or low.
Read
The Read operation of the SST39WF1601/1602 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when
either CE# or OE# is high. Refer to the Read cycle timing
diagram for further details (Figure 4).
©2009 Silicon Storage Technology, Inc.
S71297-05-000
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11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
Erase-Suspend/Erase-Resume Commands
Write Operation Status Detection
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ2 toggling and DQ6 at “1”. While in Erase-Suspend
mode, a Word-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
The SST39WF1601/1602 provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
To resume Sector-Erase or Block-Erase operation which has
been suspended the system must issue Erase Resume
command. The operation is executed by issuing one byte
command sequence with Erase Resume command (30H)
at any address in the last Byte sequence.
Data# Polling (DQ7)
Chip-Erase Operation
When the SST39WF1601/1602 are in the internal Program operation, any attempt to read DQ7 will produce the
complement of the true data. Once the Program operation
is completed, DQ7 will produce true data. Note that even
though DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 7 for
Data# Polling timing diagram and Figure 21 for a flowchart.
The SST39WF1601/1602 provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 6 for the command sequence, Figure 10 for timing diagram, and Figure 24 for the flowchart. Any commands issued during the Chip-Erase operation are
ignored. When WP# is low, any attempt to Chip-Erase will
be ignored. During the command sequence, WP# should
be statically held high or low.
©2009 Silicon Storage Technology, Inc.
S71297-05-000
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11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
Toggle Bits (DQ6 and DQ2)
Hardware Block Protection
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next operation. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6)
is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ6 will be set to “1” if a Read operation is attempted on an
Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend
mode, DQ6 will toggle.
The SST39WF1602 support top hardware block protection, which protects the top 32 KWord block of the device.
The SST39WF1601 support bottom hardware block protection, which protects the bottom 32 KWord block of the
device. The Boot Block address ranges are described in
Table 2. Program and Erase operations are prevented on
the 32 KWord when WP# is low. If WP# is left floating, it is
internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase operations on that block.
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ2) is valid after the rising edge of the last WE# (or CE#)
pulse of Write operation. See Figure 8 for Toggle Bit timing
diagram and Figure 21 for a flowchart.
TABLE 2: Boot Block Address Ranges
Product
Address Range
Bottom Boot Block
SST39WF1601
000000H-007FFFH
Top Boot Block
SST39WF1602
0F8000H-0FFFFFH
T2.0 1297
TABLE 1: Write Operation Status
Status
DQ7
DQ6
DQ2
Normal
Standard
Operation Program
DQ7#
Toggle
No Toggle
Standard
Erase
0
Toggle
Toggle
Read from
Erase-Suspended
Sector/Block
1
1
Toggle
Read from
Non- Erase-Suspended
Sector/Block
Data
Data
Data
Program
DQ7#
EraseSuspend
Mode
Toggle
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of TRHR is
required after RST# is driven high before a valid Read can
take place (see Figure 16).
The Erase or Program operation that has been interrupted
needs to be reinitiated after the device resumes normal
operation mode to ensure data integrity.
N/A
T1.0 1297
Note: DQ7 and DQ2 require a valid address when reading
status information.
Software Data Protection (SDP)
The SST39WF1601/1602 provide the JEDEC approved
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. These devices are shipped with the
Software Data Protection permanently enabled. See Table
6 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
device to read mode within TRC. The contents of DQ15-DQ8
can be VIL or VIH, but no other value, during any SDP command sequence.
Data Protection
The SST39WF1601/1602 provide both hardware and software features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
©2009 Silicon Storage Technology, Inc.
S71297-05-000
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11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
Common Flash Memory Interface (CFI)
Product Identification Mode Exit/
CFI Mode Exit
The SST39WF1601/1602 contain the CFI information to
describe the characteristics of the device. The
SST39WF1601/1602 support the original SST CFI Query
mode implementation for compatibility with existing SST
devices as well as the general CFI Query mode. Both will
be explained in subsequent paragraphs.
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 6 for software command
codes, Figure 14 for timing waveform, and Figures 22 and
23 for flowcharts.
In order to enter the SST CFI Query mode, the system
must write the three-byte sequence, same as the product
ID entry command with 98H (CFI Query command) to
address 5555H in the last byte sequence. Once the device
enters CFI Query mode, the system can read CFI data at
the addresses given in Tables 7 through 9. The system
must write the CFI Exit command to return to Read mode
from the CFI Query mode.
Security ID
In order to enter the general CFI Query mode, the system
must write a one-byte sequence with entry command with
98H to address 55H. Once the device enters the CFI
Query mode, the system can read CFI data at the
addresses given in Tables 7 through 9. The system must
write the CFI Exit command to return to Read mode from
the CFI Query mode.
The SST39WF1601/1602 devices offer a 256-bit Security
ID space. The Secure ID space is divided into two 128-bit
segments - one factory programmed segment and one
user programmed segment. The first segment is programmed and locked at SST with a random 128-bit number. The user segment is left un-programmed for the
customer to program as desired.
Product Identification
To program the user segment of the Security ID, the user
must use the Security ID Word-Program command. To
detect end-of-write for the SEC ID, read the toggle bits. Do
not use Data# Polling. Once this is complete, the Sec ID
should be locked using the User Sec ID Program Lock-Out.
This disables any future corruption of this space. Note that
regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.
The Product Identification mode identifies the devices as
the SST39WF1601, SST39WF1602 and manufacturer as
SST. This mode may be accessed software operations.
Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when
using multiple manufacturers in the same socket. For
details, see Table 6 for software operation, Figure 12 for
the Software ID Entry and Read timing diagram and Figure 22 for the Software ID Entry command sequence
flowchart.
The Secure ID space can be queried by executing a threebyte command sequence with Enter Sec ID command
(88H) at address 5555H in the last byte sequence. To exit
this mode, the Exit Sec ID command should be executed.
Refer to Table 6 for more details.
TABLE 3: Product Identification
Address
Data
0000H
BFH
SST39WF1601
0001H
BF274B
SST39WF1602
0001H
BF274A
Manufacturer’s ID
Device ID
T3.0 1297
©2009 Silicon Storage Technology, Inc.
S71297-05-000
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11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
SuperFlash
Memory
X-Decoder
Memory Address
Address Buffer & Latches
Y-Decoder
CE#
OE#
WE#
WP#
RESET#
I/O Buffers and Data Latches
Control Logic
DQ15 - DQ0
1297 B1.0
FIGURE 1: Functional Block Diagram
TOP VIEW (balls facing down)
6
5
4
3
2
1
A13 A12 A14
A15 A16 NC DQ15 VSS
A9
A8
A10
A11 DQ7 DQ14 DQ13 DQ6
WE# RST#
NC
A19 DQ5 DQ12 VDD DQ4
NC WP# A18
NC DQ2 DQ10 DQ11 DQ3
A7
A17
A6
A5
DQ0 DQ8 DQ9 DQ1
A3
A4
A2
A1
A0 CE# OE# VSS
A
B
C
D
E
F
G
H
1297 48-tfbga B3K P1.1
FIGURE 2: Pin assignments for 48-ball TFBGA
©2009 Silicon Storage Technology, Inc.
S71297-05-000
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11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
TOP VIEW (balls facing down)
SST39WF160x
6
A2
A4
A6
A17
A1
A3
A7
WP#
A0
A5
A18
NC
NC
WE# RST#
A9
A11
A10
A13
A14
A8
A12
A15
5
NC
4
3
CE#
DQ8 DQ10
VSS
OE# DQ9
DQ4 DQ11 A16
2
NC
A19
DQ5 DQ6 DQ7
1
DQ0 DQ1 DQ2 DQ3
A
B
C
D
E
VDD DQ12 DQ13 DQ14 DQ15 VSS
F
G
H
J
K
L
1297 48-wfbga MBQ P02.0
FIGURE 3: Pin assignments for 48-ball WFBGA
©2009 Silicon Storage Technology, Inc.
S71297-05-000
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11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
TABLE 4: Pin Description
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses.
During Sector-Erase AMS-A11 address lines will select the sector.
During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP#
Write Protect
To protect the top/bottom boot block from Erase/Program operation when grounded.
RST#
Reset
To reset and return the device to Read mode.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
To provide power supply voltage: 1.65-1.95V
VDD
Power Supply
VSS
Ground
NC
No Connection
Unconnected pins.
T4.0 1297
1. AMS = Most significant address
AMS = A19 for SST39WF1601/1602
TABLE 5: Operation Modes Selection
Mode
CE#
OE#
WE#
Read
Program
DQ
Address
VIL
VIL
VIL
VIH
VIH
DOUT
AIN
VIL
DIN
AIN
VIH
VIL
X1
Sector or block address,
XXH for Chip-Erase
Erase
VIL
Standby
VIH
X
X
High Z
X
X
VIL
X
High Z/ DOUT
X
X
X
VIH
High Z/ DOUT
X
VIL
VIL
VIH
Write Inhibit
Product Identification
Software Mode
See Table 6
T5.0 1297
1. X can be VIL or VIH, but no other value.
©2009 Silicon Storage Technology, Inc.
S71297-05-000
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11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
TABLE 6: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
Addr1
Data2
2nd Bus
Write Cycle
Addr1
3rd Bus
Write Cycle
Data2 Addr1 Data2
4th Bus
Write Cycle
Addr1
Data2
Data
5th Bus
Write Cycle
Addr1
6th Bus
Write Cycle
Data2 Addr1 Data2
Word-Program
5555H
AAH
2AAAH
55H
5555H
A0H
WA3
Sector-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
SAX4
Block-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
BAX4
50H
Chip-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
10H
Erase-Suspend
XXXXH
B0H
Erase-Resume
XXXXH
30H
Query Sec ID5
5555H
AAH
2AAAH
55H
5555H
88H
User Security ID
Word-Program
5555H
AAH
2AAAH
55H
5555H
A5H
WA6
Data
User Security ID
Program Lock-Out
5555H
AAH
2AAAH
55H
5555H
85H
XXH6
0000H
Software ID Entry7,8
5555H
AAH
2AAAH
55H
5555H
90H
SST CFI Query Entry
5555H
AAH
2AAAH
55H
5555H
98H
55H
98H
Software ID Exit9,10
/CFI Exit/Sec ID Exit
5555H
AAH
2AAAH
55H
5555H
F0H
Software ID Exit9,10
/CFI Exit/Sec ID Exit
XXH
F0H
General CFI Query Mode
30H
T6.0 1297
1. Address format A14-A0 (Hex).
Addresses A15-A19 can be VIL or VIH, but no other value, for Command sequence for SST39WF1601/1602.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence
3. WA = Program Word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses AMS-A15 address lines
AMS = Most significant address
AMS = A19 for SST39WF1601/1602
5. With AMS-A4 = 0; Sec ID is read with A3-A0,
SST ID is read with A3 = 0 (Address range = 000000H to 000007H),
User ID is read with A3 = 1 (Address range = 000008H to 00000FH).
User ID Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H to 00000FH.
7. The device does not remain in Software Product ID Mode if powered down.
8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,
SST39WF1601 Device ID = BF274BH, is read with A0 = 1,
SST39WF1602 Device ID = BF274AH, is read with A0 = 1.
AMS = Most significant address
AMS = A19 for SST39WF1601/1602
9. Both Software ID Exit operations are equivalent
10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID
mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and
000008H to 00000FH.
©2009 Silicon Storage Technology, Inc.
S71297-05-000
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11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
TABLE 7: CFI Query Identification String1
Address
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
Data
0051H
0052H
0059H
0002H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
Data
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T7.0 1297
1. Refer to CFI publication 100 for more details.
TABLE 8: System Interface Information
Address
Data
1BH
0016H
VDD Min (Program/Erase)
Data
1CH
0020H
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
0000H
VPP min. (00H = no VPP pin)
1EH
0000H
VPP max. (00H = no VPP pin)
1FH
0005H
Typical time out for Word-Program 2N µs (25 = 32 µs)
20H
0000H
Typical time out for min. size buffer program 2N µs (00H = not supported)
21H
0005H
Typical time out for individual Sector/Block-Erase 2N ms (25 = 30 ms)
22H
0007H
Typical time out for Chip-Erase 2N ms (27 = 128 ms)
23H
0001H
Maximum time out for Word-Program 2N times typical (21 x 25 = 64 µs)
24H
0000H
Maximum time out for buffer program 2N times typical
25H
0001H
Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 25 = 64 ms)
26H
0001H
Maximum time out for Chip-Erase 2N times typical (21 x 27 = 256 ms)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
T8.0 1297
TABLE 9: Device Geometry Information
Address
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Data
0015H
0001H
0000H
0000H
0000H
0002H
00FFH
0001H
0010H
0000H
001FH
0000H
0000H
0001H
Data
Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
Flash Device Interface description; 0001H = x16-only asynchronous interface
Maximum number of byte in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 511 + 1 = 512 sectors (01FF = 511)
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 31 + 1 = 32 blocks (001F = 31)
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T9.0 1297
©2009 Silicon Storage Technology, Inc.
S71297-05-000
10
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
Operating Range
Range
Ambient Temp
VDD
Commercial
Industrial
0°C to +70°C
-40°C to +85°C
1.65-1.95V
1.65-1.95V
AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 18 and 19
©2009 Silicon Storage Technology, Inc.
S71297-05-000
11
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
TABLE 10: DC Operating Characteristics VDD = 1.65-1.95V1
Limits
Symbol
Parameter
IDD
Power Supply Current
Min
Max
Units
Test Conditions
Address input=VILT/VIHT, at f=5 MHz,
VDD=VDD Max
Read
10
mA
CE#=VIL, OE#=WE#=VIH, all I/Os open
Program and Erase
25
mA
CE#=WE#=VIL, OE#=VIH
ISB
Standby VDD Current2
40
µA
CE#=VIHC, VDD=VDD Max
IALP
Auto Low Power
40
µA
CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
ILI
Input Leakage Current
1
µA
VIN=GND to VDD, VDD=VDD Max
ILIW
Input Leakage Current
on WP# pin and RST#
10
µA
WP#=GND to VDD or RST#=GND to VDD
ILO
Output Leakage Current
1
µA
VOUT=GND to VDD, VDD=VDD Max
VIL
Input Low Voltage
0.2VDD
V
VDD=VDD Min
VIH
Input High Voltage
V
VDD=VDD Max
VOL
Output Low Voltage
VOH
Output High Voltage
0.8VDD
0.1
VDD-0.1
V
IOL=100 µA, VDD=VDD Min
V
IOH=-100 µA, VDD=VDD Min
T10.0 1297
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 1.8V. Not 100% tested.
2. For all SST39WF160x commercial and industrial devices, ISB typical is under 5 µA.
TABLE 11: Recommended System Power-up Timings
Symbol
Parameter
Minimum
Units
TPU-READ1
Power-up to Read Operation
100
µs
Power-up to Program/Erase Operation
100
µs
TPU-WRITE
1
T11.0 1297
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: Capacitance (TA = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
Maximum
CI/O1
I/O Pin Capacitance
VI/O = 0V
12 pF
Input Capacitance
VIN = 0V
6 pF
CIN
1
T12.0 1297
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: Reliability Characteristics
Symbol
Parameter
Minimum Specification
Units
Test Method
NEND1,2
Endurance
10,000
Cycles
JEDEC Standard A117
TDR1
Data Retention
100
Years
JEDEC Standard A103
ILTH1
Latch Up
100 + IDD
mA
JEDEC Standard 78
T13.0 1297
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
©2009 Silicon Storage Technology, Inc.
S71297-05-000
12
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
AC CHARACTERISTICS
TABLE 14: Read Cycle Timing Parameters VDD = 1.65-1.95V
Symbol
Parameter
TRC
Read Cycle Time
TCE
Chip Enable Access Time
TAA
Address Access Time
70
ns
TOE
Output Enable Access Time
35
ns
TCLZ1
CE# Low to Active Output
0
ns
TOLZ1
OE# Low to Active Output
0
ns
TCHZ1
CE# High to High-Z Output
40
ns
TOHZ1
OE# High to High-Z Output
40
ns
TOH1
TRP1
Output Hold from Address Change
TRHR
1
TRY1,2
Min
Max
Units
70
ns
70
ns
0
ns
RST# Pulse Width
500
ns
RST# High before Read
50
ns
203
RST# Pin Low to Read Mode
µs
T14.0 1297
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase and Program operations.
This parameter does not apply to Chip-Erase operations.
3. This parameter is 100 µs if reset after an Erase operation.
TABLE 15: Program/Erase Cycle Timing Parameters
Symbol
Parameter
TBP
Word-Program Time
TAS
Address Setup Time
0
ns
TAH
Address Hold Time
50
ns
TCS
WE# and CE# Setup Time
0
ns
TCH
WE# and CE# Hold Time
0
ns
TOES
OE# High Setup Time
0
ns
TOEH
OE# High Hold Time
10
ns
TCP
CE# Pulse Width
50
ns
TWP
WE# Pulse Width
50
ns
TWPH1
WE# Pulse Width High
30
ns
TCPH1
CE# Pulse Width High
30
ns
TDS
Data Setup Time
50
ns
Data Hold Time
0
TDH
1
Min
Max
40
Units
µs
ns
TIDA1
Software ID Access and Exit Time
150
ns
TSE
Sector-Erase
50
ms
TBE
Block-Erase
50
ms
TSCE
Chip-Erase
200
ms
T15.0 1297
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2009 Silicon Storage Technology, Inc.
S71297-05-000
13
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
TRC
TAA
ADDRESS A19-0
TCE
CE#
TOE
OE#
TOHZ
TOLZ
VIH
WE#
HIGH-Z
DQ15-0
TCHZ
TOH
TCLZ
DATA VALID
HIGH-Z
DATA VALID
1297 F03.1
FIGURE 4: Read Cycle Timing Diagram
INTERNAL PROGRAM OPERATION STARTS
TBP
5555
ADDRESS A19-0
2AAA
5555
ADDR
TAH
TDH
TWP
WE#
TAS
TDS
TWPH
OE#
TCH
CE#
TCS
DQ15-0
XXAA
XX55
XXA0
DATA
SW0
SW1
SW2
WORD
(ADDR/DATA)
1297 F04.1
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 5: WE# Controlled Program Cycle Timing Diagram
©2009 Silicon Storage Technology, Inc.
S71297-05-000
14
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
TBP
5555
ADDRESS A19-0
2AAA
5555
ADDR
TAH
TDH
TCP
CE#
TAS
TCPH
TDS
OE#
TCH
WE#
TCS
DQ15-0
XXAA
XX55
XXA0
DATA
SW0
SW1
SW2
WORD
(ADDR/DATA)
1297 F05.1
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 6: CE# Controlled Program Cycle Timing Diagram
ADDRESS A19-0
TCE
CE#
TOES
TOEH
OE#
TOE
WE#
DQ7
DATA
DATA#
DATA#
DATA
1297 F06.1
FIGURE 7: Data# Polling Timing Diagram
©2009 Silicon Storage Technology, Inc.
S71297-05-000
15
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
ADDRESS A19-0
TCE
CE#
TOEH
TOES
TOE
OE#
WE#
DQ6 and DQ2
TWO READ CYCLES
WITH SAME OUTPUTS
1297 F07.1
FIGURE 8: Toggle Bits Timing Diagram
TSCE
SIX-BYTE CODE FOR CHIP-ERASE
ADDRESS A19-0
5555
2AAA
5555
5555
2AAA
5555
CE#
OE#
TWP
WE#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
SW0
SW1
SW2
SW3
SW4
SW5
1297 F08.1
Note: This device also supports CE# controlled Chip-Erase operation.
The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 15.)
WP# must be held in proper logic state (VIH) 1 µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 9: WE# Controlled Chip-Erase Timing Diagram
©2009 Silicon Storage Technology, Inc.
S71297-05-000
16
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
SIX-BYTE CODE FOR BLOCK-ERASE
ADDRESS A19-0
5555
2AAA
5555
5555
2AAA
TBE
BAX
CE#
OE#
TWP
WE#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
SW0
SW1
SW2
SW3
SW4
SW5
1297 F09.1
Note: This device also supports CE# controlled Block-Erase operation.
The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 15.)
BAX = Block Address
WP# must be held in proper logic state (VIH) 1 µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 10: WE# Controlled Block-Erase Timing Diagram
TSE
SIX-BYTE CODE FOR SECTOR-ERASE
ADDRESS A19-0
5555
2AAA
5555
5555
2AAA
SAX
CE#
OE#
TWP
WE#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
SW0
SW1
SW2
SW3
SW4
SW5
1297 F10.1
Note: This device also supports CE# controlled Sector-Erase operation.
The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 15.)
SAX = Sector Address
WP# must be held in proper logic state (VIH) 1 µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 11: WE# Controlled Sector-Erase Timing Diagram
©2009 Silicon Storage Technology, Inc.
S71297-05-000
17
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
Three-Byte Sequence for Software ID Entry
ADDRESS A14-0
5555
2AAA
5555
0000
0001
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
TAA
XXAA
XX55
XX90
SW0
SW1
SW2
00BF
Device ID
1297 F11.1
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1µs after the command sequence.
Device ID - See Table 3
X can be VIL or VIH, but no other value.
FIGURE 12: Software ID Entry and Read
Three-Byte Sequence for CFI Query Entry
ADDRESS A14-0
5555
2AAA
5555
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
TAA
XXAA
XX55
XX98
SW0
SW1
SW2
1297 F12.1
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 13: CFI Query Entry and Read
©2009 Silicon Storage Technology, Inc.
S71297-05-000
18
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
ADDRESS A14-0
5555
DQ15-0
2AAA
XXAA
5555
XX55
XXF0
TIDA
CE#
OE#
TWP
WE#
TWHP
SW0
SW1
SW2
1297 F13.1
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 14: Software ID Exit/CFI Exit
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS A19-0
5555
2AAA
5555
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
TAA
XXAA
XX55
XX88
SW0
SW1
SW2
1297 F20.1
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 15: Sec ID Entry
©2009 Silicon Storage Technology, Inc.
S71297-05-000
19
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
TRP
RST#
CE#/OE#
TRHR
1297 F22.0
FIGURE 16: RST# Timing Diagram (When no internal operation is in progress)
TRP
RST#
TRY
CE#/OE#
End-of-Write Detection
(Toggle-Bit)
1297 F23.1
FIGURE 17: RST# Timing Diagram (During Program or Erase operation)
©2009 Silicon Storage Technology, Inc.
S71297-05-000
20
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
VIHT
INPUT
VIT
VOT
REFERENCE POINTS
OUTPUT
VILT
1297 F14.1
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 18: AC Input/Output Reference Waveforms
VDD
TO TESTER
25K
TO DUT
CL
25K
1297 F15.1
FIGURE 19: A Test Load Example
©2009 Silicon Storage Technology, Inc.
S71297-05-000
21
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
Start
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XXA0H
Address: 5555H
Load Word
Address/Word
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
1297 F16.0
X can be VIL or VIH, but no other value
FIGURE 20: Word-Program Algorithm
©2009 Silicon Storage Technology, Inc.
S71297-05-000
22
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
Internal Timer
Toggle Bit
Data# Polling
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Wait TBP,
TSCE, TSE
or TBE
Read word
Read DQ7
Read same
word
Program/Erase
Completed
No
Is DQ7 =
true data?
Yes
No
Does DQ6
match?
Program/Erase
Completed
Yes
Program/Erase
Completed
1297 F17.0
FIGURE 21: Wait Options
©2009 Silicon Storage Technology, Inc.
S71297-05-000
23
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
General
CFI Query Entry
Command Sequence
CFI Query Entry
Command Sequence
Sec ID Query Entry
Command Sequence
Software Product ID Entry
Command Sequence
Load data: XX98H
Address: 55H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Wait TIDA
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Read CFI data
Load data: XX98H
Address: 5555H
Load data: XX88H
Address: 5555H
Load data: XX90H
Address: 5555H
Wait TIDA
Wait TIDA
Wait TIDA
Read CFI data
Read Sec ID
Read Software ID
X can be VIL or VIH, but no other value
1297 F21.0
FIGURE 22: Software ID/CFI Entry Command Flowcharts
©2009 Silicon Storage Technology, Inc.
S71297-05-000
24
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
Software ID Exit/CFI Exit/Sec ID Exit
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAAH
Wait TIDA
Load data: XXF0H
Address: 5555H
Return to normal
operation
Wait TIDA
Return to normal
operation
X can be VIL or VIH, but no other value
1297 F18.0
FIGURE 23: Software ID/CFI Exit Command Flowcharts
©2009 Silicon Storage Technology, Inc.
S71297-05-000
25
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
Chip-Erase
Command Sequence
Sector-Erase
Command Sequence
Block-Erase
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XX30H
Address: SAX
Load data: XX50H
Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
1297 F19.0
X can be VIL or VIH, but no other value
FIGURE 24: Erase Command Sequence
©2009 Silicon Storage Technology, Inc.
S71297-05-000
26
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
PRODUCT ORDERING INFORMATION
SST
39
XX
WF 1602
XX XXXX
- 70
- XXX
-
4C
XX
- B3K
- XXX
E
X
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls
Q = 48 balls (66 possible positions)
Package Type
B3 = TFBGA (6mm x 8mm)
MB = WFBGA (5mm x 6mm)
MA = WFBGA (4mm x 6mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Hardware Block Protection
1 = Bottom Boot-Block
2 = Top Boot-Block
Device Density
160 = 16 Mbit
Voltage
W = 1.65-1.95V
Product Series
39 = Multi-Purpose Flash
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
Valid Combinations for SST39WF1601
SST39WF1601-70-4C-B3KE
SST39WF1601-70-4C-MBQE
SST39WF1601-70-4C-MAQE
SST39WF1601-70-4I-B3KE
SST39WF1601-70-4I-MBQE
SST39WF1601-70-4I-MAQE
Valid Combinations for SST39WF1602
SST39WF1602-70-4C-B3KE
SST39WF1602-70-4C-MBQE
SST39WF1602-70-4C-MAQE
SST39WF1602-70-4I-B3KE
SST39WF1602-70-4I-MBQE
SST39WF1602-70-4I-MAQE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2009 Silicon Storage Technology, Inc.
S71297-05-000
27
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
BOTTOM VIEW
8.00 ± 0.20
5.60
0.45 ± 0.05
(48X)
0.80
6
6
5
5
4.00
4
4
6.00 ± 0.20
3
3
2
2
1
1
0.80
A B C D E F G H
H G F E D C B A
A1 CORNER
A1 CORNER
1.10 ± 0.10
SIDE VIEW
0.12
SEATING PLANE
1mm
0.35 ± 0.05
Note:
1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm (± 0.05 mm)
48-tfbga-B3K-6x8-450mic-4
FIGURE 25: 48-ball Thin-Profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm
SST Package Code: B3K
TOP VIEW
BOTTOM VIEW
6.00 ± 0.08
6
5
4
3
2
1
5.00
0.50
5.00 ± 0.08
0.32 ± 0.05
(48X)
6
5
4
3
2
1
2.50
0.50
A B C D E F G H J K L
L K J H G F E D C B A
A1 CORNER
DETAIL
A1 INDICATOR
0.73 max.
0.636 nom.
SIDE VIEW
0.08
SEATING PLANE
0.20 ± 0.06
Note:
1mm
1. Although many dimensions are similar to those of JEDEC Publication 95, MO-225,
this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. Ball opening size is 0.29 mm (± 0.05 mm)
48-wfbga-MBQ-5x6-32mic-0
FIGURE 26: 48-ball Very-Very-Thin-Profile, Fine-pitch Ball Grid Array (WFBGA) 5mm x 6mm
SST Package Code MBQ
©2009 Silicon Storage Technology, Inc.
S71297-05-000
28
11/09
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
TOP VIEW
BOTTOM VIEW
5.00
6.00
± 0.08
6
5
4
3
2
1
0.50
4.00
± 0.08
0.50
A1 CORNER
DETAIL
6
5
4
3
2
1
2.50
A B C D E F G H J K L
0.32 ± 0.05
(48X)
L K J H G F E D C B A
A1 INDICATOR
0.73 max.
0.636 nom.
SIDE VIEW
0.08
SEATING PLANE
0.20 ± 0.06
Note:
1mm
1. Complies with JEDEC Publication 95, MO-207, Variant CB-4 except nominal ball size is larger
and bottom side A1 indicator is triangle at corner.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. Ball opening size is 0.29 mm (± 0.05 mm)
48-wfbga-MAQ-4x6-32mic-2.0
FIGURE 27: 48-ball Very-Very-Thin-Profile, Fine-pitch Ball Grid Array (WFBGA) 4mm x 6mm
SST Package Code MAQ
TABLE 16: Revision History
Number
Description
Date
00
•
Initial release
Oct 2005
01
•
•
•
Added MBQ package information including product numbers.
Migrated document to Preliminary Specifications
Updated Table 10 on page 12
Jul 2006
02
•
•
•
Added 70 ns to Features: Fast Read Access Time
Added 70 ns columns to Table 14
Edited Product Ordering Information and Valid Combination to include 70 ns and
remove leaded parts.
Aug 2007
03
•
Added YIQE package
Jul 2008
04
•
Changed 000010H to 000017H to 000008H to 00000FH three places in footnotes
of Table 6 on page 9.
Dec 2008
05
•
EOL of SST39WF1601-70-4C-Y1QE, SST39WF1601-70-4I-Y1QE,
SST39WF1602-70-4C-Y1QE, and SST39WF1602-70-4I-Y1QE. Replacement
parts SST39WF1601-70-4C-MAQE, SST39WF1601-70-4I-MAQE,
SST39WF1602-70-4C-MAQE, and SST39WF1602-70-4I-MAQE in this document.
Added MAQE package drawing and information.
Removed all 90ns speed products
Nov 2009
•
•
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2009 Silicon Storage Technology, Inc.
S71297-05-000
29
11/09