SUMMIT S9418 MICROELECTRONICS, Inc. Quad 8-Bit Nonvolatile DACPOT™ Electronic Potentiometer With a Mute Control Input FEATURES • Four 8-Bit DACS — Differential Non-linearity - ±0.5LSB max — Integral Non-Linearity Error - ±1LSB max • Each DAC has Independent Reference Inputs — Output Buffer Amplifiers Swing Rail-to-Rail — Ground to VDD Reference Input Range • Each DAC’s Digital Inputs Maintained in EEPROM OVERVIEW The S9418 DACPOT™ is a serial input, voltage output, quad 8-bit digital to analog converter. The S9418 operates from a single +2.7V to +5.5V supply. Internal precision buffers swing rail-to-rail and the reference input range includes both ground and the positive supply. The S9418 integrates four 8-bit DACs and their associated circuits which include; an enhanced unity gain operational amplifier output, an 8-bit data latch, an 8-bit nonvolatile register and an industry standard serial interface for reading and writing data to the DACs’ data latches and registers. The DACs are independently programmable and each has its own electrically isolated Vreference inputs. • Power-On Reset Reloads Registers with Nonvolatile Data • Simple Serial Interface for Reading and Writing DAC values, SPI™ and QSPI™ compatible. • Fully operational from 2.7V to 5.5V • Low Power, 4mW max at +5V FUNCTIONAL BLOCK DIAGRAM Memory Control RDY/BSY Programming Memory Controller 8-bit E2PROM Serial Data In VREFH0 8-bit Data Register 8-bit DAC VOUT0 AMP VREFL0 DAC Section 0 Serial Data Out CS DI Control Logic VREFH1 VOUT1 VREFL1 DAC Section 1 CLK MUTE DAC Section 2 VREFH2 VOUT2 VREFL2 DAC Section 3 VREFH3 VOUT3 VREFL3 VDD GND DO 2023 ILL2 1.2 SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 © SUMMIT MICROELECTRONICS, Inc. 1999 2023 1.5 4/24/99 • Campbell, CA 95008 1 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com Characteristics subject to change without notice S9418 PINOUT and SIGNAL DEFINITION Pin Name 1, 2 VREFH 20, 19 Function Vreference High: VREFH ≤ VDD > VREFL VREFH1 1 20 VREFH2 3 VDD VREFH0 2 19 VREFH3 4 VDD 3 18 VOUT0 RDY/BSY Ready/Busy: open drain output indicating status of nonvolatile write operations RDY/BSY 4 17 VOUT1 5 CLK Clock Input Pin: used for serial data communication CLK 5 16 VOUT2 6 CS CS 6 15 VOUT3 Chip Select: When high deselects the device and places it in a low power mode DI 7 14 VREFL3 7 DI Data Input: serial data input pin DO 8 13 VREFL2 8 DO Data Output: serial data output pin MUTE 9 12 VREFL1 9 MUTE When active forces VOUT to VREFL GND 10 11 VREFL0 10 GND Power Supply Ground 11, 12 13, 14 VREFL Vreference Low 15, 16 17, 18 VOUT DAC Output: buffered D to A converter output 2023 ILL1 1.2 The analog outputs of the S9418 can be programmed to any one of 256 individual voltage steps. Each step value is 1/256th of the voltage differential between VrefH and VrefL of the respective DAC. Once programmed these settings can be retained in nonvolatile memory during all power conditions and will be automatically recalled upon a power-up sequence. Each DAC can be independently read without affecting the output voltage during the read cycle. In addition each output can be adjusted an unlimited number of times without altering the value stored in the nonvolatile memory. Power Supply Voltage Output Buffer Amplifiers The voltage outputs are from precision unity-gain followers that can slew up to 1V/µs. The outputs can swing from VREFL to VREFH. With a 0V to 5V output transition the amplifier outputs typically settle to 1LSB in 50µs. DIGITAL INTERFACE The S9418 employs a common 4-wire serial interface. It is comprised of a Clock (CLK), Chip Select (CS) and Data In (DI) input and a Data Out (DO) output. Data is clocked into the device on the clock’s rising edge and out of the device on the clock’s falling edge. Data is shifted in and out MSB first. DO only becomes active after the device has been selected and after a valid read command and address has been received. DEVICE OPERATION Analog Section The S9418 is an 8-bit, voltage output digital-to-analog converter (DAC). The DAC consists of a resistor network that converts 8-bit digital inputs into equivalent analog output voltages in proportion to the applied reference voltage. All data transfers are initiated after CS goes LOW and a logic ‘1’ is clocked into the device. This first data transfer is the start bit and must precede all operations. Following the start bit are two command bits used to specify which of four commands to execute. The next two bits are the address bits used to select one of the four DACs. The action of the next eight clock cycles will be dependent upon the command issued. Reference inputs The voltage differential between the VREFL and VREFH inputs sets the full-scale output voltage for its respective DAC. VREFL must be equal to or greater than ground (positive voltage). VREFH must be greater (more positive) than VREFL or equal to VDD. 2023 1.5 4/24/99 2 S9418 S CH CL AH AL 1 0 0 A A NV Enable - Data Don’t Care 1 0 1 A A Write Command - Data In 1 1 0 A A Read - Data Out 1 1 1 A A Recall -Data Don’t Care clocks will output on the DO pin the contents of the selected data register. This read will not affect the contents of the register or the output of the DAC. Refer to Figure 1 for an illustration of the sequence of bus conditions for a read operation. WRITE Write operations are initiated by taking CS LOW and clocking in a start bit followed by the write command and the address of the data register to be written. This action is followed by the host clocking eight bits of data into the register, MSB first. The output of the selected DAC will change as the last bit is clocked into the device. At this point the clock counter will reset the command register, requiring a full sequence to be initiated in order to write to the DAC again. NOTE: This write operation does not affect the contents of the nonvolatile register. Therefore, the nonvolatile register can contain the power-on default settings (e.g. volume), and the write DAC command can be used to make situational adjustments. Refer to Figure 2 for an illustration of the sequence of bus conditions for a write operation. 2023 PGM T1 1.0 TABLE 1. COMMAND FORMAT Internally there are four DACs and associated with each are two registers. There is one data register that is used by the DAC to hold the digital value it converts. There is also one nonvolatile register that holds the default value that can be recalled into the data register during powerup or by executing the Recall command. READ Read operations are initiated by taking CS LOW and clocking in a start bit followed by the read command and the address of the data register to be read. The next eight CS CLK DI DO S T A R T C1 C0 A1 A0 Hi Z D7 D6 D5 D4 D3 D2 D1 D0 Hi Z Pulled Up to VDD RDY/BSY 2023 ILL3 1.0 FIGURE 1. READ SEQUENCE 2023 1.5 4/24/99 3 S9418 CS CLK DI S T A R T C1 C0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi Z DO Pulled Up to VDD RDY/BSY VOUT 2023 ILL5 1.0 FIGURE 2. WRITE SEQUENCE Rising Edge Sets NV Write Enable Latch Rising Edge Starts NV Write CS CLK DI S T A R T C1 C0 A1 D0 Address and Data are Don’t Care S T A R T C1 C0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 NV Write Enable Latch is Reset Pulled Up to VDD RDY/BSY 2023 ILL4 1.0 FIGURE 3. NONVOLATILE WRITE SEQUENCE NONVOLATILE WRITE A nonvolatile write is a two step operation: it is initiated by taking CS LOW and clocking in a start bit followed by the NV Write Enable command. At this point the host can take CS back high or continue clocking in data. This data is don’t care and will be ignored by the S9418. and the data will be latched into the data register and a nonvolatile write operation will commence. The status of the nonvolatile write can be monitored on the RDY/BSY pin. A logic low indicates the write is still in progress and the S9418 will not be accessible to the host; a logic high indicates the write has completed and the S9418 is ready for the next command. Refer to Figure 3 for an illustration of the sequence of bus conditions for a nonvolatile write operation. Next, the host takes CS LOW again and issues a write command and address and then clocks in the eight data bits to be programmed. The host will then bring CS HIGH 2023 1.5 4/24/99 4 S9418 RECALL COMMAND The recall command will retrieve data from the selected nonvolatile register and write it into the data register of the associated DAC. This operation is initiated by taking CS LOW and clocking in a start bit followed by the recall command and the address of the nonvolatile register to be recalled. The eight bits of data are don’t care, so CS can be taken high any time after the address bits are clocked in. Refer to Figure 4 for an illustration of the sequence of bus conditions for a Recall operation. Power-On Recall Whenever the S9418 is powered on, the VOUT values will be returned to the analog equivalent of the data byte stored in the nonvolatile register. MUTE Operation The MUTE input is active high. Whenever the input is low, the VOUT will reflect the value in the data register. If MUTE is driven high the VOUT outputs will be switched to VREFL. Releasing the MUTE input returns the VOUT outputs to the analog equivalent of the data register contents. CS CLK DI S T A R T C1 C0 A1 A0 VOUT 2023 ILL6 1.0 FIGURE 4. RECALL COMMAND SEQUENCE 2023 1.5 4/24/99 5 S9418 ABSOLUTE MAXIMUM RATINGS Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. VDD to GND ................................................................... -0.5V to +7V Digital Inputs to Gnd ............................................. -0.5V to VDD+0.5V Analog Inputs to ground ........................................ -0.5V to VDD+0.5V Digital Outputs to Gnd ........................................... -0.5V to VDD+0.5V Analog Outputs to Gnd ......................................... -0.5V to VDD+0.5V Temperature Under Bias ........................................... -55°C to +125°C Storage Temperature ................................................ -65°C to +150°C Lead Soldering (10 Sec Max) ................................................... 300°C RECOMMENDED OPERATING CONDITIONS Condition Temperature VDD Min -40°C +2.7V Max +85°C +5.5V 2023 PGM T2 1.1 RELIABILITY CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Symbol Parameter Min VZAP ESD Susceptibility ILTH Max Unit Test Method 2000 V MS-883, TM 3015 Latch-Up 100 mA JEDEC Standard 17 TDR Data Retention 100 Years MS-883, TM 1008 NEND Endurance 1,000,000 Stores MS-883, TM 1033 2023 PGM T3 1.1 DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Symbol Parameter Conditions IDD Supply Current during store, note 1 ISB Min Max Units CS = VIL 1.8 mA Standby Supply Current CS = VIH 800 µA IIH Input Leakage Current VIN = VDD 10 µA IIL Input Leakage Current VIN =0V -10 µA VIH High Level Input Voltage 2 VDD V VIL Low Level Input Voltage 0 0.8 V VOH High Level Output Voltage VOL Low Level Output Voltage IOH = -400µA VDD-0.3 IOL=1mA, VDD = +5V IOL= 0.4mA, VDD = +2.7V 0.4 Note 1: IDD is the supply current drawn while the EEPROM is being updated 2023 1.5 4/24/99 6 V 0.4 V V 2023 PGM T4 1.2 S9418 AC ELECTRICAL CHARACTERISTICS VDD = +4.5V to +5.5V, VREFH = VDD, VREFL = 0V, TA = -40°C to +85°C, unless otherwise specified Symbol Parameter fC Clock Frequency DC tWH Minimum CLK High Time 500 ns tWL Minimum CLK Low Time 300 ns tCS Minimum CS High Time 150 ns tCSS CS Setup Time 100 ns tCSH CS Hold Time 0 ns tSU Data In Setup Time CL = 100pF 50 ns tH Data In Hold Time See Note 1 50 ns tV Output Valid Time tHO Data Out Hold Time tDIS Output Disable Time 400 tBUSY Write Cycle Time 3.3 Notes: Conditions Min. Typ. Max. Units 1 MHz 150 ns 0 ns ns 5 ms 2023 PGM T5 1.1 1. All timing measurements are defined at the point of signal crossing VDD/2. tCS CS tCSS tWL tWH tCSH CLK tSU tH DI tV Hi Z tHO tDIS Hi Z DO RDY/BSY FIGURE 5. AC TIMING DIAGRAM 2023 ILL7 1.0 2023 1.5 4/24/99 7 S9418 DAC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VrefH = VDD, VrefL = 0V, TA = -40°C to +85°C, unless specified otherwise Accuracy Symbol Parameter Conditions Min. Typ. Max. Units INL Integral Non-Linearity ILOAD = 100µA, - 0.5 ±1 LSB DNL Differential Non-Linearity ILOAD = 100µA, Guaranteed but not tested - 0.1 ±0.5 LSB References VrefH VrefH Input Voltage VrefL - VDD V VrefL VrefL Input Voltage Gnd - VrefH V RIN VrefH to VrefL Resistance - 38K - Ω TCRIN Temperature Coefficient of RIN - 600 - ppm/°C ∆RIN Input Resistance Match - ±0.5 ±1 % Analog GEFS Full-Scale Gain Error D = FF ±1 LSB Output VOUTZS Output Offset Voltage D = 00 0 20 mV TCVOUT VOUT Temperature Coefficient VDD = +5V, ILOAD = 50µA, Guaranteed but not tested - 50 µV/°C +1000 µA - IL Amplifier Output Load Current ROUT Amplifier Output Resistance VDD = VrefH PSRR Power Supply Rejection ts DAC Setting Time to 1LSB 10pf 10pf eN Amplifier Output Noise f = 1kHz, VDD = +5V - 90 - THD Total Harmonic Distortion VREFH = 2.5V VDD = +5V VIN = 1V rms, f = 1kHz - 0.08 - % VDD = +5V VREFH = +2.5V VIN = 100mV rms - 300 - kHz BW Bandwidth - 3dB -200 +5V +3V ILOAD = 10µA - 10 20 - - +5V +3V Ω Ω 1 LSB/V µs µs 20 20 nV/ HZ 2023 PGM T6 1.5 2023 1.5 4/24/99 8 S9418 20 Pin SOIC (.300) Package 0.496 - 0.512 (12.598 - 13.005) 0.394 - 0.419 (10.007 - 10.643) 0.291 - 0.299 (7.391 - 7.595) 0.010 - 0.029 0.093 - 0.104 0.037 - 0.045 (2.362 - 2.642) x45° (0.940 - 1.143 (0.254 - 0.737) 0° to 8° typ 0.009 - 0.013 0.016 - 0.050 0.050 (0.229 - 0.330) (0.406 - 1.270) (1.270) 0.004 - 0.012 (0.102 - 0.305) 0.014 - 0.019 (0.356 - 0.482) 20pn SOIC ILL.1 ORDERING INFORMATION S9418 S Package S = 20 Lead SOIC Base Part Number 2023 ILL8 1.1 2023 1.5 4/24/99 9 S9418 NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 1999 SUMMIT Microelectronics, Inc. 2023 1.5 4/24/99 10