PS12 Quad Power Sequencing Controller Features General Description ► Power supply sequencer with four outputs Many systems require that their power supplies are enabled and disabled sequentially in order to reduce transient current demand on the power bus, or to avoid damage to components having multiple supply voltages such as microprocessors, ASICs, MEMS drivers, etc. ► Power-up and power-down sequencing ► Six programmable delays ► Maximum 90V supply voltage ► Input voltage window comparator The PS12 incorporates a power-up delay timer, a window voltage comparator, 4 open drain enable outputs, and 6 enable delay timers. The enable delays are individually programmable for both the power-up (ABCD) and the powerdown (DCBA) sequence. ► Low power supply current (500µA typical) ► 16-Lead SOIC Package Applications Power-up and power-down are controlled by a window comparator formed by the ON and OV voltage comparators. VIN voltage within the window initiates power-up; VIN voltage outside of the window maintains or initiates power-down. The power-up sequence may be interrupted while in progress. The power-down sequence, once initiated, cannot be interrupted until it is brought to completion. ► Reduction of transient current demand and protection of sensitive loads ► Telecom and networking systems ► High voltage MEMS and display driver supplies Typical Application Circuit +12V 15 R1 R2 3 4 1 VEE VIN ON PSA OV PSB R3 11 ENA +12V CONVERTER OUT 12 ENA +5V CONVERTER OUT 13 ENA +3.3V CONVERTER OUT 14 ENA +1.8V CONVERTER OUT PS12NG PSC 2 PUD CPUD PSD TAB TBC TCD TDC TCB TBA 5 6 7 8 9 10 RAB RBC RCD RDC RCB RBA PS12 Pin Configuration Ordering Information Package Option Device 16-Lead SOIC PS12 VEE 1 16 NC PUD 2 15 VIN ON 3 14 PSD 4 13 PSC TAB 5 12 PSB TBC 6 11 PSA Value TCD 7 10 TBA -0.3V...+100V TDC 8 9 PS12NG-G -G indicates package is RoHS compliant (‘Green’) OV Absolute Maximum Ratings Parameter VIN1 PSA...PSD 1 TCB -0.3V...+100V 1 ON, OV 16-Lead SOIC -0.3V...+8V ESD (all pins except VIN, PSA...PSD) 2 (top view) ±2kV Operating ambient temperature -40OC...+85OC Operating junction temperature -40OC...+125OC Pin Configuration Storage temperature -65OC...+150OC Top Marking Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes: 1. Referenced to VEE 2. HBM, 1.5kΩ, 100pF PS12NG YWW LLLLLLLL Bottom Marking CCCCCCCCC AAA Thermal Resistance Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = “Green” Packaging *May be part of top marking Package θja 16-Lead SOIC 65K/W to 120K/W (PCB Layout dependent) Block Diagram VIN PS12 ON PSA INTERNAL VOLTAGE REGULATOR PU 1.20V PD 1.00V PSB OV CONTROL LOGIC PD 1.20V PU 1.00V PSC PSD 12 µA VEE 1.20 V PUD C PUD TAB TBC TCD TDC TCB TBA R AB R BC R CD R DC R CB R BA 2 PS12 Electrical Characteristics (TJ = 25°C unless otherwise specified. Voltages referenced to VEE, VVIN = +4.5V...+90V. Values marked with * apply over the full temperature range.) Symbol Parameter Min Typ Max Units VVIN Supply voltage 4.5 - 90 V IVIN Supply current - 500 625 - 400 - Conditions Supply (VIN) µA * --- - VIN = 36V, RT = 2MΩ - VIN = 12V, RT = 2MΩ Input Voltage Monitor (ON) VONPU Power-up threshold 1.16 1.22 1.28 V * VON Rising VONPD Power-down threshold 1.06 1.12 1.18 V * VON Falling VHY Power-up/Power-down hysteresis - 100 - mV - --- ION Input Current - ±1 - nA - --- Input Voltage Monitor (OV) VOVPD Power-down threshold 1.16 1.22 1.28 V * VOV Rising VOVPU Power-up threshold 1.06 1.12 1.18 V * VOV Falling VHY Power-up/power-down hysteresis - 100 - mV - --- IOV Input current - ±1 - nA - --- Power Supply Enable Outputs (PSA, PSB, PSC, PSD) ILKG High state leakage current - - 10 µA * VPS = 90V PS = HiZ VSAT Low state output voltage - - 100 mV - IPS = 1mA PS = Low Power-up Delay (PUD) IPUD Output current -8.4 -12 -16 µA - --- VPUD Threshold voltage 1.15 1.20 1.25 V - --- - 500 - Ω - IDISCH = 1mA RDISCH Discharge FET ON resistance Power Supply Enable Timing (TAB, TBC, TCD, TDC, TCB, TBA) Timing resistance range 50 - 2000 kΩ - --- TPSPS(MAX) Maximum PS-to-PS delay 160 200 240 ms - RT = 2MΩ TPSPS(MIN) Minimum PS-to-PS delay 4.0 5.0 6.0 ms - RT = 50kΩ RT 3 PS12 Pin Description Pin # Function 15 VIN Description Power supply pins. VIN positive with respect to VEE. 1 VEE 2 PUD The outputs PSA thru PSD are pulled to a logic low state upon application of power. Hookup pin for the power-up-delay (PUD) timing capacitor. Pin pulls capacitor to ground upon application of power. (See timing diagram) 3 ON Input pin of the ON comparator. Rising transition initiates power-up sequence. 4 OV Input pin of the OV comparator. Rising transition initiates the power-down sequence. 5 TAB 6 TBC Hookup pins for timing resistors. 7 TCD On power-up, the resistor at TAB determines the delay between the rising transitions of PSA and PSB; similarly, TBC relates to ( PSB / PSC ), and TCD to ( PSC / PSD ). 8 TDC 9 TCB 10 TBA 11 PSA 12 PSB On power-down, the resistor at TDC determines the delay between the falling transitions of PSD and PSC; similarly, TCB relates to ( PSC / PSB ), and TBA to ( PSB / PSA ). Power supply enable output pins. These four pins control loads, such as DC/DC converter modules, load switches, ICs, etc. Configured with open drain output stages. 13 PSC On power-up, right after expiration of the PUD delay, the sequencer asserts PSA, and subsequently asserts PSB, PSC and PSD observing the delays, programmed by the (TAB, TBC, and TCD) pins. 14 PSD On power-down, the sequencer deasserts PSD, and subsequently deasserts PSC, PSB, and PSA observing the delays, programmed by the (TAB, TBC, and TCD) pins. 16 NC No connect 4 PS12 Oscillograms The figures of typical waveforms are organized in the following way: Figure Function 1, 2, 3, 4 PS (A, B, C, D) 5, 6 ON, PUD, PS (A, B, D) 7, 8 PUD, PS (A, B) 9 OV, PUD, PS (A, B) 10 ON, PS (A, B, C) Description Power-up and power-down delays. Delay times around 5ms and 200ms. ON pin detail. Fig.6. shows a power-down / power-up sequence. PUD pin detail; PSA is asserted when voltage at PUD pin about 1.2V. PUD pin resets when PSB is deasserted. OV pin detail. Overvoltage returns to voltage window. Partial power-up sequence. Power-down triggered by loss of valid ON. Fig.1 Fig.2 Fig.3 Fig.4 5 PS12 Fig.5 Fig.6 Fig.7 Fig.8 Fig.9 Fig.10 6 PS12 Functional Description The PS12 provides power-up and power-down sequencing for devices such as power supply modules, load switches, ICs, etc. The four outputs PSA thru PSD are configured with open drain drivers, which are typically used to power supply modules. Some systems may require level-shifting or isolating drivers. Enable Outputs at Low VIN The internal circuits of the PS12 can be expected to provide well-defined outputs at a power supply voltage of about 3.3V and above. At lower power supply voltages, the existence of poorly defined output levels should typically not be an issue if the PS12 and the controlled loads share the same supply, since the loads may not be adequately biased as well. Upon application of power, the power-up delay timer is reset and the enable outputs PSA thru PSD are de-asserted. Window Comparator Some caution is warranted when the controlled loads are independently powered and the power supply voltage to the PS12 is inadequate or ill-defined. The state of the four PS outputs and the associated powerup and power-down sequencing is controlled by a window comparator formed by the ON and OV voltage comparators. Delay Time Considerations The PS12 is characterized for enable to enable delay times between 5ms and 200ms, which should cover most applications. Initial characterization of this device shows excellent linearity between delay time and programming resistance for a delay time in the range of 2.5ms to 5 seconds. These comparators define a voltage window having thresholds programmed by an external resistive divider. The ON comparator defines the lower threshold of the window, while the OV comparator defines the upper threshold of the window. Both comparator thresholds feature 200mV hysteresis. Shorting of a programming pin is not advised, and may reduce long term reliability, as internal circuits are not dimensioned for sourcing the resultant pin current. Power-up and Power-down Sequence Power supply voltage moving into the window causes the start of a power-up sequence. The sequence consists of the power-up delay, programmed by CPUD, and the subsequent assertion of the PS outputs in the sequence ABCD using the enable to enable delays (TAB, TBC, TCD), as programmed by the resistors (RAB, RBC, RCD). Power-up Delay (PUD) The power-up delay is set by the time required to charge the CPUD capacitor to 1.2V. The PUD pin sources a current of 12μA, resulting in a delay time of 100ms per µF. Charging continues past the power-up delay until a voltage of about 4V is reached. Power supply voltage moving outside the window causes the start of a power-down sequence. The sequence consists of the de-assertion of the most recently asserted PS output, typically PSD, and subsequent de-assertion of other asserted PS outputs in the sequence DCBA using the enable delays (TDC, TCB, TBA), as programmed by the resistors (RDC, RCB, RBA). An internal voltage comparator at the PUD pin inhibits the power-up sequence, should the CPUD capacitor not be discharged before initiating the power-up delay. Discharge of the CPUD capacitor occurs during the powerdown sequence. The discharge transistor is turned on at the end of the sequence when PSA is the last remaining asserted output. The power-up sequence may be terminated prematurely by a power-down sequence. On the other hand, the power-down sequence is latching in nature; once power-down is initiated, the sequence is brought to completion regardless of changes in the state of the window comparator. After the power-down sequence is completed, a new power-up sequence may start, depending on the state of the window comparator at that time. 7 PS12 Start the design by programming the power-up voltage. The power-down voltage VINONPD is fixed at 83.3% of the powerup voltage. Next, program the overvoltage power down voltage VOVPD by selecting the multiplying factor R2 / R3, knowing VINONPU. Programming ON and UV V IN R1 A numerical example: VIN = 12V and [R1, R2, R3] = [107kΩ, 4.99kΩ, 9.09kΩ], results in the following: ON (1) RDIV = 121.1kΩ, (2) IDIV = 99.1µA, (3) [VINONPU, VINONPD, VINOVPD, VINOVPU] = [10.32V, 8.60V, 15.98V, 13.32V]. ONPU 1.20V R2 ONPD 1.10V Note the following: VINOVPD OV VINONPU R3 VOVPD R3 R 1.20 ⎛⎜ R2 + R3 ⎞⎟ = = = 1+ 2 VONPU 1.20 ⎜⎝ R3 ⎟⎠ R3 R 2 + R3 OVPD 1.20V OVPU 1.10V Programming the Power-up Delay The power-up delay (TPUD) is set by the time required to charge the CPUD capacitor to the threshold voltage VPUD: The ON and OV inputs draw negligible current, allowing the use of a high impedance divider. A divider current between 10µA and 100µA is more than adequate. RDIV = R1 + R2 + R3 IDIV VPUD = 1.20V IPUD = 12µA TPUD = V = IN RDIV A numerical example: A 100nF capacitor results in a TPUD of 12ms. VIN thresholds can be determined from the following: ON Power-up: VONPU = 1.20V VINONPU VONPU = R2 + R3 RDIV ON Power-down: VONPD = 1.00V VINONPD V = ONPD R2 + R3 RDIV CPUD • VPUD IPUD Programming the PS to PS Delay The PS to PS delays are set by the six timing resistors. Delay time and resistance are related as follows: TPSPS = KT • RT KT = 100 OV Power-down: VOVPD = 1.20V VINOVPD VOVPD = RDIV R3 OV Power-up: VOVPU = 1.00V VINOVPU VOVPU = RDIV R3 ns Ω A numerical example: A resistance of 100kΩ results in a delay time of 10ms. 8 PS12 Timing Diagram VIN OVPD VIN OVPU VIN OVPD VIN OVPU VIN VIN ONPU VIN ONPD VIN ONPD TPUD PUD PSA TAB TAB PSB TBC TBC PSC TCD TDC PSD 9 PS12 16-Lead SOIC (Narrow Body) Package Outline (NG) 9.90x3.90mm body, 1.75mm height (max), 1.27mm pitch D 16 θ1 E E1 Note 1 (Index Area D/2 x E1/2) Gauge Plane L2 1 L Seating Plane θ L1 Top View View B A View B h A A2 e A1 Note 1 h Seating Plane b A Side View View A-A Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol A MIN Dimension (mm) 1.35 A1 0.10 A2 1.25 b 0.31 D 9.80 E 5.80 E1 e 3.80 NOM - - - - 9.90 6.00 3.90 MAX 1.75 0.25 1.65 0.51 10.00 6.20 4.00 h 0.25 1.27 BSC L L1 L2 0.40 - - 0.50 1.27 θ 0 1.04 REF 0.25 BSC O θ1 5O - - 8O 15O JEDEC Registration MS-012, Variation AC, Issue E, Sept. 2005. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.#DSFP-PS12 NR042707 10