TPIC6B596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS095 – MARCH 2000 D D D D D D D D Low rDS(on) . . . 5 Ω Avalanche Energy . . . 30 mJ Eight Power DMOS-Transistor Outputs of 150-mA Continuous Current 500-mA Typical Current-Limiting Capability Output Clamp Voltage . . . 50 V Enhanced Cascading for Multiple Stages All Registers Cleared With Single Input Low Power Consumption DW OR N PACKAGE (TOP VIEW) NC VCC SER IN DRAIN0 DRAIN1 DRAIN2 DRAIN3 SRCLR G GND description The TPIC6B596 is a monolithic, high-voltage, medium-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other mediumcurrent or high-voltage loads. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 NC GND SER OUT DRAIN7 DRAIN6 DRAIN5 DRAIN4 SRCK RCK GND NC – No internal connection logic symbol† G RCK SRCLR SRCK 9 EN3 12 8 13 C2 R SRG8 C1 This device contains an 8-bit serial-in, parallel-out 4 3 DRAIN0 2 1D SER IN shift register that feeds an 8-bit D-type storage 5 register. Data transfers through both the shift and DRAIN1 6 storage registers on the rising edge of the DRAIN2 7 shift-register clock (SRCK) and the register clock DRAIN3 (RCK), respectively. The storage register 14 DRAIN4 transfers data to the output buffer when shift15 DRAIN5 register clear (SRCLR) is high. When SRCLR is 16 low, all registers in the device are cleared. When DRAIN6 17 output enable (G) is held high, all data in the DRAIN7 2 18 output buffers is held low and all drain outputs are SER OUT off. When G is held low, data from the storage register is transparent to the output buffers. When † This symbol is in accordance with ANSI/IEEE Std 91-1984 data in the output buffers is low, the DMOSand IEC Publication 617-12. transistor outputs are off. When data is high, the DMOS-transistor outputs have sink-current capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sinkcurrent capability. Each output provides a 500-mA typical current limit at TC = 25°C. The current limit decreases as the junction temperature increases for additional device protection. The TPIC6B596 is characterized for operation over the operating case temperature range of – 40°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPIC6B596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS095 – MARCH 2000 logic diagram (positive logic) G RCK SRCLR 9 12 4 8 D SRCK SER IN 13 C1 D C2 CLR CLR D C1 D C2 CLR CLR D C1 D C2 CLR CLR D C1 D C2 CLR CLR D C1 D C2 CLR CLR D 5 3 C1 D C2 CLR CLR D C1 D C2 CLR CLR D C1 D C2 CLR CLR 6 7 14 15 16 17 10, 11, 19 D C1 18 CLR 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SER OUT DRAIN0 DRAIN1 DRAIN2 DRAIN3 DRAIN4 DRAIN5 DRAIN6 DRAIN7 GND TPIC6B596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS095 – MARCH 2000 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS VCC DRAIN 50 V Input 25 V 20 V 12 V GND GND absolute maximum ratings over recommended operating case temperature range (unless otherwise noted)† Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Logic input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Power DMOS drain-to-source voltage, VDS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V Continuous source-to-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Pulsed source-to-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Pulsed drain current, each output, all outputs on, ID, TC = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . 500 mA Continuous drain current, each output, all outputs on, ID, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA Peak drain current single output, IDM,TC = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Single-pulse avalanche energy, EAS (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mJ Avalanche current, IAS (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Each power DMOS source is internally connected to GND. 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%. 4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 200 mH, IAS = 0.5 A (see Figure 4). DISSIPATION RATING TABLE PACKAGE TC ≤ 25°C POWER RATING DW N DERATING FACTOR ABOVE TC = 25°C TC = 125°C POWER RATING 1389 mW 11.1 mW/°C 278 mW 1050 mW 10.5 mW/°C 263 mW POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPIC6B596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS095 – MARCH 2000 recommended operating conditions Logic supply voltage, VCC High-level input voltage, VIH MIN MAX 4.5 5.5 UNIT V 0.85 VCC Low-level input voltage, VIL Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) V 0.15 VCC V 500 mA – 500 Setup time, SER IN high before SRCK↑, tsu (see Figure 2) 15 ns Hold time, SER IN high after SRCK↑, th (see Figure 2) 15 ns Pulse duration, tw (see Figure 2) 40 Operating case temperature, TC – 40 ns °C 125 NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%. 5. Technique should limit TJ – TC to 10°C maximum. electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS V(BR)DSX Drain-to-source breakdown voltage ID = 1 mA VSD Source-to-drain diode forward voltage IF = 100 mA VOH High-level output voltage, g g , SER OUT VOL Low-level output voltage, g , SER OUT IIH IIL MIN TYP MAX 50 V 0.85 IOH = – 20 µA, VCC = 4.5 V IOH = – 4 mA, VCC = 4.5 V IOL = 20 µA, VCC = 4.5 V High-level input current IOL = 4 mA, VCC = 5.5 V, VCC = 4.5 V VI = VCC Low-level input current VCC = 5.5 V, VI = 0 4.49 4 4.2 0.005 0.1 0.3 0.5 µA –1 µA All outputs on 150 300 0.4 5 ICC(FRQ) Logic supply current at frequency fSRCK = 5 MHz, CL = 30 pF, All outputs off, See Figures 2 and 6 IN Nominal current IDSX Off state drain current Off-state rDS(on) Static drain-source on-state resistance See Notes 5, 6, and 7 VDS = 40 V, ID = 100 mA, VCC = 5.5 V, TC = 125°C VCC = 4.5 V ID = 100 mA, VCC = 4.5 V ID = 350 mA, TC = 125°C, See Notes 5 and 6 and Figures 7 and 8 V 1 100 5V VCC = 5 5.5 V V 20 Logic supply current VDS(on) = 0.5 V, IN = ID, TC = 85°C VDS = 40 V, VCC = 5.5 V 4.4 1 All outputs off ICC UNIT 90 µA mA mA 0.1 5 0.15 8 4.2 5.7 6.8 9.5 µA Ω VCC = 4.5 V 5.5 8 NOTES: 5. Technique should limit TJ – TC to 10°C maximum. 6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0.5 V at TC = 85°C. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC6B596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS095 – MARCH 2000 switching characteristics, VCC = 5 V, TC = 25°C PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low-to-high-level output from G tr tf Rise time, drain output Propagation delay time, high-to-low-level output from G MIN TYP CL = 30 pF,, ID = 100 mA,, See Figures 1, 2, and 9 Fall time, drain output tpd Propagation delay time, SRCK↓ to SEROUT CL = 30 pF, See Figure 2 f(SRCK) Serial clock frequency CL = 30 pF, See Note 8 ta trr Reverse-recovery-current rise time ID = 100 mA, ID = 100 mA, UNIT ns 90 ns 200 ns 200 ns 15 ns 10 IF = 100 mA,, di/dt = 20 A/µs, µ , See Notes 5 and 6 and Figure 3 Reverse-recovery time MAX 150 100 MHz ns 300 NOTES: 5. Technique should limit TJ – TC to 10°C maximum. 6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 8. This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second stage. The clock period allows for SRCK → SEROUT propagation delay and setup time plus some timing margin. thermal resistance PARAMETER RθJA TEST CONDITIONS DW package Thermal resistance, resistance junction-to-ambient junction to ambient MIN 90 All 8 outputs with equal power N package MAX 95 UNIT °C/W PARAMETER MEASUREMENT INFORMATION 24 V 5V 7 2 8 13 Word Generator (see Note A) 3 12 9 SRCLR SRCK 5 4 3 2 1 0 DRAIN 4 –7, 14 –17 Output G 0V 5V SER IN CL = 30 pF (see Note B) RCK 5V G RL = 235 Ω DUT 5V 0V ID VCC SER IN 6 SRCK 0V 5V RCK 0V 5V SRCLR 0V GND 10, 11, 19 24 V DRAIN1 0.5 V VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 1. Resistive-Load Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPIC6B596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS095 – MARCH 2000 PARAMETER MEASUREMENT INFORMATION 5V G 50% 50% 0V 5V tPLH 24 V Output 2 8 13 Word Generator (see Note A) 3 12 9 V SRCLR CC SRCK ID 4 –7, 14 –17 DUT 90% 24 V 90% 10% 10% tr RL = 235 Ω SWITCHING TIMES Output 5V 50% SRCK 0V CL = 30 pF (see Note B) RCK 0.5 V tf DRAIN SER IN G tPHL tsu th GND 5V 10, 11, 19 SER IN 50% 50% 0V TEST CIRCUIT tw INPUT SETUP AND HOLD WAVEFORMS SRCK 50% 50% tpd SER OUT 50% tpd 50% SER OUT PROPAGATION DELAY WAVEFORM NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 2. Test Circuit, Switching Times, and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC6B596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS095 – MARCH 2000 PARAMETER MEASUREMENT INFORMATION TP K DRAIN 0.1 A 2500 µF 250 V Circuit Under Test di/dt = 20 A/µs + 25 V L = 1 mH IF (see Note A) IF – 0 TP A 25% of IRM t2 t1 t3 Driver IRM RG VGG (see Note B) ta 50 Ω trr TEST CIRCUIT CURRENT WAVEFORM NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the TP A test point. B. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.1 A, where t1 = 10 µs, t2 = 7 µs, and t3 = 3 µs. Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode 5V 15 V tw 2 8 10.5 Ω V SRCLR CC Word Generator (see Note A) 3 12 9 DUT 4 –7, 14 –17 DRAIN RCK See Note B 200 mH SER IN G 5V Input ID 13 SRCK tav 0V IAS = 0.5 A ID VDS GND V(BR)DSX = 50 V MIN VDS 10, 11, 19 SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT VOLTAGE AND CURRENT WAVEFORMS NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω. B. Input pulse duration, tw, is increased until peak current IAS = 0.5 A. Energy test level is defined as EAS = IAS × V(BR)DSX × tav/2 = 30 mJ. Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPIC6B596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS095 – MARCH 2000 TYPICAL CHARACTERISTICS PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE SUPPLY CURRENT vs FREQUENCY 10 2.5 VCC = 5 V TC = – 40°C to 125°C 4 I CC – Supply Current – mA IAS – Peak Avalanche Current – A TC = 25°C 2 1 0.4 2 1.5 1 0.5 0.2 0.1 0.1 0.2 0.4 1 2 4 0 0.1 10 1 tav – Time Duration of Avalanche – ms Figure 5 14 TC = 125°C 12 10 8 6 TC = 25°C 4 TC = – 40°C 2 0 0 100 200 300 400 500 ID – Drain Current – mA 600 700 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE r DS(on) – Static Drain-to-Source On-State Resistance – Ω r DS(on) – Drain-to-Source On-State Resistance – Ω VCC = 5 V See Note A 16 8 ID = 100 mA See Note A 7 TC = 125°C 6 5 TC = 25°C 4 3 TC = – 40°C 2 1 0 4 4.5 5 5.5 Figure 8 POST OFFICE BOX 655303 6 6.5 VCC – Logic Supply Voltage – V Figure 7 8 100 Figure 6 DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 18 10 f – Frequency – MHz • DALLAS, TEXAS 75265 7 TPIC6B596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS095 – MARCH 2000 TYPICAL CHARACTERISTICS SWITCHING TIME vs CASE TEMPERATURE 300 ID = 100 mA See Note A tf Switching Time – ns 250 tr 200 tPLH 150 tPHL 100 50 – 50 – 25 0 25 50 75 100 TC – Case Temperature – °C 125 Figure 9 NOTE A: Technique should limit TJ – TC to 10°C maximum. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPIC6B596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS095 – MARCH 2000 THERMAL INFORMATION I D – Maximum Continuous Drain Current of Each Output – A 0.45 VCC = 5 V 0.4 0.35 0.3 0.25 TC = 25°C 0.2 0.15 TC = 100°C 0.1 TC = 125°C 0.05 0 1 2 3 4 5 6 7 8 N – Number of Outputs Conducting Simultaneously I D – Maximum Peak Drain Current of Each Output – A MAXIMUM PEAK DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY MAXIMUM CONTINUOUS DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY 0.5 d = 10% 0.45 d = 20% 0.4 0.35 d = 50% 0.3 0.25 d = 80% 0.2 0.15 VCC = 5 V TC = 25°C d = tw/tperiod = 1 ms/tperiod 0.1 0.05 0 1 3 4 Figure 11 Figure 10 10 2 POST OFFICE BOX 655303 5 6 7 8 N – Number of Outputs Conducting Simultaneously • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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