19-3119; Rev 0; 12/03 ±10V, 12-Bit, Serial, Voltage-Output DAC Features The MAX5312 12-bit, serial-interface, digital-to-analog converter (DAC) provides bipolar ±5V to ±10V outputs from ±12V to ±15V power-supply voltages, or a unipolar 5V to 10V output from a single 12V to 15V powersupply voltage. The MAX5312 features excellent linearity with both integral nonlinearity (INL) and differential nonlinearity (DNL) guaranteed to ±1 LSB (max). The device also features a fast 10µs to 0.5 LSB settling time, and a hardwareshutdown feature that reduces current consumption to 3.5µA. The output goes to midscale at power-up in bipolar mode (0V), and to zero scale at power-up in unipolar mode (0V). A clear input (CLR) asynchronously clears the DAC register and sets the output to 0V. The output can be asynchronously updated with the load DAC (LDAC) input. The device features a 10MHz SPI™-/QSPI™-/ MICROWIRE™-compatible serial interface that operates with 3V or 5V logic. Additional features include a serial-data output (DOUT) for daisy chaining and readback functions. The MAX5312 requires a 2V to 5.25V external reference voltage and is available in a 16-pin SSOP package that operates over the extended -40°C to +85°C temperature range. ♦ Unipolar or Bipolar Output-Voltage Ranges Unipolar: 0 to (+2 x VREF) (Single or Dual Supply) Bipolar: (-2 x VREF) to (+2 x VREF) (Dual Supply) ♦ Guaranteed INL ≤ ±1 LSB (max) ♦ Guaranteed Monotonic: DNL ≤ ±1 LSB (max) ♦ 10µs Settling Time to 0.5 LSB ♦ Low 3.5µA Shutdown Current ♦ 10MHz SPI-/QSPI-/MICROWIRE-Compatible Serial Interface ♦ Power-On Reset Sets DAC Output to 0V ♦ Schmitt Trigger Inputs for Direct Optocoupler Interface ♦ Serial-Data Output Allows Daisy Chaining of Devices ♦ Small 16-Pin SSOP Ordering Information Applications Motor Control Industrial Process Controls Industrial Automation Automatic Test Equipment (ATE) Analog I/O Boards Data-Acquisition Systems PART MAX5312EAE TEMP RANGE PIN-PACKAGE -40°C to +85°C 16 SSOP Pin Configuration TOP VIEW SCLK 1 16 LDAC DIN 2 15 CLR CS 3 DOUT 4 14 VDD MAX5312 DGND 5 13 REF 12 VSS VCC 6 11 AGND SHDN 7 10 SGND UNI/BIP 8 9 OUT SSOP SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5312 General Description MAX5312 ±10V, 12-Bit, Serial, Voltage-Output DAC ABSOLUTE MAXIMUM RATINGS REF to AGND............................................................-0.3V to +6V Maximum Current into REF...............................................±10mA Maximum Current into Any Pin Excluding REF.................±50mA Continuous Power Dissipation (TA = +70°C) 16-Pin SSOP (derate 7.1mW/°C above +70°C) ...........571mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C VDD to AGND..........................................................-0.3V to +17V VSS to AGND ..........................................................-17V to +0.3V VDD to VSS ..........................................................................+34V VCC to DGND ...........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V SGND to AGND .....................................................-0.3V to +0.3V SCLK, DIN, CS, SHDN, UNI/BIP, CLR, LDAC, DOUT to DGND ..........................-0.3V to (VCC + 0.3V) OUT to AGND ..................................(VSS - 0.3V) to (VDD + 0.3V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (DUAL SUPPLY) (VDD = +15V ±5%, VSS = -15V ±5%, VCC = +5V ±10%, AGND = DGND = SGND = 0V, VREF = 5V, RLOAD = 2kΩ, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY Resolution N Integral Nonlinearity INL Differential Nonlinearity DNL Zero-Scale Error Zero-Scale Temperature Coefficient Gain Error Gain-Error Temperature Coefficient 12 Bits ±1 LSB Guaranteed monotonic ±1 LSB Bipolar, code = 800hex ±1 Unipolar, code = 000hex ±2 Bipolar 0.3 Unipolar 0.5 ppm FSR/°C Bipolar, no load ±2 Unipolar, no load ±2 Bipolar, no load 2 Unipolar, no load 2 LSB LSB ppm FSR/°C ANALOG OUTPUT (OUT) Output Voltage Range (VSS + 1.5V) < VOUT < (VDD - 1.5V) Resistive Load to GND RLOAD Capacitive Load to GND CLOAD -2 x VREF +2 x VREF 2 kΩ 250 DC Output Resistance V pF 0.5 Ω 92 kΩ SGND INPUT (SGND) Input Impedance REFERENCE INPUT (REF) Reference-Voltage Input Range Input Resistance Reference Bandwidth 2 2.00 RREF Code = 555hex, worst-case code 15 5.25 22 Shutdown 22 VREF = 200mVP-P + 5VDC 200 _______________________________________________________________________________________ V kΩ kHz ±10V, 12-Bit, Serial, Voltage-Output DAC (VDD = +15V ±5%, VSS = -15V ±5%, VCC = +5V ±10%, AGND = DGND = SGND = 0V, VREF = 5V, RLOAD = 2kΩ, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN, CS, SHDN, UNI/BIP, CLR, LDAC) Input-Voltage High VIH Input-Voltage Low VIL Input Capacitance C Input Current (Note 1) +2.7V ≤ VCC ≤ +3.6V 0.7 x VCC +4.5V ≤ VCC ≤ +5.5V 2.4 V +2.7V ≤ VCC ≤ +3.6V 0.6 +4.5V ≤ VCC ≤ +5.5V 0.8 +2.7V ≤ VCC ≤ +3.6V 10 +4.5V ≤ VCC ≤ +5.5V 10 V pF 0 ≤ all digital inputs ≤ VCC, +2.7V ≤ VCC ≤ +3.6V ±1 0 ≤ all digital inputs ≤ VCC, +4.5V ≤ VCC ≤ +5.5V ±1 µA DIGITAL OUTPUT (DOUT) Output-Voltage High VOH ISOURCE = 2mA Output-Voltage Low VOL ISINK = 2mA VCC 0.5 V 0.4 V Tri-State Leakage Current 0.2 µA Tri-State Capacitance 10 pF 2.5 V/µs DYNAMIC PERFORMANCE Voltage-Output Slew Rate Output Settling Time To ±0.5 LSB of full scale, code 000 to code FFF 10 µs Digital Feedthrough CS = high, fSCLK = 10MHz, VOUT = 0V 10 nV-s 130 nV/√Hz Output-Noise Spectral Density at 10kHz POWER SUPPLIES Positive Analog-Supply Voltage VDD 10.80 15.75 V Negative Analog-Supply Voltage VSS -10.80 -15.75 V Positive Digital-Supply Voltage VCC 2.7 5.5 V Positive Analog-Supply Current IDD Output unloaded, VOUT = FS 1.8 4 mA Negative Analog-Supply Current ISS Output unloaded, VOUT = FS 0.75 -2 mA Digital-Supply Current ICC All digital inputs = 0 or VCC 30 200 µA Positive analog supply 0.4 Negative analog supply 0.6 Positive analog supply 1.7 50 Negative analog supply 2.4 50 Digital supply 3.5 10 Power-Supply Rejection Ratio (Note 2) Shutdown Current PSRR LSB/V µA _______________________________________________________________________________________ 3 MAX5312 ELECTRICAL CHARACTERISTICS (DUAL SUPPLY) (continued) MAX5312 ±10V, 12-Bit, Serial, Voltage-Output DAC ELECTRICAL CHARACTERISTICS (SINGLE SUPPLY) (VDD = +15V ±5%, VSS = 0V, VCC = +5V ±10%, AGND = DGND = SGND = 0V, VREF = 5V, RLOAD = 10kΩ, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS (Note 3) ±1 LSB STATIC ACCURACY Resolution N Integral Nonlinearity INL Differential Nonlinearity DNL 12 Bits Guaranteed monotonic ±1 LSB Unipolar Zero-Scale Error Code = 14hex ±2 LSB Unipolar Zero-Scale Temperature Coefficient Code = 14hex Gain Error No load Gain-Error Temperature Coefficient No load ppm FSR/°C 0.05 ±2 LSB ppm FSR/°C 2 ANALOG OUTPUT (OUT) Output Voltage Range +2 x VREF 0 Resistive Load to GND RLOAD Capacitive Load to GND CLOAD 10 kΩ 250 DC Output Resistance V pF 0.5 Ω 92 kΩ SGND INPUT (SGND) Input Impedance REFERENCE INPUT (REF) Reference-Voltage Input Range 2.00 Input Resistance Code = 555hex, worst-case code Reference Input Bandwidth VREF = 200mVP-P + 5VDC 15 5.25 V 22 kΩ 150 kHz DIGITAL INPUTS (SCLK, DIN, CS, SHDN, UNI/BIP, CLR, LDAC) Input-Voltage High VIH Input-Voltage Low VIL Input Capacitance CIN Input Current IIN +2.7V ≤ VCC ≤ +3.6V 0.7 x VCC +4.5V ≤ VCC ≤ +5.5V 2.4 V +2.7V ≤ VCC ≤ +3.6V 0.6 +4.5V ≤ VCC ≤ +5.5V 0.8 +2.7V ≤ VCC ≤ +3.6V 10 +4.5V ≤ VCC ≤ +5.6V 10 V pF 0 ≤ VIN ≤ VCC, +2.7V ≤ VCC ≤ +3.6V ±1 0 ≤ VIN ≤ VCC, +4.5V ≤ VCC ≤ +5.5V ±1 µA DIGITAL OUTPUT (DOUT) Output-Voltage High VOH ISOURCE = 2mA Output-Voltage Low VOL ISINK = 2mA Tri-State Leakage Current 4 VCC 0.5 V 0.4 0.2 _______________________________________________________________________________________ V µA ±10V, 12-Bit, Serial, Voltage-Output DAC (VDD = +15V ±5%, VSS = 0V, VCC = +5V ±10%, AGND = DGND = SGND = 0V, VREF = 5V, RLOAD = 10kΩ, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN Tri-State Capacitance TYP MAX UNITS 10 pF 2.5 V/µs DYNAMIC PERFORMANCE Voltage-Output Slew Rate Output Settling Time To ±0.5 LSB of full scale, code 14hex to code FFF 10 µs Digital Feedthrough CS = high, fSCLK = 10MHz, VOUT = 0V 10 nV-s 130 nV/√Hz Output-Noise Spectral Density at 1kHz POWER SUPPLIES Positive Analog-Supply Voltage VDD Negative Analog-Supply Voltage VSS Positive Digital-Supply Voltage VCC Positive Analog-Supply Current IDD Output unloaded, VOUT = 0 1.8 4 mA Negative Analog-Supply Current ISS Output unloaded, VOUT = 0 0.75 -2 mA 30 200 Digital-Supply Current Power-Supply Rejection Ratio Shutdown Current ICC PSRR 10.80 15.75 0 2.7 All digital inputs = 0 or VCC ∆VDD = 14.5V to 15.5V, code FFF V V 5.5 0.04 V µA LSB/V Analog supply 1.7 50 Digital supply 3.5 10 µA _______________________________________________________________________________________ 5 MAX5312 ELECTRICAL CHARACTERISTICS (SINGLE SUPPLY) (continued) MAX5312 ±10V, 12-Bit, Serial, Voltage-Output DAC TIMING CHARACTERISTICS (VDD = +15V, VSS = -15V or 0V, VCC = +2.7V to +5.5V, AGND = DGND = SGND = 0, VREF = 5V, RLOAD = 2kΩ, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP SCLK Frequency SCLK Clock Period tCP SCLK Pulse-Width High tCH For nondaisy-chain use SCLK Pulse-Width Low tCL For nondaisy-chain use CS Fall to SCLK Rise Setup Time tCSS SCLK Rise to CS Rise Hold Time tCSH MAX UNITS 10 MHz 100 ns 45 ns 45 ns 40 ns +2.7V ≤ VCC ≤ +3.6V 15 +4.5V ≤ VCC ≤ +5.5V 10 ns DIN Setup Time tDS 20 ns DIN Hold Time tDH 10 ns LDAC Pulse Width tLD 50 ns CS Rise to LDAC Low Setup Time tLDS SCLK Fall to DOUT Valid Propagation Delay tDO1 SCLK Rise to CS Fall Delay tCS0 CS Low to DOUT Valid Time tCSE CS High to DOUT Disabled Time tCSD CS Rise to SCLK Rise Hold Time tCS1 CS Pulse-Width High tCSW CLR Pulse-Width Low tCLR +2.7V ≤ VCC ≤ +3.6V 100 +4.5V ≤ VCC ≤ +5.5V 50 CLOAD = 20pF, +2.7V ≤ VCC ≤ +3.6V 100 CLOAD = 20pF, +4.5V ≤ VCC ≤ +5.5V 80 10 CLOAD = 20pF 120 50 +2.7V ≤ VCC ≤ +3.6V 200 +4.5V ≤ VCC ≤ +5.5V 100 ns ns 120 ns ns ns ns 50 Note 1: Output unloaded, digital inputs = VCC or DGND. Note 2: ∆VDD = +14.5V to +15.5V, ∆VSS = -15.5V to -14.5V, code = FFF. Note 3: Measured from code 14hex to FFFhex. 6 ns _______________________________________________________________________________________ ns ±10V, 12-Bit, Serial, Voltage-Output DAC INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE 0.4 0.3 0.5 MAX5312 toc02 0.50 MAX5312 toc01 0.5 DIFFERENTIAL NONLINEARITY vs. INPUT CODE 0.45 0.4 0.3 0.40 0.2 0 -0.1 0.35 DNL (LSB) 0.1 INL (LSB) 0.30 0.25 -0.2 0.1 0 -0.1 -0.2 0.20 -0.3 -0.3 0.15 -0.4 -0.4 0.10 -0.5 0 1024 2048 2.0 4096 3072 -0.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1024 2048 4096 3072 VREF (V) INPUT CODE (DECIMAL) DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE INTEGRAL NONLINEARITY vs. TEMPERATURE DIFFERENTIAL NONLINEARITY vs. TEMPERATURE (WORST-CASE CODES) 0.8 0.6 0.40 INL (LSB) 0.35 0.30 0.25 0.20 0.15 0.10 3.0 3.5 4.0 4.5 5.0 0.6 0.4 0.4 0.2 0.2 0 -0.2 0 -0.4 -0.6 -0.6 -0.8 -0.8 5.5 CODE = 9FFhex -0.2 -0.4 CODE = 7FFhex -1.0 -1.0 2.5 0.8 DNL (LSB) 0.45 1.0 MAX5312 toc05 1.0 MAX5312 toc04 0.50 2.0 0 INPUT CODE (DECIMAL) MAX5312 toc06 INL (LSB) 0.2 DNL (LSB) MAX5312 toc03 INTERGRAL NONLINEARITY vs. INPUT CODE -40 -15 10 35 60 VREF (V) TEMPERATURE (°C) UNIPOLAR SETTLING TIME (CLOAD = 250pF, RLOAD = 2kΩ) BIPOLAR SETTLING TIME (CLOAD = 250pF, RLOAD = 10kΩ) -40 85 -15 10 35 MAX5312 toc07 5V/div 5V/div CS 2V/div VOUT 5V/div 0 VOUT 85 BIPOLAR MAJOR CARRY GLITCH ENERGY, CLOAD = 250pF MAX5312 toc09 MAX5312 toc08 CS 60 TEMPERATURE (°C) 5V/div CS VOUT 100mV/div 0 t = 10.0µs/div t = 10.0µs/div t = 4.00µs/div _______________________________________________________________________________________ 7 MAX5312 Typical Operating Characteristics (VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND = 0, VREF = +5.0V, output unloaded, TA = +25°C, all graphs apply to both unipolar and bipolar, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND = 0, VREF = +5.0V, output unloaded, TA = +25°C, all graphs apply to both unipolar and bipolar, unless otherwise noted.) 2.5 MAX5312 toc11 50 CS 5V/div BIPOLAR MIDSCALE VOLTAGE vs. TEMPERATURE UNIPOLAR ZERO-SCALE VOLTAGE vs. TEMPERATURE MAX5312 toc10 CODE = 014hex 49 VOUT (mV) VOUT (mV) VOUT 100mV/div 46 CODE = 800hex 2.0 48 47 MAX5312 toc12 BIPOLAR MAJOR CARRY GLITCH CLOAD = 10pF 45 44 1.5 1.0 0.5 43 42 9.998 MAX5312 toc13 CODE = FFFhex 9.999 -15 10 35 85 60 CODE = FFFhex -9.993 VOUT (mV) VOUT (mV) 9.995 -9.995 9.995 9.993 -9.997 -9.998 9.992 35 85 60 -40 -15 10 35 4.0 3.0 2.5 2.5 2.0 1.5 1.0 1.0 0.5 0.5 13.76 VDD (V) 14.78 60 2.0 1.5 12.74 15.80 VSS = -15V 3.5 3.0 11.72 35 BIPOLAR POSITIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE IDD (mA) IDD (mA) 3.5 10 TEMPERATURE (°C) MAX5312 toc16 VSS = 0V 0 10.70 -15 TEMPERATURE (°C) UNIPOLAR SUPPLY CURRENT vs. SUPPLY VOLTAGE 4.0 -40 85 60 MAX5312 toc17 10 85 -9.994 TEMPERATURE (°C) 8 CODE = 000hex -9.996 -15 60 -9.992 9.994 -40 35 BIPOLAR NEGATIVE FULL-SCALE VOLTAGE vs. TEMPERATURE 9.996 9.994 10 BIPOLAR POSITIVE FULL-SCALE VOLTAGE vs. TEMPERATURE 9.996 9.997 -15 TEMPERATURE (°C) 9.997 9.998 -40 TEMPERATURE (°C) MAX5312 toc15 UNIPOLAR FULL-SCALE VOLTAGE vs. TEMPERATURE 10.000 0 -40 MAX5312 toc14 t = 4.00µs/div VOUT (mV) MAX5312 ±10V, 12-Bit, Serial, Voltage-Output DAC 0 10.70 11.72 12.74 13.76 14.78 VDD (V) _______________________________________________________________________________________ 15.80 85 ±10V, 12-Bit, Serial, Voltage-Output DAC BIPOLAR NEGATIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE -0.5 VSS = 0V 2.2 2.5 2.1 -1.0 -2.0 IDD (mA) 2.0 -1.5 IDD (mA) ISS (mA) MAX5312 toc20A VDD = 15V MAX5312 toc19 3.0 MAX5312 toc18 0 BIPOLAR POSITIVE SUPPLY CURRENT vs. TEMPERATURE UNIPOLAR SUPPLY CURRENT vs. TEMPERATURE 1.5 2.0 1.9 -2.5 1.0 -3.0 -4.0 -15.80 1.7 0 -14.78 -13.76 -12.74 -10.70 -11.72 -40 -15 10 35 -40 85 60 -15 10 35 85 60 VSS (V) TEMPERATURE (°C) TEMPERATURE (°C) BIPOLAR NEGATIVE SUPPLY CURRENT vs. TEMPERATURE UNIPOLAR SHUTDOWN CURRENT vs. TEMPERATURE BIPOLAR SHUTDOWN CURRENT vs. TEMPERATURE -0.60 -0.65 -0.70 -0.75 -0.80 ICC 3 2 ISS 1 0 -1 10 35 -40 85 60 -15 10 35 0 -1 -2 ISS -4 85 60 IDD 1 -40 -15 TEMPERATURE (°C) TEMPERATURE (°C) 0.135 MAX5312 toc23A CODE = FFFhex 10.000 9.995 35 60 85 UNIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT UNIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT 10.005 10 TEMPERATURE (°C) MAX5312 toc23B -15 CODE = 014hex 0.125 0.115 0.105 VOUT (V) 9.990 VOUT (V) -40 2 -3 -0.90 -0.95 ICC 3 IDD MAX5312 toc22 4 -0.85 4 SHUTDOWN CURRENT (µA) -0.55 5 MAX5312 toc21 -0.50 SHUTDOWN CURRENT (µA) MAX5312 toc20B -0.45 ISS (mA) 1.8 0.5 -3.5 9.985 9.980 0.095 0.085 9.975 0.075 9.970 0.065 9.965 0.055 0.045 9.960 0 4 8 12 IOUT (mA) 16 20 0 0.2 0.4 0.6 0.8 1.0 1.2 IOUT (mA) _______________________________________________________________________________________ 9 MAX5312 Typical Operating Characteristics (continued) (VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND = 0, VREF = +5.0V, output unloaded, TA = +25°C, all graphs apply to both unipolar and bipolar, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND = 0, VREF = +5.0V, output unloaded, TA = +25°C, all graphs apply to both unipolar and bipolar, unless otherwise noted.) CODE = FFFhex 10.000 9.995 -9.975 9.990 VOUT (V) -9.980 -9.985 -9.990 9.985 9.980 9.975 -9.995 9.970 -10.000 9.965 -16 -12 -8 4 0 0 -4 8 12 16 3072 2048 IOUT (mA) IOUT (mA) INPUT CODE (DECIMAL) BIPOLAR REF INPUT RESISTANCE vs. INPUT CODE UNIPOLAR REFERENCE INPUT BANDWIDTH BIPOLAR REFERENCE INPUT BANDWIDTH REF = 0.2VP-P + 5.0VDC 3 10 6 REF = 0.2VP-P + 5.0VDC 3 0 0.1 0.01 RESPONSE (dB) RESPONSE (dB) 0 1 -3 -6 2048 3072 -6 -9 -12 -12 4096 -15 0.01 INPUT CODE (DECIMAL) 0.1 1 10 100 1000 0.01 0.1 1 UNIPOLAR STARTUP RESPONSE, CLOAD = 250pF MAX5312 toc29A VDD MAX5312 toc29B 20V/div VCC 5V/div 10 FREQUENCY (kHz) FREQUENCY (kHz) UNIPOLAR STARTUP RESPONSE, CLOAD = 10pF 20V/div -3 -9 -15 1024 VDD VCC 5V/div VREF 5V/div VREF 5V/div VOUT 2V/div VOUT 1V/div t = 10.0µs/div 4096 MAX5312 toc28 6 MAX5312 toc26 100 0 1024 0 20 MAX5312 toc27 -20 0.1 0.01 9.960 -10.005 10 1 MAX5312 toc25 -9.970 10.005 REF INPUT RESISTANCE (MΩ) CODE = 000hex MAX5312 toc24B MAX5312 toc24A -9.965 VOUT (V) UNIPOLAR REF INPUT RESISTANCE vs. INPUT CODE BIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT BIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT REF INPUT RESISTANCE (MΩ) MAX5312 ±10V, 12-Bit, Serial, Voltage-Output DAC t = 10.0µs/div ______________________________________________________________________________________ 100 1000 ±10V, 12-Bit, Serial, Voltage-Output DAC BIPOLAR STARTUP RESPONSE, CLOAD = 250pF BIPOLAR STARTUP RESPONSE, CLOAD = 10pF MAX5312 toc30B MAX5312 toc30A VDD 20V/div 20V/div VCC 5V/div VDD VCC 5V/div 10V/div 10V/div VSS VSS VOUT 2V/div VOUT 1V/div t = 10.0µs/div t = 10.0µs/div UNIPOLAR RELEASE FROM HARDWARE-SHUTDOWN RESPONSE BIPOLAR RELEASE FROM HARDWARE-SHUTDOWN RESPONSE MAX5312 toc32 MAX5312 toc31 VOUT VOUT 5V/div 5V/div VSHDN VSHDN 2V/div 2V/div t = 100µs/div t = 100µs/div UNIPOLAR SOFTWARE-SHUTDOWN RESPONSE BIPOLAR SOFTWARE-SHUTDOWN RESPONSE MAX5312 toc33A MAX5312 toc33B CS CS 5V/div 5V/div VOUT VOUT 10V/div 5V/div t = 40.0µs/div t = 40.0µs/div ______________________________________________________________________________________ 11 MAX5312 Typical Operating Characteristics (continued) (VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND = 0, VREF = +5.0V, output unloaded, TA = +25°C, all graphs apply to both unipolar and bipolar, unless otherwise noted.) MAX5312 ±10V, 12-Bit, Serial, Voltage-Output DAC Pin Description PIN 12 NAME FUNCTION 1 SCLK Serial-Clock Input. Data is shifted from DIN into the internal register on the rising edge of SCLK. Data is clocked out at DOUT on the falling edge of SCLK. SCLK is active only while CS is low. 2 DIN Serial-Data Input. DIN is the data input port for the serial interface. Clock data in on the rising edge of SCLK. 3 CS Active-Low Chip-Select Input. CS activates the serial interface. Drive CS low to initiate serial communication. 4 DOUT 5 DGND 6 VCC 7 SHDN 8 UNI/BIP 9 OUT 10 SGND 11 AGND Serial-Data Output. DOUT is the data output port for the serial interface. Data shifted into DIN appears at DOUT 16.5 clock cycles later, valid on the falling edge of SCLK. DOUT is high impedance when CS is high. Digital Ground Digital Power Input. VCC ranges from +2.7V to +5.5V. Bypass VCC with a 0.1µF and 1.0µF capacitor to Active-Low Shutdown Input. SHDN places the device into low-power shutdown mode. When shut down REF and DOUT are high impedance, drive SHDN low to place the device into shutdown mode. Unipolar/Bipolar-Select Input. UNI/BIP selects unipolar or bipolar output. In unipolar mode, the analog output range is 0 to (+2 x VREF). In bipolar mode, the analog output range is (-2 x VREF) to (+2 x VREF). Drive UNI/BIP high for unipolar output. Drive UNI/BIP low for bipolar output. Dual supplies are required for bipolar operation. Analog Output. OUT is the output port for the DAC. Read OUT relative to SGND. Signal Ground. SGND is the ground-reference node for the output amplifier’s internal feedback resistors. Connect SGND directly to AGND. (See Figure 1.) Analog Ground. AGND is the ground return for VDD and VSS. 12 VSS Negative Power Input. Bypass VSS with a 0.1µF and 1.0µF capacitor to AGND. If operating with a single supply, connect VSS to AGND. 13 REF External Reference Input. Apply an external reference voltage of +2V to +5.25V to REF to determine the output voltage range. In unipolar mode, the output range is from 0 to (+2 x VREF). In bipolar mode, the output range is from (-2 x VREF) to (+2 x VREF). 14 VDD Positive Power Input. Bypass VDD with a 0.1µF and 1.0µF capacitor to AGND. 15 CLR Active-Low Clear Input. CLR clears input and DAC registers and resets the DAC output to 0V. Drive CLR low to assert the clear condition. 16 LDAC Active-Low Load Input. Use LDAC to update the DAC register. LDAC is an asynchronous control input. Drive low to force an update. ______________________________________________________________________________________ ±10V, 12-Bit, Serial, Voltage-Output DAC The MAX5312 12-bit DAC operates from either single or dual supplies. Dual ±12V to ±15V power supplies provide a bipolar ±5V to ±10V output, or a unipolar 0 to 10V output. Single 12V to 15V power supplies provide only a unipolar 0 to 10V output. The reference input accepts voltages from 2V to 5.25V. The DAC features INL and DNL less than ±1 LSB (max), a fast 10µs settling time, and a hardware-shutdown mode that reduces current consumption to 3.5µA (max). The device features a 10MHz SPI-/QSPI-/MICROWIRE-compatible serial interface that operates with 3V or 5V logic, an asynchronous load input, and a serial-data output. The device offers a CLR that sets the DAC output to 0V. Figure 1 shows the functional diagram of the MAX5312. Serial Interface An SPI-/QSPI-/MICROWIRE-compatible serial interface allows complete control of the DAC through a 16-bit control word. The first 4 bits form the control bits that determine register loading and software-shutdown functions. The last 12 bits form the DAC data. The 16bit word is entered MSB first. Table 1 shows the serial-data format. Table 2 shows the interface commands. The MAX5312 can be programmed while in shutdown. The serial interface contains three registers: a 16-bit shift register, a 12-bit input register, and a 12-bit DAC register (Figure 1). The shift register accepts data from the serial interface. The input register acts as a holding register for data going to the DAC register and isolates the shift register from the DAC register. The DAC register controls the DAC ladder and thus the output voltage. Any update in the DAC register updates the output voltage. 2R 2R VDD VCC SW2 A1 REF SW1 12-BIT DAC SW3 12 LDAC CLR A2 OUT 2R DAC REGISTER 2R 12 SGND INPUT REGISTER 12 DOUT 16-BIT SHIFT REGISTER DIN SCLK CS UNI/BIP SERIAL INTERFACE AND CONTROL MAX5312 AGND SHDN VSS DGND Figure 1. Functional Diagram ______________________________________________________________________________________ 13 MAX5312 Detailed Description MAX5312 ±10V, 12-Bit, Serial, Voltage-Output DAC DAC Architecture Data in the shift register is transferred to the input register during the appropriate software command only. Data in the input register is transferred to the DAC register in one of two ways: using the software command, or through external logic control using the asynchronous load input (LDAC). Table 2 shows the software commands that transfer the data from the shift register to the input and/or DAC registers. The CLR, an external logic control, asynchronously forces the input and DAC registers to zero code, and the output to 0V, in both unipolar and bipolar modes. The interface timing is shown in Figures 2 and 3. Wait a minimum of 100ns after CS goes high before implementing LDAC or CLR. If either of these logic inputs activates during a data transfer, the incoming data is corrupted and needs to be reloaded. For software control only, connect LDAC and CLR high. The MAX5312 uses an inverted DAC ladder architecture to convert the digital input into an analog output voltage. The digital input controls weighted-switches that connect the DAC ladder nodes to either REF or GND (Figure 4). The sum of the weights produces the analog equivalent of the digital-input word and is then buffered at the output. Table 1. Serial-Data Format CONTROL BITS DATA BITS MSB LSB C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 2. Serial-Interface Programming Commands CONTROL BITS* INPUT DATA FUNCTION C3 C2 C1 C0 D11–D0 0 0 0 0 XXXXXXXXXXXX No operation; command is ignored. 0 0 1 0 12-bit DAC data Load input register from shift register; DAC output unchanged. 0 1 0 0 12-bit DAC data Load input and DAC registers from shift register; DAC output updated. 0 1 1 0 XXXXXXXXXXXX Load DAC register from input register; DAC output updated; input register unchanged. 1 0 0 0 XXXXXXXXXXXX Enter shutdown; input and DAC registers unchanged. 1 1 0 0 XXXXXXXXXXXX Exit shutdown; input and DAC registers unchanged. X = Don’t care. *All unlisted commands are reserved commands. Do not use. COMMAND EXECUTED CS SCLK 1 DIN C3 8 C2 C1 C0 D11 D10 D9 D8 9 D7 16 D6 D5 D4 D3 D2 D1 D0 Figure 2. Serial-Interface Signals 14 ______________________________________________________________________________________ (1) ±10V, 12-Bit, Serial, Voltage-Output DAC MAX5312 tCSW CS tCSS tCS0 tCP tCSH tCS1 SCLK tCH tDS DIN tCL tDH LSB MSB tCSE tCSD tDO1 DOUT tLDS tLD LDAC Figure 3. Serial-Interface Timing Diagram 2R R 2R R MAX5312 R SW2 2R 2R 2R 2R 2R SW1 OUT D0 1 0 D1 1 0 D10 1 0 D11 1 SW3 2R 0 REF 2R AGND SGND DAC REGISTER UNI/BIP CONTROL LOGIC Figure 4. Basic Inverted DAC Ladder ______________________________________________________________________________________ 15 MAX5312 ±10V, 12-Bit, Serial, Voltage-Output DAC External Reference and Transfer Functions Connect an external 2V to 5.25V reference to REF (the MAX6350 is recommended). Set the output voltage range with the reference and the input code by using the equations below. Unipolar Output Voltage: VOUT _ UNI = LSBUNI × CODE where LSBUNI = 2 × VREF 212 Bipolar Output Voltage: VOUT _ BIP = (LSBBIP × CODE) − (2 × VREF ) where LSBBIP = 4 × VREF 212 where VOUT_UNI is the unipolar output voltage, VOUT_BIP is the bipolar output voltage, LSBUNI is the unipolar LSB step size, LSBBIP is the bipolar LSB step size, VREF is the reference voltage, and CODE is the decimal equivalent of the binary, 12-bit, DAC input code. In either case, a 000hex input code produces the minimum output (-2 x VREF for bipolar and 0 for unipolar), an 800hex input code produces the midscale output (0 for bipolar and VREF for unipolar), and a FFFhex input code produces the full-scale output (2 x VREF for bipolar and unipolar). Output Amplifiers The output-amplifier section can be configured as either unipolar or bipolar by the UNI/BIP logic input. With UNI/BIP forced low, SW1 and SW2 in Figure 4 are closed, and SW3 is open. This configuration channels the DAC output through two output stages to generate the ±2 x VREF output swing. The first amplifier generates the ±VREF voltage range and the second amplifier increases it by two. When configured for bipolar operation, the MAX5312 must be driven with dual ±12V to ±15V power supplies. With UNI/BIP forced high, switches SW1 and SW2 are open, and SW3 is closed. This configuration channels the DAC output through only a single gain stage to generate a 0 to (2 x VREF) output swing. Daisy Chaining SPI-/QSPI-/MICROWIRE-compatible devices can be daisy chained to reduce I/O lines from the host controller (Figure 7). Daisy chain devices by connecting the DOUT of one device to the DIN of the next, and connect the SCLK of all devices to a common clock. Data is shifted out of DOUT 16.5 clock cycles after it is shifted into DIN, and is available on the rising edge of the 17th clock cycle. The SPI-/QSPI-/MICROWIRE-compatible serial interface normally works at up to 10MHz, but must be slowed to 6.0MHz if daisy chaining. DOUT is high impedance when CS is high. Shutdown Shutdown is controlled by software commands or by the SHDN logic input. The SHDN logic input can be implemented at any time. The SPI-/QSPI-/MICROWIRE-compatible serial interface remains fully functional, and the device is programmable while shut down. When shut down, the MAX5312 supply current reduces to 3.5µA, DOUT is high impedance, and OUT is pulled to SGND through the internal feedback resistors of the output amplifier (Figure 1). When coming out of shutdown, or during device powerup, allow 350µs for the output to stabilize. Table 3. Output Voltage as Input Code Examples BINARY DAC CODE MSB 16 LSB ANALOG OUTPUT UNIPOLAR (UNI/BIP_ = HIGH) BIPOLAR (UNI/BIP_ = LOW) 1111 1111 1111 +2 x VREF (4095 / 4096) +2 x VREF (2047 / 2048) 1000 0000 0001 +2 x VREF (2049 / 4096) +2 x VREF (1 / 2048) 1000 0000 0000 +2 x VREF (2048 / 4096) = VREF 0 0111 1111 1111 +2 x VREF (2047 / 4096) -2 x VREF (1 / 2048) 0000 0000 0001 +2 x VREF (1 / 4096) -2 x VREF (2047 / 2048) 0000 0000 0000 0 -2 x VREF (2048 / 2048) = -2 x VREF ______________________________________________________________________________________ ±10V, 12-Bit, Serial, Voltage-Output DAC 4 x VREF 4096 +2047 +2046 +2045 +2044 +1 0 -1 3 2 1 -2045 0 -2048 4 x VREF 2 x VREF 2049 2048 2047 ANALOG OUTPUT VOLTAGE (LSB) 1 LSB = 4095 4094 4093 4092 -2046 hex DIGITAL INPUT CODE (LSB) Figure 5. Unipolar Transfer Function FFC FFD FFE FFF 801 800 7FF 000 001 002 003 FFC FFD FFE FFF 801 800 7FF -2047 000 001 002 003 ANALOG OUTPUT VOLTAGE (LSB) 2 x VREF 4096 MAX5312 1 LSB = hex DIGITAL INPUT CODE (LSB) Figure 6. Bipolar Transfer Function Applications Information Power-Supply Bypassing and Ground Management Power Supplies Bypass VDD and VSS with 0.1µF and 1.0µF capacitors to AGND, and bypass VCC with 0.1µF and 1.0µF capacitors to DGND. Minimize trace lengths to reduce inductance. Digital and AC transient signals on AGND or DGND can create noise at the output. Connect AGND and DGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a lowinductance ground plane or star connect all groundreturn paths back to AGND. Carefully lay out the traces between channels to reduce AC crosscoupling and crosstalk. Wire-wrapped boards, sockets, and breadboards are not recommended. A single +12V to +15V supply is required to realize a 0 to 10V output swing. A dual ±12V to ±15V supply is required to realize a ±10V output swing, and allows unipolar, 0 to +10V output if UNI/BIP is forced high. A +3V to +5V digital power supply and a +2.000V to +5.250V external reference voltage are also required. Always bring up the reference voltage last. The other power supplies do not require sequencing. ______________________________________________________________________________________ 17 MAX5312 ±10V, 12-Bit, Serial, Voltage-Output DAC SCLK CS CS CS CS TO OTHER SERIAL DEVICES MAX5312 MAX5312 SCLK DIN MAX5312 SCLK DOUT DIN DIN SCLK DOUT DIN DOUT Figure 7. Daisy Chaining Devices Chip Information TRANSISTOR COUNT: 3280 TECHNOLOGY: BiCMOS 18 ______________________________________________________________________________________ ±10V, 12-Bit, Serial, Voltage-Output DAC SSOP.EPS 2 1 INCHES E H MILLIMETERS DIM MIN MAX MIN MAX A 0.068 0.078 1.73 1.99 A1 0.002 0.008 0.05 0.21 B 0.010 0.015 0.25 0.38 C D 0.20 0.09 0.004 0.008 SEE VARIATIONS E 0.205 e 0.212 0.0256 BSC 5.20 MILLIMETERS INCHES D D D D D 5.38 MIN MAX MIN MAX 0.239 0.239 0.278 0.249 0.249 0.289 6.07 6.07 7.07 6.33 6.33 7.33 0.317 0.397 0.328 0.407 8.07 10.07 8.33 10.33 N 14L 16L 20L 24L 28L 0.65 BSC H 0.301 0.311 7.65 7.90 L 0.025 0∞ 0.037 8∞ 0.63 0∞ 0.95 8∞ N A C B e L A1 D NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, SSOP, 5.3 MM APPROVAL DOCUMENT CONTROL NO. 21-0056 REV. C 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX5312 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)