TI TMS320VC549PGE

2 SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Data Bus With a Bus Holder Feature
Address Bus With a Bus Holder Feature
Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space
192K × 16-Bit Maximum Addressable
Memory Space (64K Words Program,
64K Words Data, and 64K Words I/O)
On-Chip ROM with Some Configurable to
Program/Data Memory
Dual-Access On-Chip RAM
Single-Access On-Chip RAM
Single-Instruction Repeat and
Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for Better
Program and Data Management
Instructions With a 32-Bit Long Word
Operand
Instructions With Two- or Three-Operand
Reads
Arithmetic Instructions With Parallel Store
and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
– Software-Programmable Wait-State
Generator and Programmable Bank
Switching
– On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
– Time-Division Multiplexed (TDM) Serial
Port
– Buffered Serial Port (BSP)
– 8-Bit Parallel Host Port Interface (HPI)
– One 16-Bit Timer
– External-Input/Output (XIO) Off Control
to Disable the External Data Bus,
Address Bus and Control Signals
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1† (JTAG) Boundary Scan
Logic
12.5-ns Single-Cycle Fixed-Point
Instruction Execution Time (80 MIPS) for
3.3-V Power Supply)
10-ns Single-Cycle Fixed-Point Instruction
Execution Time (100 MIPS) for 3.3-V Power
Supply (2.5-V Core)
8.3-ns Single-Cycle Fixed-Point Instruction
Execution Time (120 MIPS) for 3.3-V Power
Supply (2.5-V Core) (Product Preview Data)
Available in a 144-Pin Plastic Thin Quad
Flatpack (TQFP) (PGE Suffix) and a 144-Pin
Ball Grid Array (BGA) (GGU Suffix)
NOTE: The data provided in this data sheet for the 8.3-ns, 120 MIPS device is considered to be
Product Preview data as the devices have not completed reliability performance qualification
testing according to TI Quality Systems Specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright  2000, Texas Instruments Incorporated
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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . 12
Recommended Operating Conditions . . . . . . . . . . . 12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 13
Parameter Measurement Information . . . . . . . . . . . . 14
Timing Parameter Symbology . . . . . . . . . . . . . . . . . . 14
Signal Transition Reference Points . . . . . . . . . . . . . . 14
Internal Oscillator With External Crystal . . . . . . . . . 15
Divide-By-Two/Divide-By-Four Clock Option . . . . . 16
Multiply-By-N Clock Option . . . . . . . . . . . . . . . . . . . . 18
Memory and Parallel I/O Interface Timing . . . . . . . .
Timing Requirements for a Parallel I/O Port Read .
SPICE Simulation Results . . . . . . . . . . . . . . . . . . . . .
Ready Timing for Externally Generated Wait States
HOLD and HOLDA Timing . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timings . . . . . . .
Serial Port Receive Timing . . . . . . . . . . . . . . . . . . . . .
Buffered Serial Port Receive Timing . . . . . . . . . . . . .
Serial-Port Receive Timing in TDM Mode . . . . . . . .
Host-Port Interface Timing . . . . . . . . . . . . . . . . . . . . .
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
26
28
31
36
38
42
45
49
53
59
description
The TMS320VC549 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’549) is based on
an advanced modified Harvard architecture that has one program memory bus and three data memory buses.
The processor also provides an arithmetic logic unit (ALU) that has a high degree of parallelism,
application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The ’549 also utilizes
a highly specialized instruction set, which is the basis of its operational flexibility and speed.
Separate program and data spaces allow simultaneous access to program instructions and data, providing the
high degree of parallelism. Two reads and one write operation can be performed in a single cycle. Instructions
with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be
transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic,
and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the ’549
includes the control mechanisms to manage interrupts, repeated operations, and function calls.
This data sheet contains the pin layouts, signal descriptions, and electrical specifications for the TMS320VC549
DSP. For additional information, see the TMS320C54x, TMS320LC54x, TMS320VC54x Fixed-Point Digital
Signal Processors data sheet (literature number SPRS039). The SPRS039 is considered a family functional
overview and should be used in conjunction with this data sheet.
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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
109
111
110
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
75
35
74
36
73
A18
A17
VSS
A16
D5
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
HD3
CLKOUT
VSS
HPIENA
CVDD
VSS
TMS
TCK
TRST
TDI
TDO
EMU1/OFF
EMU0
TOUT
HD2
TEST1
CLKMD3
CLKMD2
CLKMD1
VSS
DVDD
BDX1
BFSX1
VSS
BCLKR1
HCNTL0
VSS
BCLKR0
TCLKR
BFSR0
TFSR/TADD
BDR0
HCNTL1
TDR
BCLKX0
TCLKX
VSS
HINT
CVDD
BFSX0
TFSX/TFRM
HRDY
DVDD
VSS
HD0
BDX0
TDX
IACK
HBIL
NMI
INT0
INT1
INT2
INT3
CVDD
HD1
VSS
BCLKX1
VSS
72
76
34
71
77
33
70
78
32
69
79
31
68
80
30
67
81
29
66
82
28
65
83
27
64
84
26
63
85
25
62
86
24
61
87
23
60
88
22
59
89
21
58
90
20
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91
19
56
92
18
55
93
17
54
94
16
53
95
15
52
96
14
51
97
13
50
98
12
49
99
11
48
100
10
47
101
9
46
102
8
45
103
7
44
104
6
43
105
5
42
106
4
41
3
40
107
39
108
2
38
1
37
VSS
A22
VSS
DVDD
A10
HD7
A11
A12
A13
A14
A15
CVDD
HAS
VSS
VSS
CVDD
HCS
HR/W
READY
PS
DS
IS
R/W
MSTRB
IOSTRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
DVDD
VSS
BDR1
BFSR1
143
144
V SS
A21
CV DD
A9
A8
A7
A6
A5
A4
HD6
A3
A2
A1
A0
DVDD
HDS2
V SS
HDS1
V SS
CVDD
HD5
D15
D14
D13
HD4
D12
D11
D10
D9
D8
D7
D6
DVDD
VSS
A20
A19
PGE PACKAGE†‡
(TOP VIEW)
† NC = No connection
‡ DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU, and VSS is the ground for both the I/O pins and the
core CPU.
For the 144-pin TQFP, the letter B in front of CLKRn, FSRn, DRn, CLKXn, FSXn, and DXn pin names denotes
buffered serial port (BSP), where n = 0 or 1 port. The letter T in front of CLKR, FSR, DR, CLKX, FSX, and DX
pin names denotes time-division multiplexed (TDM) serial port.
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3
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
GGU PACKAGE
(BOTTOM VIEW)
13 12 11 10 9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
The pin assignments table to follow lists each signal quadrant and BGA ball pin number for the 144-pin BGA
package.
The ’549 signal descriptions table lists each terminal name, function, and operating mode(s).
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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
Pin Assignments for the 144-Pin GGU Package†
SIGNAL
QUADRANT 1
BGA BALL #
SIGNAL
QUADRANT 2
BGA BALL #
SIGNAL
QUADRANT 4
BGA BALL #
VSS
A22
A1
BFSX1
N13
B1
BDX1
M13
VSS
BCLKR1
N1
A19
A13
N2
A20
VSS
DVDD
C2
C1
DVDD
VSS
A12
L12
HCNTL0
M3
B11
L13
N3
K10
VSS
BCLKR0
VSS
DVDD
A10
D4
CLKMD1
K4
D6
D10
HD7
D3
A11
D2
CLKMD2
K11
TCLKR
L4
D7
C10
CLKMD3
K12
BFSR0
M4
D8
A12
D1
B10
TEST1
K13
TFSR/TADD
N4
D9
A10
A13
A14
E4
HD2
J10
BDR0
K5
D10
D9
E3
TOUT
J11
HCNTL1
L5
D11
C9
B9
BGA BALL #
SIGNAL
QUADRANT 3
A11
A15
E2
EMU0
J12
TDR
M5
D12
CVDD
E1
EMU1/OFF
J13
BCLKX0
N5
HD4
A9
HAS
F4
TDO
H10
TCLKX
K6
D13
D8
VSS
VSS
F3
TDI
H11
D14
C8
TRST
H12
VSS
HINT
L6
F2
M6
D15
B8
CVDD
F1
TCK
H13
CVDD
N6
HD5
A8
HCS
G2
TMS
G12
BFSX0
M7
CVDD
B7
HR/W
G1
G13
TFSX/TFRM
N7
G3
G11
HRDY
L7
VSS
HDS1
A7
READY
VSS
CVDD
PS
G4
HPIENA
G10
DVDD
K7
DS
H1
F13
N8
F12
VSS
HD0
VSS
HDS2
M8
DVDD
B6
F11
BDX0
L8
A0
C6
IS
H2
VSS
CLKOUT
R/W
H3
HD3
C7
D7
A6
MSTRB
H4
X1
F10
TDX
K8
A1
D6
IOSTRB
J1
X2/CLKIN
E13
IACK
N9
A2
A5
MSC
J2
RS
E12
HBIL
M9
A3
B5
XF
J3
D0
E11
NMI
L9
HD6
C5
HOLDA
J4
D1
E10
INT0
K9
A4
D5
A4
IAQ
K1
D2
D13
INT1
N10
A5
HOLD
K2
D3
D12
INT2
M10
A6
B4
BIO
K3
D4
D11
INT3
L10
A7
C4
MP/MC
L1
D5
C13
CVDD
N11
A8
A3
DVDD
L2
A16
C12
HD1
M11
A9
B3
VSS
BDR1
L3
VSS
A17
C11
CVDD
C3
B13
VSS
BCLKX1
L11
M1
N12
A21
A2
BFSR1
M2
A18
B12
VSS
M12
VSS
B2
† DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU, and VSS is the ground for both the I/O pins and the
core CPU.
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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
’549 Signal Descriptions
TERMINAL
NAME
TYPE†
DESCRIPTION
DATA SIGNALS
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
(MSB)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(MSB)
Parallel port address bus A22 (MSB) through A0 (LSB). The sixteen LSBs (A15–A0) are multiplexed to address
external data/program memory or I/O. A15–A0 are placed in the high-impedance state in the hold mode. A15–A0
also go into the high-impedance state when EMU1/OFF is low. The seven MSBs (A22 to A16) are used for
extended program memory addressing.
The address bus have a feature called bus holder that eliminates passive components and the power dissipation
associated with it. The bus holders keep the address bus at the previous logic level when the bus goes into a
high-impedance state. The bus holders on the address bus are always enabled.
O/Z
(LSB)
I/O/Z
Parallel port data bus D15 (MSB) through D0 (LSB). D15–D0 are multiplexed to transfer data between the core
CPU and external data/program memory or I/O devices. D15–D0 are placed in the high-impedance state when
not output or when RS or HOLD is asserted. D15–D0 also go into the high-impedance state when EMU1/OFF
is low.
The data bus has a feature called bus holder that eliminates passive components and the power dissipation
associated with it. The bus holders keep the data bus at the previous logic level when the bus goes into a
high-impedance state. These bus holders are enabled or disabled by the BH bit in the bank switching control
register (BSCR).
(LSB)
INITIALIZATION, INTERRUPT AND RESET OPERATIONS
IACK
O/Z
Interrupt acknowledge signal. IACK indicates the receipt of an interrupt and that the program counter is fetching
the interrupt vector location designated by A15–0. IACK also goes into the high-impedance state when
EMU1/OFF is low.
INT0
External user interrupt inputs. INT0–INT3 are prioritized and are maskable by the interrupt mask register and the
INT1
I
interrupt mode bit. INT0 –INT3 can be polled and reset by the interrupt flag register.
INT2
INT3
† I = Input, O = Output, Z = High impedance
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’549 Signal Descriptions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
INITIALIZATION, INTERRUPT AND RESET OPERATIONS (CONTINUED)
NMI
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When
NMI is activated, the processor traps to the appropriate vector location.
RS
I
Reset input. RS causes the DSP to terminate execution and forces the program counter to 0FF80h. When RS
is brought to a high level, execution begins at location 0FF80h of the program memory. RS affects various
registers and status bits.
MP/MC
I
Microprocessor/microcomputer mode-select pin. If active-low at reset (microcomputer mode), MP/MC causes
the internal program ROM to be mapped into the upper program memory space. In the microprocessor mode,
off-chip memory and its corresponding addresses (instead of internal program ROM) are accessed by the DSP.
CNT
I
I/O level select. With CMOS-compatible I/O interface levels, CNT is pulled to a high level.
BIO
I
Branch control input. A branch can be conditionally executed when BIO is active. If low, the processor executes
the conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC
instruction, and all other instructions sample BIO during the read phase of the pipeline.
XF
O/Z
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
by RSBX XF instruction or by loading the ST1 status register. XF is used for signaling other processors in
multiprocessor configurations or as a general-purpose output pin. XF goes into the high-impedance state when
OFF is low, and is set high at reset.
MULTIPROCESSING SIGNALS
MEMORY CONTROL SIGNALS
DS
PS
IS
O/Z
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for communicating
to a particular external space. Active period corresponds to valid address information. Placed into a
high-impedance state in hold mode. DS, PS, and IS also go into the high-impedance state when EMU1/OFF is
low.
MSTRB
O/Z
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data
or program memory. Placed in high-impedance state in hold mode. MSTRB also goes into the high-impedance
state when OFF is low.
I
Data-ready input. READY indicates that an external device is prepared for a bus transaction to be completed.
If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready-detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
R/W
O/Z
Read/write signal. R/W indicates transfer direction during communication to an external device and is normally
high (in read mode), unless asserted low when the DSP performs a write operation. Placed in the high-impedance
state in hold mode, R/W also goes into the high-impedance state when EMU1/OFF is low.
IOSTRB
O/Z
I/O strobe signal. IOSTRB is always high unless low level asserted to indicate an external bus access to an I/O
device. Placed in high-impedance state in hold mode. IOSTRB also goes into the high-impedance state when
EMU1/OFF is low.
I
Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged,
these lines go into high-impedance state.
O/Z
Hold acknowledge signal. HOLDA indicates to the external circuitry that the processor is in a hold state and that
the address, data, and control lines are in a high-impedance state, allowing them to be available to the external
circuitry. HOLDA also goes into the high-impedance state when EMU1/OFF is low.
O/Z
Microstate complete signal. Goes low on CLKOUT falling at the start of the first software wait state. Remains low
until one CLKOUT cycle before the last programmed software wait state. If connected to the READY line, MSC
forces one external wait state after the last internal wait state has been completed. MSC also goes into the
high-impedance state when EM1/OFF is low.
READY
HOLD
HOLDA
MSC
† I = Input, O = Output, Z = High impedance
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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
’549 Signal Descriptions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
MEMORY CONTROL SIGNALS (CONTINUED)
IAQ
O/Z
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address
bus and goes into the high-impedance state when EMU1/OFF is low.
OSCILLATOR/TIMER SIGNALS
CLKOUT
O/Z
Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle
is bounded by the falling edges of this signal. CLKOUT also goes into the high-impedance state when EMU1/OFF
is low.
CLKMD1
CLKMD2
CLKMD3
I
Clock mode external/internal input signals. CLKMD1, CLKMD2, and CLKMD3 allow you to select and configure
different clock modes, such as crystal, external clock, and various PLL factors. Refer to PLL section for a detailed
functional description of these pins.
X2/CLKIN
I
Input pin to internal oscillator from the crystal. If the internal (crystal) oscillator is not being used, a clock can
become input to the device using this pin. The internal machine cycle time is determined by the clock
operating-mode pins (CLKMD1, CLKMD2 and CLKMD3).
X1
O
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when EMU1/OFF is low.
O/Z
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT-cycle
wide. TOUT also goes into the high-impedance state when EMU1/OFF is low.
I
Receive clocks. External clock signal for clocking data from the data-receive (DR) pin into the buffered serial port
receive shift registers (RSRs). Must be present during buffered serial port transfers. If the buffered serial port is
not being used, BCLKR0 and BCLKR1 can be sampled as an input by way of IN0 bit of the SPC register.
I/O/Z
Transmit clock. Clock signal for clocking data from the serial port transmit shift register (XSR) to the data transmit
(DX) pin. BCLKX can be an input if MCM in the serial port control register is cleared to 0. It also can be driven
by the device at 1/(CLKDV + 1) where CLKDV range is 0–31 CLKOUT frequency when MCM is set to 1. If the
buffered serial port is not used, BCLKX can be sampled as an input by way of IN1 of the SPC register. BCLKX0
and BCLKX1 go into the high-impedance state when OFF is low.
TOUT
BUFFERED SERIAL PORT 0 AND BUFFERED SERIAL PORT 1 SIGNALS
BCLKR0
BCLKR1
BCLKX0
BCLKX1
BDR0
BDR1
I
BDX0
BDX1
O/Z
Buffered serial-port-transmit output. Serial data is transmitted from the XSR by way of BDX. BDX0 and BDX1 are
placed in the high-impedance state when not transmitting and when EMU1/OFF is low.
I
Frame synchronization pulse for receive input. The falling edge of the BFSR pulse initiates the data-receive
process, beginning the clocking of the RSR.
I/O/Z
Frame synchronization pulse for transmit input/output. The falling edge of the BFSX pulse initiates the
data-transmit process, beginning the clocking of the XSR. Following reset, the default operating condition of
BFSX is an input. BFSX0 and BFSX1 can be selected by software to be an output when TXM in the serial control
register is set to 1. This pin goes into the high-impedance state when EMU1/OFF is low.
BFSR0
BFSR1
BFSX0
BFSX1
Buffered serial-data-receive input. Serial data is received in the RSR by BDR0/BDR1.
SERIAL PORT 0 AND SERIAL PORT 1 SIGNALS
CLKR0
CLKR1
CLKX0
CLKX1
DR0
DR1
I
Receive clocks. External clock signal for clocking data from the data receive (DR) pin into the serial port receive
shift register (RSR). Must be present during serial port transfers. If the serial port is not being used, CLKR0 and
CLKR1 can be sampled as an input via IN0 bit of the SPC register.
I/O/Z
Transmit clock. Clock signal for clocking data from the serial port transmit shift register (XSR) to the data transmit
(DX) pin. CLKX can be an input if MCM in the serial port control register is cleared to 0. It also can be driven by
the device at 1/4 CLKOUT frequency when MCM is set to 1. If the serial port is not used, CLKX can be sampled
as an input via IN1 of the SPC register. CLKX0 and CLKX1 go into the high-impedance state when EMU1/OFF
is low.
I
Serial-data-receive input. Serial data is received in the RSR by DR.
† I = Input, O = Output, Z = High impedance
8
POST OFFICE BOX 1443
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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
’549 Signal Descriptions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
SERIAL PORT 0 AND SERIAL PORT 1 SIGNALS (CONTINUED)
DX0
DX1
FSR0
FSR1
FSX0
FSX1
O/Z
Serial port transmit output. Serial data is transmitted from the XSR via DX. DX0 and DX1 are placed in the
high-impedance state when not transmitting and when EMU1/OFF is low.
I
Frame synchronization pulse for receive input. The falling edge of the FSR pulse initiates the data-receive
process, beginning the clocking of the RSR.
I/O/Z
Frame synchronization pulse for transmit input/output. The falling edge of the FSX pulse initiates the data transmit
process, beginning the clocking of the XSR. Following reset, the default operating condition of FSX is an input.
FSX0 and FSX1 can be selected by software to be an output when TXM in the serial control register is set to 1.
This pin goes into the high-impedance state when EMU1/OFF is low.
TDM SERIAL PORT SIGNALS
TCLKR
I
TDM receive clock input
TDR
I
TDM serial data-receive input
TFSR/TADD
I/O
TDM receive frame synchronization or TDM address
TCLKX
I/O/Z
TDM transmit clock
TDX
O/Z
TDM serial data-transmit output
TFSX/TFRM
I/O/Z
TDM transmit frame synchronization
HOST PORT INTERFACE SIGNALS
HD0–HD7
I/O/Z
Parallel bidirectional data bus. HD0–HD7 are placed in the high-impedance state when not outputting data. The
signals go into the high-impedance state when EMU1/OFF is low. These pins each have bus holders similar to
those on the address/data bus, but which are always enabled.
HCNTL0
HCNTL1
I
Control inputs
HBIL
I
Byte-identification input
HCS
I
Chip-select input
HDS1
HDS2
I
Data strobe inputs
HAS
I
Address strobe input
HR/W
I
Read/write input
HRDY
O/Z
Ready output. This signal goes into the high-impedance state when EMU1/OFF is low.
HINT
O/Z
Interrupt output. When the DSP is in reset, this signal is driven high. The signal goes into the high-impedance
state when EMU1/OFF is low.
I
HPI module select input. This signal must be tied to a logic 1 state to have HPI selected. If this input is left open
or connected to ground, the HPI module will not be selected, internal pullup for the HPI input pins are enabled,
and the HPI data bus has keepers set. This input is provided with an internal pull-down resistor which is active
only when RS is low. HPIENA is sampled when RS goes high and ignored until RS goes low again. Refer to the
Electrical Characteristics section for the input current requirements for this pin.
HPIENA
SUPPLY PINS
CVDD
Supply
DVDD
Supply
+VDD. CVDD is the dedicated power supply for the core CPU.
+VDD. DVDD is the dedicated power supply for I/O pins.
VSS
Supply
Ground. VSS is the dedicated power ground for the device.
† I = Input, O = Output, Z = High impedance
POST OFFICE BOX 1443
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9
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
’549 Signal Descriptions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
IEEE1149.1 TEST PINS
TCK
I
IEEE standard 1149.1 test clock. Pin with internal pullup device. This is normally a free-running clock signal with
a 50% duty cycle. The changes on the test-access port (TAP) of input signals TMS and TDI are clocked into the
TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP
output signal (TDO) occur on the falling edge of TCK.
TDI
I
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDO
O/Z
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) is shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when EMU1/OFF is low.
TMS
I
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
TRST
I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and
the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
EMU0
I/O/Z
Emulator interrupt 0 pin. When TRST is driven low, EMU0 must be high for the activation of the EMU1/OFF
condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined
as input/output by way of IEEE standard 1149.1 scan system.
I/O/Z
Emulator interrupt 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or
from the emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When
TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output
drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not
for multiprocessing applications). Therefore, for the OFF condition, the following conditions apply:
TRST = low,
EMU0 = high
EMU1/OFF = low
EMU1/OFF
DEVICE TEST PIN
TEST1
I
Test1 – Reserved for internal use only. This pin must not be connected (NC).
† I = Input, O = Output, Z = High impedance
10
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage I/O range, DVDD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V
Supply voltage core range, CVDD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 3.75 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 100°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltage values are with respect to VSS.
recommended operating conditions
DVDD
Device supply voltage, I/O†
CVDD
Device supply voltage, core†
VSS
Supply voltage, GND
VIH
High
level input
in ut voltage, I/O
High-level
NOM
MAX
3
3.3
3.6
V
2.4
2.5
2.75
V
0
Schmitt trigger inputs, DVDD =
3.30.3 V‡
All other inputs
VIL
IOH
MIN
Low-level input voltage
V
2.5
DVDD + 0.3
2
DVDD + 0.3
–0.3
High-level output current
UNIT
V
0.8
V
–300
µA
IOL
Low-level output current
1.5
mA
TC
Operating case temperature
–40
100
°C
† Texas Instrument DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be
designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage.
Excessive exposure to these conditions can adversely affect the long term reliability of the devices. System-level concerns such as bus contention
may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and
powered down after), the I/O buffers. For additional power sequencing information, see the Power Supply Sequencing Solutions For Dual Supply
Voltage DSPs application report (literature number SLVA073).
‡ On the ’VC549 devices, the following pins have schmitt trigger inputs: RS, INTn, NMI, X2/CLKIN, CLKMDn, TCK, HAS, HCS, HDSn, BCLKRn,
TCLKR, BCLKXn, and TCLKX
Refer to Figure 1 for 3.3-V device test load circuit values.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
11
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
electrical characteristics over recommended operating case temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
VOH
High-level output voltage‡
VDD = 3.30.3 V, IOH = MAX
VOL
Low-level output voltage‡
In ut current in high
Input
impedance
A[22:0]
–150
250
IIZ
IOL = MAX
VDD = MAX
All other pins
VDD = MAX, VI = VSS to VDD
–10
10
TRST
With internal pulldown
–10
800
HPIENA
With internal pulldown, RS = 0
–10
400
TMS, TCK, TDI, HPI||
With internal pullups
–400
10
D[15:0], HD[7:0]
Bus holders enabled, VDD = MAX
–150
250
X2/CLKIN
Oscillator enabled
–40
40
II
In ut current
Input
((VI = VSS to VDD)
2.4
V
0.4
All other input-only pins
UNIT
–10
V
µA
µA
A
10
IDDC
Supply current, core CPU
CVDD = 2.5 V, fx = 40 MHz,§ TC = 25°C
20¶
mA
IDDP
Supply current, pins
DVDD = 3.3 V, fx = 40 MHz,§ TC = 25°C
12#
mA
2
mA
IDLE2
IDD
Ci
Supply current,
standby
IDLE3
PLL × 1 mode,
40 MHz input
Divide-by-two mode, CLKIN stopped
(’VC549-80 and ’VC549-100)
15
Divide-by-two mode, CLKIN stopped
(’VC549-120 only)
170
Input capacitance
µA
10
pF
Co
Output capacitance
10
pF
† All values are typical unless otherwise specified.
‡ All input and output voltage levels except RS, INT0–INT3, NMI, CNT, X2/CLKIN, CLKMD0–CLKMD3 are LVTTL-compatible.
§ Clock mode: PLL × 1 with external source
¶ This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being
executed.
# This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed,
refer to the Calculation of TMS320C54x Power Dissipation application report (literature number SPRA164).
|| HPI input signals except for HPIENA.
VIL(MIN) ≤ VI ≤ VIL(MAX) or VIH(MIN) ≤ VI ≤ VIH(MAX)
12
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100-A. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
dis
disable time
Z
High impedance
en
enable time
f
fall time
h
hold time
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
X
Unknown, changing, or don’t care level
signal transition reference points
All timing references are made at a voltage of 1.5 volts, except rise and fall times which are referenced at the
10% and 90% points of the specified low and high logic levels, respectively.
IOL
50 Ω
Tester Pin
Electronics
VLoad
CT
Output
Under
Test
IOH
Where: IOL
IOH
VLoad
CT
=
=
=
=
1.5 mA (all outputs)
300 µA (all outputs)
1.5 V
40 pF typical load circuit capacitance.
Figure 1. 3.3-V Test Load Circuit
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
13
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
internal oscillator with external crystal
The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is device dependent –
see PLL section) and connecting a crystal or ceramic resonator across X1 and X2/CLKIN. The CPU clock
frequency is one-half the crystal’s oscillation frequency following reset. After reset, the clock mode of the devices
with the software PLL can also be changed to divide-by-four.
The crystal should be in fundamental mode operation and parallel resonant with an effective series resistance
of 30ohms and power dissipation of 1 mW. The connection of the required circuit, consisting of the crystal and
two load capacitors, is shown in Figure 2. The load capacitors, C1 and C2, should be chosen such that the
equation below is satisfied. CL in the equation is the load specified for the crystal.
CL C 1C 2
( C 1 C 2)
recommended operating conditions (see Figure 2)
’549-80
MIN
10†
NOM
’549-100
MAX
20‡
MIN
10†
NOM
’549-120
MAX
20‡
MIN
10†
NOM
MAX
20‡
UNIT
fx
Input clock frequency
MHz
† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
‡ It is recommended that the PLL clocking option be used for maximum frequency operation.
X1
X2/CLKIN
Crystal
C1
C2
Figure 2. Internal Divide-by-Two Clock Option With External Crystal
14
POST OFFICE BOX 1443
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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
divide-by-two/divide-by-four clock option – PLL disabled
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four to
generate the internal machine cycle.
When an external clock source is used, the frequency injected must conform to specifications listed in the timing
requirements table.
switching characteristics over recommended operating conditions for divide-by-two/
divide-by-four clock option – PLL disabled [H = 0.5tc(CO)] (see Figure 2 and Figure 3, and the
recommended operating conditions table)
’549-80
PARAMETER
tc(CO)
Cycle time, CLKOUT
td(CIH-CO)
Delay time, X2/CLKIN high to
CLKOUT high/low
tf(CO)
tr(CO)
Fall time, CLKOUT†
Rise time, CLKOUT†
MIN
12.5‡
3
TYP
’549-100
2tc(CI)
MAX
†
MIN
10‡
6
10
3
TYP
’549-120
2tc(CI)
MAX
†
MIN
8.33‡
TYP
2tc(CI)
MAX
†
6
10
3
6
10
UNIT
ns
ns
2
2
2
ns
2
2
2
ns
tw(COL)
Pulse duration, CLKOUT low†
H–3
H–1
H
H–2
H–1
H
H–2
H–1
H
ns
tw(COH)
Pulse duration, CLKOUT high†
H–3
H–1
H
H–2
H–1
H
H–2
H–1
H
ns
† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
‡ It is recommended that the PLL clocking option be used for maximum frequency operation.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
15
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
divide-by-two/divide-by-four clock option – PLL disabled (continued)
timing requirements for divide-by-two/divide-by-four clock option – PLL disabled (see Figure 3)
’549-80
MIN
20‡
’549-100
MAX
†
MIN
20‡
’549-120
MAX
†
MIN
20‡
MAX
†
UNIT
tc(CI)
tf(CI)
Cycle time, X2/CLKIN
ns
Fall time, X2/CLKIN
8
8
8
ns
tr(CI)
tw(CIL)
Rise time, X2/CLKIN
8
†
8
†
8
†
ns
Pulse duration, X2/CLKIN low
5
5
5
ns
†
†
†
tw(CIH) Pulse duration, X2/CLKIN high
5
5
5
ns
† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
‡ It is recommended that the PLL clocking option be used for maximum frequency operation.
tr(CI)
tw(CIH)
tc(CI)
tf(CI)
X2/CLKIN
tw(CIL)
tc(CO)
tw(COH)
tf(CO)
tr(CO)
td(CIH-CO)
CLKOUT
Figure 3. External Divide-by-Two Clock Timing
16
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
tw(COL)
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
multiply-by-N clock option – PLL enabled
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate
the internal machine cycle.
When an external clock source is used, the frequency injected must conform to specifications listed in the timing
requirements table.
switching characteristics over recommended operating conditions for multiply-by-N clock option
– PLL enabled [H = 0.5tc(CO)] (see Figure 2 and Figure 4, and the recommended operating
conditions table)
’549-80
PARAMETER
MIN
tc(CO)
Cycle time, CLKOUT
td(CIH-CO)
Delay time, X2/CLKIN high/low to
CLKOUT high/low
TYP
’549-100
MAX
12.5 tc(CI)/N
3
6
10
MIN
TYP
10
tc(CI)/N
3
6
2
’549-120
MAX
10
MIN
TYP
8.33
tc(CI)/N
3
6
UNIT
ns
10
Fall time, CLKOUT
tw(COL)
tw(COH)
Pulse duration, CLKOUT low
H–3
H–1
H
H–2
H–1
H
H–2
H–1
H
ns
Pulse duration, CLKOUT high
H–3
H–1
H
H–2
H–1
H
H–2
H–1
H
ns
tp
Transitory phase, PLL lock-up time
45
s
2
POST OFFICE BOX 1443
2
ns
tf(CO)
tr(CO)
Rise time, CLKOUT
2
MAX
2
29
• HOUSTON, TEXAS 77251–1443
ns
2
35
ns
17
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
multiply-by-N clock option – PLL enabled (continued)
timing requirements for multiply-by-N clock option – PLL enabled (see Figure 4)
’549-100
’549-120
’549-80
Integer PLL multiplier N (N = 1–15)
tc(CI)
20†
20†
PLL multiplier N = x.5
Cycle time, X2/CLKIN
PLL multiplier N = x.25, x.75
tf(CI)
tr(CI)
MIN
20†
MAX
200
100
50
MAX
20†
20†
100
200
ns
50
Fall time, X2/CLKIN
8
8
ns
Rise time, X2/CLKIN
8
8
ns
tw(CIL) Pulse duration, X2/CLKIN low
tw(CIH) Pulse duration, X2/CLKIN high
† Note that for all values of tc(CI), the minimum tc(CO) period must not be exceeded.
tw(CIL)
tw(CIH)
tc(CI)
5
5
ns
5
5
ns
tr(CI)
tf(CI)
X2/CLKIN
td(CIH-CO)
tc(CO)
tw(COH)
CLKOUT
Unstable
Figure 4. External Multiply-by-One Clock Timing
POST OFFICE BOX 1443
tf(CO)
tw(COL)
tp
18
UNIT
MIN
20†
• HOUSTON, TEXAS 77251–1443
tr(CO)
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing
switching characteristics over recommended operating conditions for a memory read
(MSTRB = 0)†‡ (see Figure 5)
’549-80
PARAMETER
’549-100
’549-120
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
td(CLKL-A)
td(CLKH-A)
Delay time, address valid from CLKOUT low§
–1
5
–1
4
–1
4
ns
Delay time, address valid from CLKOUT high (transition)¶
–1
5
–1
4
–1
4
ns
td(CLKL-MSL)
td(CLKL-MSH)
Delay time, MSTRB low from CLKOUT low
–1
5
–1
4
–1
3
ns
Delay time, MSTRB high from CLKOUT low
Hold time, address valid after CLKOUT low§
–1
5
–1
5
–1
3
ns
5
–1
4
–1
4
ns
5
–1
4
–1
4
ns
th(CLKL-A)R
–1
th(CLKH-A)R
Hold time, address valid after CLKOUT high¶
–1
† Address, PS, and DS timings are all included in timings referenced as address.
‡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.
§ In the case of a memory read preceded by a memory read
¶ In the case of a memory read preceded by a memory write
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
19
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing (continued)
timing requirements for a memory read (MSTRB = 0) [H = 0.5 tc(CO)]†‡ (see Figure 5)
’549-80
MIN
’549-100
MAX
MIN
2H–9
MAX
’549-120
MIN
UNIT
ta(A)M
ta(MSTRBL)
Access time, read data access from address valid
tsu(D)R
th(D)R
Setup time, read data before CLKOUT low
5
5
5
ns
Hold time, read data after CLKOUT low
0
0
0
ns
th(A-D)R
Hold time, read data after address invalid
0
0
0
ns
0
0
ns
Access time, read data access from MSTRB low
2H–8
th(D)MSTRBH Hold time, read data after MSTRB high
0
† Address, PS, and DS timings are all included in timings referenced as address.
‡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.
20
POST OFFICE BOX 1443
2H–8
MAX
• HOUSTON, TEXAS 77251–1443
2H–7
2H–8
ns
2H–7
ns
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing (continued)
CLKOUT
td(CLKL-A)
th(CLKL-A)R
A[15:0]
th(A-D)R
tsu(D)R
ta(A)M
th(D)R
D[15:0]
th(D)MSTRBH
td(CLKL-MSL)
td(CLKL-MSH)
ta(MSTRBL)
MSTRB
R/W
PS, DS
Figure 5. Memory Read (MSTRB = 0)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a memory write
(MSTRB = 0) [H = 0.5 tc(CO)]†‡ (see Figure 6)
’549-80
PARAMETER
UNIT
MIN
MAX
MIN
MAX
Delay time, address valid from CLKOUT high§
Delay time, address valid from CLKOUT low¶
–1
5
–1
4
–1
4
ns
–1
5
–1
4
–1
4
ns
td(CLKL-MSL)
td(CLKL-D)W
Delay time, MSTRB low from CLKOUT low
–1
5
–1
4
–1
3
ns
0
7
0
7
0
5
ns
td(CLKL-MSH)
td(CLKH-RWL)
Delay time, MSTRB high from CLKOUT low
–1
5
–1
5
–1
3
ns
0
5
0
4
–1
4
ns
td(CLKH-RWH)
td(RWL-MSTRBL)
Delay time, R/W high from CLKOUT high
–1
5
–1
4
–1
4
ns
H–2
H+3
H–2
H+2
H–2
H+ 2
ns
th(A)W
Hold time, address valid after CLKOUT high§
–1
5
–1
4
–1
4
ns
H+3¶
ns
Delay time, data valid from CLKOUT low
Delay time, R/W low from CLKOUT high
Delay time, MSTRB low after R/W low
Hold time, write data valid after MSTRB high
Pulse duration, MSTRB low
H–4
MAX
’549-120
td(CLKH-A)
td(CLKL-A)
th(D)MSH
tw(SL)MS
MIN
’549-100
H+4¶
2H–5
tsu(A)W
Setup time, address valid before MSTRB low
2H–5
tsu(D)MSH
Setup time, write data valid before MSTRB high
2H–7
2H+7¶
† Address, PS, and DS timings are all included in timings referenced as address.
‡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.
§ In the case of a memory write preceded by a memory write.
¶ In the case of a memory write preceded by an I/O cycle.
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
H–3
H+3¶
2H–4
2H–4
2H–5
H–3
2H–4
ns
2H–4
2H+5¶
2H–4
UNIT
ns
2H+4¶
ns
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing (continued)
CLKOUT
td(CLKH-A)
td(CLKL-A)
th(A)W
A[15:0]
td(CLKL-D)W
th(D)MSH
tsu(D)MSH
D[15:0]
td(CLKL-MSL)
td(CLKL-MSH)
tsu(A)W
MSTRB
td(CLKH-RWL)
td(CLKH-RWH)
tw(SL)MS
td(RWL-MSTRBL)
R/W
PS, DS
Figure 6. Memory Write (MSTRB = 0)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a parallel I/O port read
(IOSTRB = 0)†‡ (see Figure 7)
’549-80
PARAMETER
td(CLKL-A)
td(CLKH-ISTRBL)
’549-120
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Delay time, address valid from CLKOUT low
–1
5
–1
4
–1
4
ns
Delay time, IOSTRB low from CLKOUT high
0
5
0
4
0
4
ns
5
–1
4
–1
4
ns
5
–1
4
–1
4
ns
td(CLKH-ISTRBH) Delay time, IOSTRB high from CLKOUT high
–1
th(A)IOR
Hold time, address after CLKOUT low
–1
† Address and IS timings are included in timings referenced as address.
‡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.
24
’549-100
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing (continued)
timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 tc(CO)]†‡ (see Figure 7)
’549-80
MIN
MAX
’549-100
MIN
MAX
’549-120
MIN
MAX
UNIT
ta(A)IO
ta(ISTRBL)IO
Access time, read data access from address valid
3H–9
3H–8
3H–8
ns
Access time, read data access from IOSTRB low
2H–9
2H–8
2H–7
ns
tsu(D)IOR
th(D)IOR
Setup time, read data before CLKOUT high
4
4
4
ns
Hold time, read data after CLKOUT high
0
0
0
ns
0
0
ns
th(ISTRBH-D)R
Hold time, read data after IOSTRB high
0
† Address and IS timings are included in timings referenced as address.
‡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.
CLKOUT
th(A)IOR
td(CLKL-A)
A[15:0]
tsu(D)IOR
ta(A)IO
th(D)IOR
D[15:0]
th(ISTRBH-D)R
td(CLKH-ISTRBH)
ta(ISTRBL)IO
td(CLKH-ISTRBL)
IOSTRB
R/W
IS
Figure 7. Parallel I/O Port Read (IOSTRB = 0)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
25
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a parallel I/O port write
(IOSTRB = 0) [H = 0.5 tc(CO)] (see Figure 8)†
’549-80
PARAMETER
’549-100
’549-120
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
–1
5
–1
4
–1
4
ns
0
5
0
4
0
4
ns
H–5
H+7
H–5
H+7
H–5
H+6
ns
–1
5
–1
4
–1
4
ns
td(CLKL-A)
td(CLKH-ISTRBL)
Delay time, address valid from CLKOUT low‡
td(CLKH-D)IOW
td(CLKH-ISTRBH)
Delay time, write data valid from CLKOUT high
td(CLKL-RWL)
td(CLKL-RWH)
Delay time, R/W low from CLKOUT low
0
5
0
4
0
4
ns
Delay time, R/W high from CLKOUT low
0
5
0
4
0
4
ns
th(A)IOW
Hold time, address valid from CLKOUT low‡
–1
5
–1
4
–1
4
ns
th(D)IOW
Hold time, write data after IOSTRB high
H–4
H+4
H–3
H+3
H–3
H+3
ns
tsu(D)IOSTRBH
Setup time, write data before IOSTRB high
H–5
H+1
H–5
H+1
H–5
H
ns
H+5
H–3
H+3
H–3
H+3
ns
Delay time, IOSTRB low from CLKOUT high
Delay time, IOSTRB high from CLKOUT high
tsu(A)IOSTRBL
Setup time, address valid before IOSTRB low
H–5
† See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.
‡ Address and IS timings are included in timings referenced as address.
26
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing (continued)
CLKOUT
tsu(A)IOSTRBL
td(CLKL-A)
th(A)IOW
A[15:0]
td(CLKH-D)IOW
th(D)IOW
D[15:0]
td(CLKH-ISTRBL)
td(CLKH-ISTRBH)
tsu(D)IOSTRBH
IOSTRB
td(CLKL-RWH)
td(CLKL-RWL)
R/W
IS
Figure 8. Parallel I/O Port Write (IOSTRB = 0)
I/O timing variation with load capacitance: SPICE simulation results
Condition: Temperature
Capacitance
Voltage
Model
: 125° C
: 0–100pF
: 2.7/3.0/3.3 V
: Weak/Nominal/Strong
90%
10%
Figure 9. Rise and Fall Time Diagram
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
27
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
I/O timing variation with load capacitance: SPICE simulation results (continued)
Table 1. Timing Variation With Load Capacitance: [2.7 V] 10% – 90%
WEAK
NOMINAL
STRONG
RISE
FALL
RISE
FALL
RISE
FALL
0 pF
0.476 ns
0.457 ns
0.429 ns
0.391 ns
0.382 ns
0.323 ns
10 pF
1.511 ns
1.278 ns
1.386 ns
1.148 ns
1.215 ns
1.049 ns
20 pF
2.551 ns
2.133 ns
2.350 ns
1.956 ns
2.074 ns
1.779 ns
30 pF
3.614 ns
3.011 ns
3.327 ns
2.762 ns
2.929 ns
2.512 ns
40 pF
4.664 ns
3.899 ns
4.394 ns
3.566 ns
3.798 ns
3.264 ns
50 pF
5.752 ns
4.786 ns
5.273 ns
4.395 ns
4.655 ns
4.010 ns
60 pF
6.789 ns
5.656 ns
6.273 ns
5.206 ns
5.515 ns
4.750 ns
70 pF
7.817 ns
6.598 ns
7.241 ns
6.000 ns
6.442 ns
5.487 ns
80 pF
8.897 ns
7.531 ns
8.278 ns
6.928 ns
7.262 ns
6.317 ns
90 pF
10.021 ns
8.332 ns
9.152 ns
7.735 ns
8.130 ns
7.066 ns
100 pF
11.072 ns
9.299 ns
10.208 ns
8.537 ns
8.997 ns
7.754 ns
Table 2. Timing Variation With Load Capacitance: [3 V] 10% – 90%
WEAK
28
NOMINAL
STRONG
RISE
FALL
RISE
FALL
RISE
FALL
0 pF
0.436 ns
0.387 ns
0.398 ns
0.350 ns
0.345 ns
0.290 ns
10 pF
1.349 ns
1.185 ns
1.240 ns
1.064 ns
1.092 ns
0.964 ns
20 pF
2.273 ns
1.966 ns
2.098 ns
1.794 ns
1.861 ns
1.634 ns
30 pF
3.226 ns
2.765 ns
2.974 ns
2.539 ns
2.637 ns
2.324 ns
40 pF
4.168 ns
3.573 ns
3.849 ns
3.292 ns
3.406 ns
3.013 ns
50 pF
5.110 ns
4.377 ns
4.732 ns
4.052 ns
4.194 ns
3.710 ns
60 pF
6.033 ns
5.230 ns
5.660 ns
4.811 ns
5.005 ns
4.401 ns
70 pF
7.077 ns
5.997 ns
6.524 ns
5.601 ns
5.746 ns
5.117 ns
80 pF
8.020 ns
6.899 ns
7.416 ns
6.336 ns
6.559 ns
5.861 ns
90 pF
8.917 ns
7.709 ns
8.218 ns
7.124 ns
7.323 ns
6.498 ns
100 pF
9.885 ns
8.541 ns
9.141 ns
7.830 ns
8.101 ns
7.238 ns
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
I/O timing variation with load capacitance: SPICE simulation results (continued)
Table 3. Timing Variation With Load Capacitance: [3.3 V] 10% – 90% [3 V] 10% – 90%
WEAK
NOMINAL
STRONG
RISE
FALL
RISE
FALL
RISE
FALL
0 pF
0.404 ns
0.361 ns
0.371 ns
0.310 ns
0.321 ns
0.284 ns
10 pF
1.227 ns
1.081 ns
1.133 ns
1.001 ns
1.000 ns
0.892 ns
20 pF
2.070 ns
1.822 ns
1.915 ns
1.675 ns
1.704 ns
1.530 ns
30 pF
2.931 ns
2.567 ns
2.719 ns
2.367 ns
2.414 ns
2.169 ns
40 pF
3.777 ns
3.322 ns
3.515 ns
3.072 ns
3.120 ns
2.823 ns
50 pF
4.646 ns
4.091 ns
4.319 ns
3.779 ns
3.842 ns
3.466 ns
60 pF
5.487 ns
4.859 ns
5.145 ns
4.503 ns
4.571 ns
4.142 ns
70 pF
6.405 ns
5.608 ns
5.980 ns
5.234 ns
5.301 ns
4.767 ns
80 pF
7.284 ns
6.463 ns
6.723 ns
5.873 ns
5.941 ns
5.446 ns
90 pF
8.159 ns
7.097 ns
7.560 ns
6.692 ns
6.740 ns
6.146 ns
100 pF
8.994 ns
7.935 ns
8.300 ns
7.307 ns
7.431 ns
6.822 ns
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
29
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
ready timing for externally generated wait states
timing requirements for externally generated wait states [H = 0.5 tc(CO)]† (see Figure 10, Figure 11,
Figure 12, and Figure 13)
’549-80
MIN
tsu(RDY)
th(RDY)
tv(RDY)MSTRB
th(RDY)MSTRB
tv(RDY)IOSTRB
th(RDY)IOSTRB
MAX
’549-100
MIN
MAX
’549-120
MIN
MAX
UNIT
Setup time, READY before CLKOUT low
6
5
5
ns
Hold time, READY after CLKOUT low
Valid time, READY after MSTRB low‡
0
0
0
ns
Hold time, READY after MSTRB low‡
Valid time, READY after IOSTRB low‡
4H
Hold time, READY after IOSTRB low‡
5H
4H–10
4H–8
4H
5H–10
4H–8
4H
5H–8
5H
ns
5H–8
5H
ns
ns
ns
tv(MSCL)
Valid time, MSC low after CLKOUT low
0
5
0
4
0
4
ns
tv(MSCH)
Valid time, MSC high after CLKOUT low
0
5
0
4
0
4
ns
† The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by
READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
30
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
ready timing for externally generated wait states (continued)
CLKOUT
A[15:0]
tsu(RDY)
th(RDY)
READY
tv(RDY)MSTRB
th(RDY)MSTRB
MSTRB
tv(MSCH)
tv(MSCL)
MSC
Wait States
Generated Internally
Wait State
Generated
by READY
Figure 10. Memory Read With Externally Generated Wait States
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
31
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
ready timing for externally generated wait states (continued)
CLKOUT
A[15:0]
D[15:0]
th(RDY)
tsu(RDY)
READY
tv(RDY)MSTRB
th(RDY)MSTRB
MSTRB
tv(MSCH)
tv(MSCL)
MSC
Wait States
Generated Internally
Wait State Generated
by READY
Figure 11. Memory Write With Externally Generated Wait States
32
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
ready timing for externally generated wait states (continued)
CLKOUT
A[15:0]
th(RDY)
tsu(RDY)
READY
tv(RDY)IOSTRB
th(RDY)IOSTRB
IOSTRB
tv(MSCH)
tv(MSCL)
MSC
Wait
States
Generated
Internally
Wait State Generated
by READY
Figure 12. I/O Read With Externally Generated Wait States
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
33
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
ready timing for externally generated wait states (continued)
CLKOUT
A[15:0]
D[15:0]
th(RDY)
tsu(RDY)
READY
tv(RDY)IOSTRB
th(RDY)IOSTRB
IOSTRB
tv(MSCH)
tv(MSCL)
MSC
Wait States
Generated
Internally
Figure 13. I/O Write With Externally Generated Wait States
34
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Wait State Generated
by READY
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
HOLD and HOLDA timing
switching characteristics over recommended operating conditions for memory control signals
and HOLDA [H = 0.5 tc(CO)] (see Figure 14)
’549-80
’549-100
’549-120
PARAMETER
MIN
tdis(CLKL-A)
tdis(CLKL-RW)
tdis(CLKL-S)
UNIT
MAX
Disable time, CLKOUT low to address, PS, DS, IS high impedance
5
ns
Disable time, CLKOUT low to R/W high impedance
5
ns
Disable time, CLKOUT low to MSTRB, IOSTRB high
impedance
5
ns
ten(CLKL-A)
ten(CLKL-RW)
Enable time, CLKOUT low to address, PS, DS, IS
2H+5
ns
Enable time, CLKOUT low to R/W enabled
2H+5
ns
ten(CLKL-S)
Enable time, CLKOUT low to MSTRB, IOSTRB enabled
2
2H+5
ns
Valid time, HOLDA low after CLKOUT low
0
5
ns
Valid time, HOLDA high after CLKOUT low
0
5
ns
tv(HOLDA)
tw(HOLDA)
Pulse duration, HOLDA low duration
2H–3
ns
timing requirements for HOLD [H = 0.5 tc(CO)] (see Figure 14)
’549-80
’549-100
’549-120
MIN
tw(HOLD)
tsu(HOLD)
Pulse duration, HOLD low duration
Setup time, HOLD before CLKOUT low
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
UNIT
MAX
4H+10
ns
10
ns
35
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
HOLD and HOLDA timing (continued)
CLKOUT
tsu(HOLD)
tsu(HOLD)
tw(HOLD)
HOLD
tv(HOLDA)
tv(HOLDA)
tw(HOLDA)
HOLDA
tdis(CLKL-A)
ten(CLKL-A)
A[15:0]
PS, DS, IS
D[15:0]
tdis(CLKL-RW)
ten(CLKL-RW)
tdis(CLKL-S)
ten(CLKL-S)
tdis(CLKL-S)
ten(CLKL-S)
R/W
MSTRB
IOSTRB
Figure 14. HOLD and HOLDA Timing (HM = 1)
36
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
reset, BIO, interrupt, and MP/MC timings
timing requirements over recommended operating conditions for reset, interrupt, BIO, and MP/MC
[H = 0.5 tc(CO)] (see Figure 15, Figure 16, and Figure 17) (continued)
’549-80
MIN
’549-100
MAX
MIN
’549-120
MAX
MIN
MAX
UNIT
th(RS)
th(BIO)
Hold time, RS after CLKOUT low
0
0
0
ns
Hold time, BIO after CLKOUT low
0
0
0
ns
th(INT)
th(MPMC)
Hold time, INTn, NMI, after CLKOUT low†
0
0
0
ns
0
ns
tw(RSL)
tw(BIO)S
Hold time, MP/MC after CLKOUT low
Pulse duration, RS lowद
4H+7
0
4H+5
4H+5
ns
Pulse duration, BIO low, synchronous
2H+7
2H+5
2H+5
ns
tw(BIO)A
tw(INTH)S
Pulse duration, BIO low, asynchronous
tw(INTH)A
tw(INTL)S
Pulse duration, INTn, NMI high (asynchronous)
tw(INTL)A
tw(INTL)WKP
Pulse duration, INTn, NMI low (asynchronous)
4H
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
Setup time, RS before X2/CLKIN low§
Setup time, BIO before CLKOUT low
10
tsu(RS)
tsu(BIO)
0
4H
Pulse duration, INTn, NMI high (synchronous)
4H
4H
ns
2H+7
2H+7
ns
4H
4H
ns
2H+7
2H+7
ns
4H
4H
ns
10
8
8
ns
5
5
5
2H+7
4H
Pulse duration, INTn, NMI low (synchronous)
2H+7
2H
9
2H
8
ns
2H
ns
tsu(INT)
Setup time, INTn, NMI, RS before CLKOUT low
10
2H
9
2H
8
2H
ns
tsu(MPMC)
Setup time, MP/MC before CLKOUT low
10
8
8
ns
† The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two flip-flop synchronizer which samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1–0–0 sequence at the timing that is
corresponding to three CLKOUTs sampling sequence.
‡ If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to assure synchronization
and lock-in of the PLL.
§ Divide-by-two mode
¶ Note that RS may cause a change in clock frequency, therefore changing the value of H (see the PLL section).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
37
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
reset, BIO, interrupt, and MP/MC timings (continued)
X2/CLKIN
tsu(RS)
tw(RSL)
RS, INTn, NMI
tsu(INT)
th(RS)
CLKOUT
tsu(BIO)
th(BIO)
BIO
tw(BIO)S
Figure 15. Reset and BIO Timings
CLKOUT
tsu(INT)
tsu(INT)
th(INT)
INTn, NMI
tw(INTH)A
tw(INTL)A
Figure 16. Interrupt Timing
CLKOUT
RS
th(MPMC)
tsu(MPMC)
MP/MC
Figure 17. MP/MC Timing
38
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timing
switching characteristics over recommended operating conditions for IAQ and IACK
[H = 0.5 tc(CO)] (see Figure 18)
PARAMETER
’549-80
’549-100
’549-120
MIN
MAX
MIN
MAX
UNIT
td(CLKL-IAQL)
td(CLKL-IAQH)
Delay time, IAQ low from CLKOUT low
–1
5
–1
4
ns
Delay time, IAQ high from CLKOUT low
–1
5
–1
4
ns
td(A)IAQ
td(CLKL-IACKL)
Delay time, address valid before IAQ low
4
ns
Delay time, IACK low from CLKOUT low
0
5
0
4
ns
td(CLKL-IACKH)
td(A)IACK
Delay time , IACK high from CLKOUT low
0
5
0
4
ns
3
ns
th(A)IAQ
th(A)IACK
Hold time, address valid after IAQ high
tw(IAQL)
tw(IACKL)
Pulse duration, IAQ low
Pulse duration, IACK low
2H–3
4
Delay time, address valid before IACK low
3
–3
Hold time, address valid after IACK high
–3
ns
–3
–3
ns
2H–3
2H–3
ns
2H–3
ns
CLKOUT
A[15:0]
td(CLKL-IAQH)
td(CLKL-IAQL)
th(A)IAQ
td(A)IAQ
tw(IAQL)
IAQ
td(CLKL-IACKL)
td(CLKL-IACKH)
th(A)IACK
td(A)IACK
tw(IACKL)
IACK
MSTRB
Figure 18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
39
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timing
(continued)
switching characteristics over recommended operating conditions for external flag (XF) and TOUT
[H = 0.5 tc(CO)] (see Figure 19 and Figure 20)
’549-80
’549-100
PARAMETER
td(XF)
’549-120
UNIT
MIN
MAX
MIN
MAX
Delay time, XF high after CLKOUT low
0
5
0
4
Delay time, XF low after CLKOUT low
0
5
0
4
ns
td(TOUTH)
td(TOUTL)
Delay time, TOUT high after CLKOUT low
0
5
–1
4
ns
Delay time, TOUT low after CLKOUT low
–1
5
–1
4
ns
tw(TOUT)
Pulse duration, TOUT
2H–3
CLKOUT
td(XF)
XF
Figure 19. External Flag (XF) Timing
CLKOUT
td(TOUTH)
td(TOUTL)
TOUT
tw(TOUT)
Figure 20. TOUT Timing
40
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
2H–3
ns
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
serial port receive timing
timing requirements over recommended operating conditions for serial port receive [H = 0.5 tc(CO)]
(see Figure 21)
’549-80
’549-100
’549-120
UNIT
MIN
MAX
6H
†
ns
Fall time, serial port clock
6
ns
Rise time, serial port clock
6
ns
tc(SCK)
tf(SCK)
Cycle time, serial port clock
tr(SCK)
tw(SCK)
3H
ns
tsu(FSR)
th(FSR)
Setup time, FSR before CLKR falling edge
4
ns
Hold time, FSR after CLKR falling edge
4
ns
th(DR)
Hold time, DR after CLKR falling edge
6
ns
Pulse duration, serial port clock low/high
tsu(DR)
Setup time, DR before CLKR falling edge
6
ns
† The serial port design is fully static and, therefore, can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
tc(SCK)
tf(SCK)
tw(SCK)
CLKR
th(FSR)
tw(SCK)
tr(SCK)
tsu(FSR)
tsu(DR)
FSR
th(DR)
DR
BIT
1
2
7/15
8/16
Figure 21. Serial Port Receive Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
41
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
serial port transmit timing
switching characteristics over recommended operating conditions for serial port transmit with
external clocks and frames [H = 0.5tc(CO)] (see Figure 22)
’549-80
’549-100
’549-120
PARAMETER
MIN
td(DX)
th(DX)
Delay time, DX valid after CLKX rising
tdis(DX)
Disable time, DX after CLKX rising
UNIT
MAX
25
Hold time, DX valid after CLKX rising
–5
ns
ns
40
ns
timing requirements over recommended operating conditions for serial port transmit with external
clocks and frames [H = 0.5tc(CO)] (see Figure 22)
’549-80
’549-100
’549-120
MIN
tc(SCK)
th(FSX)
Cycle time, serial port clock
6H
Hold time, FSX after CLKX falling edge (see Note 1)
UNIT
MAX
†
6
ns
ns
2H–3‡
ns
2H–3
ns
th(FSX)H
td(FSX)
Hold time, FSX after CLKX rising edge (see Note 1)
tf(SCK)
tr(SCK)
Fall time, serial port clock
6
ns
Rise time, serial port clock
6
ns
Delay time, FSX after CLKX rising edge
tw(SCK)
Pulse duration, serial port clock low/high
3H
ns
† The serial port design is fully static and, therefore, can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
‡ If the FSX pulse does not meet this specification, the first bit of serial data is driven on DX until the falling edge of FSX. After the falling edge of
FSX, data is shifted out on DX pin. The transmit buffer-empty interrupt is generated when the th(FSX) and th(FSX)H specification is met.
NOTE 1: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending on
the source of FSX, and CLKX timings always are dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX
is independent of the source of CLKX.
tc(SCK)
tf(SCK)
tw(SCK)
CLKX
td(FSX)
th(FSX)H
tw(SCK)
th(FSX)
tr(SCK)
FSX
td(DX)
tdis(DX)
th(DX)
DX BIT
1
2
7/15
Figure 22. Serial Port Transmit Timing With External Clocks and Frames
42
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
8/16
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
serial port transmit timing (continued)
switching characteristics over recommended operating conditions for serial port transmit with
internal clocks and frames [H = 0.5tc(CO)] (see Figure 23)
’549-80
’549-100
’549-120
PARAMETER
MIN
TYP
UNIT
MAX
tc(SCK)
td(FSX)
Cycle time, serial port clock
8H
Delay time, CLKX rising to FSX
7
ns
td(DX)
tdis(DX)
Delay time, CLKX rising to DX
7
ns
20
ns
th(DX)
tf(SCK)
Hold time, DX valid after CLKX rising edge
tr(SCK)
tw(SCK)
Rise time, serial port clock
Disable time, CLKX rising to DX
ns
–2
Fall time, serial port clock
Pulse duration, serial port clock low/high
4H–4
ns
3
ns
3
ns
ns
tc(SCK)
tf(SCK)
tw(SCK)
CLKX
td(FSX)
tw(SCK)
tr(SCK)
td(FSX)
td(DX)
FSX
tdis(DX)
th(DX)
DX
1
2
7/15
8/16
Figure 23. Serial Port Transmit Timing With Internal Clocks and Frames
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
43
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
buffered serial port receive timing
timing requirements over recommended operating conditions (see Figure 24)
’549-80
’549-100
’549-120
MIN
20
UNIT
MAX
†
ns
tc(SCK)
tf(SCK)
Cycle time, serial port clock
Fall time, serial port clock
4
ns
tr(SCK)
tw(SCK)
Rise time, serial port clock
4
ns
Pulse duration, serial port clock low/high
6
tsu(BFSR)
th(BFSR)
Setup time, BFSR before BCLKR falling edge (see Note 2)
2
Hold time, BFSR after BCLKR falling edge (see Note 2)
7
ns
ns
tc(SCK)–2‡
ns
tsu(BDR)
Setup time, BDR before BCLKR falling edge
0
ns
th(BDR)
Hold time, BDR after BCLKR falling edge
7
ns
† The serial port design is fully static and therefore can operate with tc(SCK) approaching infinity. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
‡ First bit is read when BFSR is sampled low by BCLKR clock.
NOTE 2: Timings for BCLKR and BFSR are given with polarity bits (BCLKP and BFSP) set to 0.
tc(SCK)
tw(SCK)
tf(SCK)
BCLKR
th(BFSR)
tr(SCK)
tw(SCK)
tsu(BFSR)
tsu(BDR)
BFSR
th(BDR)
BDR
1
2
8/10/12/16
Figure 24. Buffered Serial Port Receive Timing
44
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
buffered serial port transmit timing of external frames
switching characteristics over recommended operating conditions (see Figure 25)
’549-80
’549-100
’549-120
PARAMETER
MIN
UNIT
MAX
td(BDX)
tdis(BDX)
Delay time, BDX valid after BCLKX rising
tdis(BDX)pcm
ten(BDX)pcm
Disable time, PCM mode, BDX after BCLKX rising
Enable time, PCM mode, BDX after BCLKX rising
8
ns
th(BDX)
Hold time, BDX valid after BCLKX rising
2
ns
Disable time, BDX after BCLKX rising
4
18
ns
6
ns
6
ns
timing requirements over recommended operating conditions (see Figure 25)
’549-80
’549-100
’549-120
MIN
tc(SCK)
tf(SCK)
Cycle time, serial port clock
tr(SCK)
tw(SCK)
Rise time, serial port clock
20
Fall time, serial port clock
Pulse duration, serial port clock low/high
UNIT
MAX
†
ns
4
ns
4
ns
ns
th(BFSX)
Hold time, BFSX after CLKX falling edge (see Notes 3 and 4)
6 tc(SCK)–6‡
ns
tsu(BFSX)
Setup time, FSX before CLKX falling edge (see Notes 3 and 4)
6
ns
† The serial port design is fully static and therefore can operate with tc(SCK) approaching infinity. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
‡ If BFSX does not meet this specification, the first bit of the serial data is driven on BDX until BFSX goes low (sampled on falling edge of BCLKX).
After falling edge of the BFSX, data will be shifted out on the BDX pin.
NOTES: 3. Internal clock with external BFSX and vice versa are also allowable. However, BFSX timings to BCLKX always are defined
depending on the source of BFSX, and BCLKX timings always are dependent upon the source of BCLKX.
4. Timings for BCLKX and BFSX are given with polarity bits (BCLKP and BFSP) set to 0.
POST OFFICE BOX 1443
6
• HOUSTON, TEXAS 77251–1443
45
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
buffered serial port transmit timing of external frames (continued)
tc(SCK)
tw(SCK)
tf(SCK)
BCLKX
tr(SCK)
th(BFSX)
tw(SCK)
tsu(BFSX)
BFSX
th(BDX)
td(BDX)
tdis(BDX)
BDX
1
2
8/10/12/16
Figure 25. Buffered Serial Port Transmit Timing of External Clocks and External Frames
46
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
buffered serial port transmit timing of internal frame and internal clock
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 26)
’549-80
’549-100
’549-120
PARAMETER
UNIT
MIN
MAX
20
tc(SCK)
Cycle time, serial port clock, internal clock
62H
ns
td(BFSX)
Delay time, BFSX after BCLKX rising edge
(see Notes 3 and 4)
7
ns
td(BDX)
tdis(BDX)
Delay time, BDX valid after BCLKX rising edge
7
ns
5
ns
tdis(BDX)pcm
ten(BDX)pcm
Disable time, PCM mode, BDX after BCLKX rising edge
5
ns
Enable time, PCM mode, BDX after BCLKX rising edge
7
th(BDX)
tf(SCK)
Hold time, BDX valid after BCLKX rising edge
0
tr(SCK)
tw(SCK)
Rise time, serial port clock
Disable time, BDX after BCLKX rising edge
0
Fall time, serial port clock
Pulse duration, serial port clock low/high
ns
ns
3.5
ns
3.5
ns
6
ns
NOTES: 3. Internal clock with external BFSX and vice versa are also allowable. However, BFSX timings to BCLKX always are defined
depending on the source of BFSX, and BCLKX timings always are dependent upon the source of BCLKX.
4. Timings for BCLKX and BFSX are given with polarity bits (BCLKP and BFSP) set to 0.
tc(SCK)
tw(SCK)
tf(SCK)
BCLKX
tr(SCK)
td(BFSX)
tw(SCK)
td(BFSX)
BFSX
th(BDX)
td(BDX)
tdis(BDX)
BDX
1
2
8/10/12/16
Figure 26. Buffered Serial Port Transmit Timing of Internal Clocks and Internal Frames
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
47
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
serial-port receive timing in TDM mode
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5tc(CO)] (see Figure 27)
’549-80
’549-100
’549-120
MIN
UNIT
MAX
†
ns
Fall time, serial-port clock
6
ns
Rise time, serial-port clock
6
ns
tc(SCK)
tf(SCK)
Cycle time, serial-port clock
16H
tr(SCK)
tw(SCK)
Pulse duration, serial-port clock low/high
8H
ns
tsu(TD-TCH)
th(TCH-TD)
Setup time, TDAT/TADD before TCLK rising edge
10
ns
1
ns
Hold time, TDAT/TADD after TCLK rising edge
tsu(TF-TCH)
Setup time, TFRM before TCLK rising edge‡
10
ns
th(TCH-TF)
Hold time, TFRM after TCLK rising edge‡
10
ns
† The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching infinity. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
‡ TFRM timing and waveforms shown in Figure 27 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 28.
48
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
serial-port receive timing in TDM mode (continued)
tw(SCK)
tf(SCK)
tw(SCK)
TCLK
tc(SCK)
B0
tr(SCK)
tsu(TD-TCH)†
th(TCL-TD)‡
TDAT
tsu(TD-TCL)‡
tsu(TD-TCL)‡
th(TCL-TD)‡
th(TCH-TD)
B15
B14
B13
B12
B11
A0
A1
A2
A3
A4
B2
B1
B0
tsu(TF-TCH)
TADD
A7
th(TCH-TF)
TFRM
† All devices except ’542/’543
‡ ’542/’543 only
Figure 27. Serial-Port Receive Timing in TDM Mode
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
49
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
serial-port transmit timing in TDM mode
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 28)
’549-80
549-100
’549-120
PARAMETER
MIN
th(TCH-TDV)
th(TCH-TDV)
td(TCH-TFV)
td(TC-TDV)
d(TC TDV)
UNIT
MAX
Hold time, TDAT/TADD valid after TCLK rising edge, TCLK external
1
Hold time, TDAT/TADD valid after TCLK rising edge, TCLK internal
Delay time, TFRM valid after TCLK rising edge, TCLK ext†
1
ns
H–3
3H+22
Delay time, TFRM valid after TCLK rising edge, TCLK int†
H–3
3H+12
ns
Delay time, TCLK to valid TDAT/TADD, TCLK ext
25
Delay time, TCLK to valid TDAT/TADD, TCLK int
18
ns
ns
† TFRM timing and waveforms shown in Figure 28 are for internal TFRM. TFRM can also be configured as external. The TFRM external case is
illustrated in the receive timing diagram in Figure 27.
50
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
serial-port transmit timing in TDM mode (continued)
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5tc(CO)] (see Figure 28)
’549–80
’549-100
’549-120
tc(SCK)
tf(SCK)
MIN
16H†
Cycle time, serial-port clock
UNIT
MAX
‡
ns
6
ns
Fall time, serial-port clock
tr(SCK)
Rise time, serial-port clock
6
ns
†
tw(SCK)
Pulse duration, serial-port clock low/high
8H
ns
† When SCK is generated internally, this value is typical.
‡ The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching . It is characterized approaching an input frequency
of 0 Hz but tested as a much higher frequency to minimize test time.
tw(SCK)
tw(SCK)
tf(SCK)
TCLK
tc(SCK)
td(TC-TDV)
tr(SCK)
B15
TDAT
B0
B14
B13
B12
B8
A2
A3
A7
B7
B2
B1
B0
th(TCH-TDV)
td(TC-TDV)
th(TCH-TDV)
A1
TADD
td(TCH-TFV)
A0
td(TCH-TFV)
TFRM
Figure 28. Serial-Port Transmit Timing in TDM Mode
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
51
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
host port interface timing
switching characteristics over recommended operating conditions
(see Notes 5 and 6) (see Figure 29 through Figure 32) (continued)
Delay time, DS low to HD driven
0.5tc(CO)]
UNIT
MIN
MAX
5
12
Case 1: Shared-access mode if
tw(DSH) < 7H
td(HEL-HDV1)
=
’549-80
’549-100
’549-120
PARAMETER
td(DSL-HDV)
[H
ns
7H+20–tw(DSH)
Case 2: Shared-access mode if
Delay time, HDS falling to HD valid for first byte tw(DSH) > 7H
of a non-subsequent read: → max 20 ns†‡
Case 3: Host-only mode if
tw(DSH) < 20 ns
20
ns
40–tw(DSH)
Case 4: Host-only mode if
tw(DSH) > 20 ns
20
5‡
td(DSL-HDV2)
td(DSH-HYH)
Delay time, DS low to HD valid, second byte
tsu(HDV-HYH)
th(DSH-HDV)R
Setup time, HD valid before HRDY rising edge
3H–10
Hold time, HD valid after DS rising edge, read
0
td(COH-HYH)
td(DSH-HYL)
Delay time, DS high to HRDY high
20
10H+10
ns
ns
ns
12
ns
Delay time, CLKOUT rising edge to HRDY high
10
ns
Delay time, HDS or HCS high to HRDY low
12
ns
td(COH-HTX)
Delay time, CLKOUT rising edge to HINT change
15
ns
† Host-only mode timings apply for read accesses to HPIC or HPIA, write accesses to BOB, and resetting DSPINT or HINT to 0 in shared-access
mode. HRDY does not go low for these accesses.
‡ Shared-access mode timings will be met automatically if HRDY is used.
NOTES: 5. SAM = shared-access mode, HOM = host-only mode
HAD stands for HCNTRL0, HCNTRL1, and HR/W.
HDS refers to either HDS1 or HDS2.
DS refers to the logical OR of HCS and HDS.
6. On host read accesses to the HPI, the setup time of HD before DS rising edge depends on the host waveforms and cannot be
specified here.
52
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
host port interface timing (continued)
timing requirements over recommended operating conditions [H = 0.5tc(CO)] (see Note 7)
(see Figure 29 through Figure 32)
’549-80
’549-100
MIN
tsu(HBV-DSL)
th(DSL-HBV)
Setup time, HAD/HBIL valid before DS or HAS falling edge
tsu(HSL-DSL)
tw(DSL)
tw(DSH)
Pulse duration, DS high
tc(DSH-DSH)
tsu(HDV-DSH)
td(DSH-HSL)‡
MAX
’549-120
MIN
UNIT
MAX
10
10
ns
5
5
ns
Setup time, HAS low before DS falling edge
12
12
ns
Pulse duration, DS low
30
30
ns
10
10
ns
50
40
10H
10H
12
12
ns
10H
10H
ns
Hold time, HAD/HBIL valid after DS or HAS falling edge
Cycle time, DS rising
edge to next DS rising
edge
Case 1: HOM access timings
(see Access Timing Without HRDY)
Case 2a: SAM accesses and HOM active writes
to DSPINT or HINT†
(see Access Timings With HRDY)
Setup time, HD valid before DS rising edge
Delay time, DS high to next HAS low
ns
th(DSH – HDV)W
Hold time, HD valid after DS rising edge, write
3
3
ns
† A host not using HRDY should meet this timing requirement all the time unless a software handshake is used to change the access rate according
to the HPI mode.
‡ Must only be met if HAS is going low when not accessing the HPI (as would be the case where multiple devices are being driven by one host).
NOTE 7: SAM = shared-access mode, HOM = host-only mode
HAD stands for HCNTRL0, HCNTRL1, and HR/W.
HDS refers to either HDS1 or HDS2.
DS refers to the logical OR of HCS and HDS.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
53
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
host port interface timing (continued)
FIRST BYTE
Valid
HAD
SECOND BYTE
Valid
Valid
th(DSL-HBV)
th(DSL-HBV)
tsu(HBV-DSL)
tsu(HBV-DSL)
HBIL
tw(DSH)
tw(DSH)
tw(DSL)
tw(DSL)
HCS
HDS
tc(DSH-DSH)
td(DSL-HDV2)
td(HEL-HDV1)
th(DSH-HDV)
td(DSL-HDV)
HD
READ
Valid
th(DSH-HDV)R
Valid
tsu(HDV-DSH)
tsu(HDV-DSH)
th(DSH-HDV)W
th(DSH-HDV)
HD
WRITE
Valid
Valid
Figure 29. Read/Write Access Timings Without HRDY or HAS
54
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
host port interface timing (continued)
FIRST BYTE
SECOND BYTE
HAS
tsu(HBV-DSL)
td(DSH-HSL)
th(DSL-HBV)
tsu(HSL-DSL)
Valid
HAD
Valid
Valid
th(DSL-HBV)†
tsu(HBV-DSL)†
HBIL
tc(DSH-DSH)
tw(DSH)
tw(DSL)
HCS
HDS
td(HEL-HDV1)
td(DSL-HDV2)
th(DSH-HDV)R
th(DSH-HDV)R
td(DSL-HDV)
HD
READ
Valid
Valid
tsu(HDV-DSH)
tsu(HDV-DSH)
th(DSH-HDV)W
th(DSH-HDV)W
HD
WRITE
Valid
Valid
† When HAS is tied to VDD
Figure 30. Read/Write Access Timings Using HAS Without HRDY
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
55
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
host port interface timing (continued)
FIRST BYTE
SECOND BYTE
HAS
tsu(HSL-DSL)
td(DSH-HSL)
tsu(HBV-DSL)
th(DSL-HBV)
HAD
th(DSL-HBV)†
tsu(HBV-DSL)†
HBIL
tc(DSH-DSH)
tw(DSH)
tw(DSL)
HCS
HDS
tsu(HDV-HYH)
td(DSH-HYH)
HRDY
td(DSH-HYL)
td(HEL-HDV1)
td(DSL-HDV2)
th(DSH-HDV)R
td(DSL-HDV)
HD
READ
Valid
th(DSH-HDV)R
Valid
tsu(HDV-DSH)
tsu(HDV-DSH)
th(DSH-HDV)W
th(DSH-HDV)W
HD
WRITE
Valid
Valid
td(COH-HYH)
CLKOUT
td(COH-HTX)
HINT
† When HAS is tied to VDD
Figure 31. Read/Write Access Timing With HRDY
56
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
host port interface timing (continued)
HCS
td(DSH-HYL)
HRDY
td(DSH-HYH)
HDS
Figure 32. HRDY Signal When HCS is Always Low
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
57
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
MECHANICAL DATA
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
0,08 M
0,50
144
0,13 NOM
37
1
36
Gage Plane
17,50 TYP
20,20 SQ
19,80
22,20
SQ
21,80
0,25
0,05 MIN
0°–7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Thermal Resistance Characteristics
58
PARAMETER
°C/W
RΘJA
56
RΘJC
5
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
MECHANICAL DATA
TMS320VC5409 144-Pin Plastic Ball Grid Array Package (BGA)
GGU (S-PBGA-N144)
PLASTIC BALL GRID ARRAY PACKAGE
12,10
SQ
11,90
13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
0,80
0,80
0,95
0,85
0,12
0,08
1,40 MAX
0,55
0,45
0,08 M
0,45
0,35
0,10
4073221/A 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Thermal Resistance Characteristics
PARAMETER
°C/W
RΘJA
38
RΘJC
5
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