73M2901CE V.22bis Single Chip Modem Simplifying System Integration™ DATA SHEET DS_2901CE_031 April 2009 DESCRIPTION FEATURES The 73M2901CE low speed modem integrates a data pump, controller, and analog front end in a 3.3 V device with a powerful "AT" command host interface. The modem reduces external component count/cost by incorporating many features like parallel phone detect, Line-In-Use and Ring detection in software without requiring additional components. • • The device is a "one chip fits all” solution for applications including set-top boxes, point-of-sale terminals, automatic teller machines, utility meters, vending machines and smart card readers. Another distinctive feature of this device is pin compatibility with Teridian’s flagship embedded hard modems, the 73M2901CL, and the 73M1903 soft modem AFE. This offers customers a cost effective method to design for both hard or soft modem solutions in the same system as a risk-free cost reduction path. Complete support, modem reference designs and error correction software are part of the solution offered by Teridian. Our in-house application engineering team is here to help meet your international certification needs. • • • • • • • • • • • • • • • • Rev. 3.3 True one chip solution for embedded systems As low as 9.5 mA operating with standby and power down mode available Power supply operation from 3.6 V to 2.7 V Data modes and speeds: V.22bis – 2400bps V.22/Bell212 – 1200 bps V.21/Bell103 – 300 bps V.23 – 1200/75 bps (with PAVI turnaround) Bell202 – 1200 bps Bell202/V23 1200 bps FDX 4-wire operation V.22/Bell 212A/V.22bis synchronous modes International Call Progress support: FCC part 68, CTR21, JATE, etc. DTMF generation and detection Worldwide Caller ID capability U.S. Type I and II support EIA 777A compliant SIA-2000 compliant SMS messaging support On chip hybrid driver Blacklisting capability Line-In-Use and Parallel Pick-Up (911) detection with voltage or low cost energy detection method Incoming ring energy detection through CID path; no optocoupler circuitry required Manufacturing Self Test capability Backward compatible with 73M2901CL Packaging: 32 lead QFN, 32-pin TQFP © 2009 Teridian Semiconductor Corporation 1 73M2901CE Data Sheet DS_2901CE_031 Table of Contents 1 Hardware Description ......................................................................................................................... 4 Power Supply............................................................................................................................. 4 1.1 Low Power Mode ....................................................................................................................... 4 1.2 Analog Line / Hybrid Interface ................................................................................................... 4 1.3 Interrupt pins .............................................................................................................................. 4 1.4 Crystal Oscillator ....................................................................................................................... 5 1.5 1.5.1 Specifying a Crystal ......................................................................................................... 5 Reset ......................................................................................................................................... 5 1.6 Asynchronous and Synchronous Serial Data Interface ............................................................. 5 1.7 2 Pinout ................................................................................................................................................... 6 3 Pin Descriptions .................................................................................................................................. 7 Power Pins................................................................................................................................. 7 3.1 Analog Interface Pins ................................................................................................................ 7 3.2 Digital Interface Pins.................................................................................................................. 7 3.3 External Interrupt Pins ............................................................................................................... 8 3.4 Oscillator Pins ............................................................................................................................ 8 3.5 4 Electrical Specifications..................................................................................................................... 9 Absolute Maximum Ratings ....................................................................................................... 9 4.1 Recommended Operating Conditions ....................................................................................... 9 4.2 4.3 Receiver..................................................................................................................................... 9 Transmitter............................................................................................................................... 10 4.4 Maximum Transmit Level ........................................................................................................ 10 4.5 DC Characteristics, Vcc = 3.3 V .............................................................................................. 11 4.6 4.6.1 DC Supply Current, VDD = 2.7 V (Battery EOL) ........................................................... 11 4.6.2 DC Supply Current ,VDD = 3.0 V .................................................................................. 11 4.6.3 DC Supply Current VDD = 3.3 V ................................................................................... 12 4.6.4 DC Supply Current VDD = 3.6 V ................................................................................... 12 5 Firmware Description ....................................................................................................................... 13 Firmware Overview .................................................................................................................. 13 5.1 Firmware Features .................................................................................................................. 13 5.2 6 Design Considerations ..................................................................................................................... 14 Layout Considerations ............................................................................................................. 14 6.1 73M2901CE Design Compatibility ........................................................................................... 14 6.2 Telephone Line Interface ......................................................................................................... 14 6.3 7 Reference Designs ............................................................................................................................ 15 Low Cost Design Using DSP Ring and Status Monitoring ...................................................... 15 7.1 Reference Design Using Traditional Hardware Line Monitoring ............................................. 16 7.2 8 Modem Performance Characteristics ............................................................................................. 18 BER vs. SNR ........................................................................................................................... 18 8.1 BER vs. Receive Level ............................................................................................................ 18 8.2 9 Package Mechanical Drawing .......................................................................................................... 19 32-pin QFN .............................................................................................................................. 19 9.1 32-pin TQFP ............................................................................................................................ 20 9.2 10 Ordering Information ........................................................................................................................ 21 11 Related Documentation .................................................................................................................... 21 12 Contact Information .......................................................................................................................... 21 Revision History ........................................................................................................................................ 22 2 Rev. 3.3 DS_2901CE_031 73M2901CE Data Sheet Figures Figure 1: 32-pin QFN Pinout ..................................................................................................................... 6 Figure 2: 32-pin TQFP Pinout ..................................................................................................................... 6 Figure 3: Low Cost Design Using DSP Ring and Status Monitoring .......................................................... 15 Figure 4: Modem and Hybrid Circuitry – Traditional Line Monitoring ......................................................... 16 Figure 5: Traditional DAA Circuit Showing Hardware Detection Circuitry .................................................. 17 Figure 6: BER vs SNR ............................................................................................................................ 18 Figure 7: BER vs Receive Level ................................................................................................................. 18 Figure 8: 32-pin QFN Drawing .................................................................................................................... 19 Figure 9: 32 Pin TQFP Drawing .................................................................................................................. 20 Tables Table 1: 73M2901CE QFN and TQFP Pinout............................................................................................... 6 Table 2: 73M2901CE Order Numbers and Packaging Marks .................................................................... 21 Rev. 3.3 3 73M2901CE Data Sheet DS_2901CE_031 1 Hardware Description The 73M2901CE is designed to operate from a +3.6 to +2.7 volt supply with low power consumption (~30 mW @ 3.0 volts). The modem supports automatic standby idle mode. The modem will also accept a request to power down from the DTE via hardware control. No additional major components are required to complete the modem core logic. The modem provides direct firmware LED support via the port pins (pins 3, 4, 5, 6, 31, and 32). The 73M2901 CE includes the following hardware features: • Fully self-contained. “AT” Command interpreter and data pump. • User pins available. • Synchronous serial data I/O available. • Asynchronous serial port. • On-chip hybrid and line driver. • Autobaud capability from 300 bps to 9600 bps. • Reduced external hardware support required with energy incoming ring detection. 1.1 Power Supply Power is supplied to the 73M2901CE by the VPD and VPA pins. The 73M2901CE is designed for a single +3.6 to +2.7 volt supply and for low power consumption (~30mW @ 3.0 volts). Ground is supplied to the 73M2901CE by the VND and VNA pins. The 73M2901CE has been designed with separated analog and digital supplies to insure the best performance of the part by using separately filtered power supplies. It is recommended that separate locally bypassed traces be used to apply power to the analog supply VPA and the digital supply VPD. 1.2 Low Power Mode The Teridian 73M2901CE supports a low power standby mode. If the low power standby option is enabled, the 73M2901CE will go into a power saving mode when idle. While in this mode, the oscillator will be running and clocks will be supplied to the UART, timers and interrupt blocks, but no clocks will be supplied to the CPU. Instruction processing and activity on the internal busses is halted. Normal operation is resumed when an interruption such as assertion of DTR or RING occurs, a character is sent to the 73M2901CE TXD input, or a reset occurs. 1.3 Analog Line / Hybrid Interface The 73M2901CE provides a differential analog output (TXAP and TXAN) and a single-ended analog input (RXA) with internal A/D and D/A converters. A driver is provided for an internal hybrid function. The internal hybrid driver is capable of driving an external load matching impedance and a line-coupling transformer. The internal hybrid/line driver senses the load and adapts itself to its requirements. The 73M2901CE provides firmware control for a hook relay driver (RELAY) as well as interrupt support for a ring detect opto-coupler (RING). 1.4 Interrupt pins The external interrupt sources, DTR and RING, come from dedicated input pins of the same name. DTR informs the 73M2901CE that the host has requested the 73M2901CE to perform a specific function. The function of DTR can be changed by “AT” commands (described in full in the 73M2901CE AT Command User Guide). 4 Rev. 3.3 DS_2901CE_031 73M2901CE Data Sheet RING is used to inform the 73M2901CE that the external DAA circuitry or ring energy detector has detected a ring signal. It will go active when each “RING” message is sent on RXD. In addition, sending any character on the TXD line also generates an internal interrupt. 1.5 Crystal Oscillator The Teridian 73M2901CE single chip modem can use an external 11.0592 MHz reference clock or can generate a clock using only a crystal and two capacitors. If an external clock is used, it should be applied to the OSCIN pin. 1.5.1 Specifying a Crystal The manufacturer of a crystal resonator verifies its frequency of oscillation in a test set-up, but to ensure that the same frequency is obtained in the application, the circuit conditions must be the same. The Teridian 73M2901CE modem requires a parallel mode (anti-resonant) crystal, the important specifications of which are as follows: Mode: Frequency: Frequency tolerance: Temperature drift: Load capacitance: ESR: Drive level: Parallel (anti-resonant) 11.0592 MHz ±50 ppm at initial temperature An additional ±50 ppm over full range 18 pF to 22 pF 75 Ω max Less than 1mW The peak voltage level of the oscillator should be checked to assure it will not violate the maximum voltage levels allowed on the oscillator pins. A resistor in series with the crystal can be used, if necessary, to reduce the oscillator’s peak voltage levels. Crystals with low ESRs may oscillate at higher than specified voltage levels. 1.6 Reset A reset is accomplished by holding the RESET pin high. To ensure a proper power-on reset, the reset pin must be held high for a minimum of 3 µs. At power on, the voltage at VPD, VPA, and RESET must come up at the same time for a proper reset. The signals DCD, CTS and DSR will be held inactive for 25 ms, acknowledging the reset operation, within a 250 ms time window after the reset-triggering event. The 73M2901CE is ready for operation after the 250 ms window and/or after the signals DCD, CTS and DSR become active. 1.7 Asynchronous and Synchronous Serial Data Interface The serial data interface consists of the TXD and RXD data paths (LSB shifted in and out first) and the TXCLK and RXCLK serial synchronous clock outputs associated with the data pins; CTS/RTS flow control; DCD, DSR and DTR. In asynchronous mode, the data is passed at the bit rate (tolerance is +1%, -2.5%). Rev. 3.3 5 73M2901CE Data Sheet DS_2901CE_031 2 Pinout The 73M2901CE is available in a 32-pin QFN or 32-pin TQFP package. Table 1 lists the pins for both packages. Table 1: 73M2901CE QFN and TQFP Pinout 4 DSR 12 TXAP 20 VPD 28 DTR 5 CTS 13 VREF 21 NC 29 USR20 6 RTS 14 VBG 22 VND 30 RING 7 USR11 15 RXA 23 TXD 31 RELAY 8 USR10 16 VNA 24 TXCLK 32 RI VND 1 24 TXCLK VND 1 24 TXCLK VPD 2 23 TXD VPD 2 23 TXD DCD 3 22 VND DCD 3 22 VND DSR 4 21 NC DSR 4 21 NC CTS 5 20 VPD CTS 5 20 VPD RTS 6 19 OSCIN RTS 6 19 OSCIN 7 18 OSCOUT USR11 7 18 OSCOUT 8 17 VND USR10 8 17 VND 12 13 14 15 16 VREF VBG RXA VNA 16 VNA TXAP 15 RXA 11 14 VBG TXAN 13 VREF 10 12 TXAP VPA 11 TXAN 9 10 VPA Figure 1: 32-pin QFN Pinout TERIDIAN 73M2901CE RESET 9 USR10 TERIDIAN 73M2901CE RESET USR11 6 VPD RXCLK 25 27 RXD OSCIN 26 19 RXCLK TXAN 27 11 DTR DCD 28 3 USR20 RXD 29 26 RING OSCOUT 30 18 RELAY VPA 31 10 RI VPD 32 2 VPD VPD 25 25 RXD VND 26 17 RXCLK RESET 27 9 DTR VND 28 1 USR20 Name 29 Pin RING Name 30 Pin RELAY Name 31 Pin RI Name 32 Pin Figure 2: 32-pin TQFP Pinout Rev. 3.3 DS_2901CE_031 73M2901CE Data Sheet 3 Pin Descriptions 3.1 Power Pins Pin Name Pin Number Type VPA 10 I Positive analog voltage (analog supply) VNA 16 I Negative analog voltage (analog ground) VPD 2, 20, 25 I Positive digital voltage (digital supply) VND 1, 17, 22 I Negative digital voltage (digital ground) 3.2 Description Analog Interface Pins Pin Name Pin Number Type RXA 15 I Receive analog input TXAN 11 O Transmit analog - output TXAP 12 O Transmit analog + output VBG 14 O Analog Band Gap voltage reference (0.1 µF to VNA). This pin must not be connected to external circuitry other than the decoupling capacitor. VREF 13 O Analog reference voltage (0.1 µF to VNA) 3.3 Description Digital Interface Pins Pin Name Pin Number Type RESET 9 I Reset RXCLK 27 O Receive data synchronous clock, valid on rising edge TXCLK 24 O Transmit data synchronous clock, valid on rising edge TXD 23 I Serial data input from DTE RXD 26 O Serial output to DTE USR10 8 I/O Programmable I/O port. This pin can optionally be used to control an external switch for external Line In Use circuitry. USR11 7 I/O Programmable I/O port. This pin can optionally be used to control an external switch for caller ID operation. RTS 6 I Request to send CTS 5 O Clear to send DSR 4 O Data set ready DCD 3 O Data carrier detect RI 32 O Ring indicator RELAY 31 O Relay driver output USR20 29 I/O Programmable I/O port Rev. 3.3 Description 7 73M2901CE Data Sheet 3.4 DS_2901CE_031 External Interrupt Pins Pin Name Pin Number Type RING 30 I External interrupt – Line interface ring detection circuitry input DTR 28 I External interrupt – DTE DTR signal input 3.5 Description Oscillator Pins Pin Name Pin Number Type OSCIN 19 I Crystal input for internal oscillator, also input for external source OSCOUT 18 O Crystal oscillator output 8 Description Rev. 3.3 DS_2901CE_031 73M2901CE Data Sheet 4 Electrical Specifications 4.1 Absolute Maximum Ratings Parameter Rating Supply Voltage -0.5 V to +4.0 V Pin Input Voltage (except OSCIN) -0.5 V to + 6.0 V Pin Input Voltage (OSCIN) -0.5 V to VPD + 0.5 V Storage Temperature -55 ºC to 150 ºC Absolute maximum ratings are stress ratings ONLY, functional operation of the device at these or any other conditions above those indicated in the recommended operation sections of this specification is not implied. Exposure to absolute maximum conditions for extended periods of time may affect reliability. 4.2 Recommended Operating Conditions Parameter Rating Supply Voltage 2.7 V to 3.6 V Oscillator Frequency 11.0592 MHz +/- 50 ppm Operating Temperature -40 ºC to 85 ºC 4.3 Receiver Parameter Conditions Min Nominal Max Carrier Detect On Tip and Ring -43 dBm0 1 Carrier Detect Off Tip and Ring -48 dBm01 Carrier Detect Hysteresis Tip and Ring Receive Level Tip and Ring Idle Channel Noise 0.2 kHz to 4.0 kHz Input Impedance RXA 150 Receive Gain Boost S110 bit 5=1, CID mode 18.8 19.3 19.8 dB Max Input Level at RXA VREF=1.25 V 0.587 0.622 0.658 Vpk Total Harmonic Distortion (THD) 1kHz 450 mVpk on RXA THD=2nd and 3rd harmonic -70 -50 dB 2 -43 -70 Units dB -9 dBm01 -65 dB kΩ 1 dBm0 refers to the Teridian recommended line interface (8 dB loss from transmit pins to the line and 5 dB loss from the line to the receiver pin). Results may vary depending on the selected DAA components. 0dBm=0.775 mVrms; dBm=10log(Vrms2/(1mW)(600Ω)) Rev. 3.3 9 73M2901CE Data Sheet 4.4 DS_2901CE_031 Transmitter Parameter Conditions Min Nominal Max Units ITU Guard tone power 550 Hz (relative to carrier) -5 -3.5 -2 dB 1800 Hz (relative to carrier) -8 -6.5 -5 dB Calling Tone 1300 Hz -11 -10 -9 dBm0 1 Answer Tone power 2225 Hz / 2100 Hz -11 -10 -9 dBm01 DTMF Transmit power High band tones -12 -11.5 -11 dBm01 Low band tones -13.7 -13.2 -12.7 dBm01 Gain adjust tolerance By step -0.3 0 0.3 dBm01 Total Harmonic Distortion (THD) 1 kHz sine wave at output (TXAP-TXAN) 1.5 Vpk (2.7 dBm) for VREF=1.25 V THD=2nd and 3rd harmonic -50 dB Intermod Distortion At output (TXAP-TXAN) 1 kHz, 1.2 kHz sine waves summed 2 Vpk for VREF=1.25 V Each unwanted frequency component -33 dBm Sum of unwanted frequency components in pass band -20 dB below low tone 30 dB Max Units Power supply rejection ratio 4.5 -30 dBm signal at VPA 300 Hz to 30 kHz measured TXAP to TXAN Maximum Transmit Level Parameter Conditions Min Nominal QAM VREF=1.25 V VPA=3.3 V -9.6 dBm01 DPSK VREF=1.25 V VPA=3.3 V -7.4 dBm01 FSK VREF=1.25 V VPA=3.3 V -5.3 dBm01 DTMF (High Tone) VREF=1.25 V VPA=3.3 V S13=$20, S85=80 -8 -7 dBm01 DTMF (Low Tone) VREF=1.25V VPA=3.3V S13=$20, S85=80 -9.7 -8.7 dBm01 1 dBm0 refers to the Teridian recommended line interface (8 dB loss from transmit pins to the line and 5 dB loss from the line to the receiver pin). Results may vary depending on the selected DAA components. 0dBm=0.775 mVrms; dBm=10log(Vrms2/(1mW)(600Ω)) 10 Rev. 3.3 DS_2901CE_031 4.6 73M2901CE Data Sheet DC Characteristics, Vcc = 3.3 V (Vdd stands for VPD and VPA) Parameter Symbol Input low voltage (except OSCIN) VIL Input low voltage OSCIN Conditions Min Nom Max Unit -0.5 0.8 V VIL -0.5 0.2 Vdd V Input high voltage (except OSCIN) VIH 0.7 Vdd +5.5 V Input high voltage OSCIN VIH 0.7 Vdd Vdd+0.5 V Output low voltage (except OSCOUT) VOL IOL=4 mA 0.45 V Output low voltage OSCOUT VOLOSC IOL=3 mA 0.7 V Output high voltage (except OSCOUT) VOH IOH=-4 mA Vdd-0.45 V Output high voltage OSCOUT VOHOSC IOH=-3 mA Vdd-0.9 V Input leakage current (except OSCIN) IIH Vss<Vin<Vdd Input leakage current OSCIN IIH Vss<Vin<Vdd 1 1 µA 30 µA Parameter Conditions Min Nom Max Unit VBG Vdd=3.3 V 1.19 1.25 1.31 V VREF Vdd=3.3 V 1.19 1.25 1.31 V TXAP to TXAN offset Vdd=3.3 V, steady state 50 mV Nom Max Unit 4.6.1 DC Supply Current, VDD = 2.7 V (Battery EOL) Parameter Symbol Conditions Maximum power supply, normal operation IDD1 30 pF/pin 9.5 10.5 mA Maximum power supply, Idle mode IDD2 30 pF/pin 900 1500 µA Maximum power supply, Power Down mode IDD3 30 pF/pin 10 µA Nom Max Unit 4.6.2 Min DC Supply Current ,VDD = 3.0 V Parameter Symbol Conditions Maximum power supply, normal operation IDD1 30 pF/pin 10.6 11.9 mA Maximum power supply, Idle mode IDD2 30 pF/pin 1.1 1.7 mA Maximum power supply, Power Down mode IDD3 30 pF/pin 10 µA Rev. 3.3 Min 11 73M2901CE Data Sheet 4.6.3 DS_2901CE_031 DC Supply Current VDD = 3.3 V Parameter Symbol Conditions Maximum power supply, normal operation IDD1 Maximum power supply, Idle mode Maximum power supply, Power Down mode 4.6.4 Min Nom Max Unit 30 pF/pin 11.8 13.6 mA IDD2 30 pF/pin 1.25 1.85 mA IDD3 30 pF/pin 10 µA Nom Max Unit DC Supply Current VDD = 3.6 V Parameter Symbol Conditions Maximum power supply, normal operation IDD1 30 pF/pin 13.4 15.5 mA Maximum power supply, Idle mode IDD2 30 pF/pin 1.4 2.0 mA Maximum power supply, Power Down mode IDD3 30 pF/pin 10 µA 12 Min Rev. 3.3 DS_2901CE_031 73M2901CE Data Sheet 5 Firmware Description An “AT” command interpreter provides command and configuration of the 73M2901CE. This provides the user a uniform interface to control the modem in embedded applications. The signal processing is performed to provide data to the DAC and process data from the A/D converter. A MAC hardware coprocessor is provided for computation. To provide maximum flexibility, the system host processor can access the internal RAM and Control Register space in the modem. This will allow the OEM user to modify parameters such as filter response and transmit levels through the AT command set using proprietary commands. The host processor can also access the modem I/O port pins, providing extended I/O capability. Refer to the 73M2901CE AT Command User Guide for a complete description of the software. 5.1 Firmware Overview The modem always powers up in the idle (on hook) mode. “AT” commands are issued via the serial interface from the host. All modem configuration commands are received in this manner. The data modem firmware is contained in an internal ROM. The firmware will automatically enter a power saving idle mode if the modem is on hook and there are no incoming host commands. The modem automatically powers up upon receiving the next command. This power up sequence occurs without delay to the host. This function, while saving power, is transparent to the host processor and can be disabled by the host via an “AT” command. The host can also program the modem to power down via an external pin (DTR) or via a firmware command. 5.2 • • • • • • • • • • • • • • • • • • • • Firmware Features “AT” command set Supports data standards through V.22bis Provides DAA control firmware (e.g. ring detect, hook control) Multinational Call Progress support (FCC part 68, ITU CTR21, Japan JATE, etc.) Caller ID capability FSK demodulation (V.23, V.21, Bell 202 and Bell 103) DTMF detection and decoding Selectable number of rings and line reversal for CID data operation On hook CID data operation On hook Line-In-Use detection support (No line seizure will occur when a Line-In-Use condition is detected) Off hook Parallel Pick-Up detection support (Line seizure will be aborted as soon as a Parallel Pick-Up condition is detected) Off hook voltage change detection (requires external circuitry) Receive energy change detection Directly interfaces with standard V.24/EIA-232 bus drivers (3.3 V inverted level) serial interface using the built in serial port and firmware control of port pins Provides tone generation and detection including four imprecise and four precise call progress detect filters with programmable frequency and detection threshold Blacklisting capability Long Space disconnect support Inactivity timeout Host access to program RAM provided User programmable general purpose I/O Rev. 3.3 13 73M2901CE Data Sheet DS_2901CE_031 6 Design Considerations The 73M2901CE single chip modem includes all the basic modem functions. Programmable configuration options make this device highly adaptable to a wide variety of applications. Unlike digital logic circuitry, modem designs must contend with precise frequency tolerances and verify low-level analog signals to ensure acceptable performance. Using good analog circuit design practices will generally result in a sound design. The crystal oscillator should be held to a 50 ppm tolerance. The recommendations in this section should be taken into consideration when starting new designs. 6.1 Layout Considerations Good analog/digital design rules must be used to control system noise in order to obtain high performance in modem designs. The more digital circuitry present in the application, the more attention to noise control is needed. High speed, digital devices should be locally bypassed, and the telephone line interface and the modem should be located next to each other near where the telephone line connection is accessed. It is recommended that power supplies and ground traces be routed separately to the analog and digital portions on the board. Digital signals should not be routed near low-level or high impedance analog traces. The 73M2901CE should be considered a high performance analog device. A 3.3 µF electrolytic capacitor in parallel with a 0.1 µF Ceramic capacitor should be placed between each VPD and VND pin and a 10 µF and 0.1 µF between VPA and VNA. A 0.1 µF ceramic capacitor should be placed between VREF and VNA as well as between VBG and VNA. Use of ground planes and large traces on power is recommended. 6.2 73M2901CE Design Compatibility The Teridian 73M2901CE is an enhanced version of the Teridian 73M2901CL and has a number of additional features. These parts are highly compatible with the earlier 73M2901, however, users should pay special attention when changing an existing 73M2901 design to use the 73M2901CE or 73M2901CL. From a hardware standpoint, the key differences involve the User I/O pins USR10 and USR11, the ASRCH pin and the HBDEN pin. An additional user I/O pin, USR20, replaces the ASRCH pin on the 73M2901CE. This pin may remain safely connected to TXD as long as the host software does not reconfigure USR20 as an output (S104 bit0=0). The 73M2901CE contains a high efficiency low power hybrid driver. Due to this enhancement, HBDEN is no longer required. This pin is an internal no-connect and can safely remain connected to its previous VPD or GND. The functions of USR10 and USR11 are related to Caller ID and Line In Use/Parallel Pickup support. Software enhancements to the 73M2901CE are typically achieved by the addition of new AT commands. The device can be considered a superset of the 73M2901CL and 73M2901C. When converting a design to the 73M2901CE, it is recommended that the user check the commands and register settings for backward compatibility to the earlier parts (refer to the 73M2901CE AT Command User Guide for complete details). 6.3 Telephone Line Interface Transmit levels at the line are dependent on the interface used between the pins and the line. The internal hybrid line drivers eliminate the need for additional active circuitry to drive the line-coupling transformer. The analog outputs TXAP and TXAN can be connected directly to the transformer (with the required impedance matching series resistor or network). Depending upon transformer design (specifically dry transformers), operation may be affected by the limited amount of DC current generated by the analog outputs (DC offset). For this reason, Teridian recommends using a coupling capacitor with those transformers to insure maximum performance. The line interface circuits shown in Section 7 Reference Designs represent the basic components and values for interfacing the Teridian 73M2901CE analog pins to the telephone line. The values of these components have been calculated to minimize the transmission and reception path hybrid losses and are linked by the following equation: R15=0.242 x R13. 14 Rev. 3.3 DS_2901CE_031 73M2901CE Data Sheet 7 Reference Designs 7.1 Low Cost Design Using DSP Ring and Status Monitoring 11.0592 MHz C3 VCC3_3D C2 VCC3_3D 33pF Y1 C11 0.1uF 27pF + C12 3.3uF C13 C14 3.3uF 0.1uF + TXD 24 23 22 21 20 19 18 17 73M2901CE 25 26 27 28 29 30 31 32 DTRB VPD RXD RXCLK DTR USR20 RING RELAY RI VNA RXA VBG VREF TXAP TXAN VPA RESET 16 15 14 13 12 11 10 9 R13 21K DCDB DSRB C4 56nF R2 2.7K HY BRID2 VCC3_3A 1 2 3 4 5 6 7 8 RIB R15 5.1K VND VPD DCD DSR CTS RTS USR11 USR10 RXD HY BRID1 TXCLK TXD VND N/C VPD OSCIN OSCOUT VND U1 R17 475 C7 C8 0.1uF 0.1uF + C9 10uF C10 VCC3_3D R20 27K 0.1uF CTSB RTSB DETECT R18 100 LIUCHK R16 100 HOOKB C1 10uF + VCC3_3D C5 0.1uF 3.3uF 1 1 - F1 BR1 CBRHD-04 3 4 1 VCC3_3D + E1 TISP4350T3BJR Bourns Thy ristor 2 1 4 L1 NLC322522T-4R7M 4 HY BRID2 T1 Sumida MIT4115 2 3 2 HY BRID1 R1 10K C6 + 3 2 U2 TLP627 R9 C19 63K 0.22uF 250V L2 NLC322522T-4R7M MF-R015/600 Bourns PTC f use J2 4 3 2 1 RJ-11 HOOKB ISOLATION BARRIER Figure 3: Low Cost Design Using DSP Ring and Status Monitoring Rev. 3.3 15 73M2901CE Data Sheet 7.2 DS_2901CE_031 Reference Design Using Traditional Hardware Line Monitoring 11.0592 MHz C3 VCC3_3D C2 VCC3_3D 33pF Y1 C11 0.1uF + C12 3.3uF 27pF C13 C14 3.3uF 0.1uF + TXD DTRB RIB DCDB DSRB 24 23 22 21 20 19 18 17 VPD RXD RXCLK DTR USR20 RING RELAY RI VNA RXA VBG VREF TXAP TXAN VPA RESET 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 RXD 25 26 27 28 29 30 31 32 R15 5.1K VND VPD DCD DSR CTS RTS USR11 USR10 73M2901CE HY BRID1 TXCLK TXD VND N/C VPD OSCIN OSCOUT VND U1 R17 475 R13 21K C4 56nF R2 2.7K HY BRID2 VCC3_3A C7 C8 0.1uF 0.1uF + C9 10uF C10 VCC3_3D R20 27K 0.1uF CTSB RTSB R18 100 R16 100 LIUCHK HOOKB C1 10uF + VCC3_3D DETECT C5 3.3uF + C6 R1 10K 0.1uF Figure 4: Modem and Hybrid Circuitry – Traditional Line Monitoring 16 Rev. 3.3 DS_2901CE_031 73M2901CE Data Sheet R4 13K R5 13K R6 27K 2 R3 33K PPU Circuit 3 Q3 CMPT6429 C 15V 0.5W 1 D2 CMR1F-04M D3 R19 20K D7 A C A C C HY BRID2 R21 100 OHMS C16 1uF R10 62K A 4 R12 20K A D1 2 2 HY BRID1 R7 1K 1 CMPT6429 + C15 10uF R14 62K Q2 3 3 1 T1 Sumida MIT4114 3 2 Q1 2N5087 1 CMR1F-04M 12V DETECT 4 1 D8 RING detection R11 9.1K C17 S1A D6 D5 A C U2 TLP627 A C 22V 22V 3 2 0.47UF 250V L1 NLC322522T-4R7M 4 R8 51K 4 1 VCC3_3D F1 4 1 LIUCHK VCC3_3D - 2 U5 Z602 + 1 E1 P3100EA70 TECCOR SIDACTOR 3 CID coupling 3 2 U3 TLP627 L2 NLC322522T-4R7M 3 2 U4 TLP627 C18 0.15uF 250V R9 TR250-145 RAY CHEM POLY SWITCH J2 4 3 2 1 C19 CON4 HOOKB 9.1K RING/CID detection 0.47uF 250V Figure 5: Traditional DAA Circuit Showing Hardware Detection Circuitry Rev. 3.3 17 73M2901CE Data Sheet DS_2901CE_031 8 Modem Performance Characteristics The curves presented in this data sheet define modem IC performance under a variety of line conditions typical of those encountered over the Public Switched Telephone Network. 8.1 BER vs. SNR This test represents the ability of the modem to operate over noisy lines with a minimum amount of data transfer errors. Since some noise is generated in the best dial up lines, the modem must operate with the lowest signal to noise ratio (SNR) possible. Better modem performance is indicated by test curves that are closest to the BER axis. A narrow spread between curves representing the four line parameters indicates minimal variation in performance while operating over a range of typical operating conditions. A DPSK or QAM modem will exhibit better BER performance test curves receiving in the low band (answer mode) than in the high band (originate mode). 8.2 BER vs. Receive Level This test measures the dynamic range of the modem. Because signal levels vary widely over dial up lines, the widest possible dynamic range is desirable. The SNR is held constant at the indicated values as the receive level is lowered from a very high to a very low signal level. The width of the bowl of these curves, taken at the BER break points is the measure of the dynamic range. Figure 6: BER vs SNR 18 Figure 7: BER vs Receive Level Rev. 3.3 DS_2901CE_031 73M2901CE Data Sheet 9 Package Mechanical Drawing 9.1 32-pin QFN 0.85 NOM./ 0.9MAX. 0.00 / 0.005 5 0.20 REF. 2.5 1 2.5 2 3 5 SEATING PLANE SIDE VIEW TOP VIEW 0.35 / 0.45 3.0 / 3.75 CHAMFERED 0.30 0.18 / 0.3 1.5 / 1.875 1 2 3 3.0 / 3.75 0.25 1.5 / 1.875 0.5 0.2 MIN. 0.35 / 0.45 0.5 0.25 BOTTOM VIEW Figure 8: 32-pin QFN Drawing Rev. 3.3 19 73M2901CE Data Sheet 9.2 DS_2901CE_031 32-pin TQFP Figure 9: 32 Pin TQFP Drawing 20 Rev. 3.3 DS_2901CE_031 73M2901CE Data Sheet 10 Ordering Information Table 2 lists the order numbers and packaging marks used to identify 73M2901CE products. Table 2: 73M2901CE Order Numbers and Packaging Marks Part Description Order Number Packaging Mark 73M2901CE 32-Pin QFN Lead Free 73M2901CE-IM/F M2901CEM 73M2901CE 32-Pin QFN Lead Free Tape & Reel 73M2901CE-IMR/F M2901CEM 73M2901CE 32-Pin Thin Quad Flat Pack Lead Free 73M2901CE-IGV/F 73M2901CEIGV 73M2901CE 32-Pin Thin Quad Flat Pack Lead Free Tape & Reel 73M2901CE-IGVR/F 73M2901CEIGV 11 Related Documentation The following 73M2901CE documents are available from Teridian Semiconductor Corporation: 73M2901CE AT Command User Guide 73M2901CE Demo Board User Guide 12 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 73M2901CE, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: [email protected] For a complete list of worldwide sales offices, go to http://www.teridian.com. Rev. 3.3 21 73M2901CE Data Sheet DS_2901CE_031 Revision History Revision Date Description 2.2.1 4/20/2004 First publication. 3.1 12/14/2007 Replaced 32QFN punched with SAWN package, removed leaded package option, updated schematic and minor clean up. 3.2 1/21/2008 Changed dimension of bottom exposed pad on 32QFN mechanical package figure. 3.3 4/3/2009 Formatted to new Teridian style. Assigned new document number. Minor corrections have been made to Section 5.3 and Section 6.3. © 2009 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners. Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. Accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales representative. Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com 22 Rev. 3.3