TERIDIAN 73S8010R

73S8010R
Low Cost Smart Card Interface
DATA SHEET
January 2008
DESCRIPTION
The TERIDIAN 73S8010R is a single smart card interface
IC. The TERIDIAN 73S8010R has been designed to
provide full electrical compliance with ISO-7816-3 and
EMV 4.0 (EMV2000) specifications.
Interfacing with the host is done through the two-wire I2C
bus, and one interrupt output to inform the system
controller of the card presence and faults.
The card clock signal can be generated by an on-chip
oscillator using an external crystal, or by connection to a
clock signal.
The TERIDIAN 73S8010R incorporates an ISO-7816-3
activation/deactivation sequencer that controls the card
signals. Level-shifters drive the card signals with the
selected card voltage (3V or 5V), coming from an internal
Low Drop-Out (LDO) voltage regulator. This LDO regulator
is powered by a dedicated power supply input VPC. Digital
circuitry is separately powered by a digital power supply
VDD.
ADVANTAGES
•
•
•
Greatly reduced power dissipation
Fewer external components are required
Better noise performance
High current capability (90mA supplied to the card)
•
•
•
Card Interface:
Complies with ISO-7816-3 and EMV 4.0
A LDO voltage regulator provides 3V / 5V to the
card from an external power supply input
Provides at least 90mA to the card
ISO-7816-3 Activation / Deactivation sequencer
with emergency automated deactivation on card
removal or fault detected by the protection circuitry
Protection includes 3 voltage supervisors that
detects voltage drops on VCC card and on power
supplies VDD and VPC
The VDD voltage supervisor threshold value can be
externally adjusted
Over-current detection 150mA max.
1 card detection input
Auxiliary I/O lines, for C4 / C8 contact signals
CLK signal up to 20MHz
•
Host Interface:
Fast mode, 400kbps I2C slave bus
8 possible devices in parallel
One control register and one status register
Interrupt output to the host for fault detection
Crystal oscillator or host clock, up to 27MHz
•
Power Supply:
VPC: 4.75V to 5.5V
VDD: 2.7V to 5.5V
6kV ESD Protection on the card interface
Package: SO28 or QFN32
Emergency card deactivation is initiated upon card
extraction or upon any fault generated by the protection
circuitry. The fault can be a card over-current, a VDD
(digital power supply), a VPC (regulator power supply), a
VCC (card power supply) or an over-heating fault.
The card over-current circuitry is a true current detection
function, as opposed to VCC voltage drop detection, as
usually implemented in ICC interface ICs.
APPLICATIONS
•
•
•
•
Set-Top-Box Conditional Access and Pay-perView
Point of Sales & Transaction Terminals
Control Access & Identification
Multiple card and SAM reader configurations
Page: 1 of 24
Small format (5x5x0.8mm) QFN32 package option
True card over-current detection
FEATURES
With its embedded LDO regulator, the TERIDIAN
73S8010R is a cost-effective solution for any application
where a 5V (typically -5% +10%) power supply is
available.
Hardware support for auxiliary I/O lines, C4 / C8 contacts,
is provided.
The VDD voltage fault has a threshold voltage that can be
adjusted with an external resistor or resistor network. It
allows automated card deactivation at a customized VDD
voltage threshold value. It can be used, for instance, to
match the system controller operating voltage range.
Single smart card interface
IC firmware compatible with TDA8020
Traditional step-up converter is replaced by a
LDO regulator:
•
•
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
FUNCTIONAL DIAGRAM
VDD
[20] 21
GND
VDDF_ADJ
[17] 18
[2] 5
VPC
[3] 6
[4, 5, 6, 9, 16, 25, 32] 7, 8, 9
NC
VPC FAULT
[21] 22
[1] 4
VDD VOLTAGE SUPERVISOR
VOLTAGE REFERENCE
GND
VDD FAULT
VCC FAULT
[18] 19
SCL
Int_Clk
[19] 20
SDA
R-C
OSC.
I2C
DIGITAL
&
FAULT LOGIC
[29] 1
SAD0
[30] 2
SAD1
[31] 3
SAD2
[22] 23
INT
LDO
REGULATOR
&
VOLTAGE
SUPERVISORS
ISO-7816
SEQUENCER
GND
[12] 14
GND
[15] 17
VCC
ICC RESET
BUFFER
[14] 16
ICC CLOCK
BUFFER
[13] 15
RST
CLK
[7] 10
PRES
[23] 24
XTALIN
[24] 25
XTALOUT
XTAL
OSC
CLOCK
GENERATION
OVER
TEMP
TEMP FAULT
[8] 11
[26] 26
I/O
IOUC
[27] 27
AUX1UC
ICC I/O BUFFERS
[11] 13
AUX1
[10] 12
[28] 28
AUX2
AUX2UC
Pin numbers reference to the SO28 package
[Pin numbers] reference to the QFN32 Package
Figure 1: 73S8010R Block Diagram
Page: 2 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
PIN DESCRIPTION
CARD INTERFACE
NAME
PIN
(SO)
PIN
(QFN)
DESCRIPTION
I/O
11
8
Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC.
AUX1
13
11
AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
AUX2
12
10
AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
RST
16
14
Card reset: provides reset (RST) signal to card.
CLK
15
13
Card clock: provides clock (CLK) signal to card. The rate of this clock is determined by crystal
oscillator frequency and CLKSEL bits in the control register.
PRES
10
7
Card Presence switch: active high indicates card is present. Includes a pull-down resistor.
VCC
17
15
Card power supply – logically controlled by sequencer, output of LDO regulator. Requires an
external filter capacitor to the card GND.
GND
14
12
Card ground.
MISCELLANEOUS INPUTS AND OUTPUTS
NAME
PIN
(SO)
PIN
(QFN)
XTALIN
24
23
Crystal oscillator input: can either be connected to crystal or driven as a source for the card clock.
DESCRIPTION
XTALOUT
25
24
Crystal oscillator output: connected to crystal. Left open if XTALIN is being used as external
clock input.
VDDF_ADJ
18
17
VDD threshold adjustment input: this pin can be used to overwrite higher VDDF value (that controls
deactivation of the card). Must be left open if unused.
7, 8, 9
4, 5, 6,
9, 16,
25, 32
NC
Non-connected pin.
POWER SUPPLY AND GROUND
PIN
(SO)
PIN
(QFN)
VDD
21
20
System controller interface supply voltage and supply voltage for internal circuitry.
VPC
6
3
LDO regulator power supply source.
GND
4
1
LDO regulator ground.
Smart Card I/O Ground.
NAME
GND
14
12
GND
5, 22
2,21
Page: 3 of 24
DESCRIPTION
Digital ground.
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
MICROCONTROLLER INTERFACE
NAME
PIN
(SO)
PIN
(QFN)
INT
23
22
SAD0
SAD1
SAD2
1
2
3
29
30
31
DESCRIPTION
Interrupt output(negative assertion). Interrupt output signal to the processor. A 20kΩ pull up to
VDD is provided internally
Serial device address bits. Digital inputs for address selection that allows for the connection of up
to 8 devices in parallel. Address selections as follows:
SAD2
0
0
0
0
1
1
1
1
SAD1
0
0
1
1
0
0
1
1
SAD0
0
1
0
1
0
1
0
1
2
I C Address (7 bits)
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
Note: Pins SADO and SAD1 are internally pulled-down and SAD2 is internally pulled-up.
The default address when left unconnected is 48h.
2
SCL
19
18
I C clock signal input
SDA
20
19
I C bi-directional serial data signal
I/OUC
26
26
System controller data I/O to/from the card. Includes internal pull-up resistor to VDD
AUX1UC
27
27
System controller auxiliary data I/O to/from the card. Includes internal pull-up resistor to VDD
AUX2UC
28
28
System controller auxiliary data I/O to/from the card. Includes internal pull-up resistor to VDD
Page: 4 of 24
2
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
SYSTEM CONTROLLER INTERFACE (I2C BUS)
A fast-mode 400kHz I2C bus slave interface is used for controlling the device and reading the status of the device
via the data pin SDA and clock pin SCL. The bus has 3 address select pins, SAD0, SAD1, and SAD2. This
allows up to 8 devices to be connected in parallel.
Device Address Selections
SAD2
SAD1
SAD0
I2C Address
(7 bits)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
2
Note: bit 0 of the I C address is the R/W bit. Refer to figures 2 and 3 for usage.
CONTROL register
Power On Reset = 00h
Name
Bit
Start/Stop
0
Warm reset
1
5Vand 3V
2
Clock Stop
Clock Stop Level
Clksel1
Clksel2
3
4
5
6
I/O enable
7
Description
When set, initiates an activation and a cold reset procedure; when reset, initiates
a deactivation sequence
When set, initiates a warm reset procedure; automatically reset by hardware
when the card starts answering or when the card is declared mute
When set, VCC = 3v; when reset, VCC = 5v. When de-activating (setting bit 0 = 0)
and operating with 3V (bit 2 =1), do not simultaneously set bit 2 =0.
When set, the card clock is stopped. Bit 4 determines the card clock stop level
When set, card clock stops high; when reset card clock stops low
Bits 5 and 6 determine the clock rate to the. See card clock rate selection table
for more details.
I/O enable bit. When set, I/O is transferred on I/OUC; when reset I/O to I/OUC is
high impedance.
Card clock rate selection table
Bit Clksel2
Bit Clksel1
Card Clock
0
0
1
1
0
1
0
1
Clkin/8
Clkin/4
Clkin/2
Clkin (Xtalin)
Page: 5 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
I2C-bus Write to Control Register:
I2C-bus Write command to the control register follows the format shown below. After the START condition, a slave
address is sent by the master. This address is seven bits long followed by an eighth bit which is an opcode bit
(R/W) – a ‘zero’ indicates the master will write data to the control register. After the R/W bit, the ’zero’ ACK bit is
sent to the master by the device. The master now starts sending the 8 bits of data to the control register during
the DATA bits. After the DATA bits, the ‘zero’ ACK bit is sent to the master by the device. The master should send
the STOP condition after receiving this ACK bit.
SDA
MSB
LSB
MSB
LSB
SCL
1-7
START
condition
ADDRESS bits
8
9
R/W bit
ACK bit
1-8
DATA bits
9
ACK bit
STOP
condition
Figure 2 - I2C Bus Write Protocol
STATUS register
Power On Reset = 04h
Name
Bit
PRES
0
Set when the card is present (pin PRES is high); reset when the card is
not present.
PRESL
1
Set when the PRES pin changes state (rising/falling edge); reset when
the status register is read. Generates an interrupt when set.
I/O
2
Set when I/O is high; reset when I/O is low.
SUPL
3
Set when a voltage fault is detected; reset when the status register is
read. Generates an interrupt when set
PROT
4
Set when an over-current or over-heating fault has occurred during a
card session; reset when the status register is read. Generates an
interrupt when set
MUTE
5
Set during ATR when the card has not answered during the ISO 7816-3
time window (40000 card clock cycles); reset when the next session
begins.
EARLY
6
Set during ATR when the card has answered before 400 card clock
cycles; reset when the next session begin.
ACTIVE
7
Set when the card is active (VCC is on); reset when the card is inactive.
Page: 6 of 24
Description
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
I2C-bus Read from Status Register:
I2C-bus Read Command from the Status Register follows the format shown below. After the START condition, a
slave address is sent by the master. This address is seven bits long followed by an eighth bit which is an opcode
bit (R/W) – a ‘one’ indicates the master will read data from the status register. After the R/W bit, the ’zero’ ACK bit
is sent to the master by the device. The device now starts sending the 8-bit status register data to the control
register during the DATA bits. After the DATA bits, the ‘one’ ACK bit is sent to the device by the master. The
master should send the STOP condition after receiving the ACK bit.
SDA
MSB
LSB
MSB
LSB
SCL
1-7
START
condition
ADDRESS bits
8
9
R/W bit
ACK bit
9
1-8
DATA bits
STOP
condition
ACK bit
Figure 3 - I2C Bus Read Protocol
I2C-bus timing definition:
SDA
Tbuf
SCL
Thi
T h d s ta
T sudat
T lo w
Thddat
T s u s to
Figure 4 - I2C Bus Timing Definitions
Symbol
Parameter
Fsclk
Tlow
Thi
Thdsta
Tsudat
Thddat
Tsusto
Clock frequency
Clock low
Clock high
Hold time START condition
Data set up time
Data hold time
Set up time STOP condition
Bus free time between a STOP
and START condition
Tbuf
Page: 7 of 24
Min.
1.3
0.6
0.6
100
5
0.6
1.3
© 2005-2008 TERIDIAN Semiconductor Corporation
Typ.
Max.
Unit
400
kHz
µs
µs
µs
ns
ns
µs
900
µs
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
POWER SUPPLY AND VOLTAGE SUPERVISON
The TERIDIAN 73S8010R smart card interface IC incorporates a LDO voltage regulator. The voltage output is
controlled by the digital input 5V/#V. This regulator is able to provide either 3V or 5V card voltage from the power
supply applied on the VPC pin.
Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to
interface with the system controller.
Three voltage supervisors constantly check the presence of the voltages VDD, VPC and VCC. A card deactivation
sequence is forced upon fault of any of these voltage supervisors. The two voltage supervisors for VPC and VCC
are linked so that a fault is generated to activate a deactivation sequence when the voltage VPC becomes lower
than VCC. It allows the 73S8010R to operate at lower VPC voltage when using 3V cards only.
The voltage regulator can provide a current of at least 90mA on VCC that comply easily with EMV 4.0 specification.
The VPC voltage supervisor threshold values are defined from EMV 4.0 standard. A third voltage supervisor
monitors the VDD voltage. It is used to initialize the ISO-7816-3 sequencer at power-on, and to deactivate the card
at power-off or upon fault. The voltage threshold of the VDD voltage supervisor is internally set by default to 2.3V
nominal. However, it may be desirable, in some applications, to modify this threshold value. The pin VDDF_ADJ
(pin 18 in the SO package, pin 17 in the QFN package) is used to connect an external resistor REXT to ground to
raise the VDD fault voltage to another value VDDF. The resistor value is defined as follows:
REXT= 56kΩ /(VDDF - 2.33)
An alternative method (more accurate) of adjusting the VDD fault voltage is to use a resistive network of R3 from
the pin to supply and R1 from the pin to ground (see applications diagram). In order to set the new threshold
voltage, the equivalent resistance must be determined. This resistance value will be designated Kx. Kx is
defined as R1/(R1+R3). Kx is calculated as:
Kx = (2.789 / VTH) - 0.6125 where VTH is the desired new threshold voltage.
To determine the values of R1 and R3, use the following formulas.
R3 = 24000 / Kx
R1 = R3*(Kx / (1 – Kx))
Taking the example above, where a VDD fault threshold voltage of 2.7V is desired, solving for Kx gives:
Kx = (2.789 / 2.7) - 0.6125 = 0.42046.
Solving for R3 gives:
R3 = 24000 / 0.42046 = 57080.
Solving for R1 gives:
R1 = 57080 *(0.42046 / (1 – 0.42046)) = 41412.
Using standard 1 % resistor values gives R3 = 57.6KΩ and R1 = 42.4KΩ.
These values give an equivalent resistance of Kx = 0.4228, a 0.6% error.
If the 2.3V default threshold is used, this pin must be left unconnected.
Page: 8 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
CARD POWER SUPPLY
The card power supply is provided by the LDO regulator, and controlled by the digital ISO-7816-3 sequencer.
Card voltage selection is carried out by bit 2 of the control register.
Choice of the VCC capacitor:
Depending on the applications, the requirements in terms of both VCC minimum voltage and transient currents that
the interface must be able to provide to the card are different. An external capacitor must be connected between
the VCC pin and to the card ground in order to guarantee stability of the LDO regulator, and to handle the
transient requirements. The type and value of this capacitor can be optimized to meet the desired specification.
The table below shows the recommended capacitors for each VPC power supply configuration and applicable
specification.
Specification Requirements
System Requirements
Min VCC Voltage
allowed during
transient current
Max
transient
current
charge
Min VPC
Power
Supply
required
EMV 4.0
4.6V
30nA.s
4.75V
ISO-7816-3
4.5V
20nA.s
4.75V
Specification
Capacitor
Type
X5R/X7R
w/
ESR < 100mΩ
Capacitor Value
3.3 µF
1µF
Table 1: Choice of VCC pin capacitor
OVER-TEMPERATURE MONITOR
A built-in detector monitors die temperature. Upon over-temperature condition (most likely resulting from a heavily
loaded card interface, including short circuits), a card deactivation sequence is initiated, and a fault condition is
reported to the system controller (sets bit 4 of the status register and generates an interrupt).
ON-CHIP OSCILLATOR AND CARD CLOCK
The TERIDIAN 73S8010R device has an on-chip oscillator that can generate the smart card clock using an
external crystal, connected between the pins XTALIN and XTALOUT, to set the oscillator frequency. When the
card clock signal is available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT
should be left unconnected.
The card clock frequency may be chosen between 4 different division rates, defined by bits 5 and 6 of the I2C
Control register, as per the following table:
Bit
Clksel2
0
0
1
1
Bit
Clksel1
0
1
0
1
Card Clock
Clkin/8
Clkin/4
Clkin/2
Clkin (Xtalin)
Card power down mode (card clock STOP) is supported and is controllable through the dedicated digital inputs
bits 3 and 4 of the I2C Control register, respectively Clock Stop, and Clock Stop Level.
Page: 9 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
ACTIVATION SEQUENCE
After Power on Reset, the signal INT is low until the VDD is stable. When VDD has been stable for approximately
10 ms and the signal INT is high, the system controller may read the status register to see if the card is present. If
all the status bits are satisfied, the system controller can initiate the activation sequence by writing a ‘1’ to
Start/Stop bit (bit 0) of control register.
The following steps show the activation sequence and the timing of the card control signals when the system
controller initiates the Start/Stop bit (bit 0) of the control register:
-
Voltage VCC to the card should be valid by the end of t1. If VCC is not valid for any reason, then the
session is aborted.
Turn I/O to reception mode at the end of t1.
CLK is applied to the card at the end of t2.
RST (to the card) is set high at the end of t3.
Start/Stop
VCC
IO
CLK
RST
t1
t2
t3
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator), I/O in reception mode
t2 =1.5µs, CLK starts
t3 = >42000 card clock cycles, RST set high
Figure 5 - Activation Sequence
Page: 10 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
DEACTIVATION SEQUENCE
Deactivation is initiated either by the system controller by resetting the Start/Stop bit, or automatically in the event
of hardware faults. Hardware faults are over-current, over-temperature, VDD fault, VPC fault, VCC fault, and card
extraction during the session.
The following steps show the deactivation sequence and the timing of the card control signals when the system
controller clears the start/stop bit:
-
RST goes low at the end of t1.
CLK goes low at the end of t2.
I/O goes low at the end of t3. Out of reception mode.
Shut down VCC at the end of time t4.
Start/Stop
RST
CLK
IO
VCC
t1
t1 =
t2 =
t3 =
t4 =
t2
t3
t4
> .5µs
> 7.5µs
> .5µs
> .5µs
Figure 6 - Deactivation Sequence
Page: 11 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
INTERRUPT
Interrupt is an active low interrupt. It is set low if any of these internal faults are detected:
-VCC fault
-VDD fault
-VPC fault
Or if one of these status bits condition is detected:
-Early ATR
-Mute ATR
-Card insert or card extract
-Protection status from Over-current or Over-heating
In case the interrupt is set low by the detection of these status bits, then the interrupt is set high when these
status bits are read. (READ STATUS DONE)
INT
ANY FAULT
STATUS BITS
READ STATUS DONE
Figure 7 - FAULT Functions, INT operation
Note that a power-on-reset event will reset all of the control and status registers to their default states. A VDD fault
event does not reset these registers, but it will signal an interrupt condition and by the action of the timer that
creates interval “t1,” not clearing the interrupt until VDD is valid for at least t1. VDD fault can be considered valid for
VDD as low as 1.5 to 1.8 volts. At the lower range of VDD fault, POR will be asserted.
Page: 12 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
WARM RESET
The 73S8010R automatically asserts a warm reset to the card when instructed through the bit 1 of the I2C Control
register (bit Warm Reset). The warm reset length is automatically defined as 42,000 card clock cycles. The bit
Warm Reset is automatically reset when the card starts answering or when the card is declared mute.
IO
Warm Reset
(bit 1)
RST
t1
t2
t3
t1 > 1.5µs, Warm Reset Starts
t2 = 42000 card clock cycles, End of Warm Reset
t3 = Resets Warm Reset bit 1 when detected ATR or Mute
Figure 8 – Warm Reset operation
Page: 13 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
I/O CIRCUITRY AND TIMING
The states of the I/O, AUX1, and AUX2 pins are low after power-on-reset and they are high when the activation
sequencer enables the I/O reception state. See Activation Sequence timing section for more details on when the
I/O reception is enabled. The states of the I/OUC, AUX1UC, and AUX2UC are high after power on reset. When
the control I/O enable bit 7 of control register is set, the first I/O line on which a falling edge is detected becomes
the input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected then
both I/O lines return to their neutral state. The delay between these signals is shown in Figure 9.
IO
IOUC
tIO_HL
Delay from I/O to I/OUC:
Delay from I/OUC to I/O:
tIO_LH
tIO_HL = 100ns
tIOuc_HL = 100ns
tIOUC_HL
tIOUC_LH
tIO_LH = 25ns
tIOUC_LH = 25ns
Figure 9 - I/O Timing Definition
Page: 14 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010C
Low Cost Smart Card Interface
DATA SHEET
TYPICAL APPLICATION SCHEMATIC
AUX2UC_to/from_uC
AUX1UC_to.from_uC
See NOTE 5
I/OUC_to/from_uC
See note 7
See NOTE 3
SAD0
External_clock_from uC
SAD1
- OR -
SAD2
C2
VDD
VPC
C4
100nF
C5
10uF
See note 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SAD0
SAD1
SAD2
GND
GND
VPC
NC
NC
NC
PRES
I/O
AUX2
AUX1
GND
AUX2UC
AUX1UC
I/OUC
XTALOUT
XTALIN
INT
GND
VDD
SDA
SCL
VDDF_ADJ
VCC
RST
CLK
73S8010R
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Y1
R3
Rext2
CRYSTAL
22pF
C3
22pF
See NOTE 4
See NOTE 1
VDD
C6
R1
Rext1
SO28
100nF
R4
R5
2K
2K
See note 6
INT_interrupt_to_uC
SDA_to/from_uC
SCK_from_uC
VDD
ISO7816=1uF, EMV=3.3uF
Low ESR (<100mohms) C1
should be placed near the SC
connecter contact
8
7
6
5
4
3
2
1
C8
I/O
VPP
GND
C4
CLK
RST
VCC
10
9
C1
SW-2
SW-1
R2
NOTES:
Card detection
1) VDD = 2.7V to 5.5V DC.
20K
switch is
normally closed
2) VPC = 4.75V(EMV, ISO) to 5.5V DC
3) Required if external clock from uP is used.
4) Required if crystal is used.
Y1, C2 and C3 must be removed if external clock is used.
5) Optional. Can be left open.
6) R1 and R3 are external resistors that adjust the VDD
fault voltage. Can be left open.
7) Hardware to define address of device
CLK track should be routed
far from RST, I/O, C4 and
C8.
Smart Card Connector
Figure 10: 73S8010R – Typical Application Schematic
Page: 15 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
ELECTRICAL SPECIFICATION
ABSOLUTE MAXIMUM RATINGS
Operation outside these rating limits may cause permanent damage to the device.
PARAMETER
RATING
Supply Voltage VDD
-0.5 to 6.0 VDC
Supply Voltage VPC
-0.5 to 6.0 VDC
Input Voltage for Digital Inputs
-0.3 to (VDD +0.5) VDC
Storage Temperature
-60 to 150°C
Pin Voltage (except card interface)
-0.3 to (VDD +0.5) VDC
Pin Voltage (card interface)
-0.3 to (VCC + 0.5) VDC
ESD Tolerance – Card interface pins
+/- 6kV
ESD Tolerance – Other pins
+/- 2kV
Note: ESD testing on smart card pins is HBM condition, 3 pulses, each polarity referenced to ground.
RECOMMENDED OPERATING CONDITIONS
Page: 16 of 24
PARAMETER
RATING
Supply Voltage VDD
2.7 to 5.5 VDC
Supply Voltage VPC
4.75 to 5.5 VDC
Ambient Operating Temperature
-40°C to +85°C
Input Voltage for Digital Inputs
0V to VDD + 0.3V
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
CHARACTERISTICS: CARD INTERFACE
SYMBOL
PARAMETER
Condition
MIN
Typ.
MAX
UNIT
-0.1
0.1
V
-0.1
0.4
V
4.60
5.25
V
Card Power Supply (VCC) Regulator
General conditions, -40°C < T < 85°C, 4.75v < VPC < 5.5v, 2.7v < VDD < 5.5v
Inactive mode
VCC
Card supply voltage including
ripple and noise
Inactive mode
ICC = 1mA
Active mode; ICC
<65mA; 5v
Active mode; ICC
<90mA; 5v
Active mode; ICC
<90mA; 3v
Active mode; single
pulse of 100mA for
2µs; 5 volt, fixed load
= 25mA
Active mode; single
pulse of 100mA for
2µs; 3v, fixed load =
25mA
Active mode; current
pulses of 40nAs with
peak |ICC | <200mA,
t <400ns; 5v
Active mode; current
pulses of 40nAs with
peak |ICC | <200mA,
t <400ns; 3v
Static load current,
VCC>4.6 or 2.7 volts
as selected,
4.55
2.80
3.2
V
4.6
5.25
V
2.76
3.2
V
4.6
5.25
V
2.76
3.2
V
ICCmax
Maximum supply current to
the card
ICCF
ICC fault current
VSR
VCC slew rate - Rise rate on
activate
CF = 3.3µF on VCC
0.02
VSF
VCC slew rate - Fall rate on
de-activate
CF = 3.3µF on VCC
CF
External filter capacitor (VCC
to GND)
Page: 17 of 24
V
90
mA
100
150
mA
0.05
0.08
V/µs
0.025
0.06
0.08
V/µs
1
3.3
5
µF
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
SYMBOL
PARAMETER
Condition
MIN
Typ.
MAX
UNIT
Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC.
ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, and AUX2UC.
VOH
Output level, high (I/O,
AUX1, AUX2)
ILEAK
IIL
Output level, high (I/OUC,
AUX1UC, AUX2UC)
Output level, low
Input level, high (I/O, AUX1,
AUX2)
Input level, high (I/OUC,
AUX1UC, AUX2UC)
Input level, low
Output voltage when outside
of session
Input leakage
Input current, low
ISHORTL
Short circuit output current
ISHORTH
Short circuit output current
tR, tF
Output rise time, fall times
tIR, tIF
Input rise, fall times
VOH
VOL
VIH
VIH
VIL
VINACT
Internal pull-up resistor
FDMAX
Maximum data rate
Delay, I/O to I/OUC,
I/OUC to I/O, AUX1 to
AUX1UC, AUX1UC to
AUX1, AUX2 to AUX2UC,
AUX2UC to AUX2
Delay, I/O to I/OUC,
I/OUC to I/O, AUX1 to
AUX1UC, AUX1UC to
AUX1, AUX2 to AUX2UC,
AUX2UC to AUX2
Input capacitance
TRDIO
CIN
Page: 18 of 24
0.9 VCC
0.75 VCC
0.9 VDD
0.75 VDD
VCC+v0.1
VCC + 0.1
VDD+0.1
VDD + 0.1
0.3
V
V
V
V
V
1.8
VCC +0.30
V
1.8
VDD +0.30
V
-0.3
0.8
0.1
0.3
10
0.65
V
V
V
µA
mA
15
mA
15
mA
100
ns
1
µs
14
kΩ
1
MHz
100
200
ns
25
90
ns
10
pF
IOL = 0
IOL = 1mA
VIH = VCC
VIL = 0
For output low,
shorted to VCC
through 33 ohms
For output high,
shorted to ground
through 33 ohms
CL = 80pF, 10% to
90% For I/OUC,
AUX1UC, AUX2UC,
CL=50pF
Output stable for
>200ns
RPU
TFDIO
IOH =0
IOH = -40µA
IOH =0
IOH = -40µA
IOL=1mA
Falling edge from
master to slave
measured at 50%
point
8
60
Rising edge from
master to slave
measured at 50%
point
© 2005-2008 TERIDIAN Semiconductor Corporation
11
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
SYMBOL
PARAMETER
Condition
MIN
IOH =-200µA
IOL=200µA
IOL = 0
IOL = 1mA
0.9 VCC
0
Typ.
MAX
UNIT
VCC
0.3
0.1
0.3
30
70
V
V
V
V
mA
mA
CL = 35pF for CLK,
10% to 90%
8
ns
CL = 200pF for RST,
10% to 90%
100
ns
55
%
MAX
UNIT
0.8
VDD + 0.3
0.45
V
V
V
V
Reset and Clock for card interface, RST, CLK
VOH
VOL
VINACT
IRST_LIM
ICLK_LIM
tR, tF
δ
Output level, high
Output level, low
Output voltage when outside
of session
Output current limit, RST
Output current limit, CLK
Output rise time, fall time
Duty cycle for CLK
CL =35Pf, FCLK
≤ 20MHz
45
Condition
MIN
CHARACTERISTICS: DIGITAL SIGNALS
SYMBOL
PARAMETER
Typ.
Digital I/O except for OSC I/O
VIL
VIH
VOL
VOH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
ROUT
Pull-up resistor, INT
|IIL1|
Input Leakage Current
-0.3
0.7*VDD
IOL = 2mA
IOH = -1mA
VDD - 0.45
20
GND < VIN < VDD
kΩ
-5
5
µA
-0.3
0.7*VDD
0.5
VDD+0.3
V
V
GND < VIN < VDD
-30
30
µA
Condition
MIN
Typ.
MAX
UNIT
1.5
3.0
mA
0.45
0.65
mA
Oscillator (XTALIN) I/O Parameters
VILXTAL
VIHXTAL
IILXTAL
Input Low Voltage - XTALIN
Input High Voltage - XTALIN
Input Current XTALIN
DC CHARACTERISTICS
SYMBOL
PARAMETER
IDD
Supply Current on VDD
IPC
Supply Current on VPC
Page: 19 of 24
VCC on, ICC=0
I/O, AUX1,
AUX2=high
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
CHARACTERISTICS I2C INTERFACE
SYMBOL
PARAMETER
Condition
MIN
Typ.
MAX
UNIT
0.3* VDD
VDD + 0.3
0.40
10
250
V
V
V
pF
V
ns
50
ns
MAX
UNIT
2.4
V
SDA, SCL
VIL
VIH
VOL
CIN
IIN
TF
TSP
Input Low Voltage
Input High Voltage
Output Low Voltage
Pin capacitance
Output High Voltage
Output fall time
-0.3
0.7*VDD
IOL = 3mA
IOH = -1mA
VDD - 0.45
20 + 0.1*CL
CL = 0 to 400pF
Transition from valid
Pulse width of spikes that are
logic level to opposite
suppressed
level
VOLTAGE / TEMPERATURE FAULT DETECTION CIRCUITS
SYMBOL
VDDF
VPCF
VCCF
TF
Page: 20 of 24
PARAMETER
VDD fault
(VDD Voltage supervisor
threshold)
VPC fault
(VPC Voltage supervisor
threshold)
VCC fault
(VCC Voltage supervisor
threshold)
Die over temperature fault
Condition
MIN
No external resistor
on VDDF_ADJ pin
2.15
VPC<VCC, a transient
event
Typ.
VCC - 0.2
V
VCC = 5v
4.20
4.55
V
VCC= 3v
2.5
2.7
V
115
145
°C
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
MECHANICAL DRAWING (QFN)
0 .8 5 N O M . / 0 .9 M A X .
5
0 .0 0 / 0 .0 0 5
2.5
0 .2 0 R E F .
1
2.5
2
3
5
S E A T IN G
PLANE
TOP VIEW
S ID E V IE W
0.35 / 0.45
3.0 / 3.75
0.18 / 0.3
CHAMFERED
0.30
1.5 / 1.875
1
2
3
3.0 / 3.75
0.25
1.5 / 1.875
0.5
0.2 MIN.
0.35 / 0.45
0.5
0.25
BOTTOM VIEW
Figure 11: QFN 32
Page: 21 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
CAUTION: Use handling procedures necessary
for a static sensitive component
PACKAGE PIN DESIGNATION (QFN)
NC
SAD2
SAD1
SAD0
AUX2UC
AUX1UC
I/OUC
NC
32
31
30
29
28
27
26
25
(Top View)
GND
1
24
XTALOUT
GND
2
23
XTALIN
VPC
3
22
INT
NC
4
21
GND
NC
5
20
VDD
NC
6
19
SDA
PRES
7
18
SCL
I/O
8
17
VDDF_ADJ
9
10
11
12
13
14
15
16
NC
AUX2
AUX1
GND
CLK
RST
VCC
NC
TERIDIAN
73S8010R
Figure 12: QFN32 73S8010R Pin Out
Page: 22 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
MECHANICAL DRAWING (SO)
.050 TYP. (1.270)
.305 (7.747)
.285 (7.239)
PIN NO. 1
BEVEL
.715 (18.161)
.695 (17.653)
.420 (10.668)
.390 (9.906)
.0115 (0.29)
.003 (0.076)
.110 (2.790)
.092 (2.336)
.016 nom (0.40)
.335 (8.509)
.320 (8.128)
Figure 13: 28 Lead SO
PACKAGE PIN DESIGNATION (SO)
CAUTION: Use handling procedures necessary
for a static sensitive component
(Top View)
SAD0
1
28
AUX2UC
SAD1
2
27
AUX1UC
SAD2
3
26
I/OUC
GND
4
25
XTALOUT
GND
5
24
XTALIN
VPC
6
23
INT
NC
7
22
GND
NC
8
21
VDD
NC
9
20
SDA
PRES
10
19
SCL
I/O
11
18
VDDF_ADJ
AUX2
12
17
VCC
AUX1
13
16
RST
GND
14
15
CLK
73S8010R
Figure 14: 28SO 73S8010R Pin Out
Page: 23 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8010R
Low Cost Smart Card Interface
DATA SHEET
ORDERING INFORMATION
PART DESCRIPTION
73S8010R -SOL
28-pin Lead-Free SO
73S8010R -SOL
28-pin Lead-Free SO Tape / Reel
73S8010R -QFN
32-pin Lead-Free QFN
73S8010R -QFN
32-pin Lead-Free QFNTape / Reel
ORDER NO.
PACKAGING MARK
73S8010R -IL/F
73S8010R -IL
73S8010R -ILR/F
73S8010R -IL
73S8010R -IM/F
73S8010R
73S8010R -IMR/F
73S8010R
Data Sheet
This final data sheet is proprietary to TERIDIAN Semiconductor Corporation (TSC) and sets forth design goals for the
described product. The data sheet is subject to change. TSC assumes no obligation regarding future manufacture, unless
agreed to in writing. If and when manufactured and sold, this product is sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of
liability. TERIDIAN Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time
without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes
no liability for applications assistance.
TERIDIAN Semiconductor Corp. • 6440 Oak Canyon, Suite 100 • Irvine, CA • 92618-5201
TEL (714) 508-8800 • FAX (714) 508-8877
http://www.teridian.com
01/17/08 Rev 1.5
Page: 24 of 24
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 1.5