TERIDIAN 73S8014R-IL/F

73S8014R
Smart Card Interface
Simplifying System Integration™
DATA SHEET
September 2008
APPLICATIONS
DESCRIPTION
The Teridian 73S8014R is a single smart card (ICC) interface
circuit, firmware compatible with 8024-type devices for
configurations where only asynchronous cards must be
supported. It is derived from the 73S8024RN industrystandard electrical interface. The 73S8014R has been
optimized to match most of the typical Set-Top-Box / A/V
Conditional Access applications. Optimization essentially
involved a smaller pin-count, support for single I/O, and
maximum card current of 65mA (ISO-7816 / EMV
compliance).
The 73S8014R interfaces with the host processor through the
same bus (digital I/Os) as the 73S8024RN, which is
compatible with any other 8024-type IC. As a result, the
73S8014R is a very attractive cost-reduction path from
traditional 8024 ICs. The 73S8014R has been designed to
provide full electrical compliance with ISO 7816-3 and EMV
4.0 specifications.
•
•
ADVANTAGES
•
•
•
•
•
Card Interface:
ƒ Complies with ISO 7816-3 and EMV 4.0
ƒ Supports 3V / 5V cards
ƒ ISO 7816-3 Activation / Deactivation sequencer
ƒ Automated deactivation upon hardware fault (i.e. upon
drop on VDD power supply or card overcurrent)
ƒ The VDD voltage supervisor threshold value (fault) can
be externally adjusted
ƒ Over-current detection 130mA max
ƒ Card CLK clock frequency up to 20MHz
•
System Controller Interface:
ƒ 3 Digital inputs control the card activation /
deactivation, card reset and card voltage
ƒ 2 Digital inputs control the card clock frequency
ƒ 1 Digital output, interrupt to the system controller,
reports to the host the card presence and faults
ƒ Crystal oscillator or host clock, up to 27MHz
•
Regulator Power Supply:
ƒ 4.75V to 5.5V
•
Digital Interfacing: 2.7V to 5.5V
•
•
•
6kV ESD protection on the card interface
Package: SO 20-pin
RoHS compliant (6/6) lead-free package
The card clock can be generated by an on-chip oscillator
using an external crystal or by connection to an externally
supplied clock signal.
Emergency card deactivation is initiated upon card extraction
or upon any fault detected by the protection circuitry. The
fault can be a card over-current, VCC undervoltage or power
supply fault (VDD). The card over-current circuitry is a true
current detection function, as opposed to VCC voltage drop
detection, as usually implemented in non-Teridian 8024
interface ICs.
Same advantages as the Teridian 73S80xxR family:
ƒ VCC card generated by an LDO regulator
ƒ Very low power dissipation (saves up to 1/2W)
ƒ Fewer external components are required
ƒ Better noise performance
True card over-current detection
Firmware compatibility with all 8024 ICs
Small format 20SO package
FEATURES
Interfacing with the system controller is done through a
control bus, composed of digital inputs to control the
interface, and one interrupt output to inform the system
controller of the card presence and faults.
The 73S8014R incorporates an ISO 7816-3
activation/deactivation sequencer that controls the card
signals. Level-shifters drive the card signals with the
selected card voltage (3V or 5V), coming from an internal
Low Drop-Out (LDO) voltage regulator. This LDO regulator is
powered by a dedicated power supply input VPC. Digital
circuitry is powered separately by a digital power supply VDD.
With its embedded LDO regulator, the 73S8024RN is a
cost-effective solution for any application where a 5V
(typically -5% +10%) power supply is available.
Set-Top-Box Conditional Access and Pay-per-View
General purpose smart card readers
The VDD voltage fault has a threshold voltage that can be
adjusted with an external resistor network. It allows
automated card deactivation at a customized VDD voltage
threshold value. It can be used, for instance, to match the
system controller operating voltage range.
Rev. 1.0
© 2008 Teridian Semiconductor Corporation
1
73S8014R Data Sheet
DS_8014R_012
FUNCTIONAL DIAGRAM
VDD
VPC
vdd circuits
VCC FAULT
VDDF_ADJ
INTERNAL POWER SUPPLY
VOLTAGE REFERENCE
VDD FAULT
vref
LDO
REGULATOR
bias currents
VPD - internal supply
CMDVCC
CONTROLLER
AND
REGISTERS
RSTIN
5V/#V
TEST
1.5MHz
R-C
OSC.
GND
VCC
FAULT LOGIC
RESET
BUFFER
RST
CLOCK
BUFFER
CLK
OFF
SC
SEQUENCER
CKDIV1
CKDIV2
CLOCK
XTALIN
XTAL
OSC
CLOCK
GENERATION
VDD CKT
PRES
XTALOUT
vdd circuits
I/O
SMART CARD I/O BUFFER
IOUC
vcc circuits
GND
Figure 1: 73S8014R Block Diagram
2
Rev. 1.0
DS_8014R_012
73S8014R Data Sheet
Table of Contents
1 2 Pinout ................................................................................................................................................................ 5 Electrical Specifications .................................................................................................................................. 8 2.1 Absolute Maximum Ratings ........................................................................................................................ 8 2.2 Recommended Operating Conditions ......................................................................................................... 8 2.3 Package Thermal Parameters .................................................................................................................... 9 2.4 Smart Card Interface Requirements ........................................................................................................... 9 2.5 Characteristics: Digital Signals.................................................................................................................. 11 2.6 DC Characteristics .................................................................................................................................... 12 2.7 Voltage Fault Detection Circuits ................................................................................................................ 13 3 Applications Information ............................................................................................................................... 14 3.1 Example 73S8014R Schematics .............................................................................................................. 14 3.2 System Controller Interface....................................................................................................................... 16 3.3 Power Supply and Voltage Supervision .................................................................................................... 16 3.4 Card Power Supply ................................................................................................................................... 17 3.5 On-Chip Oscillator and Card Clock ........................................................................................................... 17 3.6 Activation Sequence ................................................................................................................................. 18 3.7 Deactivation Sequence ............................................................................................................................. 19 3.8 Fault Detection and OFF ........................................................................................................................... 20 3.9 I/O Circuitry and Timing ............................................................................................................................ 20 4 Equivalent Circuits ......................................................................................................................................... 22 5 Mechanical Drawing ....................................................................................................................................... 27 6 Ordering Information ..................................................................................................................................... 28 7 Related Documentation ................................................................................................................................. 28 8 Contact Information ....................................................................................................................................... 28 Rev. 1.0
3
73S8014R Data Sheet
DS_8014R_012
Figures
Figure 1: 73S8014R Block Diagram .......................................................................................................................... 2 Figure 2: 73S8014R 20-SOP Pin Out........................................................................................................................ 5 Figure 3: 73S8014R – Typical Application Schematic ............................................................................................ 15 Figure 4: Activation Sequence – RSTIN Low When CMDVCC Goes Low ............................................................. 18 Figure 5: Activation Sequence – RSTIN High When CMDVCC Goes Low............................................................. 19 Figure 6: Deactivation Sequence ............................................................................................................................ 19 Figure 7: Timing Diagram – Management of the Interrupt Line OFF ...................................................................... 20 Figure 8: I/O and I/OUC State Diagram................................................................................................................... 21 Figure 9: I/O – I/OUC Delays – Timing Diagram ..................................................................................................... 21 Figure 10: Open Drain type – OFF .......................................................................................................................... 22 Figure 11: Power Input/Output Circuit, VDD, VPC, VCC ........................................................................................ 22 Figure 12: Smart Card CLK Driver Circuit ............................................................................................................... 23 Figure 13: Smart Card RST Driver Circuit ............................................................................................................... 23 Figure 14: Smart Card IO Interface Circuit .............................................................................................................. 24 Figure 15: Smart Card IOUC Interface Circuit ......................................................................................................... 24 Figure 16: General Input Circuit .............................................................................................................................. 25 Figure 17: Oscillator Circuit ..................................................................................................................................... 25 Figure 18: VDDF_ADJ ............................................................................................................................................. 26 Figure 19: Mechanical Drawing 20-Pin SO Package .............................................................................................. 27 Tables
Table 1: 73S8014R 20-Pin SOP Pin Definitions ....................................................................................................... 6 Table 2: Absolute Maximum Device Ratings ............................................................................................................. 8 Table 3: Recommended Operating Conditions ......................................................................................................... 8 Table 4: Package Thermal Parameters ..................................................................................................................... 9 Table 5: DC Smart Card Interface Requirements ..................................................................................................... 9 Table 6: Digital Signals Characteristics ................................................................................................................... 11 Table 7: DC Characteristics ..................................................................................................................................... 12 Table 8: Voltage Fault Detection Circuits ................................................................................................................ 13 Table 9: Order Numbers and Packaging Marks ...................................................................................................... 28 4
Rev. 1.0
DS_8014R_012
73S8014R Data Sheet
1 Pinout
The 73S8014R is supplied as a 20-pin SO package.
OFF
1
20
CLKDIV1
RSTIN
2
19
PRES
I/OUC
3
18
VCC
VPC
4
17
CLK
CLKDIV2
5
16
GND
CMDVCC
6
15
RST
5V/#V
7
14
I/O
GND
8
13
VDD
XTALIN
9
12
VDDF_ADJ
10
11
GND
XTALOUT
73S8014R
Figure 2: 73S8014R 20-SOP Pin Out
Rev. 1.0
5
73S8014R Data Sheet
DS_8014R_012
Table 1 provides the 73S8014R pin names, pin numbers, type, equivalent circuits and descriptions.
Table 1: 73S8014R 20-Pin SOP Pin Definitions
Pin Name
Pin
Number Type
Equivalent
Circuit
Description
Card Interface
I/O
14
IO
Figure 14
Card I/O: Data signal to/from card. Includes an 11k pull-up
resistor to VCC.
RST
15
O
Figure 13
Card reset: provides reset (RST) signal to card.
CLK
17
O
Figure 12
Card clock: provides clock signal (CLK) to card. The rate of this
clock is determined by the external crystal frequency or frequency
of the external clock signal applied on XTALIN and CLKDIV
selections.
PRES
19
I
Figure 16
Card Presence switch: active high indicates card is present.
Includes a high-impedance pull-down current source.
VCC
18
PSO
Figure 11
Card power supply – logically controlled by sequencer, output of
LDO regulator. Requires an external filter capacitor to the card
GND.
GND
16
GND
–
Card ground.
Host Processor Interface
CMDVCC
5V/#V
6
7
I
I
Figure 16
Command VCC (negative assertion): Logic low on this pin causes
the LDO regulator to ramp the VCC supply to the card and initiates
a card activation sequence, if a card is present.
Figure 16
5 volt / 3 volt card selection: Logic one selects 5 volts for VCC and
card interface, logic low selects 3 volt operation. When the part is
to be used with a single card voltage, this pin should be tied to
either GND or VDD. However, it includes a high impedance pull-up
resistor to default this pin high (selection of 5V card) when not
connected. This pin shall not be changed when CMDVCC is low.
Sets the divide ratio from the XTAL oscillator (or external clock
input) to the card clock. These pins include a pull-up resistor for
CLKDIV1 and CLKLDIV2 to provide a default rate of divide by
two.
CLKDIV1
CLKDIV2
20
5
I
Figure 16
CLKDIV1
CLKDIV2
CLOCK RATE
0
0
XTALIN/8
0
1
XTALIN/4
1
1
XTALIN/2
1
0
XTALIN
OFF
1
O
Figure 10
Interrupt signal to the processor. Active Low - Multi-function
indicating fault conditions and card presence. Open drain output
configuration – It includes an internal 20kΩ pull-up to VDD.
RSTIN
2
I
Figure 16
Reset Input: This signal is the reset command to the card.
I/OUC
3
IO
Figure 15
System controller data I/O to/from the card. Includes an 11K
pull-up resistor to VDD.
6
Rev. 1.0
DS_8014R_012
73S8014R Data Sheet
Miscellaneous Inputs and Outputs
XTALIN
9
Figure 17
Crystal oscillator input: can either be connected to crystal or
driven as a source for the card clock. Note: When not using the
crystal, the capacitors must be removed.
XTALOUT
10
Figure 17
Crystal oscillator output: connected to crystal. Left open if
XTALIN is being used as external clock input. Note: When not
using the crystal, the capacitors must be removed.
VDDF_ADJ
12
Figure 18
VDD fault threshold adjustment input: this pin can be used to adjust
the VDDF value (that controls deactivation of the card). Must be
left open if unused.
Power Supply and Ground
VDD
13
PSO
Figure 11
System interface supply voltage and supply voltage for internal
circuitry.
VPC
4
PSO
Figure 11
LDO regulator power supply source.
GND
8, 11
GND
–
Rev. 1.0
Digital ground.
7
73S8014R Data Sheet
DS_8014R_012
2 Electrical Specifications
This section provides the following:
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
2.1
Absolute maximum ratings
Recommended operating conditions
Package thermal parameters
Smart card interface requirements
Digital signals characteristics
DC Characteristics
Voltage Fault Detection Circuits
Absolute Maximum Ratings
Table 2 lists the maximum operating conditions for the 73S8014R. Permanent device damage may occur if
absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended
periods may affect device reliability. The smart card interface pins are protected against short circuits to VCC,
ground, and each other.
Table 2: Absolute Maximum Device Ratings
Parameter
Rating
Supply Voltage VDD
-0.5 to 6.0 VDC
Supply Voltage VPC
-0.5 to 6.0 VDC
Input Voltage for Digital Inputs
-0.3 to (VDD +0.5) VDC
Storage Temperature
-60 to 150°C
Pin Voltage (except card interface)
-0.3 to (VDD +0.5) VDC
Pin Voltage (card interface)
-0.3 to (VCC + 0.5) VDC
ESD Tolerance – Card interface pins
+/- 6kV
ESD Tolerance – Other pins
+/- 2kV
*Note: ESD testing on smart card pins is HBM condition, 3 pulses, each polarity referenced to ground.
Note: Smart Card pins are protected against shorts between any combinations of Smart Card pins.
2.2
Recommended Operating Conditions
Function operation should be restricted to the recommended operating conditions specified in Table 3.
Table 3: Recommended Operating Conditions
8
Parameter
Rating
Supply Voltage VDD
2.7 to 5.5 VDC
Supply Voltage VPC
4.75 to 5.5 VDC
Ambient Operating Temperature
-40°C to +85°C
Input Voltage for Digital Inputs
0V to VDD + 0.3V
Rev. 1.0
DS_8014R_012
2.3
73S8014R Data Sheet
Package Thermal Parameters
Table 4 lists the 73S8014R Smart Card interface requirements.
Table 4: Package Thermal Parameters
2.4
Parameter
Rating
20 SO
50 °C / W
Smart Card Interface Requirements
Table 5 lists the 73S8014R Smart Card interface requirements.
Table 5: DC Smart Card Interface Requirements
Symbol
Parameter
Condition
Min
Nom
Max
Unit
Card Power Supply (VCC) Regulator
General conditions, -40°C < T < 85°C, 4.75V < VPC < 5.5V, 2.7V < VDD < 5.5V
VCC
Card supply voltage
including ripple and
noise
Inactive mode
-0.1
0.1
V
Inactive mode, ICC = 1mA
-0.1
0.4
V
Active mode; ICC <65mA; 5V
4.65
5.25
V
Active mode; ICC <65mA; 3V
2.85
3.15
V
Active mode; ICC <40mA; 1.8V
1.68
1.92
V
Active mode; single pulse of 100mA for
2μs; 5 volt, fixed load = 25mA
4.6
5.25
V
Active mode; single pulse of 100mA for
2μs; 3v, fixed load = 25mA
2.76
3.2
V
Active mode; current pulses of 40nAs
with peak |ICC | <200mA,
t <400ns; 5V
4.6
5.25
V
Active mode; current pulses of 40nAs
with peak |ICC | <200mA,
t <400ns; 3V
2.7
3.15
V
350
mV
VCCrip
VCC Ripple
fRIPPLE = 20K – 200MHz
ICCmax
Card supply output
current
Static load current, VCC>4.6V or 2.7V
as selected
ICCF
ICC fault current
VSR
VCC slew rate, rise
CF = 1.0μF on VCC
0.06
VSF
VCC slew rate, fall
CF = 1.0μF on VCC
CF
External filter cap
(VCC to GND)
CF should be ceramic with low ESR
(<100mΩ).
Rev. 1.0
65
mA
70
130
mA
0.150
0.30
V/μs
0.075
0.150
0.60
V/μs
0.5
1.0
1.5
μF
9
73S8014R Data Sheet
Symbol
DS_8014R_012
Parameter
Condition
Min
Nom
Max
Unit
Interface Requirements – Data Signals: I/Oand host interfaces: I/OUC.
ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC.
IOH =0
0.9 VCC
VCC+0.1
V
IOH = -40μA
0.75 VCC
VCC+0.1
V
IOH =0
0.9 VDD
VDD+0.1
V
IOH = -40μA
0.75 VDD
VDD+0.1
V
0.15 VCC
V
0.3
V
0.6 VCC
VCC+0.30
V
1.8
VDD + 0.3
V
Input level, low (I/O)
-0.15
0.2 VCC
V
Input level, low (I/OUC)
-0.3
0.8
V
IOL = 0
0.1
V
IOL = 1mA
0.3
V
VIH = VCC
10
μA
VIL = 0
0.65
mA
Output level, high (I/O)
VOH
Output level, high (I/OUC)
VOL
VIH
VIL
Output level, low (I/O)
Output level, low (I/OUC)
IOL=1mA
Input level, high (I/O)
Input level, high (I/OUC)
VINACT
Output voltage when outside
of session
ILEAK
Input leakage
IIL
Input current, low
ISHORTL
Short circuit output current
For output low,
shorted to VCC
through 33 Ω
15
mA
ISHORTH
Short circuit output current
For output high,
shorted to ground
through 33 Ω
15
mA
tR, tF
Output rise time, fall times
100
ns
tIR, tIF
Input rise, fall times
1
μs
RPU
Internal pull-up resistor
14
kΩ
FDMAX
Maximum data rate
1
MHz
200
ns
TFDIO
TRDIO
CIN
10
Delay, I/O to I/OUC,
I/OUC to I/O, (respectively
falling edge to falling edge
and rising edge to rising
edge)
Input capacitance
CL = 80pF, 10% to
90%.
Output stable for
>400ns
Edge from master to
slave, measured at
50%
8
60
11
100
15
ns
10
pF
Rev. 1.0
DS_8014R_012
Symbol
73S8014R Data Sheet
Parameter
Condition
Min
Nom
Max
Unit
Reset and Clock for card interface, RST, CLK
VOH
Output level, high
IOH =-200μA
0.9 VCC
VCC
V
VOL
Output level, low
IOL=200μA
0
0.15 VCC
V
VINACT
Output voltage when outside
of session
IOL = 0
0.1
V
IOL = 1mA
0.3
V
IRST_LIM
Output current limit, RST
30
mA
ICLK_LIM
Output current limit, CLK
70
mA
CLKSR3V
CLK slew rate
Vcc = 3V
0.3
V/ns
CLKSR5V
CLK slew rate
Vcc = 5V
0.5
V/ns
tR, tF
Output rise time, fall time
δ
2.5
CL = 35pF for CLK,
10% to 90%
8
ns
CL = 200pF for RST,
10% to 90%
100
ns
55
%
Max
Unit
CL =35pF,
FCLK ≤ 20MHz
Duty cycle for CLK
45
Characteristics: Digital Signals
Table 6 lists the 73S8014R digital signals characteristics.
Table 6: Digital Signals Characteristics
Symbol
Parameter
Condition
Min
Nom
Digital I/O except for XTALIN and XTALOUT
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
1.8
VDD + 0.3
V
VOL
Output Low Voltage
IOL = 2mA
0.45
V
VOH
Output High Voltage
IOH = -1mA
ROUT
Pull-up resistor, OFF
|IIL1|
Input Leakage Current
Rev. 1.0
VDD - 0.45
16
GND < VIN < VDD
-5
V
20
24
kΩ
5
μA
11
73S8014R Data Sheet
DS_8014R_012
Oscillator (XTALIN) I/O Parameters
VILXTAL
Input Low Voltage - XTALIN
-0.3
0.3 VDD
V
VIHXTAL
Input High Voltage - XTALIN
0.7 VDD
VDD+0.3
V
IILXTAL
Input Current XTALIN
-30
30
μA
fMAX
Max freq. Osc or external
clock
27
MHz
δin
External input duty cycle limit
52
%
Nom
Max
Unit
12 MHz XTAL
2.7
7.0
mA
Ext CLK,
VDD = 2.7 – 3.6V,
VCC Off
1.7
2.6
GND < VIN < VDD
tR/F < 10% fIN,
45% < δCLK < 55%
48
DC Characteristics
Table 7 lists the 73S8014R DC characteristics.
Table 7: DC Characteristics
Symbol
Parameter
IDD
Supply Current
IPC
Supply Current
IPCOFF
VPC supply current when
VCC = 0
12
Condition
Min
mA
Ext CLK,
VDD = 2.7 – 3.6V,
VCC On
mA
2.2
Ext CLK,
VDD = 4.5 – 5.5V,
VCC Off
2.7
mA
Ext CLK,
VDD = 4.5 – 5.5V,
VCC On
3
mA
VCC on, ICC=0
I/O, AUX1,
AUX2=high,
Clock not toggling
450
700
μA
CMDVCC High
345
650
μA
Rev. 1.0
DS_8014R_012
2.7
73S8014R Data Sheet
Voltage Fault Detection Circuits
Table 8 lists the 73S8014R Voltage Fault Detection Circuits.
Table 8: Voltage Fault Detection Circuits
Symbol
Parameter
VDDF
VDD fault
(VDD Voltage supervisor
threshold)
VCCF
VCC fault
(VCC Voltage supervisor
threshold)
Rev. 1.0
Condition
Min
No external resistor
on VDDF_ADJ pin
2.15
Nom
Max
Unit
2.4
V
VCC = 5v
4.6
V
VCC= 3v
2.7
V
13
73S8014R Data Sheet
DS_8014R_012
3 Applications Information
This section provides general usage information for the design and implementation of the 73S8014R. The
documents listed in Related Documentation provide more detailed information.
3.1
Example 73S8014R Schematics
Figure 3 shows a typical application schematic for the implementation of the 73S8014R. Note that minor changes
may occur to the reference material from time to time and the reader is encouraged to contact Teridian for the
latest information.
14
Rev. 1.0
DS_8014R_012
73S8014R Data Sheet
CLKDIV1_from_uC
OFF_interrupt_to_uC
RSTIN_from_uC
See
note 5
I/OUC_to/from_uC
VDD
CLKDIV2_from_uC
VPC
100nF
See NOTE 2
C4
1
2
3
4
5
6
7
8
9
10
10uF
C5
22pF
C2
CRYSTAL
Y1
CMDVCC_from_uC
22pF
5V/#V_select_from_uC
OFF
RSTIN
I/OUC
VPC
CLKDIV2
CMDVCC
5V3V
GND
XTALIN
XTALOUT
CLKDIV1
PRES
VCC
CLK
GND
RST
I/O
VDD
VDDF_ADJ
TEST
R3
Rext2
20
19
18
17
16
15
14
13
12
11
VDD
See NOTE 1
C6
R1
Rext1
73S8014R
C3
100nF
See NOTE 4
See NOTE 3
- OR -
External_clock_from uC
R2
47K
5) R1 and R3 are external resistors that adjust the VDD
fault voltage. Can be left open.
10
9
EMV & ISO7816=1uF
Low ESR (<100mohms) C1
should be placed near the SC
connecter contact
8
7
6
5
4
3
2
1
C8
I/O
VPP
GND
C4
CLK
RST
VCC
normally open
C1
SW-2
SW-1
NOTES:
1) VDD = 2.7V to 5.5V DC.
VDD
2) VPC = 4.75V to 5.5V DC
R4
3) Required if external clock from uP is used.
10K
4) Required if crystal is used.
Card detection
Y1, C2 and C3 must be removed if external clock is used. switch is
CLK track should be routed
far from RST, I/O, C4 and
C8.
Smart Card Connector
Figure 3: 73S8014R – Typical Application Schematic
Rev. 1.0
15
73S8014R Data Sheet
3.2
DS_8014R_012
System Controller Interface
Three digital inputs allow direct control of the card interface by the host. The 73S8014R is controlled as follows:
ƒ
ƒ
ƒ
Pin CMDVCC: When asserted low, starts an activation sequence
Pin RSTIN: controls the card RST signal (when enabled by the sequencer)
Pin 5V/#V: Defines the card VCC voltage (5V when high and 3V when low)
Card clock frequency can be controlled by 2 digital inputs:
ƒ
CLKDIV1 and CLKDIV2 define the division rate for the clock frequency, from the input clock frequency (crystal
or external clock)
Note: The maximum CLK frequency is 20MHz. Therefore, if using an input clock source greater than 20MHz, a
divisor rate of 2X or higher must be used.
Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about the card
presence only (Low = No card in the reader). When CMDVCC is asserted low (Card activation sequence
requested from the host), low level on OFF means a fault has been detected (e.g. card removal during card
session, voltage fault, or over-current fault) that automatically initiates a deactivation sequence.
3.3
Power Supply and Voltage Supervision
The 73S8014R smart card interface IC incorporates a LDO voltage regulator. The voltage output is controlled by
the digital input 5V/#V of the 73S8014R. This regulator is able to provide either 3V or 5V card voltage from the
power supply applied on the VPC pin. The voltage regulator can provide a current of at least 65mA on VCC for
both 3V and 5V that complies with EMV 4.0.
Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to
interface with the system controller. A card deactivation sequence is forced upon fault of any of this voltage
supervisor. One voltage supervisor constantly monitors the VDD voltage. It is used to initialize the ISO 7816-3
sequencer at power-on, and to deactivate the card at power-off or upon fault. The voltage threshold of the VDD
voltage supervisor is internally set by default to 2.33V nominal. However, it may be desirable, in some
applications, to modify this threshold value. The pin VDDF_ADJ is used to connect an external resistor REXT to
ground to change the VDD fault voltage to another value, VDDF. The resistor value is defined as follows:
REXT = 56kΩ /(VDDF - 2.33)
An alternative (more accurate) method of adjusting the VDD fault voltage is to use a resistive network of R3 from
the pin to supply and R1 from the pin to ground (see Figure 3). In order to set the new threshold voltage, the
equivalent resistance must be determined. This resistance value will be designated Kx. Kx is defined as
R1/(R1+R3). Kx is calculated as:
Kx = (2.789 / VTH) - 0.6125 where VTH is the desired new threshold voltage.
To determine the values of R1 and R3, use the following formulas.
R3 = 24000 / Kx
R1 = R3*(Kx / (1 – Kx))
Taking the example above, where a VDD fault threshold voltage of 2.7V is desired, solving for Kx gives:
Æ Kx = (2.789 / 2.7) - 0.6125 = 0.42046.
Solving for R3 gives:
Æ R3 = 24000 / 0.42046 = 57080.
Solving for R1 gives:
Æ R1 = 57080 *(0.42046 / (1 – 0.42046)) = 41412.
Using standard 1 % resistor values gives R3 = 57.6KΩ and R1 = 42.4KΩ.
These values give an equivalent resistance of Kx = 0.4228, a 0.6% error.
If the 2.33V default threshold is used, this pin must be left unconnected.
16
Rev. 1.0
DS_8014R_012
3.4
73S8014R Data Sheet
Card Power Supply
The card power supply is internally provided by the LDO regulator, and controlled by the digital ISO 7816-3
sequencer. Card voltage selection on the 73S8014R is carried out by the digital input 5V/#V.
Choice of the VCC capacitor:
Depending on the application, the requirements in terms of both VCC minimum voltage and transient currents that
the interface must be able to provide to the card are different. An external capacitor must be connected between
the VCC pin and to the card ground in order to guarantee stability of the LDO regulator, and to handle the
transient requirements. The type of capacitor should be an X5R/X7R with ERS<100 mΩ.
3.5
On-Chip Oscillator and Card Clock
The 73S8014R device has an on-chip oscillator that can generate the smart card clock using an external crystal
(connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. When the clock signal is
available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT should be left
unconnected.
The card clock frequency may be chosen between 4 different division rates, defined by digital inputs CLKDIV 1
and CLKDIV 2, as per the following table:
Rev. 1.0
CLKDIV1
CLKDIV2
CLK
Max XTALIN
0
0
1/8 XTALIN
27MHz
0
1
¼ XTALIN
27MHz
1
0
XTALIN
20MHz
1
1
½ XTALIN
27MHz
17
73S8014R Data Sheet
3.6
DS_8014R_012
Activation Sequence
The 73S8014R smart card interface ICs have an internal 10ms delay on the application of VDD where VDD >
VDDF. No activation is allowed during this 10ms period. The CMDVCC (edge triggered) signal must then be set
low to activate the card. In order to initiate activation, the card must be present; there can be no VDD fault.
The following steps show the activation sequence and the timing of the card control signals when the system
controller sets CMDVCC low while the RSTIN is low:
-
-
CMDVCC is set low at t0.
VCC will rise to the selected level and then the internal VCC control circuit checks the presence of VCC at
the end of t1. In normal operation, the voltage VCC to the card becomes valid before t1. If VCC is not
valid at t1, the OFF goes low to report a fault to the system controller, and VCC to the card is shut off.
Turn I/O to reception mode at t2.
CLK is applied to the card at t3.
RST is a copy of RSTIN after t3.
CMDVCC
VCC
I/O
CLK
RSTIN
RST
t0
t1
t2
t3
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)
t2 = 1.5μs, I/O goes to reception state
t3 = >0.5μs, CLK starts, RST to become the copy of RSTIN
Figure 4: Activation Sequence – RSTIN Low When CMDVCC Goes Low
The following steps show the activation sequence and the timing of the card control signals when the system
controller pulls the CMDVCC low while the RSTIN is high:
-
-
18
CMDVCC is set low at t0.
VCC will rise to the selected level and then the internal VCC control circuit checks the presence of VCC at
the end of t1. In normal operation, the voltage VCC to the card becomes valid before t1. If VCC is not
valid at t1, the OFF goes low to report a fault to the system controller, and VCC to the card is shut off.
At the fall of RSTIN at t2, CLK is applied to the card
RST is a copy of RSTIN after t2.
Rev. 1.0
DS_8014R_012
73S8014R Data Sheet
CMDVCC
VCC
I/O
CLK
RSTIN
RST
t0
t1
t2
t1 = 0.510 ms (timing by 1.5MHz internal oscillator, I/O goes to reception state)
t2 = RSTIN goes low and CLK becomes active
t3 = > 0.5μs, CLK active, RST to become the copy of RSTIN
Figure 5: Activation Sequence – RSTIN High When CMDVCC Goes Low
3.7
Deactivation Sequence
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in the event of
hardware faults. Hardware faults are over-current, VDD fault, VCC fault, and card extraction during the session.
The following steps show the deactivation sequence and the timing of the card control signals when the system
controller sets the CMDVCC high or OFF goes low due to a fault or card removal:
-
RST goes low at the end of t1.
CLK is set low at the end of t2.
I/O goes low at the end of t3. Out of reception mode.
VCC is shut down at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low.
CMDVCC
-- OR --
OFF
RST
CLK
I/O
VCC
t1
t1 =
t2 =
t3 =
t4 =
t5 =
t2
t3
t4
t5
> 0.5μs, timing by 1.5MHz internal Oscillator
> 7.5μs
> 0.5μs
> 0.5μs
depends on VCC filter capacitor.
Figure 6: Deactivation Sequence
Rev. 1.0
19
73S8014R Data Sheet
3.8
DS_8014R_012
Fault Detection and OFF
There are two different cases that the system controller can monitor the OFF signal: to query regarding the card
presence outside card sessions, or for fault detection during card sessions.
Outside a card session: In this condition, CMDVCC is/are always high, OFF is low if the card is not present, and
high if the card is present. Because it is outside a card session, any fault detection will not act upon the OFF
signal. No deactivation is required during this time.
During a card session: CMDVCC is/are always low, and OFF falls low if the card is extracted or if any fault
detection is detected. At the same time that OFF is set low, the sequencer starts the deactivation process.
Figure 7 shows the timing diagram for the signals CMDVCC, PRES, and OFF during a card session and outside
e
the card session:
OFF is low by
card extracted
OFF is low by
any fault
PRES
OFF
CMDVCC
VCC
outside card session
within card session
within card
session
Figure 7: Timing Diagram – Management of the Interrupt Line OFF
3.9
I/O Circuitry and Timing
The state of the I/O pin is low after power on reset and it goes high when the activation sequencer turns on the
I/O reception state. See the Activation Sequence section for details on when the I/O reception is enabled. The
state of I/OUC is high after power on reset.
Within a card session and when the I/O reception state is turned on, the first I/O line on which a falling edge is
detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising
edge is detected then both I/O lines return to their neutral state.
Figure 8 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output. The
delay between the I/O signals is shown in Figure 9.
20
Rev. 1.0
DS_8014R_012
73S8014R Data Sheet
Neutral
State
No
I/O
reception
Yes
I/O
&
not I/OUC
No
Yes
No
I/OUC
&
not I/O
Yes
I/OUC
in
I/OICC
in
No
No
I/OUC
I/O
yes
yes
Figure 8: I/O and I/OUC State Diagram
I/O
I/OUC
tI/O_HL
Delay from I/O to I/OUC:
Delay from I/OUC to I/O:
tI/O_LH
tI/O_HL = 100ns
tI/OUC_HL = 100ns
tI/OUC_HL
tI/OUC_LH
tI/O_LH = 25ns
tI/OUC_LH = 25ns
Figure 9: I/O – I/OUC Delays – Timing Diagram
Rev. 1.0
21
73S8014R Data Sheet
DS_8014R_012
4 Equivalent Circuits
This section provides illustrations of circuits equivalent to those described in the pinout section.
VDD
Output
Disable
20K
PIN
Data
From
circuit
ESD
STRONG
NFET
Figure 10: Open Drain type – OFF
To
Internal
circuits
PIN
ESD
Figure 11: Power Input/Output Circuit, VDD, VPC, VCC
22
Rev. 1.0
DS_8014R_012
73S8014R Data Sheet
VCC
VERY
STRONG
PFET
ESD
From
circuit
CLK
PIN
VERY
STRONG
NFET
ESD
Figure 12: Smart Card CLK Driver Circuit
VCC
STRONG
PFET
ESD
From
circuit
RST
PIN
ESD
STRONG
NFET
Figure 13: Smart Card RST Driver Circuit
Rev. 1.0
23
73S8014R Data Sheet
DS_8014R_012
VCC
ESD
STRONG
PFET
RL=11K
400ns
DELAY
From
circuit
IO
PIN
STRONG
NFET
CMOS
To
circuit
ESD
Figure 14: Smart Card IO Interface Circuit
VDD
ESD
STRONG
PFET
RL=11K
400ns
DELAY
From
circuit
UC
PIN
To
circuit
CMOS
STRONG
NFET
ESD
Figure 15: Smart Card IOUC Interface Circuit
24
Rev. 1.0
DS_8014R_012
73S8014R Data Sheet
VDD
VERY
WEAK
PFET
Pull-up
Disable
ESD
TTL
To
circuit
PIN
VERY
WEAK
NFET
Pull-down
Enable
Note:
ESD
Pins CMDVCC,5V/#V, CLKDIV1 and CLKDIV2 have the pull-up enabled.
Pins RSTIN, CLKIN, PRES have the pull-down enabled.
Figure 16: General Input Circuit
VDD
ENABLEB
VERY
WEAK
FETs
STRONG
PFET
ESD
ESD
STRONG
PFET
XTALIN
XTALOUT
PIN
PIN
STRONG
NFET
ESD
ENABLE
ESD
STRONG
NFET
Figure 17: Oscillator Circuit
Rev. 1.0
25
73S8014R Data Sheet
DS_8014R_012
VDD
PIN
ESD
R = 40k
VREF = 1.400v +
VDD FAULT
DETECTION
-
VDDF_
ADJ
ESD
PIN
R = 60k
R = 0.4k
(approx.)
ESD
Figure 18: VDDF_ADJ
26
Rev. 1.0
DS_8014R_012
73S8014R Data Sheet
5 Mechanical Drawing
+ .005(.127)
0.5050(12.82) - .009(.228)
+ .003(.076)
0.2960(7.51) - .004(.101)
0.4065(10.32)
± .0125(.318)
Inches (mm)
+ .005(.127)
- .009(.228)
BASE PLANE
+ .004(.101)
- .003(.076)
0.016(.406)
0.050(1.27)
TYP
SEATING PLANE
0.0082
(.208)
0.1000 + .004(.101)
- .007(.178)
(2.54)
0.5050(12.82)
+ .0025(.0634)
0.01(.254) - .0010(.0254)
0°- 8°
± .017(.431)
Detail A
.033
(.838)
Detail “A”
Figure 19: Mechanical Drawing 20-Pin SO Package
Rev. 1.0
27
73S8014R Data Sheet
DS_8014R_012
6 Ordering Information
Table 9 lists the order numbers and packaging marks used to identify 73S8014R products.
Table 9: Order Numbers and Packaging Marks
Part Description
Order Number
Packaging Mark
73S8014R 20-pin Lead-Free
73S8014R-IL/F
73S8014R
73S8014R 20-pin Lead-Free Tape / Reel
73S8014R-ILR/F
73S8014R
7 Related Documentation
The following 73S8014R document is available from Teridian Semiconductor Corporation:
73S8014R/RN/RT 20SO Demo Board User Manual
8 Contact Information
For more information about Teridian Semiconductor products or to check the availability of the 73S8014R, contact
us at:
6440 Oak Canyon Road
Irvine, CA 92618-5201
Telephone: (714) 508-8800
FAX: (714) 508-8878
Email: [email protected]
For a complete list of worldwide sales offices, go to http://www.teridian.com.
28
Rev. 1.0
DS_8014R_012
73S8014R Data Sheet
Revision History
Revision
1.0
Date
9/3/2008
Description
First publication.
© 2008 Teridian Semiconductor Corporation. All rights reserved.
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.
Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.
All other trademarks are the property of their respective owners.
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms and
Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves
the right to change devices or specifications detailed herein at any time without notice and does not make any
commitment to update the information contained herein. Accordingly, the reader is cautioned to verify that this
document is current by comparing it to the latest version on http://www.teridian.com or by checking with your
sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon Rd., Suite 100, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.Teridian.com
Rev. 1.0
29