78Q8392L/A03 Low Power Ethernet Coaxial Transceiver November 2008 DESCRIPTION FEATURES The 78Q8392L/A03 Ethernet Transceiver is a replacement for the SSI/TDK/Teridian 78Q8392L/A02 coax line transmitter/receiver. Only a single resistor value change is required for upgrading an existing 78Q8392L/A02 design to the 78Q8392L/A03. • Very low power consumption • Compliant w ith Ethernet II, IEEE 802.3 10Base5 and 10Base2 • Integrates all transceiver functions except signal and power isolation The device includes analog transmit and receive buffers, a 10 MHz on-board oscillator, timing logic for jabber and heartbeat functions, output drivers and bandgap reference, in addition to a current reference and collision detector. • Innovative design minimizes external component count and power consumption • Jabber timer function integrated on chip • Externally selectable CED heartbeat allows operation with IEEE 802.3 compatible repeaters • Squelch circuitry at all inputs rejects noise • Power-on reset and test modes • Advanced BiCMOS process This transceiver provides the interface between the single-ended coaxial cable signals and the Manchester-encoded differential logic signals. Primary functional blocks include the receiver, transmitter, collision detection and jabber timer. This IC may be used in either internal or external MAU environments. The 78Q8392L/A03 is available in lead-free 16-pin plastic and 28-pin PLCC packages. CONNECT DIAGRAM 510 ±5% x4 –9V 1 COLLISION SIGNAL TO DTE CD+ VEE VEE 2 CD– VEE CDS 3 TXO RXI DATA TO DTE 6 7 DATA FROM DTE RX+ RX– GND HBE RRTXRR+ Page: 1 of 14 5 13 16 15 14 10 9 TX+ 78 8 4 © 2008 Teridian Semiconductor Corporation 12 COAX 11 Rev 1.3 78Q8392L/A03 Low Power Ethernet Coaxial Transceiver FUNCTIONAL DESCRIPTION The 78Q8392L/A03 incorporates six basic functions of the Ethernet Transceiver, including receiving, transmitting, collision signaling, collision detection, jabber timing, and the heartbeat function. Refer to Figure 1 for a general system block diagram. RECEIVER FUNCTIONS The receiver senses signals through the RXI input, which minimizes reflections on the transmission media using a low capacitance, high resistance input buffer amplifier. The CDS ground input attaches directly to the input buffer from the coaxial shield to eliminate ground loop noise. In addition to the input buffer, the receiver data path consists of an equalizer, data slicer, receiver squelch circuitry, and an output line driver. The equalizer improves the cable-induced jitter; the data slicer restores equalized received signals to fast transition signals with binary levels to drive the receiver line driver; and the receiver line driver drives the AUI cable through an isolation transformer that connects to the AUI interface. Noise on the transmission media is rejected by the receiver squelch circuitry, which determines valid data via three criteria: Average DC level, pulse width and transition period. The DC voltage level is detected and compared to a set level in the receiver comparator circuit. The pulse width must be greater than 20 ns to pass the narrow pulse filter; the transition timer outputs a true level on the RX Data Valid line provided the time between transitions is less than about 200 ns. As long as a valid RXI signal is detected, the output line driver remains enabled. The transition timer disables the line driver when there are no further transitions on the data medium, and the RX+, RX- pins go to a zero differential voltage state (Figure 3). TRANSMITTER FUNCTIONS The transmitter data path consists of a transmit input buffer, pulse-shaping filter, transmit squelch circuitry and transmit output line driver. The self-biasing transmit input buffer receives data through an isolation transformer and translates the AUI differential analog signal to a square pulse suitable for driving the pulse shaping filter. Page: 2 of 14 The filter outputs a correctly shaped and band limited signal to the transmit output driver, which drives the transmission medium through a high impedance current source. When the transmitter is off, the capacitance of the transmit driver is isolated from the transmission media by an external diode with a low capacitance node. The shield of the transmission media serves as the ground return for the transmitter function. A transmit squelch circuit, which consists of a pulse threshold detector, a pulse width detector, and a pulse duration timer, is used to suppress noise, as well as crosstalk on the AUI cable. The squelch circuitry disables the transmit driver if the signal at TX+ or TX- is smaller than the pulse threshold. Pulse noise is rejected by a pulse width detector that passes only pulses with durations greater than 20 ns. The pulse duration timer disables the transmit driver if no pulses are received for two-bit periods following valid pulses. At the end of a transmission, the pulse duration timer disables the transmitter and triggers the blanking timer, used to block “dribble” bits. COLLISION DETECTION A collision occurs when two or more transmitters simultaneously transmit on the transmission media. A collision is detected by comparing the average DC level of the transmission media to a collision threshold. The received signal at RXI is buffered and sent through a low pass filter, then compared in the collision threshold circuit. If the average DC level exceeds a collision threshold, a 10 MHz signal is output on the CD± pins. COLLISION SIGNALING When collision signaling is enabled (HBE pin is high and the average DC level on RXI exceeds the collision threshold VCD), a 10 MHz signal is sent from the CD± pins through an isolation transformer to the DTE. When the function is disabled, this output goes to a zero differential state. The 10 MHz signal output from the CD± pins indicates a collision on the transmission media, a heartbeat function, or that the transmitter is in jabber mode. © 2008 Teridian Semiconductor Corporation Rev 1.3 78Q8392L/A03 Low Power Ethernet Coaxial Transceiver JABBER FUNCTION HEARTBEAT FUNCTION When valid data on the TX± pins is detected, the jabber timer is started. If there is valid data for more than 20 ms, a latch is set which disables the transmitter output and enables the 10 MHz output on the CD± pins. The latch is reset within 0.5 seconds after the valid data is removed from the transmitter input (TX±). This action resets the jabber timer and disables the 10 MHz signal on the CD± pins. The TX± inputs must remain inactive during the 0.5 second reset period. The 10 MHz CD outputs are enabled for about 1 µs at approximately 1.1 µs after the end of each transmission. The heartbeat signal tells the DTE that the circuit is functioning. This is implemented by starting the heartbeat timer when the valid data signal indicates the end of a transmission. This function is disabled when HBE pin is tied to VEE. DATA MEDIA RXI RECEIVER INPUT BUFFER SLICER RX+ EQUALIZER RXCDS RX DATA VALID NARROW PULSE FILTER TRANSITION PERIOD TAMER ENABLE SQUELCH COMPARATOR LP FILTER SQUELSH THRESHOLD COLLISION COMPARATOR TRANSMIT OUTPUT DRIVER COLLISION THRESHOLD TRANSMIT INPUT BUFFER TXO BUFFERED TX PULSE SHAPING FILTER TX+ SLICER TXTX DISABLE TX ON CONTROL LOGIC JABBER TIMER TX DATA VALID TRANSITION PERIOD TIMER NARROW PULSE FILTER TX ± > -250 mV TX ± < -250 mV BLANKING TIMER COMPARATOR END TRANSMIT HEART BEAT TIMER TRANSITION END TIMER TX± DISABLE SIGNAL PRESET DETECT 10 MHz OSC CD ± ON ENABLE CD+ CD- BANDGAP REFERENCE AND CURRENT REFERENCE RR+ RR- FIGURE 1: 78Q8392L/A03 General System Block Diagram Page: 3 of 14 © 2008 Teridian Semiconductor Corporation Rev 1.3 78Q8392L/A03 Low Power Ethernet Coaxial Transceiver PIN DESCRIPTION NAME TYPE DESCRIPTION CD+*/CD- O Collision Output. Balanced differential line driver outputs from the collision detect circuitry. The 10 MHz signal from the internal oscillator is transferred to these outputs in the event of collision, excessive transmission (jabber), or during CD Heartbeat condition. These outputs are open emitters; pulldown resistors to VEE are required. When operating into a 78Ω transmission line, these resistors should be 510Ω. In Cheapernet applications, where the 78Ω drop cable is not used, higher resistor values (up to 1.5k) may be used to save power. RX+*/RX- O Receive Output. Balanced differential line driver outputs from the Receiver. These outputs also require 510Ω pulldown resistors. TX+*/TX- I Transmit Input. Balanced differential line receiver inputs to the Transmitter. The common mode voltage for these inputs is determined internally and must not be externally established. Signals meeting Transmitter squelch requirements are waveshaped and output at TXO. HBE I Heartbeat Enable. This input enables CD Heartbeat when grounded or left opened, disables it when connected to VEE. RR+/RR- I External Resistor. A fixed 976Ω 1% resistor connected between these pins establishes internal operating currents. Note: The previous generation 78Q8392L/A02 used a 1kΩ 1% resistor RXI I Receive Input. Connects directly to the coaxial cable. Signals meeting Receiver squelch requirements are equalized for inter-symbol distortion, amplified, and output at RX+ and RX- pins. TXO O Transmit Output. Connects via an isolation diode to the coaxial cable. CDS I Collision Detect Sense. Ground sense connection for the collision detect circuit. This pin should be connected separately to the shield to avoid ground drops from altering the receive mode collision threshold. GND S Positive Supply Pin. Negative Supply Pins. These pins should be connected to a large metal frame area on the PC board to handle heat dissipation, and bypassed to the GND pin with a 0.1µF capacitor as close to the package as possible. *IEEE names for CD± = CI±, RX± = DI±, TX± = DO± Notes: Pin type: I-input; O-output; S-power supply VEE Page: 4 of 14 S © 2008 Teridian Semiconductor Corporation Rev 1.3 78Q8392L/A03 Low Power Ethernet Coaxial Transceiver ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not recommended; operations should be limited to those conditions specified under recommended operating characteristics. PARAMETER RATING Supply Voltage -10V Input Voltage 0 to VEE Storage Temperature -65 to 150°C Soldering (Reflow or Dip) 235°C for 10 sec Package power dissipation 1.0 watts @ 25°C DC OPERATING CHARACTERISTICS 0°C ≤ T (ambient) ≤ +70°C, VEE = -9V ± 5% PARAMETER IEE1 Supply current out of VEE pin - non-transmitting CONDITION MIN IEE2 Supply current out of VEE pin - transmitting IRXI Receive input bias current (RXI) Transmit output dc current level (TXO) Transmit output ac current level (TXO) Collision threshold (Receive mode) Differential output voltage (RX±, CD±) Common mode output voltage (RX±, CD±) Differential output voltage imbalance (RX±, CD±) Transmitter squelch threshold (TX±) Input capacitance (RXI) See Note 3 -2 See Note 4 37 See Notes 4 & 5 ±28 Shunt resistance – non-transmitting (RXI) Shunt resistance – transmitting (TXO) See Note 3 100 See Note 4 200 ITDC ITAC VCD VOD VOC VOB VTS CX RRXI RTXO Page: 5 of 14 See Note 9 -1.58 See Notes 3 & 7 ±550 See Note 3, 6 & 7 -3.0 NOM MAX UNIT 6 8 mA 50 65 mA +25 µA 45 mA ITDC mA -1.404 V ±1200 mV -2.0 V ±40 mV -200 mV 41 -1.52 -2.5 See Notes 3, 7 & 8 -340 © 2008 Teridian Semiconductor Corporation -260 1.2 pF 150 kΩ kΩ Rev 1.3 78Q8392L/A03 Low Power Ethernet Coaxial Transceiver DC OPERATING CHARACTERISTICS (continued) NOTES 1. Currents into device pins are positive, currents out of device pins are negative. If not specified, voltages are referenced to ground. 2. All typical are for VEE = -9V, Ta = 25°C. 3. -8.55V > VEE > -9.45V. 4. The voltage on TXO is -4V < V(TXO) < 0.0V. 5. The AC current measurement is referenced to the DC current level. 6. Operating or idle state. 7. Test load as shown in Figure 2. 8. Device measurement taken in idle state. 9. This threshold can be determined by monitoring the CD± output with a DC level in RXI. GND + VOC - RX+ or CD+ ETHERNET XCVR + 510Ω ±5% 50 µH ±1% VEE VOB VOD = VCOM 78 ±1% - RXor CD- + - 510Ω ±5% VEE FIGURE 2: Test Load for CD± or RX± Page: 6 of 14 © 2008 Teridian Semiconductor Corporation Rev 1.3 78Q8392L/A03 Low Power Ethernet Coaxial Transceiver AC OPERATING CHARACTERISTICS 0°C < T(ambient) < +70°C, VEE = 9V ± 5% PARAMETER tRON Receiver startup delay (RXI to RX±) tRd Receiver propagation delay (RXI to RX±) tRr Differential outputs rise time (RX± , CD±) tRf Differential outputs fall time (RX± , CD±) tRJ Receiver & cable total jitter tTST tTd tTr tTf tTM CONDITION Transmitter startup delay (TX± to TXO) Transmitter propagation delay (TX± to TXO) Transmitter rise time – 10% to 90% (TXO) Transmitter fall time90% to 10% (TXO) tTr and tTf mismatch MIN NOM 400 MAX 500 UNIT ns 10 50 ns 4 5 ns 4 5 ns 2 4 ns 100 200 ns 35 50 ns 20 25 30 ns 20 25 30 ns 0.5 2 ns tTON Transmit turn-on pulse width at VTS (TX±) 8 20 30 ns tTOFF Transmit turn-off pulse width at VTS (TX±) 140 160 180 ns tCON Collision turn-on delay 700 900 ns tCOFF Collision turn-off delay 2000 ns 11.5 MHz 60 ns fCD Collision frequency (CD±) 8.5 tCP Collision pulse width (CD±) 40 tHON CD Heartbeat delay (TX± to CD±) CD Heartbeat duration (CD±) Jabber activation delay (TX± to TXO off and CD±) Jabber reset unjab time (TX± to TXO and CD±) Receive Off Pulse Width (RX+ to RX-) 0.6 1.0 1.6 µs 0.6 1.0 1.5 µs 60 ms 650 ms tHW tJA tJR tRO Page: 7 of 14 10 20 250 200 © 2008 Teridian Semiconductor Corporation 500 ns Rev 1.3 78Q8392L/A03 Low Power Ethernet Coaxial Transceiver ELECTRICAL SPECIFICATIONS (continued) RECEIVE SPECIFICATIONS TRANSMIT SPECIFICATIONS The first bit sent from RX± may have data and phase violations. The second through last bit reproduce the received signal with less than or equal to the specified jitter. The first bit transmitted from TXO may have data and phase violations. The second through last bit reproduce the TX± signal with less than or equal to the specified jitter. There is no logical signal inversion between the RXI input and the RX± output. A high level at RXI produces a positive differential voltage from RX+ to RX-. There is no logical signal inversion between TX± and TXO output. A low level from TX+ to TX- results in more current flowing from the coaxial cable into the TXO pin. At the end of transmission, when the transmitter changes from the enabled state to the idle state, no spurious pulses are generated, i.e., the transition on TXO proceeds monotonically to zero current. RXI 50% tRd tRON tRO 90% 50% RX± 10% 1st BIT tRr tRf FIGURE 3: Receiver Timing TX± 50% VTS VTS tTON tTOFF tTd tTST TXO 90% 50% 10% 90% tTF 10% tTr FIGURE 4: Transmitter Timing Page: 8 of 14 © 2008 Teridian Semiconductor Corporation Rev 1.3 78Q8392L/A03 Low Power Ethernet Coaxial Transceiver INPUT STEP FUNCTION R = 1K RXI C = 150 pF 78Q8392L COLLISION DETECTOR CD± OUTPUT RC NETWORK SIMULATES WORST CASE CABLE STEP RESPONSE VCD (MAX) VCD (MIN) RXI tCOFF tCON CD± 1 fCD tCP FIGURE 5: Collision Timing TX± tHON tHW CD± FIGURE 6: Heartbeat Timing TX± tJA tJR TXO CD± FIGURE 7: Jabber Timing Page: 9 of 14 © 2008 Teridian Semiconductor Corporation Rev 1.3 78Q8392L/A03 Low Power Ethernet Coaxial Transceiver R = 1kΩ INPUT SIGNAL WITH 30 ns RISE AND FALL TIMES RXI 78Q8392L RECEIVER RX± OUTPUT C = 36 pF RC NETWORK SIMULATES WORST CASE CABLE JITTER ±tRJ Input jitter <= ±1 ns RX± Output jitter <= ± 7 ns Difference <= ± 6 ns FIGURE 8: Receive Jitter Timing TRANSMIT OUTPUT (TXO) 25Ω FIGURE 9: Test Loads TXO Page: 10 of 14 © 2008 Teridian Semiconductor Corporation Rev 1.3 78Q8392L/A03 Low Power Ethernet Coaxial Transceiver 1:1 TX+ 39Ω ±1% 10 MHz VTS 39Ω ±1% 78Q8392L/A03 TX- GND FIGURE 10: Test Circuit for TX± Input Page: 11 of 14 © 2008 Teridian Semiconductor Corporation Rev 1.3 78Q8392L/A03 Low Power Ethernet Coaxial Transceiver PACKAGE PIN DESIGNATIONS CAUTION: Use handling procedures necessary for a static sensitive component. TXO N/C RXI CDS CDS 16 CD+ 1 CD- CD+ RX+ (Top View) 4 3 2 1 28 27 26 VEE 5 25 VEE VEE 6 24 VEE VEE 7 23 VEE VEE 8 22 VEE CD- 2 15 TXO RX+ 3 14 RXI VEE 4 13 VEE VEE 5 12 RR- VEE 9 21 VEE RX- 6 11 RR+ VEE 10 20 VEE TX+ 7 10 GND VEE 11 19 RR- 16-Pin DIP 15 16 17 18 HBE GND GND RR+ HBE 14 TX- 9 13 TX+ 8 12 RX- TX- 78Q8392L 78Q8392L 28-Pin PLCC ΘJA = 45°C/W for the 28_pin PLCC package Page: 12 of 14 © 2008 Teridian Semiconductor Corporation Rev 1.3 78Q8392L/A03 Low Power Ethernet Coaxial Transceiver MECHANICAL DRAWING (inch / mm) 28-Pin PLCC 16-Pin DIP Page: 13 of 14 © 2008 Teridian Semiconductor Corporation Rev 1.3 78Q8392L/A03 Low Power Ethernet Coaxial Transceiver ORDERING INFORMATION PART DESCRIPTION ORDER NUMBER PACKAGE MARK 78Q8392L-CP 78Q8392L/A03 16-Pin Plastic DIP (lead free) 78Q8392LA03-CP/F SP(Date Code)P3F (Lot Number) 78Q8392L/A03 28-Pin Plastic PLCC (lead free) 78Q8392LA03-28CH/F SP(Date Code)P3F (Lot Number) 78Q8392L-28CH REVISION HISTORY Rev. # 1.1 1.2 1.3 Date December 2005 January 2006 November, 2008 Comments Final Data Sheet release Corrected package marking error (from C to P) Added package dimensions This product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. Teridian Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. TSC assumes no liability for applications assistance. Teridian Semiconductor Corp., 6440 Oak Canyon Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com Page: 14 of 14 © 2008 Teridian Semiconductor Corporation Rev 1.3