SN74LV4052A-Q1 SCLS469D – MARCH 2003 – REVISED JUNE 2011 www.ti.com DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS Check for Samples: SN74LV4052A-Q1 FEATURES 1 • • • • • • • D OR PW PACKAGE (TOP VIEW) Qualified for Automotive Applications Supports Mixed-Mode Voltage Operation on All Ports Fast Switching High On-Off Output-Voltage Ratio Low Crosstalk Between Switches Extremely Low Input Current Latch-Up Performance Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 2Y0 2Y2 2-COM 2Y3 2Y1 INH GND GND VCC 1Y2 1Y1 1-COM 1Y0 1Y3 A B DESCRIPTION These dual 4-channel CMOS analog multiplexers/demultiplexers are designed for 2-V to 5.5-V VCC operation. The ’LV4052A devices handle both analog and digital signals. Each channel permits signals with amplitudes up to 5.5 V (peak) to be transmitted in either direction. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 105°C –40°C to 125°C (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC − D Tape and reel SN74LV4052ATDRQ1 L4052AQ TSSOP – PW Tape and reel SN74LV4052ATPWRQ1 L4052AQ TSSOP – PW Tape and reel SN74LV4052AQPWRQ1 4052AQ1 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. FUNCTION TABLE INPUTS INH B A ON CHANNEL L L L 1Y0, 2Y0 L L H 1Y1, 1Y1 L H L 1Y2, 2Y2 L H H 1Y3, 2Y3 H X X None 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2011, Texas Instruments Incorporated SN74LV4052A-Q1 SCLS469D – MARCH 2003 – REVISED JUNE 2011 www.ti.com LOGIC DIAGRAM (POSITIVE LOGIC) 13 1-COM 12 10 14 15 9 11 1 5 2 4 6 3 2 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 2-COM Copyright © 2003–2011, Texas Instruments Incorporated SN74LV4052A-Q1 SCLS469D – MARCH 2003 – REVISED JUNE 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC –0.5 V to 7 V Supply voltage range (2) –0.5 V to 7 V VI Input voltage range VIO Switch I/O voltage range (2) IIK Input clamp current VI < 0 –20 mA IIOK I/O diode current VIO < 0 –50 mA IT Switch through current VIO = 0 to VCC ±25 mA (3) –0.5 V to VCC + 0.5 V ±50 mA Continuous current through VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) D package 73°C/W PW package 108°C/W –65°C to 150°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 5.5 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage High-level input voltage, control inputs MAX (2) 5.5 2 VCC = 2 V VIH MIN Low-level input voltage, control inputs VI Control input voltage VIO Input/output voltage VCC = 2.3 V to 2.7 V VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 V 0.5 VCC = 2.3 V to 2.7 V VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 0 5.5 V 0 VCC V VCC = 2.3 V to 2.7 V 200 VCC = 3 V to 3.6 V 100 Δt/Δv Input transition rise or fall rate TA Operating free-air temperature SN74LV4052ATDRQ1,SN74LV4052ATPWRQ1 –40 105 TA Operating free-air temperature SN74LV4052AQPWRQ1 –40 125 VCC = 4.5 V to 5.5 V (2) V VCC × 0.3 VCC = 4.5 V to 5.5 V (1) V 1.5 VCC = 2 V VIL UNIT ns/V 20 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals be transmitted at these low supply voltages. Copyright © 2003–2011, Texas Instruments Incorporated 3 SN74LV4052A-Q1 SCLS469D – MARCH 2003 – REVISED JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = -40 to 105°C MIN ron ron(p) On-state switch resistance Peak on-state resistance IT = 2 mA, VI = VCC or GND, VINH = VIL (see Figure 1) IT = 2 mA, VI = VCC or GND, VINH = VIL Δron Difference in on-state resistance between switch IT = 2 mA, VI = VCC or GND, VINH = VIL II Control input current VI = 5.5 V or GND IS(off) TA = -40 to 125°C MAX MIN UNIT MAX 2.3 V 225 225 3V 190 190 4.5 V 100 100 2.3 V 600 600 3V 225 225 4.5 V 125 125 2.3 V 40 40 3V 30 30 Ω Ω Ω 4.5 V 20 20 0 V to 5.5 V ±1 ±2 μA Off-state switch leakage current VI = VCC and VO = GND, or VI = GND and VO = VCC, VINH = VIH (see Figure 2) 5.5 V ±1 ±2 μA IS(on) On-state switch leakage current VI = VCC or GND, VINH = VIL (see Figure 3) 5.5 V ±1 ±2 μA ICC Supply current VI = VCC or GND 5.5 V 20 40 μA 4 Copyright © 2003–2011, Texas Instruments Incorporated SN74LV4052A-Q1 SCLS469D – MARCH 2003 – REVISED JUNE 2011 www.ti.com SWITCHING CHARACTERISTICS VCC = 3.3 V ± 0.3 V, over recommended operating free-air temperature range (unless otherwise noted) tPLH tPHL tPZH tPZL tPHZ tPLZ TA = -40 to 105°C TA = -40 to 125°C FROM (INPUT) TO (OUTPUT TEST CONDITIONS COM or Y Y or COM CL = 50 pF (see Figure 4) 12 14 ns Enable delay time INH COM or Y CL = 50 pF (see Figure 5) 25 25 ns Disable delay time INH COM or Y CL = 50 pF (see Figure 5) 25 25 ns PARAMETER Propagation delay time MIN MAX MIN MAX UNIT SWITCHING CHARACTERISTICS VCC = 5 V ± 0.5 V, over recommended operating free-air temperature range (unless otherwise noted) tPLH tPHL tPZH tPZL tPHZ tPLZ TA = -40 to 105°C TA = -40 to 125°C FROM (INPUT) TO (OUTPUT TEST CONDITIONS COM or Y Y or COM CL = 50 pF (see Figure 4) 8 10 ns Enable delay time INH COM or Y CL = 50 pF (see Figure 5) 18 18 ns Disable delay time INH COM or Y CL = 50 pF (see Figure 5) 18 18 ns PARAMETER Propagation delay time Copyright © 2003–2011, Texas Instruments Incorporated MIN MAX MIN MAX UNIT 5 SN74LV4052A-Q1 SCLS469D – MARCH 2003 – REVISED JUNE 2011 www.ti.com ANALOG SWITCH CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER Frequency response (switch on) Crosstalk (between any switches)) Crosstalk (control input to signal output) Feedthrough attenuation (switch off) Sine-wave distortion (1) (2) FROM (INPUT) TO (OUTPUT) COM or Y Y or COM COM or Y INH COM or Y COM or Y TEST CONDITIONS VCC TA = 25°C MIN TYP CL = 50 pF, RL = 600 Ω, fin = 1 MHz (sine wave) (1) (see Figure 6) 2.3 V 30 3V 35 4.5 V 50 CL = 50 pF, RL = 600 Ω, fin = 1 MHz (sine wave) (seeFigure 7 ) 2.3 V –45 Y or COM 3V –45 4.5 V –45 2.3 V 20 COM or Y CL = 50 pF, RL = 600 Ω, fin = 1 MHz (square wave) (see Figure 8) 3V 35 4.5 V 65 2.3 V –45 Y or COM CL = 50 pF, RL = 600 Ω, fin = 1 MHz (2) (see Figure 9) 3V –45 4.5 V –45 2.3 V 0.1 Y or COM CL = 50 pF, RL = 10 kΩ, fin = 1 kHz (sine wave) (see Figure 10) 3V 0.1 4.5 V 0.1 VI = 2 Vp-p VI = 2.5 Vp-p VI = 4 Vp-p MAX UNIT MHz dB mV dB % Adjust fin voltage to obtain 0-dBm output. Increase fin frequency until dB meter reads −3 dB. Adjust fin voltage to obtain 0-dBm input. OPERATING CHARACTERISTICS VCC = 3.3 V, TA = 25°C (unless otherwise noted) PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 10 MHz TYP UNIT 11.8 pF Copyright © 2003–2011, Texas Instruments Incorporated SN74LV4052A-Q1 SCLS469D – MARCH 2003 – REVISED JUNE 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION = x W – Figure 1. On-State Resistance Test Circuit Figure 2. Off-State Switch Leakage-Current Test Circuit Figure 3. On-State Switch Leakage-Current Test Circuit W Figure 4. Propagation Delay Time, Signal Input to Signal Output Copyright © 2003–2011, Texas Instruments Incorporated 7 SN74LV4052A-Q1 SCLS469D – MARCH 2003 – REVISED JUNE 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) W W ≈ ≈ ≈ – ≈ Figure 5. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output m W = 50 pF = 600 W Figure 6. Frequency Response (Switch On) 8 Copyright © 2003–2011, Texas Instruments Incorporated SN74LV4052A-Q1 SCLS469D – MARCH 2003 – REVISED JUNE 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) m 600 W W = 600 W = 50 pF (OFF) = 600 W 600 W = 50 pF Figure 7. Crosstalk Between Any Two Switches W = 600 W W = 50 pF Figure 8. Crosstalk Between Control Input and Switch Output m W W = 600 W = 50 pF Figure 9. Feedthrough Attenuation (Switch Off) Copyright © 2003–2011, Texas Instruments Incorporated 9 SN74LV4052A-Q1 SCLS469D – MARCH 2003 – REVISED JUNE 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 10 m W = 10 kW = 50 pF Figure 10. Sine-Wave Distortion 10 Copyright © 2003–2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 1-Jul-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) CLV4052ATPWRG4Q1 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4052AQPWRQ1 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4052ATDRQ1 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4052ATPWRQ1 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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OTHER QUALIFIED VERSIONS OF SN74LV4052A-Q1 : Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 1-Jul-2011 • Catalog: SN74LV4052A • Enhanced Product: SN74LV4052A-EP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LV4052AQPWRQ1 Package Package Pins Type Drawing TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV4052AQPWRQ1 TSSOP PW 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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