TLC3702-Q1 www.ti.com SGLS156E – MARCH 2003 – REVISED AUGUST 2012 DUAL MICROPOWER LinCMOS™ VOLTAGE COMPARATORS Check for Samples: TLC3702-Q1 FEATURES 1 • • 2 • • • • • Qualified for Automotive Applications ESD Protection Exceeds 2000 V Per MIL-STD883, Method 3015; Exceeds 100-V Machine Model (C = 200 pF, R = 0); Exceeds 1500-V Charged Device Model (C = 200 pF, R = 0) Push-Pull CMOS Output Drives Capacitive Loads Without Pullup Resistor, IO = ± 8 mA Very Low Power . . . 100 μW Typ at 5 V Fast Response Time . . . tPLH = 2.7 μs Typ With 5-mV Overdrive Single-Supply Operation . . . 3 V to 16 V On-Chip ESD Protection D OR PW PACKAGE (TOP VIEW) SYMBOL (EACH COMPARATOR) DESCRIPTION The TLC3702-Q1 consists of two independent micropower voltage comparators designed to operate from a single supply and be compatible with modern HCMOS logic systems. They are functionally similar to the LM339 but use one-twentieth of the power for similar response times. The push-pull CMOS output stage drives capacitive loads directly without a power-consuming pullup resistor to achieve the stated response time. Eliminating the pullup resistor not only reduces power dissipation, but also saves board space and component cost. The output stage is also fully compatible with TTL requirements. The Texas Instruments LinCMOS™ process offers superior analog performance to standard CMOS processes. Along with the standard CMOS advantages of low power without sacrificing speed, high input impedance, and low bias currents, the LinCMOS process offers extremely stable input offset voltages with large differential input voltages. This characteristic makes it possible to build reliable CMOS comparators. The TLC3702-Q1 is characterized for operation over the full automotive temperature range of −40°C to 125°C. ORDERING INFORMATION (1) TA –40°C to 125°C (1) (2) PACKAGE (2) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING SOP − D Tape and reel TLC3702QDRQ1 3702Q1 TSSOP − PW Tape and reel TLC3702QPWRQ1 3702Q1 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinCMOS is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2012, Texas Instruments Incorporated TLC3702-Q1 SGLS156E – MARCH 2003 – REVISED AUGUST 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM (EACH COMPARATOR) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT −0.3 V to 18 V V ±18 V Input voltage range, VI −0.3 V to VDD V Output voltage range, VO −0.3 V to VDD V Input current, II ±5 mA Output current, IO (each output) ±20 mA Total supply current into VDD 40 mA Total current out of GND 40 mA Supply voltage range, VDD (2) Differential input voltage, VID (3) Continuous total power dissipation See Thermal Table Operating free-air temperature range, TA −40 to 125 °C Storage temperature range, Tstg −65 to 150 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) (3) D package 260 PW package 260 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to GND. Differential voltages are at IN+ with respect to IN −. THERMAL INFORMATION THERMAL METRIC (1) TLC3702QDRQ1 TLC3702QPWRQ1 D (8 PINS) PW (8 PINS) 117.7 181.1 θJA Junction-to-ambient thermal resistance θJCtop Junction-to-case (top) thermal resistance 63.9 49.9 θJB Junction-to-board thermal resistance 57..8 110.1 ψJT Junction-to-top characterization parameter 15.3 2.4 ψJB Junction-to-board characterization parameter 57.3 108.2 θJCbot Junction-to-case (bottom) thermal resistance N/A N/A (1) 2 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 TLC3702-Q1 www.ti.com SGLS156E – MARCH 2003 – REVISED AUGUST 2012 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX VDD Supply voltage 4 5 16 VIC Common-mode input voltage 0 IOH High-level output current IOL Low-level output current TA Operating free-air temperature UNIT V VDD- 1.5 –40 V -20 mA 20 mA 125 °C ELECTRICAL CHARACTERISTICS (1) at specified operating free-air temperature range, VDD= 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS VIO Input offset voltage VDD = 5 V to 10 V, VIC = VICRmin, See IIO Input offset current VIC = 2.5 V IIB Input bias current VIC = 2.5 V VICR Common-mode input voltage range CMRR kSVR Common-mode rejection ratio Supply-voltage rejection ratio (2) MIN VDD = 5 V to 10 V High-level output voltage VID = 1 V, IOH = −4 mA VOL Low-level output voltage VID = 1 V, IOH = −4 mA IDD Supply current (both comparators) Outputs low, No load MAX 1.2 5 10 25°C 1 125°C 15 25°C 5 125°C 25°C VIC = VICRmin TYP −40°C to 125°C −40°C to 125°C VOH (1) (2) TA 25°C 0 to VDD − 1 25°C 84 125°C 83 −40°C 82 25°C 85 125°C 85 −40°C 82 4.5 4.2 25°C 210 dB dB 300 500 19 −40°C to 125°C nA V 125°C 25°C pA V 0 to VDD − 1.5 25°C mV pA 30 125°C UNIT 40 90 mV µA All characteristics are measured with zero common-mode voltage unless otherwise noted. The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V. Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 3 TLC3702-Q1 SGLS156E – MARCH 2003 – REVISED AUGUST 2012 www.ti.com SWITCHING CHARACTERISTICS at recommended operating conditions, VDD = 5 V, TA = 25°C (unless otherwise noted) PARAMETER t(PLH) TEST CONDITIONS Propagation response time, low-to-high-level output (1) f = 10 kHz, CL = 50 pF t(PHL) f = 10 kHz, CL = 50 pF 4.5 Overdrive = 5 mV 2.7 Overdrive = 10 mV 1.9 Overdrive = 20 mV 1.4 Overdrive = 40 mV 1.1 tf Fall time tr Rise time f = 10 kHz, CL = 50 pF (1) 4 MAX UNIT µs 1.1 Overdrive = 2 mV 4 Overdrive = 5 mV 2.3 Overdrive = 10 mV 1.5 Overdrive = 20 mV 0.95 Overdrive = 40 mV 0.65 VI = 1.4 V step at IN+ f = 10 kHz, CL = 50 pF TYP Overdrive = 2 mV VI = 1.4 V step at IN+ Propagation response time, high-to-low-level output (1) MIN µs 0.15 Overdrive = 50 mV 50 ns Overdrive = 50 mV 125 ns Simultaneous switching of inputs causes degradation in output response. Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 TLC3702-Q1 www.ti.com SGLS156E – MARCH 2003 – REVISED AUGUST 2012 PRINCIPLES OF OPERATION LinCMOS™ Process The LinCMOS process is a linear polysilicon-gate CMOS process. Primarily designed for single-supply applications, LinCMOS products facilitate the design of a wide range of high-performance analog functions from operational amplifiers to complex mixed-mode converters. While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers. This short guide is intended to answer the most frequently asked questions related to the quality and reliability of LinCMOS products. Further questions should be directed to the nearest TI field sales office. Electrostatic Discharge CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to CMOS devices. It can occur when a device is handled without proper consideration for environmental electrostatic charges, for example, during board assembly. If a circuit in which one amplifier from a dual op amp is being used and the unused pins are left open, high voltages tend to develop. If there is no provision for ESD protection, these voltages may eventually punch through the gate oxide and cause the device to fail. To prevent voltage buildup, each pin is protected by internal circuitry. Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more transistors break down at voltages higher than the normal operating voltages but lower than the breakdown voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as tens of picoamps. To overcome this limitation, TI design engineers developed the patented ESD-protection circuit shown in Figure 1. This circuit can withstand several successive 2-kV ESD pulses, while reducing or eliminating leakage currents that may be drawn through the input pins. A more detailed discussion of the operation of the TI ESDprotection circuit is presented in the following sections. All input and output pins on LinCMOS and Advanced LinCMOS products have associated ESD-protection circuitry that undergoes qualification testing to withstand 2000 V discharged from a 100-pF capacitor through a 1500-Ω resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor (charged device model). These tests simulate both operator and machine handling of devices during normal test and assembly operations. Figure 1. LinCMOS™ ESD-Protection Schematic Input Protection Circuit Operation TI's patented protection circuitry allows for both positive- and negative-going ESD transients. These transients are characterized by extremely fast rise times and usually low energies, and can occur both when the device has all pins open and when it is installed in a circuit. Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 5 TLC3702-Q1 SGLS156E – MARCH 2003 – REVISED AUGUST 2012 www.ti.com Positive ESD Transients Initial positive charged energy is shunted through Q1 to VSS. Q1 turns on when the voltage at the input rises above the voltage on the VDD pin by a value equal to the VBE of Q1. The base current increases through R2 with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2 to exceed its threshold level (VT ∼ 22 to 26 V) and turn Q2 on. The shunted input current through Q1 to VSS is now shunted through the n-channel enhancement-type MOSFET Q2 to VSS. If the voltage on the input pin continues to rise, the breakdown voltage of the zener diode D3 is exceeded and all remaining energy is dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 V to 27 V, which is well below the gate-oxide voltage of the circuit to be protected. Negative ESD Transients The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1 and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is −0.3 V to −1 V (the forward voltage of D1 and D2). Circuit-Design Considerations LinCMOS products are being used in actual circuit environments that have input voltages that exceed the recommended common-mode input voltage range and activate the input protection circuit. Even under normal operation, these conditions occur during circuit power up or power down, and in many cases, when the device is being used for a signal conditioning function. The input voltages can exceed VICR and not damage the device only if the inputs are current limited. The recommended current limit shown on most product data sheets is ±5 mA. Figure 2 and Figure 3 show typical characteristics for input voltage versus input current. Normal operation and correct output state can be expected even when the input voltage exceeds the positive supply voltage. Again, the input current should be externally limited even though internal positive current limiting is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input current. This base current is forced into the VDD pin and into the device IDD or the VDD supply through R2 producing the current limiting effects shown in Figure 2. This internal limiting lasts only as long as the input voltage is below the VT of Q2. When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be severely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is required (see Figure 4). 6 Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 TLC3702-Q1 www.ti.com SGLS156E – MARCH 2003 – REVISED AUGUST 2012 Figure 2. Figure 3. VDD VI RI Positive Voltage Input Current Limit: 1/2 TLC3702-Q1 Vref RI Negative Voltage Input Current Limit: RI See Note A A. VI – VDD – 0.3 V 5 mA –VI – VDD – (–0.3 V) 5 mA If the correct input state is required when the negative input exceeds GND, a Schottky clamp is required. Figure 4. Typical Input Current-Limiting Configuration for a LinCMOS™ Comparator Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 7 TLC3702-Q1 SGLS156E – MARCH 2003 – REVISED AUGUST 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION The TLC3702-Q1 contains a digital output stage which, if held in the linear region of the transfer curve, can cause damage to the device. Conventional operational amplifier and comparator testing incorporates the use of a servo loop which is designed to force the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, we offer the following alternatives for measuring parameters such as input offset voltage, common-mode rejection, and so forth. To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown in Figure 5(a). With the noninverting input positive with respect to the inverting input, the output should be high. With the input polarity reversed, the output should be low. A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can be slewed to provide greater accuracy, as shown in Figure 5(b) for the VICR test. This slewing is done instead of changing the input voltages. A close approximation of the input offset voltage can be obtained by using a binary search method to vary the differential input voltage while monitoring the output state. When the applied input voltage differential is equal, but opposite in polarity, to the input offset voltage, the output changes states. Figure 6 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the comparator in the linear region. The circuit consists of a switching mode servo loop in which IC1a generates a triangular waveform of approximately 20-mV amplitude. IC1b acts as a buffer, with C2 and R4 removing any residual dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input is driven by the output of the integrator formed by IC1c through the voltage divider formed by R8 and R9. The loop reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input exactly equals the input offset voltage. Voltage dividers R8 and R9 provide an increase in input offset voltage by a factor of 100 to make measurement easier. The values of R5, R7, R8, and R9 can significantly influence the accuracy of the reading; therefore, it is suggested that their tolerance level be one percent or lower. Measuring the extremely low values of input current requires isolation from all other sources of leakage current and compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage can be measured with no device in the socket. Subsequently, this open socket leakage value can be subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the device. Figure 5. Method for Verifying That Input Offset Voltage Is Within Specified Limits 8 Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 TLC3702-Q1 www.ti.com SGLS156E – MARCH 2003 – REVISED AUGUST 2012 PARAMETER MEASUREMENT INFORMATION (continued) Figure 6. Circuit for Input Offset Voltage Measurement Response time is defined as the interval between the application of an input step function and the instant when the output reaches 50% of its maximum value. Response time for the low-to-high-level output is measured from the leading edge of the input pulse, while response time for the high-to-low-level output is measured from the trailing edge of the input pulse. Response time measurement at low input signal levels can be greatly affected by the input offset voltage. The offset voltage should be balanced by the adjustment at the inverting input as shown in Figure 7, so that the circuit is just at the transition point. A low signal, for example 105-mV or 5-mV overdrive, causes the output to change state Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 9 TLC3702-Q1 SGLS156E – MARCH 2003 – REVISED AUGUST 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Figure 7. Response, Rise, and Fall Times Circuit and Voltage Waveforms 10 Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 TLC3702-Q1 www.ti.com SGLS156E – MARCH 2003 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution IIB Input bias current vs Free-air temperature Figure 9 CMRR Common-mode rejection ratio vs Free-air temperature Figure 10 kSVR Supply-voltage rejection ratio vs Free-air temperature Figure 11 VOH High-level output current vs Free-air temperature Figure 12 vs High-level output current Figure 13 vs Low-level output current Figure 14 vs Free-air temperature Figure 15 Transition time vs Load capacitance Figure 16 Supply current response vs Time Figure 17 Low-to-high-level output response Low-to-high level output propagation delay time Figure 18 High-to-low level output response High-to-low level output propagation delay time Figure 19 tPLH Low-to-high level output propagation delay time vs Supply voltage Figure 20 tPHL High-to-low level output propagation delay time vs Supply voltage Figure 21 vs Frequency Figure 22 vs Supply voltage Figure 23 vs Free-air temperature Figure 24 VOL tt IDD Low-level output voltage Supply current Figure 8 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the device. Figure 8. Figure 9. Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 11 TLC3702-Q1 SGLS156E – MARCH 2003 – REVISED AUGUST 2012 www.ti.com Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the device. 12 Figure 10. Figure 11. Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 TLC3702-Q1 www.ti.com SGLS156E – MARCH 2003 – REVISED AUGUST 2012 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the device. Figure 14. Figure 15. Figure 16. Figure 17. Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 13 TLC3702-Q1 SGLS156E – MARCH 2003 – REVISED AUGUST 2012 www.ti.com Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the device. 14 Figure 18. Figure 19. Figure 20. Figure 21. Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 TLC3702-Q1 www.ti.com SGLS156E – MARCH 2003 – REVISED AUGUST 2012 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the device. Figure 22. Figure 23. Figure 24. Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 15 TLC3702-Q1 SGLS156E – MARCH 2003 – REVISED AUGUST 2012 www.ti.com APPLICATION INFORMATION The inputs should always remain within the supply rails in order to avoid forward biasing the diodes in the electrostatic discharge (ESD) protection structure. If either input exceeds this range, the device is not damaged as long as the input is limited to less than 5 mA. To maintain the expected output state, the inputs must remain within the common-mode range. For example, at 25°C with VDD = 5 V, both inputs must remain between −0.2 V and 4 V to ensure proper device operation. To ensure reliable operation, the supply should be decoupled with a capacitor (0.1 μF) that is positioned as close to the device as possible. The TLC3702-Q1 has internal ESD-protection circuits that prevent functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices as exposure to ESD may result in the degradation of the device parametric performance. Table 1. Applications FIGURE Pulse-width-modulated motor speed controller 25 Enhanced supply supervisor 26 Two-phase non-overlapping clock generator 27 Micropower switching regulator 28 1/2 TLC3702-Q1 Figure 25. Pulse-Width-Modulated Motor Speed Controller 16 Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 TLC3702-Q1 www.ti.com SGLS156E – MARCH 2003 – REVISED AUGUST 2012 1/2 TLC3702-Q1 1/2 TLC3702-Q1 Figure 26. Enhanced Supply Supervisor Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 17 TLC3702-Q1 SGLS156E – MARCH 2003 – REVISED AUGUST 2012 www.ti.com 1/2 TLC3702-Q1 1/2 TLC3702-Q1 1/2 TLC3702-Q1 Figure 27. Enhanced Supply Supervisor 18 Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 TLC3702-Q1 www.ti.com SGLS156E – MARCH 2003 – REVISED AUGUST 2012 1/2 TLC3702-Q1 1/2 TLC3702-Q1 Figure 28. Micropower Switching Regulator Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 19 TLC3702-Q1 SGLS156E – MARCH 2003 – REVISED AUGUST 2012 www.ti.com REVISION HISTORY Changes from Revision D (February, 2012) to Revision E Page • Changed part numbers from TLC3702 to TLC3702-Q1 ....................................................................................................... 1 • Changed units for IIB from dB to pA and nA ......................................................................................................................... 3 20 Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated Product Folder Link(s) :TLC3702-Q1 PACKAGE OPTION ADDENDUM www.ti.com 6-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TLC3702QDRG4Q1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC3702QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC3702QPWRQ1 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF TLC3702-Q1 : • Catalog: TLC3702 Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Aug-2012 • Enhanced Product: TLC3702-EP • Military: TLC3702M NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Enhanced Product - Supports Defense, Aerospace and Medical Applications • Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC3702QPWRQ1 Package Package Pins Type Drawing TSSOP PW 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 7.0 B0 (mm) K0 (mm) P1 (mm) 3.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC3702QPWRQ1 TSSOP PW 8 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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