TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS679 – MARCH 1997 D D D D D D D D D D Organization TM124BBK32H/ I . . . 1 048 576 × 32 TM248CBK32H/ I . . . 2 097 152 × 32 Single 5-V Power Supply (±10% Tolerance) 72-Pin Single In-Line Memory Module (SIMM) for Use With Socket TM124BBK32H/ I – Uses Two 16M-Bit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages TM248CBK32H/ I – Uses Four 16M-Bit DRAMs in Plastic SOJ Packages Long Refresh Period 16 ms (1 024 Cycles) All Inputs, Outputs, Clocks Fully TTL-Compatible 3-State Output Common CAS Control for Eight Common Data-In and Data-Out Lines in Four Blocks Enhanced Page-Mode Operation With CAS-Before-RAS ( CBR), RAS-Only, and Hidden Refresh D D D D D D Presence Detect Performance Ranges: ACCESS ACCESS ACCESS READ TIME TIME TIME OR tRAC tAA tCAC WRITE CYCLE (MAX) (MAX) (MAX) (MIN) ’124BBK32H / I-50 50 ns 25 ns 13 ns 90 ns ’124BBK32H / I-60 60 ns 30 ns 15 ns 110 ns ’124BBK32H / I-70 70 ns 35 ns 18 ns 130 ns ’248CBK32H / I-50 50 ns 25 ns 13 ns 90 ns ’248CBK32H / I-60 60 ns 30 ns 15 ns 110 ns ’248CBK32H / I-70 70 ns 35 ns 18 ns 130 ns Low Power Dissipation Operating Free-Air Temperature Range 0°C to 70°C Gold-Tabbed Versions Available:† TM124BBK32H TM248CBK32H Tin-Lead (Solder) Tabbed Versions Available: TM124BBK32I TM248CBK32I description TM124BBK32H/ I The TM124BBK32H / I is a 32M-bit dynamic random-access memory (DRAM) module organized as four times 1 048 576 × 8 in a 72-pin SIMM. The SIMM is composed of two TMS418160ADZ, 1 048 576 × 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418160ADZ is described in the TMS418160A data sheet (literature number SMKS891). The TM124BBK32H/ I SIMM is available in the single-sided BK-leadless module for use with sockets. TM248CBK32H/ I The TM248CBK32H / I is a 64M-bit DRAM organized as four times 2 097 152 × 8 in a 72-pin SIMM. The SIMM is composed of four TMS418160ADZ, 1 048 576 × 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418160ADZ is described in the TMS418160A data sheet (literature number SMKS891). The TM248CBK32H / I SIMM is available in the double-sided BK-leadless module for use with sockets. operation The TM124BBK32H / I operates as two TMS418160ADZ DRAMs, connected as shown in the functional block diagram and Table 1. The TM248CBK32H / I operates as four TMS418160ADZ DRAMs connected as shown in the functional block diagram and Table 1. The common I / O feature dictates the use of early-write cycles to prevent contention on D and Q. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS679 – MARCH 1997 BK SINGLE-IN-LINE MEMORY MODULE ( TOP VIEW ) 2 VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6 NC DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VCC A8 A9 RAS3 RAS2 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 TM124BBK32H/I ( SIDE VIEW ) TM248CBK32H/I ( SIDE VIEW ) PIN NOMENCLATURE A0 – A9 CAS0 – CAS3 DQ0 – DQ31 NC PD1 – PD4 RAS0 – RAS3 VCC VSS W Address Inputs Column-Address Strobe Data In/Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable PRESENCE DETECT SIGNAL (PIN) PD1 (67) PD2 (68) PD3 (69) PD4 (70) VSS VSS VSS VSS VSS NC VSS NC 50 ns VSS NC VSS NC VSS VSS 60 ns NC NC NC VSS NC 70 ns NC NC VSS NC 50 ns TM124BBK32H/I 60 ns 70 ns TM248CBK32H/I POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 NC TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS679 – MARCH 1997 operation (continued) Table 1. Connection Table DATA BLOCK RASx SIDE 1 SIDE 2† CASx DQ0 – DQ7 RAS0 RAS1 CAS0 DQ8 – DQ15 RAS0 RAS1 CAS1 DQ16 – DQ23 RAS2 RAS3 CAS2 DQ24 – DQ31 RAS2 RAS3 CAS3 † Side 2 applies to the TM248CBK32H/I only. single in-line memory module and components PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch / inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM124BBK32H and TM248CBK32H: Nickel plate and gold plate over copper Contact area for TM124BBK32I and TM248CBK32I: Nickel plate and tin / lead over copper functional block diagram (TM124BBK32H/I and TM248CBK32H/I, side 1) 10 A0 – A9 RAS0 RAS2 W 10 CAS0 CAS1 1M × 16 A0 –A9 DQ0 – RAS DQ7 W LCAS DQ8 – UCAS DQ15 10 D0 – D7 CAS2 CAS3 D8 – D15 1M × 16 A0 –A9 DQ0 – RAS DQ7 W LCAS DQ8 – UCAS DQ15 D16 – D23 D24 – D31 functional block diagram (TM248CBK32H/I, side 2) 10 A0 – A9 RAS1 RAS3 W 10 CAS1 CAS0 1M × 16 A0 –A9 DQ0 – RAS DQ7 W LCAS DQ8 – UCAS DQ15 10 D8 – D15 D0 – D7 POST OFFICE BOX 1443 CAS3 CAS2 • HOUSTON, TEXAS 77251–1443 1M × 16 A0 –A9 DQ0 – RAS DQ7 W LCAS DQ8 – UCAS DQ15 D24 – D31 D16 – D23 3 TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS679 – MARCH 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM124BBK32H, TM124BBK32I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W TM248CBK32H, TM248CBK32I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX VCC VIH Supply voltage 4.5 5 5.5 V High-level input voltage 2.4 6.5 V VIL TA Low-level input voltage (see Note 2) –1 0.8 V 0 70 °C Operating free-air temperature UNIT NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS‡ VOH High-level output voltage IOH = – 5 mA VOL Low-level output voltage IOL = 4.2 mA II Input current (leakage) IO ICC1 ICC2 ’124BBK32H / I - 50 MIN ’124BBK32H / I - 60 MAX 2.4 MIN MAX 2.4 ’124BBK32H / I - 70 MIN MAX 2.4 UNIT V 0.4 0.4 0.4 V VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 µA Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC, CAS high ± 10 ± 10 ± 10 µA Read- or write-cycle current VCC = 5.5 V, Minimum cycle 360 320 300 mA VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high 4 4 4 mA VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high 2 2 2 mA Standby current ICC3 Average refresh current (RAS only or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 360 320 300 mA ICC4 Average page current VCC = 5.5 V, tPC = MIN, RAS low, CAS cycling 220 180 160 mA ‡ For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS679 – MARCH 1997 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS† PARAMETER VOH High-level output voltage IOH = – 5 mA VOL Low-level output voltage IOL = 4.2 mA II Input current (leakage) IO ICC1 ICC2 ’248CBK32H / I - 50 MIN MAX 2.4 ’248CBK32H / I - 60 MIN ’248CBK32H / I - 70 MAX MIN 2.4 MAX 2.4 UNIT V 0.4 0.4 0.4 V VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 µA Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC, CAS high ± 20 ± 20 ± 20 µA Read- or write-cycle current (see Note 3) VCC = 5.5 V, 368 328 308 mA VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high 8 8 8 mA VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high 4 4 4 mA Standby current Minimum cycle ICC3 Average refresh current (RAS only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 720 640 600 mA ICC4 Average page current (see Note 4) VCC = 5.5 V, RAS low, 440 360 320 mA tPC = MIN, CAS cycling † For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5) ’124BBK32H / I PARAMETER MIN MAX ’248CBK32H / I MIN MAX UNIT Ci(A) Input capacitance, A0 – A9 10 20 pF Ci(R) Input capacitance, RAS inputs 7 7 pF Ci(C) Input capacitance, CAS inputs 7 14 pF Ci(W) Input capacitance, W 14 28 pF Co(DQ) Output capacitance on DQ0 – DQ31 7 14 pF NOTE 5: VCC = 5 V ± 0.5 V, and the bias on pins under test is 0 V. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS679 – MARCH 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature ’124BBK32H / I - 50 ’248CBK32H / I - 50 PARAMETER MIN ’124BBK32H / I - 60 ’248CBK32H / I - 60 MAX MIN MAX ’124BBK32H / I - 70 ’248CBK32H / I - 70 MIN UNIT MAX tAA tCAC Access time from column address 25 30 35 ns Access time from CAS low 13 15 18 ns tRAC tCPA Access time from RAS low 50 60 70 ns Access time from column precharge 30 35 40 ns tCLZ tOH CAS to output in the low-impedance state 0 0 0 Output disable time from start of CAS high 3 3 3 tOFF Output disable time after CAS high (see Note 6) NOTE 6: tOFF is specified when the output is no longer driven. 0 13 0 15 0 ns ns 18 ns timing requirements over recommended ranges of supply voltage and operating free-air temperature ’124BBK32H / I - 50 ’248CBK32H / I - 50 MIN tRC tRWC MIN MAX ’124BBK32H / I - 70 ’248CBK32H / I - 70 MIN UNIT MAX 90 110 130 ns 131 155 181 ns Cycle time, page-mode read or write (see Notes 7 and 8) 35 40 45 ns tRASP tRAS Pulse duration, page mode, RAS low 50 100 000 60 100 000 70 100 000 ns Pulse duration, nonpage mode, RAS low 50 10 000 60 10 000 70 10 000 ns tCAS tCP Pulse duration, CAS low 13 10 000 15 10 000 18 10 000 ns Pulse duration, CAS high 8 10 10 ns tRP tWP Pulse duration, RAS high (precharge) 30 40 50 ns Pulse duration, W low 10 10 10 ns tASC tASR Setup time, column address before CAS low 0 0 0 ns Setup time, row address before RAS low 0 0 0 ns tDS tRCS Setup time, data before CAS low 0 0 0 ns Setup time, W high before CAS low 0 0 0 ns tCWL tRWL Setup time, W low before CAS high 13 15 18 ns Setup time, W low before RAS high 13 15 18 ns tWCS tCAH Setup time, W low before CAS low 0 0 0 ns Hold time, column address after CAS low 10 10 15 ns tRHCP tDH Hold time, RAS high from CAS precharge 30 35 40 ns Hold time, data after CAS low 10 10 15 ns tRAH tRCH Hold time, row address after RAS low 8 10 10 ns Hold time, W high after CAS high (see Note 9) 0 0 0 ns tRRH Hold time, W high after RAS high (see Note 9) NOTES: 7. All cycles assume tT = 5 ns. 8. To assure tPC min, tASC should be ≥ tCP . 9. Either tRRH or tRCH must be satisfied for a read cycle. 0 0 0 ns tPC 6 Cycle time, random read or write (see Note 7) MAX ’124BBK32H / I - 60 ’248CBK32H / I - 60 Cycle time, read-write POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS679 – MARCH 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature ’124BBK32H / I - 50 ’248CBK32H / I - 50 MIN MAX ’124BBK32H / I - 60 ’248CBK32H / I - 60 MIN MAX ’124BBK32H / I - 70 ’248CBK32H / I - 70 MIN UNIT MAX tWCH Hold time, W low after CAS low 10 10 15 ns tCHR Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns tCRP tCSH Delay time, CAS high to RAS low 5 5 5 ns Delay time, RAS low to CAS high 50 60 70 ns tCSR Delay time, CAS low to RAS low (CBR refresh only) 5 5 5 ns tRAD Delay time, RAS low to column address (see Note 10) 13 tRAL tCAL Delay time, column address to RAS high 25 30 35 Delay time, column address to CAS high 25 30 35 tRCD tRPC Delay time, RAS low to CAS low (see Note 10) 18 tRSH tREF Delay time, CAS low to RAS high Delay time, RAS high to CAS low (CBR only) 25 37 15 20 30 45 15 20 5 5 5 13 15 18 Refresh time interval 16 tT Transition time 2 NOTE 10: The maximum value is specified only to ensure access time. 30 16 2 30 2 35 ns ns ns 52 ns ns ns 16 ms 30 ns device symbolization (TM124BBK32H/I illustrated) TM124BBK32H -SS YY MM T -SS = = = = YYMMT Year Code Month Code Assembly Site Code Speed Code NOTE A: Location of symbolization may vary. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TM124BBK32H, TM124BBK32I 1048576 BY 32-BIT TM248CBK32H, TM248CBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS679 – MARCH 1997 MECHANICAL DATA BK (R-PSIM-N72) SINGLE-IN-LINE MEMORY MODULE 0.054 (1,37) 0.047 (1,19) 4.255 (108,08) 4.245 (107,82) 0.125 (3,18) TYP 1.005 (25,53) 0.995 (25,27) 0.050 (1,27) 0.128 (3,25) 0.120 (3,05) 0.010 (0,25) MAX 0.400 (10,16) TYP 0.040 (1,02) TYP 0.208 (5,28) MAX 0.360 (9,14) MAX (For Double-Sided SIMM) 4040197 / B 02/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Resale of TI’s products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2001, Texas Instruments Incorporated