SLLS120A − JUNE 1991 − REVISED SEPTEMBER 1991
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Meets or Exceeds the IEEE STD 802.3I,
Type 10BASE-T
Differential (Twisted-Pair) I/O
Driver/Receiver
High-Speed Receiver . . . tpd = 50 ns Max
Receiver Squelch Circuit Integrity Improved
With Noise Filter
Jabber Control Prevents Network Lockup
Collision Detection for Multiple-User
Networks
Data Link Integrity Monitored With Link
Test Pulse
Externally Addressable Test Register
Controls Signal Quality Error Testing
CMOS and Raised ECL Compatible
24-Terminal, 300-mil Dual-In-Line Package
DW PACKAGE
(TOP VIEW)
CLKOUT
TXDATAA
TXDATAB
TXEN
GND (L)
VCC(L)
GND (L)
RXDATAA
RXDATAB
RXEN
LOOP
LINK
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
X1
X2
SQEEN
TX+
TX−
GND (P)
VCC(P)
FULLD
RX+
RX−
CTL
JABB
description
The SN75LBC086 is a single-channel differential driver/receiver interface device for the medium attachment
unit (MAU) used in 10-MHz twisted-pair Ethernet applications. The device uses a 5-V supply and is designed
to interface with two pairs of telephone-grade twisted-pair cables coupled through isolation transformers. The
functional components of the device include a differential receiver and driver, receiver squelch with noise filter,
jabber controls, collision detection, data link monitor, and signal quality error (SQE) testing. The LinBiCMOS
process technology is used in the device design to ensure analog precision, low power, and high-speed
operation.
The device contains an elaborate receiver-squelch circuit† that provides an improved level of noise rejection
by qualifying the incoming signal stream with three different criteria. First, the signal is compared to a set
threshold voltage level. Then, the pulse duration is compared to a set time window. Last, the signal must follow
a set pattern of positive and negative pulses before the circuit finally opens the receiver channel to the incoming
data packet.
The jabber control is designed to prevent a defective controller from locking up the network by limiting the data
packet transmission time to 20 to 30 ms. When a packet length exceeds 20 to 30 ms, the driver is turned off for
about 600 ms. The driver-enable input must be made inactive by the controller during this period before the
jabber control will release the driver. The JABB output is active (high) when a jabber condition exists.
Collision detection is used to arbitrate access to the multiuser network. This detection is done logically by
monitoring the receive line for a valid signal during a driver transmission. When a collision is detected, this device
informs the controller with an active-high CTL output. After a valid packet transmission, the device also performs
a signal quality error test causing the CTL output to go active (high). This test is disabled when the SQEEN input
goes inactive (high).
The device tests data-link integrity during the idle state by periodically driving the driver line with a unipolar pulse
called a link-test pulse. The receiver looks for this link-test pulse on the receive line. A failed line link is indicated
by a high-impedance state at the LINK output. This output drives an LED for monitoring if needed.
An internal test register is externally controlled with inputs FULLD and LOOP to select the device testing mode.
When in the test mode, serial test-mode control patterns are clocked into the test register through input SQEEN.
These control patterns select various modes to test the internal circuits.
† Embodies technology covered by one or more Digital Equipment Corporation Patents.
LinBiCMOS is a trademark of Texas Instruments Incorporated.
Copyright 1991, Texas Instruments Incorporated
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2−1
SLLS120A − JUNE 1991 − REVISED SEPTEMBER 1991
functional block diagram
VCC(P)
VCC(L)
FULLD
LOOP
18
Clock
Generator
6
17
Test Register
and Device
Mode Control
11
TXDATAB
TXDATAA
RX−
RX+
Driver and
Pre-Emphasis
Control
SQEEN
2−2
Jabber Timer
and
Control
4
3
23
20
21
16:1
MUX
13
8:1
MUX
14
X1
X2
CLKOUT
TX−
TX+
JABB
Status
Lines
2
Collision
Detection
Control
Link Pulse
Monitor and
Control
15
Receiver
Squelch
Circuit
12
10
16
9
Receiver
Output
MUX
22
24
1
Chip and
Power-Up
Reset
TXEN
Crystal
Oscillator
Signal Quality
Error Test
Circuit
LINK
RXEN
RXDATAB
RXDATAA
5,7 GND (L)
19 GND (P)
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8
CTL
SLLS120A − JUNE 1991 − REVISED SEPTEMBER 1991
Terminal Functions
TERMINAL
NAME
LEVEL
NO.
I/O
DESCRIPTION
CLKOUT
CMOS
1
O
Clock output. This 10-MHz buffered clock drives other interface devices.
CTL
CMOS
14
O
Control. In normal mode, CTL high indicates a collision. In test mode, status lines are muxed out.
FULLD
TTL
17
I
Full-duplex mode. When active (low), the device is placed in the full-duplex operating mode for simple
point-to-point communication applications. In the full-duplex mode, the receiver and driver are both
active with collision detection disabled. After LOOP and FULLD go active (low), in that order, a device
reset is initiated and while both are active (low), test select data clocks into the test register using a
100-ns clock at the X1 input. This terminal is held inactive (high) due to an internal pullup resistor.
GND (L)
GROUND
5
7
GND (P)
GROUND
19
JABB
CMOS
13
O
Jabber control. When a jabber condition exists during normal mode operation, this signal goes active
(high) to report jabber-control status to the controller. In the test mode, this provides a multiplexed signal
for internal timer and counter functions.
LINK
CMOS
12
O
Link status. This 3-state output indicates the status of the receiver and interface link. When driving an
LED (with anode to resistor to VCC), a high-impedance level indicates a failed link and the LED is off.
A momentary high level indicates the device is receiving valid data and the LED is blinking on and off.
A continuous low level indicates the device is receiving valid link pulses but no data, and the LED is on.
LOOP
TTL
11
I
Loop-back mode. When the device is in the normal operating mode (not test mode) and LOOP is active
(low), the driver (transmit) data is directed to the receive data path to put the device in the loop-back
mode and the driver is turned off. After LOOP and FULLD go active (low), in that order, a device reset
is initiated and while both are active (low), test select data clocks into the test register using a 100-ns
clock at the X1 input. This terminal is held inactive (high) due to an internal pullup resistor.
16
I
Differential receiver inputs
RX+
RX−
Logic grounds. These terminals provide a ground return for the CMOS core logic.
Power ground. This provides a ground return for the input and output buffers, driver (transmitter), and
receiver circuits.
15
I
RXEN
CMOS
10
O
Receiver squelch status. This provides squelch status information to the controller. When active (high),
this signal indicates that the data path is valid or open from the receive channel through the device. An
inactive (low) indicates that the receive channel is squelched or closed. This signal is capable of driving
an LED monitor.
RXDATAA
RXDATAB
CMOS
ECL
8
9
O
O
Received-data serial outputs. These outputs provide a choice of logic levels and serial data either from
the differential receiver input (RX+ and RX−) or data from the controller (TXDATAA or TXDATAB) when
in the loop-back mode. When the receiver is idle, these output levels are normally high. These terminals
are held inactive (high) due to an internal pullup resistor.
SQEEN
TTL
22
I
Signal-quality error-test enable. In normal operating mode, this enables the SQE test function performed
at the end of a data packet transmission. In the test mode, SQEEN is used (with X1 clock) as a serial
data input port to load test patterns or selections into the test register. This terminal is held inactive (high)
due to an internal pullup resistor.
21
O
Differential driver outputs
TX+
TX−
20
O
TXEN
TTL
4
I
Transmitter (driver) enable. When TXEN is active (high), serial data at the TXDATA inputs starts and
stops the driver. When TXEN is inactive (low), the driver begins transmitting an idle signal independent
of the TXDATA inputs.
TXDATAA
TXDATAB
CMOS
ECL
2
3
I
I
Transmit-data inputs. A choice of logic-level inputs provide Manchester-encoded serial data to the
driver. Internal pullup resistors are included.
VCC(L)
VCC(P)
SUPPLY
6
SUPPLY
18
X1
X2
CMOS
24
23
VCC logic power supply. This provides power to the CMOS core logic.
VCC power supply. This provides power to the input and output buffers, drivers, and receivers.
I
O
Crystal input/output. X1 provides an input from an external 10-MHz crystal or another external clock
source when the crystal is disconnected. X2 provides an oscillator output.
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•
2−3
SLLS120A − JUNE 1991 − REVISED SEPTEMBER 1991
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range at any input, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Output voltage range at any output, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to device ground pins GND(L) and GND(P) shorted together.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
DW
1350 mW
10.8 mW/°C
864 mW
recommended operating conditions
Supply voltage, VCC
TXDATAA, X1
High-level output voltage, VIH
TXDATAB
(see Figure 1)
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
V
3.15
TA = 0°C
TA = 25°C
0.984VCC −0.922
0.984VCC −0.877
0.984VCC −0.763
0.984VCC −0.727
TA = 70°C
0.984VCC −0.825
0.984VCC −0.645
TXEN, LOOP,
FULLD, SQEEN
2
TXDATAA, X1
Low-level output voltage, VIH
TXDATAB
(see Figure 1)
0.8
TA = 0°C
TA = 25°C
0.75VCC −0.59
0.75VCC −0.55
0.75VCC −0.375
0.75VCC −0.35
TA = 70°C
0.75VCC −0.531
0.75VCC −0.324
TXEN, LOOP,
FULLD, SQEEN
V
0.8
Differential input voltage, VID
0.586
2.8
V
Common-mode input voltage, VIC
1.8
3.2
V
Operating free-air temperature, TA
0
70
°C
2−4
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•
SLLS120A − JUNE 1991 − REVISED SEPTEMBER 1991
electrical characteristics over recommended operating free-air temperature and supply voltage
range (unless otherwise noted)
drivers
PARAMETER
TEST CONDITIONS
CLKOUT, RXDATAA,
RXEN, JABB, CTL
VOH
High-level output
voltage
RXDATAB
VOL
Low-level output
voltage
IOH = − 12 mA
See Figure 1
CLKOUT, RXDATAA,
RXEN, JABB, CTL
RXDATAB
MIN
UNIT
3.7
V
TA = 0°C
TA = 25°C
0.984 VCC −0.922
0.984 VCC −0.763
0.984 VCC −0.877
0.984 VCC −0.727
TA = 70°C
0.984 VCC −0.825
0.984 VCC −0.645
0.5
TA = 0°C
TA = 25°C
TA = 70°C
VOD
VOD
MAX
IOL = 16 mA
See Figure 1
LINK
TYP
V
V
0.75 VCC −0.59
0.75 VCC −0.375
0.75 VCC −0.55
0.75 VCC −0.531
0.75 VCC −0.35
0.75 VCC −0.324
V
0.5
V
Differential-output voltage (peak)
IOL = 12 mA
See Figure 2
2.2
2.8
V
Differential-output voltage (step)
See Figure 2
1.53
1.982
V
8
Ω
Common-mode
driver impedance
TX+, TX−
2
5
receivers
TEST CONDITIONS†
PARAMETER
MIN
TXDATAA, TXEN, LOOP, FULLD, SQEEN
IIH
High-level input current
Low-level input current
UNIT
20
X1
VI = 5.25 V
100
TXDATAB
VIH = MAX
400
TXDATAA, TXEN, LOOP, FULLD, SQEEN
IIL
MAX
µA
−20
VI = 0
X1
−100
TXDATAB
VIL = MIN
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
µA
−400
drivers and receivers
PARAMETER
ICC
Supply current
VCC(L), VCC(P)
TEST CONDITIONS
VCC(L) = 5.25 V,
•
VCC(P) = 5.25 V
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•
MIN
MAX
UNIT
180
mA
2−5
SLLS120A − JUNE 1991 − REVISED SEPTEMBER 1991
switching characteristics
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
tpd1
Propagation delay time
RX+, RX−
RXEN
See Figure 4
5 bit
times
tpd2
Propagation delay time at startup
RX+, RX−
RXDATAA or
RXDATAB high
See Figure 4
75
ns
tsk(o)
Output skew time
RXEN high
RXDATAA or
RXDATAB low
See Figure 4
±10
ns
tpd3
Propagation delay time after startup
RX+, RX−
RXDATAA or
RXDATAB high
See Figure 4
50
ns
tsk(p)
Pulse skew time (|tpd3(LH) − tpd3(HL)|)
RX+, RX−
RXDATAA or
RXDATAAB
See Figure 4
tpd4
Propagation delay time
RX+, RX−
RXEN low
See Figure 5
tpd5
Propagation delay time
TXDATA or
TXDATAB
TX+, TX−
See Figure 6
tsk(p)
Pulse skew time (tpd5(LH) − tpd5(HL))
TXDATAA or
TXDATAB
TX+, TX−
See Figure 6
tpd6
Propagation delay time in loop mode
TXDATAA or
TXDATAB
RXDATAA,
RXDATAB
See Figure 7
50
ns
tpd7
tpd8
Propagation delay time in loop mode
TXEN high
RXEN high
See Figure 7
50
ns
Propagation delay time in loop mode
LOOP low
RXEN low
See Figure 7
30
ns
tpd10
tpd11
Propagation delay time
TXEN low
RXEN low
See Figure 8
350
ns
Propagation delay time
TXEN low
TX+, TX− high
See Figure 8
50
ns
tp1
tp2
Precompensation pulse duration
TX+, TX−
See Figure 6
45
55
ns
See Figure 9
80
120
ns
Receiver link-beat minimum pulse duration
2
155
ns
250
ns
75
ns
2
ns
ten1
Enable time
TXDATAA or
TXDATAB
ten2
Enable time
TXEN
TX+, TX−
See Figure 6
tdis1
Disable time, caused by TXDATAA or
TXDATAB high or TXEN low
TX+, TX− high
TX+, TX− at
585-mV level
See Figure 8
tpd12
Propagation delay time to looped RXEN
TXEN high
RXEN high
See Figure 6
100
ns
Propagation delay time for looped back data
TXDATAA or
TXDATAB
RXDATAA
RXDATAB
See Figure 6
75
ns
tpd13
TX+, TX−
See Figure 6
75
ns
75
ns
250
ns
timing requirements
TEST CONDITIONS
MIN
MAX
UNIT
Setup time, test mode, SQEEN before X1↑, tsu1
See Figure 10
30
ns
Setup time, test mode, LOOP low before FULLD↓, tsu2
See Figure 10
25
ns
Hold time, test mode, SQEEN after X1↑, th1
See Figure 10
25
ns
2−6
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•
SLLS120A − JUNE 1991 − REVISED SEPTEMBER 1991
PARAMETER MEASUREMENT INFORMATION
330 Ω
39 Ω
TX−
15 pF
100 Ω
39 Ω
TX+
Figure 1. ECL Load Circuit
VOD
Figure 2. Differential Load CIrcuit
20 pF
6 kΩ
Figure 3. CMOS Load Circuit
300 mV
RX+, RX−
Diff Input
0%
tpd1
RXEN
50%
RXDATAA
tpd2
tpd3
tpd2
tpd3
50%
RXDATAB
50%
tsk(o)
Figure 4. Receiver Startup Waveforms
RX+, RX−
Diff Input
> 300 mV
0%
tpd4
50%
RXEN
Figure 5. Receiver Shutdown Waveforms
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2−7
SLLS120A − JUNE 1991 − REVISED SEPTEMBER 1991
PARAMETER MEASUREMENT INFORMATION
tpd12
50%
RXEN
RXDATAA
or
RXDATAB
50%
50%
Bit Type
tpd13
TXDATAA
or
TXDATAB
(CMOS or ECL)
“1”
“1”
“0”
“1”
“0”
50%
tp1
ten1
0%
Diff TX+, TX−
Output
1.756-V Step
± 0.226 V
tpd5
tpd5
0%
0V
Diff
90%
ten2
TXEN
tp1
50%
Figure 6. Driver Startup Waveforms
50%
TXEN
tpd6
TXDATAA
or
TXDATAB
50%
tpd6
RXDATAA (CMOS)
RXDATAB (ECL)
50%
50%
tpd7
RXEN
50%
50%
tpd8
LOOP
50%
Figure 7. Propagation Delay Waveforms in Loop Mode
2−8
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•
2.5-V Peak
± 0.3 V
SLLS120A − JUNE 1991 − REVISED SEPTEMBER 1991
PARAMETER MEASUREMENT INFORMATION
Bit Type
“1”
“0”
TXDATAA
(CMOS)
or
50%
TXDATAB (ECL)
50%
tdis1
TX+, TX−
585 mV
Diff Output
tpd11
TXEN
50%
tpd10
RXEN
50%
Figure 8. Driver Shutdown Waveforms
tp2
585 mV
0
Diff Input RX+, RX−
tp2
585 mV
Diff Output TX+, TX−
0
Figure 9. Link Beat Pulse Duration Waveform
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2−9
SLLS120A − JUNE 1991 − REVISED SEPTEMBER 1991
PARAMETER MEASUREMENT INFORMATION
tsu1
X1
50%
50%
SQEEN
th1
LOOP
tsu2
FULLD
Figure 10. Setup and Hold Time Waveforms
2−10
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•
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