WINBOND W83195WG-416

Winbond Clock Generator
W83195WG-416
W83195CG-416
For ATI K8 Chipset
Date:
Feb/27/2006
Revision: 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
W83195WG-416/W83195CG-416 Data Sheet Revision History
Pages
Dates
Version
Web
Version
Main Contents
1
n.a.
01/20/2006
0.5
n.a.
All of the versions before 0.50 are for internal
use.
2
13
02/27/2006
0.6
n.a.
Add HTT66 asynchronous mode.
3
4
5
6
7
8
9
10
Please note that all data and specifications are subject to change without notice. All
the trademarks of products and companies mentioned in this data sheet belong to
their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result
in personal injury. Winbond customers using or selling these products for use in such
applications do so at their own risk and agree to fully indemnify Winbond for any
damages resulting from such improper use or sales.
I
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
TABLE OF CONTENT
1.
GENERAL DESCRIPTION ......................................................................................................... 1
2.
PRODUCT FEATURES .............................................................................................................. 1
3.
PIN CONFIGURATION ............................................................................................................... 2
4.
BLOCK DIAGRAM ...................................................................................................................... 2
5.
PIN DESCRIPTION..................................................................................................................... 3
6.
FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 5
7.
I2C CONTROL AND STATUS REGISTERS ............................................................................... 6
7.1
Register 0: ( Default : 00h ) ......................................................................................................6
7.2
Register 1: ( Default : XXh) ......................................................................................................6
7.3
Register 2: ( Default : 03h ) ......................................................................................................7
7.4
Register 3: ( Default : 03h ) ......................................................................................................7
7.5
Register 4: ( Default : FEh) ......................................................................................................8
7.6
Register 5: ( Default : 02h ) ......................................................................................................8
7.7
Register 6: ( Default : FFh )......................................................................................................9
7.8
Register 7: Winbond Chip ID – Project Code Register ( Default : 06h )...............................10
7.9
Register 8: ( Default :D0h )..................................................................................................10
7.10
Register 9: ( Default : 7Ah )....................................................................................................10
7.11
Register 10: Reserved ( Default : 3Bh ).................................................................................11
7.12
Register 11: ( Default : 0Eh )..................................................................................................11
7.13
Register 12: ( Default : XXh ) .................................................................................................11
7.14
Register 13: ( Default : 3Fh )..................................................................................................12
7.15
Register 14: ( Default : D0h ) .................................................................................................12
7.16
Register 15: ( Default : 5Ch ) .................................................................................................12
7.17
Register 16: ( Default : 24h ) ..................................................................................................13
7.18
Register 17: Reserved ( Default : 07h ) .................................................................................13
7.19
Register 18: Reserved ( Default : 7Ah ).................................................................................13
7.20
Register 19: ( Default : 04h ) ..................................................................................................14
7.21
Register 20: ( Default : 88h ) ..................................................................................................14
7.22
Register 21: ( Default : ECh ).................................................................................................14
Table3: SRC & ATIG Frequency Selection Table..............................................................................16
8.
ACCESS INTERFACE .............................................................................................................. 17
8.1
Block Write protocol ...............................................................................................................17
8.2
Block Read protocol ...............................................................................................................17
8.3
Byte Write protocol .................................................................................................................17
II
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
8.4
9.
Byte Read protocol.................................................................................................................17
SPECIFICATIONS .................................................................................................................... 18
9.1
ABSOLUTE MAXIMUM RATINGS .......................................................................................18
9.2
General Operating Characteristics ........................................................................................18
9.3
Skew Group timing clock........................................................................................................18
9.4
CPU 0.7V Electrical Characteristics ......................................................................................19
9.5
SRC 0.7V Electrical Characteristics ......................................................................................19
9.6
ATIG 0.7V Electrical Characteristics......................................................................................19
9.7
PCI Electrical Characteristics.................................................................................................20
9.8
USB Electrical Characteristics ...............................................................................................20
9.9
REF Electrical Characteristics ...............................................................................................20
10.
ORDERING INFORMATION..................................................................................................... 21
11.
HOW TO READ THE TOP MARKING...................................................................................... 21
12.
PACKAGE DRAWING AND DIMENSIONS.............................................................................. 22
III
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
1. GENERAL DESCRIPTION
The W83195WG-416/W83195CG-416 is a Clock Synthesizer for ATI K8 serial chipsets. W83195WG416/ W83195CG-416 provides all clocks required for the high-speed microprocessor and provides
step-less frequency programming and 32 different frequencies of CPU, PCI, and SRC clocks setting,
all clocks are externally selectable with smooth transitions.
The W83195WG-416/W83195CG-416 provides I2C serial bus interface to program the registers to
enable or disable each clock outputs and provides programmable S.S.T. scale to reduce EMI.
The W83195WG-416/W83195CG-416 accepts a 14.318 MHz reference crystal as its input and runs
on a 3.3V supply.
2. PRODUCT FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
2 pair push-pull Differential clock outputs for CPU.
6 pair current-mode Differential clock outputs for SRC.
2 pair current-mode Differential clock outputs for ATIG programmable.
1 PCI clock output.
1 48 MHz clock output for USB.
3 14.318MHz REF clock outputs.
1 HTT 66MHz clock output.
Smooth frequency switch with selections from 100 to 400MHz.
Step-less frequency programming.
I2C 2-wire serial interface and support byte read/write and block read/write.
Programmable S.S.T. scale to reduce EMI in M/N mode.
Programmable registers to enable/disable each output and select modes.
Programmable clock outputs slew rate control and skew control.
• 56 pin TSSOP/SSOP package.
1
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
3. PIN CONFIGURATION
XIN
XOUT
VDD48
USB_48
GND
NC
SCLK
SDATA
&
FSC
&
CLKREQA#
&
CLKREQB#
SRCT7
SRCC7
VDDSRC
GND
SRCT6
SRCC6
SRCT5
SRCC5
GND
VDDSRC
SRCT4
SRCC4
SRCT3
SRCC3
GND
ATIGT1
ATIGC1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDREF
GND
&
FSA/REF0
&
FSB/REF1
REF2
VDDPCI
PCICLK0
GND
VDDHTT
HTTCLK0
GND
CPUCLK8T0
CPUCLK8C0
VDDCPU
GND
CPUCLK8T1
CPUCLK8C1
VDDA
GNDA
IREF
GND
VDDSRC
SRCT0
SRCC0
VDDATI
GND
ATIGT0
ATIGC0
#: Active low
*: Internal pull up resistor 120K to VDD
&: Internal Pull-down resistor 120K to GND
4. BLOCK DIAGRAM
2
D ivider
A TIG LO O P
2
ATIG T 0:1
A TIG C 0:1
U SB LO O P
D ivider
& Sync
C PU LO O P
Spread
Spectrum
XIN
XO U T
48M H z
3
XTA L
O SC
R EF 0:2
3
SR C LO O P
Spread
Spectrum
M /N /R atio
ROM
FS(A:C )
C R#_(A :B )
3
V CO CLK
6
D ivider
& Snyc
6
SRC T 0,3:7
SR C C 0,3:7
H TTC LK0
Latch
& PO R
PC I0
IREF
C ontrol
Logic
&C onfig
R egister
SD ATA
SCLK
C PU CLK8T 0:1
CPU C LK8C 0:1
475
I2C
Interface
2
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
5. PIN DESCRIPTION
PIN
PIN NAME
TYPE
DESCRIPTION
IN
Crystal output at 14.318MHz nominally with internal loading
capacitors (18pF).
Crystal input with internal loading capacitors (18pF) and feedback
resistors.
1
XIN
2
XOUT
OUT
3
VDD48
PWR Power supply for USB_48
4
USB_48
OUT 3.3V USB 48Mhz clock output.
5
GND
PWR Ground pin
6
VTT_PG#/PD
IN
Notifies CK410 to sample latched input or power down mode
7
SCLK
IN
Serial clock of I2C 2-wire control interface.
8
SDATA
I/O Serial data of I2C 2-wire control interface.
9
&
IN
FSC CPU frequency select
10
&
IN
Dynamic output control
0 = active, 1 = inactive
11
&
IN
Dynamic output control
0 = active, 1 = inactive
12
SRCT7
OUT 0.7V current mode differential clock output for SRC
13
SRCC7
OUT 0.7V current mode differential clock output for SRC
14
VDDSRC
PWR Power supply for SRC
15
GND
PWR Ground pin
16
SRCT6
OUT 0.7V current mode differential clock output for SRC
17
SRCC6
OUT 0.7V current mode differential clock output for SRC
18
SRCT5
OUT 0.7V current mode differential clock output for SRC
19
SRCC5
OUT 0.7V current mode differential clock output for SRC
20
GND
PWR Ground pin
21
VDDSRC
PWR Power supply for SRC
22
SRCT4
OUT 0.7V current mode differential clock output for SRC
23
SRCC4
OUT 0.7V current mode differential clock output for SRC
24
SRCT3
OUT 0.7V current mode differential clock output for SRC
25
SRCC3
OUT 0.7V current mode differential clock output for SRC
26
GND
PWR Ground pin
27
ATIGT1
OUT 0.7V current mode differential clock output for ATIG
28
ATIGC1
OUT 0.7V current mode differential clock output for ATIG
FSC
CLKREQA#
CLKREQB#
3
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
29
ATIGC0
OUT 0.7V current mode differential clock output for ATIG
30
ATIGT0
OUT 0.7V current mode differential clock output for ATIG
31
GND
PWR Ground pin
32
VDDATIG
PWR Power supply for ATIG
33
SRCC0
OUT 0.7V current mode differential clock output for SRC
34
SRCT0
OUT 0.7V current mode differential clock output for SRC
35
VDDSRC
PWR Power supply for SRC
36
GND
PWR Ground pin
37
IREF
Deciding the reference current for the differential pairs. The pin
OUT was connected to the precision resistor tied to ground to decide
the appropriate current; 475 ohm is the standard value.
38
GNDA
PWR Ground pin for PLL core.
39
VDDA
PWR 3.3V power supply for PLL core.
40
CPUCLK8C1
OUT 3.3V Push Pull differential clock output for AMD K8
41
CPUCLK8T1
OUT 3.3V Push Pull differential clock output for AMD K8
42
GND
PWR Ground pin
43
VDDCPU
PWR Power supply for CPU
44
CPUCLK8C0
OUT 3.3V Push Pull differential clock output for AMD K8
45
CPUCLK8T0
OUT 3.3V Push Pull differential clock output for AMD K8
46
GND
PWR Ground pin
47
HTTCLK0
OUT 3.3V HTT clock output.
48
VDDHTT
PWR Power supply for HTTCLK
49
GND
PWR Ground pin
50
PCICLK0
OUT 3.3V PCI clock output.
51
VDDPCI
PWR Power supply for PCI
52
REF2
OUT 3.3V REF 14.318Mhz clock output.
53
&
I/O FSB CPU frequency select/3.3V REF 14.318Mhz clock output.
54
&
I/O FSA CPU frequency select/3.3V REF 14.318Mhz clock output.
55
GND
PWR Ground pin
56
VDDREF
PWR Power supply for REF
FSB/REF1
FSA/REF0
4
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE
This frequency table is used at power on latched FS [2:0] value or software programming at SSEL
[4:0] (Register 0 bit 7 ~ 3). If FS [2:0] no any external circuit to modify power on status the Gray
shading is Hardware default frequency.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
FS4
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
0
0
0
0
CPU (MHZ)
SRC (MHZ)
PCI (MHZ)
0
266.68
100.00
33.33
0
1
133.34
100.00
33.33
0
1
0
200.01
100.00
33.33
0
1
1
166.59
111.06
33.32
0
1
0
0
333.17
111.06
33.32
0
0
1
0
1
100.00
100.00
33.33
0
0
1
1
0
400.01
100.00
33.33
0
0
1
1
1
200.06
100.03
33.34
0
1
0
0
0
266.68
100.00
33.33
0
1
0
0
1
133.34
100.00
33.33
0
1
0
1
0
200.01
100.00
33.33
0
1
0
1
1
166.59
111.06
33.32
0
1
1
0
0
333.17
111.06
33.32
0
1
1
0
1
100.00
100.00
33.33
0
1
1
1
0
400.01
100.00
33.33
0
1
1
1
1
200.06
100.03
33.34
1
0
0
0
0
100.00
100.00
33.33
1
0
0
0
1
133.34
100.00
33.33
1
0
0
1
0
200.01
100.00
33.33
1
0
0
1
1
166.59
111.06
33.32
1
0
1
0
0
199.90
99.95
33.32
1
0
1
0
1
266.68
100.00
33.33
1
0
1
1
0
400.01
100.00
33.33
1
0
1
1
1
333.30
111.10
33.33
1
1
0
0
0
100.00
100.00
33.33
1
1
0
0
1
133.34
100.00
33.33
1
1
0
1
0
200.01
100.00
33.33
1
1
0
1
1
166.59
111.06
33.32
1
1
1
0
0
199.90
99.95
33.32
1
1
1
0
1
266.68
100.00
33.33
1
1
1
1
0
400.01
100.00
33.33
1
1
1
1
1
333.30
111.10
33.33
5
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
7. I2C CONTROL AND STATUS REGISTERS
(The register No. is increased by 1 if use byte data read/write protocol)
7.1
BIT
Register 0: ( Default : 00h )
AFFECTED PIN/
FUNCTION NAME(S)
PWD
7
SSEL<4>
0
6
SSEL<3>
0
5
SSEL<2>
0
4
SSEL<1>
0
3
SSEL<0>
0
AFFECTED PIN / FUNCTION DESCRIPTION
Software frequency table selection through I2C
TYPE
R/W
Enable software table selection FS[4:0].
2
EN_SSEL
0
0 = Hardware table setting (Jump mode).
1 = Software table setting through Bit7~3 .
R/W
(Jumpless mode)
Enable spread spectrum mode under clock output.
1
SPSPEN
0
0 = Spread Spectrum mode disable
R/W
1 = Spread Spectrum mode enable
After watchdog timeout
0 = Reload the hardware FS [4:0] latched
0
EN_SAFE_FREQ
0
R/W
pins setting.
1 = Reload the desirable frequency table
selection defined at Reg-5 Bit 4~0.
7.2
BIT
Register 1: ( Default : XXh)
AFFECTED PIN/
FUNCTION NAME(S)
PWD
FUNCTION DESCRIPTION
TYPE
7
Reserved
1
6
CPUEN<1>
1
5
CPUEN<0>
1
4
Reserved
X
Reserved
CPUCLKT1/C1 output control
1: Enable
0: Disable
CPUCLKT0/C0 output control
1: Enable
0: Disable
Reserved
3
Reserved
X
Reserved
R
2
FS2_BACK
X
Power on latched value of FS2 pin. Default : 0
R
1
FS1_BACK
X
Power on latched value of FS1 pin. Default : 0
R
0
FS0_BACK
X
Power on latched value of FS0 pin. Default : 0
R
6
R/W
R/W
R/W
R
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
7.3
BIT
Register 2: ( Default : 03h )
AFFECTED PIN/
FUNCTION NAME(S)
PWD
FUNCTION DESCRIPTION
SRCCLK7 is controlled by the CLREQA# pin
1: Controllable
0: Uncontrollable
SRCCLK6 is controlled by the CLREQA# pin
1: Controllable
0: Uncontrollable
SRCCLK5 is controlled by the CLREQA# pin
1: Controllable
0: Uncontrollable
SRCCLK4 is controlled by the CLREQA# pin
1: Controllable
0: Uncontrollable
SRCCLK3 is controlled by the CLREQA# pin
1: Controllable
0: Uncontrollable
SRCCLK0 is controlled by the CLREQA# pin
1: Controllable
0: Uncontrollable
TYPE
7
CLREQA7#_Ctr
0
6
CLREQA6#_Ctr
0
5
CLREQA5#_Ctr
0
4
CLREQA4#_Ctr
0
3
CLREQA3#_Ctr
0
2
CLREQA0#_Ctr
0
1
Reserved
1
Reserved
R/W
0
Reserved
1
Reserved
R/W
7.4
BIT
R/W
R/W
R/W
R/W
R/W
R/W
Register 3: ( Default : 03h )
AFFECTED PIN/
FUNCTION NAME(S)
PWD
7
CLREQB7#_Ctr
0
6
CLREQB6#_Ctr
0
5
CLREQB5#_Ctr
0
4
CLREQB4#_Ctr
0
3
CLREQB3#_Ctr
0
FUNCTION DESCRIPTION
SRCCLK7 is controlled by the CLREQB# pin
1: Controllable
0: Uncontrollable
SRCCLK6 is controlled by the CLREQB# pin
1: Controllable
0: Uncontrollable
SRCCLK5 is controlled by the CLREQB# pin
1: Controllable
0: Uncontrollable
SRCCLK4 is controlled by the CLREQB# pin
1: Controllable
0: Uncontrollable
SRCCLK3 is controlled by the CLREQB# pin
1: Controllable
0: Uncontrollable
7
TYPE
R/W
R/W
R/W
R/W
R/W
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
2
CLREQB0#_Ctr
0
1
PCIEN
1
0
HTTEN
1
7.5
BIT
SRCCLK0 is controlled by the CLREQB# pin
1: Controllable
0: Uncontrollable
PCI0 output control
1: Enable
0: Disable
HTT66 output control
1: Enable
0: Disable
R/W
R/W
R/W
Register 4: ( Default : FEh)
AFFECTED PIN/
FUNCTION NAME(S)
PWD
FUNCTION DESCRIPTION
TYPE
7
Reserved
1
Reserved
R/W
6
Reserved
1
Reserved
R/W
5
Reserved
1
Reserved
R/W
4
REFEN<2>
1
3
REFEN<1>
1
2
REFEN<0>
1
1
F48EN
1
0
Reserved
0
7.6
BIT
7
6
PREF2 output control
1: Enable
0: Disable
PREF1 output control
1: Enable
0: Disable
PREF0 output control
1: Enable
0: Disable
PUSB48 output control
1: Enable
0: Disable
R/W
R/W
R/W
R/W
Reserved
R/W
Register 5: ( Default : 02h )
AFFECTED PIN/
FUNCTION NAME(S)
Reserved
CNT_EN
PWD
FUNCTION DESCRIPTION
TYPE
0
Reserved
R/W
0
Program this bit =>
1 : Enable Watchdog Timer feature.
0 : Disable Watchdog Timer feature.
Enable WD sequence =>
Program this bit to 1 firstly, then program the
Reg-20 to start the counting
Read-back this bit =>
R/W
8
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
During timer count down the bit read back to 1.
If count to zero, this bit read back to 0.
0
5
WD_TIMEOUT
4
SAF_FREQ<4>
0
3
SAF_FREQ<3>
0
2
SAF_FREQ<2>
0
1
SAF_FREQ<1>
1
0
SAF_FREQ<0>
0
7.7
BIT
Read Back only. Timeout Flag.
1 : Watchdog has ever started and count to zero.
0 : a.) Watchdog is restarted and counting.
b.) Power on default state
R
These bits will be reloaded in Reg-0 to select
frequency table. As the watchdog is timeout and
EN_SAFE_FREQ=1.
R/W
Register 6: ( Default : FFh )
AFFECTED PIN/
FUNCTION NAME(S)
PWD
7
SRCEN<7>
1
6
SRCEN<6>
1
5
SRCEN<5>
1
4
SRCEN<4>
1
3
SRCEN<3>
1
2
ATIGEN<1>
1
1
ATIGEN<0>
1
0
SRCEN<0>
1
FUNCTION DESCRIPTION
SRC7 output control
1: Enable
0: Disable
SRC6 output control
1: Enable
0: Disable
SRC5 output control
1: Enable
0: Disable
SRC4 output control
1: Enable
0: Disable
SRC3 output control
1: Enable
0: Disable
ATIG1 output control
1: Enable
0: Disable
ATI clock can’t be controlled by CLKREQ# pins
ATIG0 output control
1: Enable
0: Disable
ATI clock can’t be controlled by CLKREQ# pins
SRC0 output control
1: Enable
0: Disable
9
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
7.8
BIT
Register 7: Winbond Chip ID – Project Code Register ( Default : 06h )
AFFECTED PIN/
FUNCTION NAME(S)
PWD
FUNCTION DESCRIPTION
TYPE
7
CHIP_ID [7]
0
Winbond Chip ID.W83195CG/W-416 (BA5A06).
R
6
CHIP_ID [6]
0
Winbond Chip ID.
R
5
CHIP_ID [5]
0
Winbond Chip ID.
R
4
CHIP_ID [4]
0
Winbond Chip ID.
R
3
CHIP_ID [3]
0
Winbond Chip ID.
R
2
CHIP_ID [2]
1
Winbond Chip ID.
R
1
CHIP_ID [1]
1
Winbond Chip ID.
R
0
CHIP_ID [0]
0
Winbond Chip ID.
R
7.9
BIT
Register 8: ( Default :D0h )
AFFECTED PIN/
FUNCTION NAME(S)
PWD
FUNCTION DESCRIPTION
TYPE
7
NVAL<8>
1
Programmable N divisor value. Bit 7 ~0 are defined
in the Register 9.
R/W
6
NVAL<9>
1
Programmable N divisor value. Bit 7 ~0 are defined
in the Register 9.
R/W
5
MVAL<5>
0
4
MVAL<4>
1
3
MVAL<3>
0
2
MVAL<2>
0
Programmable M divisor
R/W
1
MVAL<1>
0
0
MVAL<0>
0
7.10 Register 9: ( Default : 7Ah )
BIT
AFFECTED PIN/
FUNCTION NAME(S)
PWD
7
NVAL<7>
0
6
NVAL<6>
1
5
NVAL<5>
1
4
NVAL<4>
1
3
NVAL<3>
1
2
NVAL<2>
0
1
NVAL<1>
1
0
NVAL<0>
0
FUNCTION DESCRIPTION
TYPE
Programmable N divisor bit 7 ~0. The bit 8,9 is
defined in Register 8.
R/W
Default value follow FS=0
10
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
7.11 Register 10: Reserved ( Default : 3Bh )
7.12 Register 11: ( Default : 0Eh )
AFFECTED PIN/
FUNCTION NAME(S)
BIT
PWD
7
SPH VAL<3>
0
6
SPH VAL<2>
0
5
SPH VAL<1>
0
4
SPH VAL<0>
0
3
SPL VAL<3>
1
2
SPL VAL<2>
1
1
SPL VAL<1>
1
0
SPL VAL<0>
0
FUNCTION DESCRIPTION
TYPE
Spread Spectrum Up Counter bit 3 ~ bit 0.
R/W
Spread Spectrum Down Counter bit 3 ~ bit 0
2’s complement representation.
Ex: 1 -> 1111 ; 2 -> 1110 ; 7 -> 1001 ; 8 ->
1000
7.13 Register 12: ( Default : XXh )
AFFECTED PIN/
FUNCTION NAME(S)
BIT
PWD
FUNCTION DESCRIPTION
TYPE
7
Reserved
0
Reserved
R/W
6
KVAL<9>
X
R/W
5
KVAL<5>
X
Define the PCI divider ratio
Table-2 integrate the all divider configuration
4
KVAL<4>
X
R/W
3
KVAL<3>
X
Define the SRC divider ratio
Refer to Table-2
2
KVAL<2>
X
1
KVAL<1>
X
R/W
0
KVAL<0>
X
Define the CPU divider ratio
Refer to Table-2
Table-2 CPU, SRC, PCI divider ratio selection Table
LSB
MSB
Bit2/
HTT/PCI
SRC
CPU
BIT5
BIT3
BIT1,0
0
1
0
1
00
01
10
11
0
Reserved
Div10
Reserved
Div6
Div2
Div3
Div4
Div6
1
Div12
Div15
Div8
Div10
Div8
Div8
Div8
Div8
Bit4/
Bit9
11
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
7.14 Register 13: ( Default : 3Fh )
BIT
AFFECTED PIN/
FUNCTION NAME(S)
PWD
7
EN_MN_PROG
0
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
IVAL<3>
IVAL<2>
IVAL<1>
IVAL<0>
0
1
1
1
1
1
1
FUNCTION DESCRIPTION
TYPE
0: Output frequency depend on frequency table
1: Program all clock frequency by changing M/N
value
The equation is
VCO =14.318MHz*(N+4)/ M.
Once the watchdog timer timeout, the bit will be
clear. Then the frequency will be decided by
hardware default FS<4:0> or desired frequency
select SAF_FREQ[4:0] depend on
EN_SAFE_FREQ (Reg0 – bit0).
Reserved
R/W
Reserved
R/W
Charge pump current selection
R/W
7.15 Register 14: ( Default : D0h )
BIT
7
AFFECTED PIN/
FUNCTION NAME(S)
PWD
FUNCTION DESCRIPTION
TYPE
Reserved
1
Reserved
R/W
6
Reserved
1
Reserved
R/W
5
SPCNT<5>
0
4
SPCNT<4>
1
3
SPCNT<3>
0
2
SPCNT<2>
0
1
SPCNT<1>
0
0
SPCNT<0>
0
Spread Spectrum Programmable time, the
resolution is 280ns. Default period is 11.8us
R/W
7.16 Register 15: ( Default : 5Ch )
BIT
AFFECTED PIN/
FUNCTION NAME(S)
PWD
FUNCTION DESCRIPTION
TYPE
7
INV_CPU
0
Invert the CPUCLKT1/0 phase
0: Default
1: Inverse
R/W
6
Reserved
1
Reserved
R/W
12
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
5
DRI_CONT
0
SRCT/ ATIG output state in during POWER
DOWN assertion.
1: Driven (2*Iref)
0: Tristate (Floating)
SRCT/ ATIG output state in during STOP Mode
assertion.
1: Driven (6*Iref)
0: Tristate (Floating)
Complementary parts always tri-state (floating) in
power down or stop mode.
4
Reserved
1
Reserved
R/W
3
CPU2HTT_SYNC
1
CPU align with HTT
1 : Enable
0 : Disable
R/W
2
AZSKEW<2>
1
1
AZSKEW<1>
0
0
AZSKEW<0>
0
CPU1 to HTT66 skew control.
Skew resolution is 300ps
The decision of skew direction is same as
ASKEW<2:0> setting
R/W
R/W
7.17 Register 16: ( Default : 24h )
BIT
7
AFFECTED PIN/
FUNCTION NAME(S)
INV_SRC
PWD
FUNCTION DESCRIPTION
TYPE
0
Invert the SRC phase
0: Default
1: Inverse
R/W
Invert the HTT & PCI phase
0: Default
1: Inverse
R/W
CPUCLKT1 to CPUCLKT0 skew control
Skew resolution is 300ps
The decision of skew direction is same as
CSKEW<2:0> setting
R/W
CPU1 to PCI skew control
Skew resolution is 300ps
The decision of skew direction is same as
PSKEW<2:0> setting
R/W
6
INV_PCI
0
5
CSKEW<2>
1
4
CSKEW<1>
0
3
CSKEW<0>
0
2
PSKEW<2>
1
1
PSKEW<1>
0
0
PSKEW<0>
0
7.18 Register 17: Reserved ( Default : 07h )
7.19 Register 18: Reserved ( Default : 7Ah )
13
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
7.20 Register 19: ( Default : 04h )
BIT
AFFECTED PIN/
FUNCTION NAME(S)
PWD
7
SRC_FS<4>
0
6
SRC_FS<3>
0
5
SRC_FS<2>
0
4
SRC_FS<1>
0
3
SRC_FS<0>
0
2
CENTERSKEW<2>
1
1
CENTERSKEW<1>
0
0
CENTERSKEW<0>
0
FUNCTION DESCRIPTION
TYPE
R/W
SRC frequency table. See Table-3.
SRC_FS<4> also is spread spectrum enable bit.
CPU1 center skew control
Skew resolution is 300ps
The decision of skew direction is same as
CENTERSKEW<2:0> setting
R/W
R/W
R/W
7.21 Register 20: ( Default : 88h )
BIT
AFFECTED PIN/
FUNCTION NAME(S)
PWD
7
Reserved
1
6
SEC<6>
0
5
SEC<5>
0
4
SEC<4>
0
3
SEC<3>
1
2
SEC<2>
0
1
SEC<1>
0
0
SEC<0>
0
FUNCTION DESCRIPTION
TYPE
Reserved
R/W
Setting the down count depth (Failure decision).
One bit resolution represent 250ms. Default time
depth is 8*250ms = 2.0 second. If the watchdog
timer is counting, this register will return present
down count value.
R/W
7.22 Register 21: ( Default : ECh )
BIT
AFFECTED PIN/
FUNCTIONNAME(S)
PWD
FUNCTION DESCRIPTION
Reserved
TYPE
7
Reserved
1
R/W
6
CPU2SRC_SYNC
1
5
CPU2PCI_SYNC
1
4
Reserved
0
Reserved
R/W
3
Reserved
1
Reserved
R/W
CPU align with SRC
1 : Enable
0 : Disable
CPU align with PCI
1 : Enable
0 : Disable
14
R/W
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
2
SRCSKEW<2>
1
1
SRCSKEW<1>
0
0
SRCSKEW<0>
0
CPU1 to SRC skew control
Skew resolution is 300ps
The decision of skew direction is same as
SRCSKEW<2:0> setting
15
R/W
R/W
R/W
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
Table3: SRC & ATIG Frequency Selection Table
BIT 7
FS4
BIT 6
FS3
BIT 5
FS2
BIT 4
FS1
BIT 3
FS0
SRC,ATIG
(MHZ)
0
0
0
0
0
0
SPREAD(%)
0
0
0
0
0
1
100.00
100.00
0
0
0
1
0
100.00
0
0
0
0
1
1
100.00
0
0
0
1
0
0
0
0
1
0
1
101.00
101.00
0
0
0
1
1
0
101.00
0
0
0
1
1
1
101.00
0
0
1
0
0
0
0
0
1
0
0
1
102.00
102.00
0
0
1
0
1
0
102.00
0
0
1
0
1
1
102.00
0
0
1
1
0
0
0
0
1
1
0
1
104.00
104.00
0
0
1
1
1
0
104.00
0
0
1
1
1
1
104.00
0
-0.5
-0.5
1
0
0
0
0
100.00
1
0
0
0
1
100.00
1
0
0
1
0
100.00
1
0
0
1
1
100.00
1
0
1
0
0
101.00
1
0
1
0
1
101.00
1
0
1
1
0
101.00
1
0
1
1
1
101.00
1
1
0
0
0
102.00
1
1
0
0
1
102.00
1
1
0
1
0
102.00
1
1
0
1
1
102.00
1
1
1
0
0
104.00
1
1
1
0
1
104.00
1
1
1
1
0
104.00
1
104.00
1
1
1
1
16
0
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
8. ACCESS INTERFACE
The W83195BR-416 provides I2C Serial Bus for microprocessor to read/write internal registers. In the
W83195BR-416 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C
address is defined at 0xD2.
The register number is increased by one if using byte data read/write protocol.
Example: In block mode, byte number of program register is 1
In byte mode, byte number of program register is 2 (Byte number of block mode +1)
8.1
Block Write protocol
8.2
Block Read protocol
## In block mode, the command code must filled 8’h00
8.3
Byte Write protocol
8.4
Byte Read protocol
17
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
9. SPECIFICATIONS
9.1
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.
Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).
9.2
PARAMETER
RATING
Absolute 3.3V Core Supply Voltage
-0.5V to +4.6V
Absolute 3.3V I/O Supple Voltage
- 0.5V to + 4.6V
Operating 3.3V Core Supply Voltage
3.135V to 3.465V
Operating 3.3V I/O Supple Voltage
3.135V to 3.465V
Storage Temperature
- 65°C to + 150°C
Ambient Temperature
- 55°C to + 125°C
Operating Temperature
0°C to + 70°C
Input ESD protection (Human body model)
2000V
General Operating Characteristics
VDD= 3.3V ± 5 %, TA = 0°C to +70°C,
Parameter
Symbol
Input Low Voltage
VIL
Input High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
Operating Supply Current
Input pin capacitance
Output pin capacitance
Input pin inductance
9.3
Min
Max
Units
0.8
Vdc
2.0
Test Conditions
Vdc
0.4
2.4
Vdc
Vdc
Idd
350
mA
Cin
5
pF
Cout
6
pF
Lin
7
nH
CPU = 100 to 400 MHz
PCI = 33.3 Mhz with load 10pF
Skew Group timing clock
VDD = 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF
Parameter
Min
Max
Units
CPU pair to CPU pair Skew
100
ps
Measure Crossing point
SRC pair to SRC pair Skew
125
ps
Measure Crossing point
PCI to PCI Skew
250
ps
Measured at 1.5V
48MHz to 48MHz Skew
1000
ps
Measured at 1.5V
18
Test Conditions
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
9.4
CPU 0.7V Electrical Characteristics
VDDC= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V,
Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF
Parameter
Min
Max
Units
Rise Time
175
700
ps
Measure Single Ended waveform
Fall Time
175
700
ps
Measure Single Ended waveform
Absolute crossing point Voltages
250
550
mV
Measure Single Ended waveform
Voltage High
660
850
mV
Measure Single Ended waveform
Voltage Low
-150
mV
Measure Single Ended waveform
100
ps
Measure Differential waveform
55
%
Measure Differential waveform
Cycle to Cycle jitter
Duty Cycle
9.5
45
Test Conditions
SRC 0.7V Electrical Characteristics
VDDS= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V,
Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF
Parameter
Min
Max
Units
Rise Time
175
700
ps
Measure Single Ended waveform
Fall Time
175
700
ps
Measure Single Ended waveform
Absolute crossing point Voltages
250
550
mV
Measure Single Ended waveform
Voltage High
660
850
mV
Measure Single Ended waveform
Voltage Low
-150
mV
Measure Single Ended waveform
100
ps
Measure Differential waveform
55
%
Measure Differential waveform
Cycle to Cycle jitter
Duty Cycle
9.6
45
Test Conditions
ATIG 0.7V Electrical Characteristics
VDDPE= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V,
Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF
Parameter
Min
Max
Units
Rise Time
175
700
ps
Measure Single Ended waveform
Fall Time
175
700
ps
Measure Single Ended waveform
Absolute crossing point Voltages
250
550
mV
Measure Single Ended waveform
Voltage High
660
850
mV
Measure Single Ended waveform
Voltage Low
-150
mV
Measure Single Ended waveform
100
ps
Measure Differential waveform
55
%
Measure Differential waveform
Cycle to Cycle jitter
Duty Cycle
45
19
Test Conditions
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
9.7
PCI Electrical Characteristics
VDDP= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,
Parameter
Min
Max
Units
Rise Time
500
2000
ps
Vol=0.4V, Voh=2.4V
Fall Time
500
2000
ps
Voh=2.4V, Vol=0.4V
250
ps
Measured at 1.5V
55
%
Measured at 1.5V
Cycle to Cycle jitter
Duty Cycle
45
Pull-Up Current Min
-33
Pull-Up Current Max
Pull-Down Current Min
-33
30
Pull-Down Current Max
9.8
38
Test Conditions
mA
Vout=1.0V
mA
Vout=3.135V
mA
Vout=1.95V
mA
Vout=0.4V
USB Electrical Characteristics
VDD48= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,
Parameter
Min
Max
Units
Rise Time
500
2000
ps
Vol=0.4V, Voh=2.4V
Fall Time
500
2000
ps
Voh=2.4V, Vol=0.4V
300
ps
Measured at 1.5V
55
%
Measured at 1.5V
Long term jitter
Duty Cycle
45
Pull-Up Current Min
-29
Pull-Up Current Max
Pull-Down Current Min
-23
29
Pull-Down Current Max
9.9
27
Test Conditions
mA
Vout=1.0V
mA
Vout=3.135V
mA
Vout=1.95V
mA
Vout=0.4V
REF Electrical Characteristics
VDD= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,
Parameter
Min
Max
Units
Rise Time
500
2000
ps
Vol=0.4V, Voh=2.4V
Fall Time
500
2000
ps
Voh=2.4V, Vol=0.4V
700
ps
Measured at 1.5V
55
%
Measured at 1.5V
Cycle to Cycle jitter
Duty Cycle
45
Pull-Up Current Min
-33
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
-33
30
38
20
Test Conditions
mA
Vout=1.0V
mA
Vout=3.135V
mA
Vout=1.95V
mA
Vout=0.4V
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
10. ORDERING INFORMATION
PART NUMBER
PACKAGE TYPE
PRODUCTION FLOW
W83195WG-416
56 PIN TSSOP
Commercial, 0°C to +70°C
W83195CG-416
56 PIN SSOP
Commercial, 0°C to +70°C
11. HOW TO READ THE TOP MARKING
W83195WG-416
28051234
604LBABA
W83195CG-416
28051234
604GBABA
1st line: Winbond logo and the type number: W83195WG-416/W83195CG-416
2nd line: Tracking code 2 8051234
2:
wafers manufactured in Winbond FAB 2
8051234: wafer production series lot number
3rd line: Tracking code
604 L B A BA
604: packages made in '2006, week 04
L: assembly house ID; O means OSE, G means GR, L means Lingsen.
B: Internal use code
A: IC revision
BA: mask version
All the trademarks of products and companies mentioned in this data sheet belong to their
respective owners.
21
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
12. PACKAGE DRAWING AND DIMENSIONS
56 PIN TSSOP-240mil
56 PIN SSOP-300mil
.035
.045
DIMENSION IN MM
SYMBOL
.045
.055
A
A1
A2
b
0.40/0.50 DIA
E
END VIEW
HE
TOP VIEW
SEE DETAIL "A"
c
D
θ
A2
A
Y
SEATING PLANE
A1
e
b
SIDE VIEW
θ
c
0.13
D
HE
18.2
18.42 18.54
910.16 10.31 10.41
E
7.42
0.51
7.52
0.64
7.59
0.76
0.61
0.81
1.40
1.02
e
L
L1
PARTING LINE
Y
c
θ
DIMENSION IN INCH
MIN. NOM MAX. MIN. NOM
0.095 0.101
2.41
2.57 2.79
0.41 0.008 0.012
0.20 0.30
0.088 0.090
2.34
2.24 2.29
0.25
0.20
0.34 0.008 0.010
0
0.25
0.08
8
0.005
0.720
0.400
0.292
0.020
0.024
MAX.
0.110
0.016
0.092
0.0135
0.010
0.725 0.730
0.406 0.410
0.296 0.299
0.025 0.030
0.032 0.040
0.055
0.003
0
8
L
L1
DETAIL"A"
22
Publication Release Date: Feb 2006
Revision 0.6
W83195WG-416/W83195CG-416
STEPLESS FOR ATI K8 CLOCK GENERATOR
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62365998
Taipei Office
Winbond Electronics Corporation Japan
Winbond Electronics (H.K.) Ltd.
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
TEL: 81-45-4781881
FAX: 81-45-4781800
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
23
Publication Release Date: Feb 2006
Revision 0.6