TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS660 – MARCH 1996 D D D D D D D D D D Organization TM124FBK32F . . . 1 048 576 × 32 TM248GBK32F . . . 2 097 152 × 32 Single 5-V Power Supply (±10% Tolerance) 72-Pin Single In-Line Memory Module (SIMM) for Use With Socket TM124FBK32F – Utilizes Two 16M-Bit Dynamic Random-Access Memories (DRAMs) in Plastic Small-Outline J-Lead (SOJ) Package TM248GBK32F – Utilizes Four 16M-Bit DRAMs in Plastic SOJ Package Long Refresh Period 16 ms (1 024 Cycles) All Inputs, Outputs, Clocks Fully TTL-Compatible 3-State Output Common CAS Control for Eight Common Data-In and Data-Out Lines in Four Blocks Extended Data Out (EDO) Operation With CAS-Before-RAS ( CBR), RAS-Only, Hidden Refresh, and Self Refresh D D D D D D D Presence Detect JEDEC First Generation 72-Pin SIMM Pinout Performance Ranges: ACCESS TIME tRAC (MAX) ’124FBK32F-60 60 ns ’124FBK32F-70 70 ns ’124FBK32F-80 80 ns ’248GBK32F-60 60 ns ’248GBK32F-70 70 ns ’248GBK32F-80 80 ns ACCESS ACCESS EDO TIME TIME CYCLE tAA tCAC tHPC (MAX) (MAX) (MIN) 30 ns 15 ns 25 ns 35 ns 18 ns 30 ns 40 ns 20 ns 35 ns 30 ns 15 ns 25 ns 35 ns 18 ns 30 ns 40 ns 20 ns 35 ns Low Power Dissipation Operating Free-Air Temperature Range 0°C to 70°C Gold-Tabbed Versions Available: † TM124FBK32F TM248GBK32F Tin-Lead Solder-Tabbed Versions Available: TM124FBK32U TM248GBK32U description TM124FBK32F The TM124FBK32F is a 4M-byte DRAM organized as four times 1 048 576 × 8 in a 72-pin SIMM. The SIMM is composed of two TMS418169DZ 1 048 576 × 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418169DZ is described in the TMS418169 data sheet (literature number SMKS886). The TM124FBK32F SIMM is available in the single-sided BK-leadless module for use with sockets. TM248GBK32F The TM248GBK32F is an 8M-byte DRAM organized as four times 2 097 152 × 8 in a 72-pin SIMM. The SIMM is composed of four TMS418169DZ 1 048 576 × 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418169DZ is described in the TMS418169 data sheet (literature number SMKS886). The TM248GBK32F SIMM is available in the double-sided BK-leadless module for use with sockets. operation The TM124FBK32F operates as two TMS418169DZs connected as shown in the functional block diagram and in Table 1. The TM248GBK32F operates as four TMS418169DZs connected as shown in the functional block diagram and in Table 1. The common I / O feature dictates the use of early-write cycles to prevent contention on D and Q. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS660 – MARCH 1996 BK SINGLE IN-LINE MEMORY MODULE ( TOP VIEW ) 2 VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6 NC DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VCC A8 A9 RAS3 RAS2 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 TM124FBK32F ( SIDE VIEW ) TM248GBK32F ( SIDE VIEW ) PIN NOMENCLATURE A0 – A9 CAS0 – CAS3 DQ0 – DQ31 NC PD1 – PD4 RAS0 – RAS3 VCC VSS W Address Inputs Column-Address Strobe Data In/Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable PRESENCE DETECT SIGNAL (PIN) PD1 (67) PD2 (68) VSS VSS VSS VSS 80 ns VSS NC VSS NC 70 ns NC NC 60 ns NC NC 80 ns TM124FBK32F 70 ns 60 ns TM248GBK32F POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PD3 (69) PD4 (70) NC VSS NC VSS NC NC VSS NC NC VSS NC NC TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS660 – MARCH 1996 Table 1. Connection Table DATA BLOCK RASx SIDE 1 SIDE 2† CASx DQ0 – DQ7 RAS0 RAS1 CAS0 DQ8 – DQ15 RAS0 RAS1 CAS1 DQ16 – DQ23 RAS2 RAS3 CAS2 DQ24 – DQ31 RAS2 RAS3 CAS3 † Side 2 applies to the TM248GBK32F and the TM248GBK32U. single in-line memory module and components PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch / inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM124FBK32F and TM248GBK32F: Nickel plate and gold plate over copper Contact area for TM124FBK32U and TM248GBK32U: Nickel plate and tin/lead over copper functional block diagram (TM124FBK32F and TM248GBK32F, side 1) 10 A0 – A9 RAS0 RAS2 W 10 CAS0 CAS1 1M × 16 A0 –A9 DQ0 – DQ7 RAS W LCAS DQ8 – UCAS DQ15 10 DQ0 – DQ7 DQ8 – DQ15 CAS2 CAS3 1M × 16 A0 –A9 DQ0 – RAS DQ7 W LCAS DQ8 – UCAS DQ15 DQ16 – DQ23 DQ24 – DQ31 functional block diagram (TM248GBK32F, side 2) 10 A0 – A9 RAS1 RAS3 W 10 CAS1 CAS0 1M × 16 A0 –A9 DQ0 – RAS DQ7 W LCAS DQ8 – UCAS DQ15 10 DQ8 – DQ15 DQ0 – DQ7 POST OFFICE BOX 1443 CAS3 CAS2 • HOUSTON, TEXAS 77251–1443 1M × 16 A0 –A9 DQ0 – RAS DQ7 W LCAS DQ8 – UCAS DQ15 DQ24 – DQ31 DQ16 – DQ23 3 TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS660 – MARCH 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM124FBK32F, TM124FBK32U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W TM248GBK32F, TM248GBK32U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX VCC VIH Supply voltage 4.5 5 5.5 V High-level input voltage 2.4 6.5 V VIL TA Low-level input voltage (see Note 2) –1 0.8 V 0 70 °C Operating free-air temperature UNIT NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH VOL High-level output voltage Low-level output voltage ’124FBK32F - 60 TEST CONDITIONS ‡ MIN IOH = – 5 mA IOL = 4.2 mA MAX 2.4 ’124FBK32F - 70 MIN MAX 2.4 ’124FBK32F - 80 MIN MAX 2.4 UNIT V 0.4 0.4 0.4 V ± 10 ± 10 ± 10 µA II Input current (leakage) VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC, CAS high ± 10 ± 10 ± 10 µA ICC1 Read- or write-cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 380 360 340 mA VIH = 2.4 V (TTL), After one memory cycle, RAS and CAS high 4 4 4 mA VIH = VCC – 0.2 V (CMOS), After one memory cycle, RAS and CAS high 2 2 2 mA ICC2 Standby current ICC3 Average refresh current (RAS only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 380 360 340 mA ICC4 Average EDO current (see Note 4) VCC = 5.5 V, tHPC = MIN, CAS cycling RAS low, 200 180 160 mA ‡ For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS660 – MARCH 1996 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) VOH High-level output voltage IOH = – 5 mA VOL Low-level output voltage IOL = 4.2 mA II Input current (leakage) IO ICC1 ICC2 ’248GBK32F - 60 TEST CONDITIONS † PARAMETER MIN ’248GBK32F - 70 MAX 2.4 MIN ’248GBK32F - 80 MAX MIN 2.4 MAX 2.4 UNIT V 0.4 0.4 0.4 V VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 µA Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC, CAS high ± 20 ± 20 ± 20 µA Read- or write-cycle current (see Note 3) VCC = 5.5 V, 384 364 344 mA VIH = 2.4 V (TTL), After one memory cycle, RAS and CAS high 8 8 8 mA VIH = VCC – 0.2 V (CMOS), After one memory cycle, RAS and CAS high 4 4 4 mA Standby current Minimum cycle ICC3 Average refresh current (RAS only or CBR) (see Notes 3 and 5) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 760 720 680 mA ICC4 Average EDO current (see Note 4) VCC = 5.5 V, RAS low, 204 184 164 mA tPC = MIN, CAS cycling † For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH 5. Measured with both sides in CBR cycle capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 6) ’124FBK32F PARAMETER Ci(A) Input capacitance, A0 – A9 Ci(R) Input capacitance, RAS inputs Ci(C) Input capacitance, CAS inputs Ci(W) Input capacitance, W MIN MAX 12 Co(DQ) Output capacitance on DQ0 – DQ31 NOTE 6: VCC = 5 V ± 0.5 V, and the bias on pins under test is 0 V. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ’248GBK32F MIN MAX UNIT 22 pF 8 8 pF 8 15 pF 16 30 pF 8 15 pF 5 TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS660 – MARCH 1996 switching characteristics over recommended ranges of supply voltage and operating free-air temperature ’124FBK32F - 60 ’248GBK32F - 60 PARAMETER MIN ’124FBK32F - 70 ’248GBK32F - 70 MAX MIN MAX ’124FBK32F - 80 ’248GBK32F - 80 MIN UNIT MAX tAA tCAC Access time from column address 30 35 40 ns Access time from CAS low 15 18 20 ns tRAC tCPA Access time from RAS low 60 70 80 ns Access time from column precharge 35 40 45 ns tCLZ tREZ CAS to output in low-impedance state 0 Output disable time after RAS high (see Note 7) 3 15 3 18 3 20 ns 3 15 3 18 3 20 ns tWEZ Output disable time after W low (see Note 7) NOTE 7: tREZ and tWEZ are specified when the output is no longer driven. 0 0 ns EDO timing requirements over recommended ranges of supply voltage and operating free-air temperature ’124FBK32F - 60 ’248GBK32F - 60 MIN ’124FBK32F - 70 ’248GBK32F - 70 MAX MIN MAX ’124FBK32F - 80 ’248GBK32F - 80 MIN UNIT MAX tHPC tPRWC Cycle time, EDO page-mode read or write 25 30 35 ns Cycle time, EDO read-write 80 90 100 ns tCSH tDOH Hold time, CAS from RAS 50 55 60 ns 3 3 3 ns tCAS tWPE Pulse duration, CAS Pulse duration, W (output disable only) 5 5 5 ns tCP Precharge time, CAS 5 5 5 ns Hold time, output from CAS 10 10 000 12 10 000 15 10 000 ns timing requirements over recommended ranges of supply voltage and operating free-air temperature ’124FBK32F - 60 ’248GBK32F - 60 MIN ’124FBK32F - 70 ’248GBK32F - 70 MAX MIN MAX ’124FBK32F - 80 ’248GBK32F - 80 MIN UNIT MAX tRC tRWC Cycle time, random read or write (see Note 8) 110 130 150 Cycle time, read-write 150 175 200 tRASP tRAS Pulse duration, page mode, RAS low 60 100 000 70 100 000 80 100 000 ns Pulse duration, nonpage mode, RAS low 60 10 000 70 10 000 80 10 000 ns tRP tWP Pulse duration, RAS high (precharge) 40 50 60 ns Pulse duration, W low 10 10 10 ns tRASS tRPS Pulse duration, self refresh entry from RAS low 100 100 100 µs Pulse duration, RAS precharge after self refresh 110 130 150 ns tASC tASR Setup time, column address before CAS low 0 0 0 ns Setup time, row address before RAS low 0 0 0 ns tDS tRCS Setup time, data before CAS low 0 0 0 ns Setup time, W high before CAS low tCWL Setup time, W low before CAS high NOTE 8: The ac parameter assumes tT = 5 ns. 6 POST OFFICE BOX 1443 ns ns 0 0 0 ns 10 12 15 ns • HOUSTON, TEXAS 77251–1443 TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS660 – MARCH 1996 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) ’124FBK32F - 60 ’248GBK32F - 60 MIN ’124FBK32F - 70 ’248GBK32F - 70 MAX MIN MAX ’124FBK32F - 80 ’248GBK32F - 80 MIN UNIT MAX tRWL tWCS Setup time, W low before RAS high 10 12 15 ns Setup time, W low before CAS low 0 0 0 ns tCAH tDH Hold time, column address after CAS low 10 15 15 ns Hold time, data after CAS low 10 15 15 ns tRAH tRCH Hold time, row address after RAS low 10 10 10 ns Hold time, W high after CAS high (see Note 9) 0 0 0 ns tRRH tWCH Hold time, W high after RAS high (see Note 9) 0 0 0 ns Hold time, W low after CAS low 10 15 15 ns tRHCP tCHS Hold time, RAS high from CAS precharge 35 40 45 ns – 50 – 50 – 50 ns tCHR tCRP Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns 5 5 5 ns tCSR tRAD Delay time, CAS low to RAS low (CBR refresh only) Delay time, RAS low to column address (see Note 10) 15 tRAL tCAL Delay time, column address to RAS high 30 Delay time, column address to CAS high 20 tRCD tRPC Delay time, RAS low to CAS low (see Note 10) 20 tRSH tREF Delay time, CAS low to RAS high Hold time, CAS low after RAS high (self refresh) Delay time, CAS high to RAS low 5 Delay time, RAS high to CAS low (CBR only) 5 30 15 35 20 POST OFFICE BOX 1443 20 0 0 12 15 2 30 • HOUSTON, TEXAS 77251–1443 16 2 30 2 ns ns 30 52 0 16 ns 40 40 25 45 15 10 Refresh time interval tT Transition time NOTES: 9. Either tRRH or tRCH must be satisfied for a read cycle. 10. The maximum value is specified only to assure access time. 5 35 ns 60 ns ns ns 16 ms 30 ns 7 TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS660 – MARCH 1996 MECHANICAL DATA BK (R-PSIM-N72) SINGLE-IN-LINE MEMORY MODULE 0.054 (1,37) 0.047 (1,19) 4.255 (108,08) 4.245 (107,82) 0.125 (3,18) TYP 1.005 (25,53) 0.995 (25,27) 0.128 (3,25) 0.120 (3,05) 0.050 (1,27) 0.010 (0,25) MAX 0.400 (10,16) TYP 0.040 (1,02) TYP 0.208 (5,28) MAX 0.360 (9,14) MAX (For Double-Sided SIMM) 4040197 / C 4/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. device symbolization (TM124FBK32F illustrated) TM124FBK32F -SS YY MM T -SS = = = = Year Code Month Code Assembly Site Code Speed Code NOTE: Location of symbolization may vary. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 YYMMT IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated