XILINX XC18V02VQ44C

0
XC18V00 Series In-System
Programmable Configuration
PROMs
R
DS026 (v4.0) June 11, 2003
0
0
Features
•
•
Dual configuration modes
-
In-system programmable 3.3V PROMs for
configuration of Xilinx FPGAs
- Endurance of 20,000 program/erase cycles
-
•
•
•
•
Product Specification
Program/erase over full commercial/industrial
voltage and temperature range (–40°C to +85°C)
IEEE Std 1149.1 boundary-scan (JTAG) support
Simple interface to the FPGA
Cascadable for storing longer or multiple bitstreams
Low-power advanced CMOS FLASH process
Description
Xilinx introduces the XC18V00 series of in-system programmable configuration PROMs (Figure 1). Devices in this 3.3V
family include a 4-megabit, a 2-megabit, a 1-megabit, and a
512-kilobit PROM that provide an easy-to-use, cost-effective method for re-programming and storing Xilinx FPGA
configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after CE and OE are enabled, data is available on the
PROM DATA (D0) pin that is connected to the FPGA DIN
pin. New data is available a short access time after each rising clock edge. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the
FPGA is in Slave Serial mode, the PROM and the FPGA
are clocked by an external clock.
•
•
•
•
•
- Parallel (up to 264 Mb/s at 33 MHz)
5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals
3.3V or 2.5V output capability
Available in PC20, SO20, PC44, and VQ44 packages
Design support using the Xilinx Alliance and
Foundation series software packages.
JTAG command initiation of standard FPGA
configuration
When the FPGA is in Master-SelectMAP mode, the FPGA
generates a configuration clock that drives the PROM.
When the FPGA is in Slave-Parallel or Slave-SelectMAP
Mode, an external oscillator generates the configuration
clock that drives the PROM and the FPGA. After CE and
OE are enabled, data is available on the PROMs DATA
(D0-D7) pins. New data is available a short access time
after each rising clock edge. The data is clocked into the
FPGA on the following rising edge of the CCLK. A free-running oscillator can be used in the Slave-Parallel or
Slave-SelecMAP modes.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family or with
the XC17V00 one-time programmable Serial PROM family.
CLK CE
TCK
TMS
TDI
Control
and
JTAG
Interface
Serial Slow/Fast configuration (up to 33 MHz)
OE/Reset
Data
Memory
Address
Data
TDO
CEO
Serial
or
Parallel
Interface
D0 DATA
Serial or Parallel Mode
7
D[1:7]
Parallel Interface
CF
DS026_01_090502
Figure 1: XC18V00 Series Block Diagram
©2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you
may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS026 (v4.0) June 11, 2003
Product Specification
www.xilinx.com
1-800-255-7778
1
R
XC18V00 Series In-System Programmable Configuration PROMs
Pinout and Pin Description
Table 1 provides a list of the pin names and descriptions for the 44-pin VQFP and PLCC and the 20-pin SOIC and PLCC
packages.
Table 1: Pin Names and Descriptions
Pin
Name
Boundary
Scan
Order
Function
Pin Description
D0
4
DATA OUT
3
OUTPUT
ENABLE
6
DATA OUT
5
OUTPUT
ENABLE
2
DATA OUT
1
OUTPUT
ENABLE
8
DATA OUT
7
OUTPUT
ENABLE
24
DATA OUT
23
OUTPUT
ENABLE
10
DATA OUT
9
OUTPUT
ENABLE
17
DATA OUT
16
OUTPUT
ENABLE
14
DATA OUT
13
OUTPUT
ENABLE
CLK
0
DATA IN
OE/
RESET
20
DATA IN
19
DATA OUT
18
OUTPUT
ENABLE
15
DATA IN
D1
D2
D3
D4
D5
D6
D7
CE
2
44-pin
VQFP
44-pin
PLCC
20-pin
SOIC &
PLCC
D0 is the DATA output pin to provide data
for configuring an FPGA in serial mode.
40
2
1
D0-D7 are the output pins to provide
parallel data for configuring a Xilinx
FPGA in Slave-Parallel/SelectMap mode.
D1-D7 remain in HIGHZ state when the
PROM operates in serial mode.
D1-D7 can be left unconnected when the
PROM is used in serial mode.
29
35
16
42
4
2
27
33
15
9
15
7(1)
25
31
14
14
20
9
19
25
12
Each rising edge on the CLK input
increments the internal address counter if
both CE is Low and OE/RESET is High.
43
5
3
When Low, this input holds the address
counter reset and the DATA output is in a
high-impedance state. This is a
bidirectional open-drain pin that is held
Low while the PROM is reset. Polarity is
NOT programmable.
13
19
8
When CE is High, the device is put into
low-power standby mode, the address
counter is reset, and the DATA pins are
put in a high-impedance state.
15
21
10
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DS026 (v4.0) June 11, 2003
Product Specification
R
XC18V00 Series In-System Programmable Configuration PROMs
Table 1: Pin Names and Descriptions (Continued)
Pin
Name
Boundary
Scan
Order
Function
CF
22
DATA OUT
21
OUTPUT
ENABLE
12
DATA OUT
11
OUTPUT
ENABLE
CEO
GND
44-pin
VQFP
44-pin
PLCC
20-pin
SOIC &
PLCC
Allows JTAG CONFIG instruction to
initiate FPGA configuration without
powering down FPGA. This is an
open-drain output that is pulsed Low by
the JTAG CONFIG command.
10
16
7(1)
Chip Enable Output (CEO) is connected
to the CE input of the next PROM in the
chain. This output is Low when CE is Low
and OE/RESET input is High, AND the
internal address counter has been
incremented beyond its Terminal Count
(TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
21
27
13
6, 18, 28 &
41
3, 12, 24
& 34
11
Pin Description
GND is the ground connection.
TMS
MODE
SELECT
The state of TMS on the rising edge of
TCK determines the state transitions at
the Test Access Port (TAP) controller.
TMS has an internal 50K ohm resistive
pull-up on it to provide a logic “1” to the
device if the pin is not driven.
5
11
5
TCK
CLOCK
This pin is the JTAG test clock. It
sequences the TAP controller and all the
JTAG test and programming electronics.
7
13
6
TDI
DATA IN
This pin is the serial input to all JTAG
instruction and data registers. TDI has an
internal 50K ohm resistive pull-up on it to
provide a logic “1” to the system if the pin
is not driven.
3
9
4
TDO
DATA OUT
This pin is the serial output for all JTAG
instruction and data registers. TDO has
an internal 50K ohm resistive pull-up on it
to provide a logic “1” to the system if the
pin is not driven.
31
37
17
Positive 3.3V supply voltage for internal
logic.
17, 35 &
38(3)
23, 41 &
44(3)
18 & 20(3)
Positive 3.3V or 2.5V supply voltage
connected to the input buffers(2) and
output voltage drivers.
8, 16, 26 &
36
14, 22, 32
& 42
19
No connects.
1, 2, 4,
11, 12, 20,
22, 23, 24,
30, 32, 33,
34, 37, 39,
44
1, 6, 7, 8,
10, 17, 18,
26, 28, 29,
30, 36, 38,
39, 40, 43
VCCINT
VCCO
NC
Notes:
1.
2.
3.
By default, pin 7 is the D4 pin in the 20-pin packages. However, CF --> D4 programming option can be set to override the default and route
the CF function to pin 7 in the Serial mode.
For devices with IDCODES 0502x093h, the input buffers are supplied by VCCINT.
For devices with IDCODES, 0503x093h, these VCCINT pins are no connects: pin 38 in 44-pin VQFP package, pin 44 in 44-pin PLCC
package and pin 20 in 20-pin SOIC and20-pin PLCC packages.
DS026 (v4.0) June 11, 2003
Product Specification
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1-800-255-7778
3
R
XC18V00 Series In-System Programmable Configuration PROMs
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
PC44
Top View
NC
NC
TDO
NC
D1
GND
D3
VCCO
D5
NC
NC
20
19
18
17
16
15
14
13
12
11
SO20
Top
View
*See pin descriptions.
VCCINT*
VCCO
VCCINT*
TDO
D1
D3
D5
CEO
D7
GND
DS026_14_060403
*See pin descriptions.
DS026_12_060403
TDI
TMS
TCK
D4/CF*
OE/RESET
4
5
6
7
8
18
PC20 17
Top View 16
15
14
9
10
11
12
13
NC
OE/RESET
D6
CE
VCCO
VCCINT*
GND
D7
NC
CEO
NC
3
2
1
20
19
18
19
20
21
22
23
24
25
26
27
28
NC
NC
TDI
NC
TMS
GND
TCK
VCCO
D4
CF
NC
1
2
3
4
5
6
7
8
9
10
DATA(D0)
D2
CLK
TDI
TMS
TCK
CF/D4*
OE/RESET
D6
CE
CLK
D2
D0
VCCINT*
VCCO
6
5
4
3
2
1
44
43
42
41
40
NC
CLK
D2
GND
D0
NC
VCCINT*
NC
VCCO
VCCINT*
NC
Pinout Diagrams
VCCINT*
TDO
D1
D3
D5
D6
CE
GND
D7
CEO
NC
CLK
D2
GND
D0
NC
VCCINT*
NC
VCCO
VCCINT*
NC
*See pin descriptions.
44
43
42
41
40
39
38
37
36
35
34
DS026_15_060403
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
VQ44
Top View
NC
NC
TDO
NC
D1
GND
D3
VCCO
D5
NC
NC
NC
OE/RESET
D6
CE
VCCO
VCCINT*
GND
D7
NC
CEO
NC
12
13
14
15
16
17
18
19
20
21
22
NC
NC
TDI
NC
TMS
GND
TCK
VCCO
D4
CF
NC
*See pin descriptions.
4
DS026_13_060403
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DS026 (v4.0) June 11, 2003
Product Specification
R
XC18V00 Series In-System Programmable Configuration PROMs
Xilinx FPGAs and Compatible PROMs
Table 2 provides a list of Xilinx FPGAs and compatible
PROMs.
Table 2: Xilinx FPGAs and Compatible PROMs
Table 2: Xilinx FPGAs and Compatible PROMs
Device
Configuration
Bits
XC18V00
Solution
XC18V00
Solution
XCV800
4,715,616
Device
Configuration
Bits
XC18V04 +
XC18V512
XC2VP2
1,305,440
XC18V02
XCV1000
6,127,744
XC18V04 +
XC18V02
XC2VP4
3,006,560
XC18V04
XCV50E
630,048
XC18V01
XC2VP7
4,485,472
XC18V04 +
XC18V512
XCV100E
863,840
XC18V01
XC2VP20
8,214,624
2 of XC18V04
XCV200E
1,442,016
XC18V02
XC2VP30
11,364,608
3 of XC18V04
XCV300E
1,875,648
XC18V02
XC2VP40
15,563,264
4 of XC18V04
XCV400E
2,693,440
XC18V04
XC2VP50
19,021,472
5 of XC18V04
XCV405E
3,430,400
XC18V04
XC2VP70
25,604,096
6 of XC18V04 +
XC18V512
XCV600E
3,961,632
XC18V04
XCV812E
6,519,648
2 of XC18V04
XC2VP100
33,645,312
8 of XC18V04 +
XC18V512
XCV1000E
6,587,520
2 of XC18V04
XCV1600E
8,308,992
2 of XC18V04
XC2VP125
42,782,208
10 of XC18V04 +
XC18V01
XCV2000E
10,159,648
3 of XC18V04
XC2V40
360,096
XC18V512
XCV2600E
12,922,336
4 of XC18V04
XC2V80
635,296
XC18V01
XCV3200E
16,283,712
4 of XC18V04
XC2V250
1,697,184
XC18V02
XC2S15
197,696
XC18V512
XC2V500
2,761,888
XC18V04
XC2S30
336,768
XC18V512
XC2V1000
4,082,592
XC18V04
XC2S50
559,200
XC18V01
XC2V1500
5,659,296
XC18V04
+ XC18V02
XC2S100
781,216
XC18V01
XC2S150
1,040,096
XC18V01
XC2V2000
7,492,000
2 of XC18V04
XC2S200
1,335,840
XC18V02
XC2V3000
10,494,368
3 of XC18V04
XC2S50E
630,048
XC18V01
XC2V4000
15,659,936
4 of XC18V04
XC2S100E
863,840
XC18V01
XC2V6000
21,849,504
5 of XC18V04 +
XC18V02
XC2S150E
1,134,496
XC18V02
XC2S200E
1,442,016
XC18V02
XC2V8000
29,063,072
7 of XC18V04
XC2S300E
1,875,648
XC18V02
XCV50
559,200
XC18V01
XC2S400E
2,693,440
XC18V04
XCV100
781,216
XC18V01
XC2S600E
3,961,632
XC18V04
XCV150
1,040,096
XC18V01
XC3S50
439,264
XC18V512
XCV200
1,335,840
XC18V02
XC3S200
1,047,616
XC18V01
XCV300
1,751,808
XC18V02
XC3S400
1,699,136
XC18V02
XCV400
2,546,048
XC18V04
XC3S1000
3,223,488
XC18V04
XCV600
3,607,968
XC18V04
DS026 (v4.0) June 11, 2003
Product Specification
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1-800-255-7778
5
R
XC18V00 Series In-System Programmable Configuration PROMs
Table 2: Xilinx FPGAs and Compatible PROMs
Device
Configuration
Bits
XC18V00
Solution
XC3S1500
5,214,784
XC18V04 +
XC18V01
XC3S2000
7,673,024
2 of XC18V04
XC3S4000
11,316,864
3 of XC18V04
XC3S5000
13,271,936
3 of XC18V04 +
XC18V01
protocol as shown in Figure 2. In-system programming
offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices.
The Xilinx development system provides the programming
data sequence using either Xilinx iMPACT software and a
download cable, a third-party JTAG development system, a
JTAG-compatible board tester, or a simple microprocessor
interface that emulates the JTAG instruction sequence. The
iMPACT software also outputs serial vector format (SVF)
files for use with any tools that accept SVF format and with
automatic test equipment.
All outputs are held in a high-impedance state or held at
clamp levels during in-system programming.
Capacity
Devices
Configuration Bits
XC18V04
4,194,304
XC18V02
2,097,152
XC18V01
1,048,576
XC18V512
524,288
OE/RESET
The ISP programming algorithm requires issuance of a
reset that causes OE to go Low.
External Programming
In-System Programming
In-System Programmable PROMs can be programmed
individually, or two or more can be daisy-chained together
and programmed in-system via the standard 4-pin JTAG
Xilinx reprogrammable PROMs can also be programmed by
the Xilinx HW-130, Xilinx MultiPRO, or a third-party device
programmer. This provides the added flexibility of using
pre-programmed devices with an in-system programmable
option for future enhancements and design changes.
T
V CCIN
GND
(a)
(b)
DS026_02_06/1103
Figure 2: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
Reliability and Endurance
Design Security
Xilinx in-system programmable products provide a guaranteed endurance level of 20,000 in-system program/erase
cycles and a minimum data retention of 20 years. Each
device meets all functional, performance, and data retention specifications within this endurance limit.
The Xilinx in-system programmable PROM devices incorporate advanced data security features to fully protect the
programming data against unauthorized reading via JTAG.
Table 3 shows the security setting available.
6
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DS026 (v4.0) June 11, 2003
Product Specification
R
XC18V00 Series In-System Programmable Configuration PROMs
The read security bit can be set by the user to prevent the
internal programming pattern from being read or copied via
JTAG. When set, it allows device erase. Erasing the entire
device is the only way to reset the read security bit.
Table 3: Data Security Options
Default = Reset
Set
Read Allowed
Program/Erase Allowed
Verify Allowed
Read Inhibited via JTAG
Program/Erase Allowed
Verify Inhibited
IEEE 1149.1 Boundary-Scan (JTAG)
The XC18V00 family is fully compliant with the IEEE Std.
1149.1 Boundary-Scan, also known as JTAG. A Test
Access Port (TAP) and registers are provided to support all
required boundary scan instructions, as well as many of the
optional instructions specified by IEEE Std. 1149.1. In addition, the JTAG interface is used to implement in-system programming (ISP) to facilitate configuration, erasure, and
verification operations on the XC18V00 device.
Table 4 lists the required and optional boundary-scan
instructions supported in the XC18V00. Refer to the IEEE
Std. 1149.1 specification for a complete description of
boundary-scan architecture and the required and optional
instructions.
Table 4: Boundary Scan Instructions
Boundary-Scan
Command
Binary
Code [7:0]
Description
Required Instructions
BYPASS
11111111
Enables BYPASS
SAMPLE/
PRELOAD
00000001
Enables boundary-scan
SAMPLE/PRELOAD operation
EXTEST
00000000
Enables boundary-scan
EXTEST operation
CLAMP
11111010
Enables boundary-scan
CLAMP operation
HIGHZ
11111100
all outputs in high-impedance
state simultaneously
IDCODE
11111110
Enables shifting out
32-bit IDCODE
11111101
11101110
IR[4]
IR[3]
IR[2]
IR[1:0]
000
ISP
Status
Security
0
01
->TDO
Notes:
1. IR(1:0) = 01 is specified by IEEE Std. 1149.1
Figure 3: Instruction Register Values Loaded into IR as
Part of an Instruction Scan Sequence
Boundary Scan Register
The boundary-scan register is used to control and observe
the state of the device pins during the EXTEST, SAMPLE/PRELOAD, and CLAMP instructions. Each output pin
on the XC18V00 has two register stages that contribute to
the boundary-scan register, while each input pin only has
one register stage.
For each output pin, the register stage nearest to TDI controls and observes the output state, and the second stage
closest to TDO controls and observes the High-Z enable
state of the pin.
For each input pin, the register stage controls and observes
the input state of the pin.
The IDCODE is a fixed, vendor-assigned value that is used
to electrically identify the manufacturer and type of the
device being addressed. The IDCODE register is 32 bits
wide. The IDCODE register can be shifted out for examination by using the IDCODE instruction. The IDCODE is available to any other system component via JTAG.
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
Enables shifting out
32-bit USERCODE
where
Initiates FPGA configuration
by pulsing CF pin Low once
v = the die version number
f = the family code (50h for XC18V00 family)
a = the ISP PROM product ID (36h for the XC18V04)
Instruction Register
The Instruction Register (IR) for the XC18V00 is eight bits
wide and is connected between TDI and TDO during an
DS026 (v4.0) June 11, 2003
Product Specification
TDI->
IR[7:5]
The IDCODE register has the following binary format:
XC18V00 Specific Instructions
CONFIG
The ISP Status field, IR(4), contains logic “1” if the device is
currently in ISP mode; otherwise, it contains logic “0”. The
Security field, IR(3), contains logic “1” if the device has been
programmed with the security option turned on; otherwise, it
contains logic “0”.
Identification Registers
Optional Instructions
USERCODE
instruction scan sequence. In preparation for an instruction
scan sequence, the instruction register is parallel loaded
with a fixed instruction capture pattern. This pattern is
shifted out onto TDO (LSB first), while an instruction is
shifted into the instruction register from TDI. The detailed
composition of the instruction capture pattern is illustrated
in Figure 3.
c = the company code (49h for Xilinx)
Note: The LSB of the IDCODE register is always read as
logic “1” as defined by IEEE Std. 1149.1.
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R
XC18V00 Series In-System Programmable Configuration PROMs
the XC18V00 device. If the device is blank or was not
loaded during programming, the USERCODE register contains FFFFFFFFh.
Table 5 lists the IDCODE register values for the XC18V00
devices.
Table 5: IDCODES Assigned to XC18V00 Devices
XC18V00 TAP Characteristics
ISP-PROM
IDCODE
XC18V01
05024093h or 05034093h
XC18V02
05025093h or 05035093h
XC18V04
05026093h or 05036093h
XC18V512
05023093h or 05033093h
The XC18V00 family performs both in-system programming
and IEEE 1149.1 boundary-scan (JTAG) testing via a single
4-wire Test Access Port (TAP). This simplifies system
designs and allows standard Automatic Test Equipment to
perform both functions. The AC characteristics of the
XC18V00 TAP are described as follows.
TAP Timing
The USERCODE instruction gives access to a 32-bit user
programmable scratch pad typically used to supply information about the device’s programmed contents. By using the
USERCODE instruction, a user-programmable identification code can be shifted out for examination. This code is
loaded into the USERCODE register during programming of
Figure 4 shows the timing relationships of the TAP signals.
These TAP timing characteristics are identical for both
boundary-scan and ISP operations.
TCKMIN1,2
TCK
TMSS
TMSH
TMS
TDIS
TDIH
TDI
TDOV
TDO
DS026_04_032702
Figure 4: Test Access Port Timing
TAP AC Parameters
Table 6 shows the timing parameters for the TAP waveforms shown in Figure 4.
Table 6: Test Access Port Timing Parameters
Symbol
8
Parameter
Min
Max
Units
TCKMIN1
TCK minimum clock period
100
-
ns
TCKMIN2
TCK minimum clock period, Bypass Mode
50
-
ns
TMSS
TMS setup time
10
-
ns
TMSH
TMS hold time
25
-
ns
TDIS
TDI setup time
10
-
ns
TDIH
TDI hold time
25
-
ns
TDOV
TDO valid delay
-
25
ns
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DS026 (v4.0) June 11, 2003
Product Specification
R
XC18V00 Series In-System Programmable Configuration PROMs
Connecting Configuration PROMs
Connecting the FPGA device with the configuration PROM
(see Figure 5 and Figure 6).
•
•
•
•
•
•
The DATA output(s) of the PROM(s) drives the DIN
input of the lead FPGA device.
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s) (in Master-Serial and
Master-SelectMAP modes only).
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
The OE/RESET pins of all PROMs are connected to
the INIT pins of all FPGA devices. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration, even when a
reconfiguration is initiated by a VCCINT glitch.
The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary supply
current of 10 mA maximum.
Slave-Parallel/SelectMap mode is similar to slave serial
mode. The DATA is clocked out of the PROM one byte
per CCLK instead of one bit per CCLK cycle. See FPGA
data sheets for special configuration requirements.
Initiating FPGA Configuration
The XC18V00 devices incorporate a pin named CF that is
controllable through the JTAG CONFIG instruction. Executing the CONFIG instruction through JTAG pulses the CF
low once for 300-500 ns, which resets the FPGA and initiates configuration.
The CF pin must be connected to the PROGRAM pin on the
FPGA(s) to use this feature.
The iMPACT software can also issue a JTAG CONFIG
command to initiate FPGA configuration through the “Load
FPGA” setting.
The 20-pin packages do not have a dedicated CF pin. For
20-pin packages, the CF --> D4 setting can be used to route
the CF pin function to pin 7 only if the parallel output mode
is not used.
Selecting Configuration Modes
The XC18V00 accommodates serial and parallel methods
of configuration. The configuration modes are selectable
DS026 (v4.0) June 11, 2003
Product Specification
through a user control register in the XC18V00 device. This
control register is accessible through JTAG, and is set using
the “Parallel mode” setting on the Xilinx iMPACT software.
Serial output is the default configuration mode.
Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established by a configuration program. The program is loaded
either automatically upon power up, or on command,
depending on the state of the three FPGA mode pins. In
Master Serial mode, the FPGA automatically loads the configuration program from an external memory. Xilinx PROMs
are designed to accommodate the Master Serial mode.
Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode-select
pins are Low (M0=0, M1=0, M2=0). Data is read from the
PROM sequentially on a single data line. Synchronization is
provided by the rising edge of the temporary signal CCLK,
which is generated by the FPGA during configuration.
Master Serial Mode provides a simple configuration interface. Only a serial data line, a clock line, and two control
lines are required to configure an FPGA. Data from the
PROM is read sequentially, accessed via the internal
address and bit counters which are incremented on every
valid rising edge of CCLK. If the user-programmable,
dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal
operation. The Xilinx FPGA families take care of this automatically with an on-chip pull-up resistor.
Cascading Configuration PROMs
For multiple FPGAs configured as a serial daisy-chain, or a
single FPGA requiring larger configuration memories in a
serial or SelectMAP configuration mode, cascaded PROMs
provide additional memory (Figure 5). Multiple XC18V00
devices can be concatenated by using the CEO output to
drive the CE input of the downstream device. The clock
inputs and the data outputs of all XC18V00 devices in the
chain are interconnected. After the last data from the first
PROM is read, the next clock signal to the PROM asserts its
CEO output Low and drives its DATA line to a high-impedance state. The second PROM recognizes the Low level on
its CE input and enables its DATA output. See Figure 7.
After configuration is complete, address counters of all cascaded PROMs are reset if the PROM OE/RESET pin goes
Low or CE goes High.
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XC18V00 Series In-System Programmable Configuration PROMs
VCCO
(See Note 2)
VCCO VCCINT
VCCO VCCINT
(See Note 2)
(See Note 2)
4.7K
MODE PINS
MODE PINS
(See Note 1)
DIN
VCCINT
VCCINT
D0
VCCO
J1
1
TDI
TMS
TCK
4
TDO
VCCO
4.7K
Master
Serial
(See
Note
1)
First
PROM
Xilinx
FPGA
Slave
Serial
CLK
CCLK
CCLK
TMS
CE
TMS
CE
DONE
DONE
TCK
CEO
TCK
CEO
TDI
2
3
Xilinx
FPGA
XC18V00
Cascaded
PROM
DIN
DOUT
D0
VCCO
XC18V00
(See Note 1)
CLK
TDI
OE/RESET
OE/RESET
CF
CF
TDO
GND
TDO
GND
INIT
INIT
PROGRAM
PROGRAM
TDI
TDI
TMS
TMS
TCK
TCK
TDO
TDO
Notes:
1For Mode pin connections and DONE pin pullup value, refer to appropriate FPGA data sheet.
2For compatible voltages, refer to the appropriate FPGA data sheet.
DS026_08_061003
Figure 5: Configuring Multiple Devices in Master/Slave Serial Mode
(2)
VCCO
(2)
(2)
VCCO VCCINT
VCCO VCCINT
4.7K
(1)
MODE PINS
MODE PINS
D[0:7] (3)
VCCINT
(3)
D[0:7]
VCCO
J1
TDI
TMS
TCK
TDO
1
2
3
4
D[0:7]
VCCINT
(3)
VCCO
XC18V00
XC18V00
Cascaded
PROM
First
PROM
(2)
VCCO
(1)
**D[0:7]
Xilinx
Virtex-II
FPGA
Xilinx
Virtex-II
FPGA
4.7K
Master
Serial/
SelectMAP
Slave
Serial/
SelectMAP
CLK
CCLK
CCLK
TMS
CE
TMS
CE
DONE
DONE
TCK
CEO
TCK
CEO
TDI
GND
CLK
TDI
OE/RESET
OE/RESET
CF
CF
TDO
GND
TDO
INIT
INIT
PROGRAM
PROGRAM
TDI
TDI
TMS
TCK
Notes:
1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
2 For compatible voltges, refer to the appropriate FPGA data sheet.
3 Master/Slave Serial Mode does not require D[1:7] to be connected.
TMS
TDO
TCK
TDO
DS026_09_051003
Figure 6: Configuring Multiple Virtex-II Devices with Identical Patterns in Master/Slave or Serial/SelectMAP Modes
10
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DS026 (v4.0) June 11, 2003
Product Specification
R
XC18V00 Series In-System Programmable Configuration PROMs
OPTIONAL
Daisy-chained
FPGAs with
different
configurations
DOUT
FPGA
Vcco(2)
OPTIONAL
Slave FPGAs
with identical
configurations
VCCINT VCCO(2)
4.7K
Modes (1)
Vcco(2)
(2)
VCCINT VCCO
Vcco(2)
4.7K
VCCINT VCCO
VCCINT VCCO
DATA
First
CLK PROM
CEO
CE
DIN
CCLK
DONE
INIT
PROGRAM
DATA
CLK
Cascaded
PROM
CE
OE/RESET
OE/RESET
CF
CF
Notes:
1 For Mode pin connections and Done pullup value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate FPGA data sheet.
(a) Master Serial Mode
I/O(1)
I/O (1)
Modes(2)
WRITE
1K
VIRTEX
Select MAP
NC
External
Osc (3)
CS
VCCINT VCCO
(4)
VCCINT VCCO
(4)
1K
(4)
Vcco
Vcco(4)
BUSY
VCCINT VCCO
4.7K
(2)
(4)
Vcco
XC18Vxx
4.7K
CLK
CCLK
8
PROGRAM D[0:7]
CEO
D[0:7]
CE
DONE
OE/RESET
INIT
VCCINT VCCO
XC18Vxx
CLK
D[0:7]
CE
CF
OE/RESET
CEO
CF
Notes:
1 CS and WRITE must be either driven Low or pulled down externally. One option is shown.
2 For Mode pin connections and Done pullup value, refer to the appropriate FPGA data sheet.
3 External oscillator required for Virtex/Virtex-E SelectMAP or Virtex-II/Virtex-II Pro Slave-SelectMAP modes.
4 For compatible voltages, refer to the appropriate FPGA data sheet.
(b) Virtex/Virtex-E/Virtex-II/Virtex-II Pro SelectMAP Mode
I/O(1)
I/O (1)
Modes(2)
WRITE
Spartan-II,
Spartan-IIE
NC
External
Osc (3)
CS
BUSY
1K
1K
Vcco(4)
Vcco (4)
PROGRAM D[0:7]
VCCINT VCCO
3.3K
(2)
CCLK
(4)
VCCINT VCCO
(4)
VCCINT
XC18Vxx
4.7K
CLK
8
DONE
INIT
D[0:7]
CE
OE/RESET
CF
Notes:
1 CS and WRITE must be pulled down to be used as I/O. One option is shown.
2 For Mode pin connections and Done pullup value and if Drive Done configuration option is not active, refer to
the appropriate FPGA data sheet.
3 External oscillator required for Spartan-II/Spartan-IIE Slave-Parallel modes.
4 For compatible voltages, refer to the appropriate FPGA data sheet.
(c) Spartan-II/Spartan-IIE Slave-Parallel Mode
DS026_05_060403
Figure 7: (a) Master Serial Mode (b) Virtex/Virtex-E/Virtex-II Pro SelectMAP Mode (c) Spartan-II/Spartan-IIE
Slave-Parallel Mode (dotted lines indicate optional connection)
DS026 (v4.0) June 11, 2003
Product Specification
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11
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XC18V00 Series In-System Programmable Configuration PROMs
Reset Activation
On power up, OE/RESET is held low until the XC18V00 is
active (1 ms). OE/RESET is connected to an external resistor to pull OE/RESET HIGH releasing the FPGA INIT and
allowing configuration to begin. If the power drops below
2.0V, the PROM resets. OE/RESET polarity is not programmable. See Figure 8 for power-up requirements.
3.6V
Recommended Operating Range
3.0V
Volts
Recommended
VCCINT Rise
Time
remains in a high-impedance state regardless of the state of
the OE input. JTAG pins TMS, TDI and TDO can be in a
high-impedance state or High. See Table 7.
5V Tolerant I/Os
The I/Os on each re-programmable PROM are fully 5V tolerant even through the core power supply is 3.3V. This
allows 5V CMOS signals to connect directly to the PROM
inputs without damage. In addition, the 3.3V VCCINT power
supply can be applied before or after 5V signals are applied
to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,
the core power supply (VCCINT), and the output power supply (VCCO) can have power applied in any order. This
makes the PROM devices immune to power supply
sequencing issues.
Customer Control Bits
0V
0ms 1ms
50ms
Time (ms)
ds026_10_061103
Figure 8: VCCINT Power-Up Requirements
Standby Mode
The PROM enters a low-power standby mode whenever
CE is asserted High. The address is reset. The output
The XC18V00 PROMs have various control bits accessible
by the customer. These can be set after the array has been
programmed using “Skip User Array” in Xilinx iMPACT software. The iMPACT software can set these bits to enable the
optional JTAG read security, parallel configuration mode, or
CF-->D4 pin function. See Table 7.
Table 7: Truth Table for PROM Control Inputs
Control Inputs
Outputs
OE/RESET
CE
Internal Address
DATA
CEO
ICC
High
Low
If address < TC(1): increment
If address > TC (1): don’t change
Active
High-Z
High
Low
Active
Reduced
Low
Low
Held reset
High-Z
High
Active
High
High
Held reset
High-Z
High
Standby
Low
High
Held reset
High-Z
High
Standby
Notes:
1. TC = Terminal Count = highest address value. TC + 1 = address 0.
12
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DS026 (v4.0) June 11, 2003
Product Specification
R
XC18V00 Series In-System Programmable Configuration PROMs
Absolute Maximum Ratings(1,2)
Symbol
Description
Value
Units
Supply voltage relative to GND
–0.5 to +4.0
V
VIN
Input voltage with respect to GND
–0.5 to +5.5
V
VTS
Voltage applied to High-Z output
–0.5 to +5.5
V
TSTG
Storage temperature (ambient)
–65 to +150
°C
TSOL
Maximum soldering temperature (10s @ 1/16 in.)
+220
°C
Junction temperature
+125
°C
VCCINT/VCCO
TJ
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins can undershoot to –2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the
forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Recommended Operating Conditions
Symbol
VCCINT
VCCO
Parameter
Min
Max
Units
Internal voltage supply
3.0
3.6
V
Supply voltage for output drivers for 3.3V operation
3.0
3.6
V
Supply voltage for output drivers for 2.5V operation
2.3
2.7
V
VIL
Low-level input voltage
0
0.8
V
VIH
High-level input voltage
2.0
5.5
V
VO
Output voltage
0
VCCO
V
1
50
ms
–40°
85°
C
TVCC
TA
VCCINT rise time from 0V to nominal
voltage(1)
Operating ambient temperature
Notes:
1. At power up, the device requires the VCCINT power supply to monotonically rise from 0V to nominal voltage within the specified
VCCINT rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See
Figure 8.
Quality and Reliability Characteristics
Symbol
Description
Min
Max
Units
20
-
Years
TDR
Data retention
NPE
Program/erase cycles (Endurance)
20,000
-
Cycles
VESD
Electrostatic discharge (ESD)
2,000
-
Volts
DS026 (v4.0) June 11, 2003
Product Specification
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XC18V00 Series In-System Programmable Configuration PROMs
DC Characteristics Over Operating Conditions
Symbol
Parameter
Test Conditions
Min
Max
Units
2.4
-
V
90% VCCO
-
V
High-level output voltage for 3.3V outputs
IOH = –4 mA
High-level output voltage for 2.5V outputs
IOH = –500 µA
Low-level output voltage for 3.3V outputs
IOL = 8 mA
-
0.4
V
Low-level output voltage for 2.5V outputs
IOL = 500 µA
-
0.4
V
ICC
Supply current, active mode
25 MHz
-
25
mA
ICCS
Supply current, standby mode
-
10
mA
VOH
VOL
IILJ
JTAG pins TMS, TDI, and TDO pull-up
current
VCCINT = MAX
VIN = GND
-
100
µA
IIL
Input leakage current
VCCINT = Max
VIN = GND or
VCCINT
–10
10
µA
IIH
Input and output High-Z leakage current
VCCINT = Max
VIN = GND or
VCCINT
–10
10
µA
CIN
Input capacitance
VIN = GND
f = 1.0 MHz
-
8
pF
Output capacitance
VOUT = GND
f = 1.0 MHz
-
14
pF
COUT
Notes:
1. Internal pull-up resistors guarantee valid logic levels at unconnected input pins. These pull-up resistors do not guarantee valid logic
levels when input pins are connected to other circuits.
14
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DS026 (v4.0) June 11, 2003
Product Specification
R
XC18V00 Series In-System Programmable Configuration PROMs
AC Characteristics Over Operating Conditions for XC18V04 and XC18V02
CE
TSCE
THCE
OE/RESET
THC
TLC
THOE
TCYC
CLK
TOE
TCE
TCAC
TDF
TOH
DATA
TOH
DS026_06_012000
Symbol
Description
Min
Max
Units
TOE
OE/RESET to data delay
-
10
ns
TCE
CE to data delay
-
20
ns
TCAC
CLK to data delay
-
20
ns
TOH
Data hold from CE, OE/RESET, or CLK
0
-
ns
TDF
CE or OE/RESET to data float delay(2)
-
25
ns
Clock periods
50
-
ns
TLC
CLK Low time(3)
10
-
ns
THC
CLK High
time(3)
10
-
ns
TSCE
CE setup time to CLK (guarantees proper counting)(3)
25
-
ns
THCE
CE High time (guarantees counters are reset)
250
-
ns
THOE
OE/RESET hold time (guarantees counters are reset)
250
-
ns
TCYC
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
5. If THCE High < 2 µs, TCE = 2 µs.
6. If THCE Low < 2 µs, TOE = 2 µs.
DS026 (v4.0) June 11, 2003
Product Specification
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XC18V00 Series In-System Programmable Configuration PROMs
AC Characteristics Over Operating Conditions for XC18V01 and XC18V512
CE
TSCE
THCE
OE/RESET
THC
TLC
THOE
TCYC
CLK
TOE
TCE
TCAC
TDF
TOH
DATA
TOH
DS026_06_012000
Symbol
Description
Min
Max
Units
TOE
OE/RESET to data delay
-
10
ns
TCE
CE to data delay
-
15
ns
TCAC
CLK to data delay
-
15
ns
TOH
Data hold from CE, OE/RESET, or CLK
0
-
ns
TDF
CE or OE/RESET to data float delay(2)
-
25
ns
Clock periods
30
-
ns
TLC
CLK Low time(3)
10
-
ns
THC
CLK High time(3)
10
-
ns
TSCE
CE setup time to CLK (guarantees proper counting)(3)
20
-
ns
THCE
CE High time (guarantees counters are reset)
250
-
ns
THOE
OE/RESET hold time (guarantees counters are reset)
250
-
ns
TCYC
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
5. If THCE High < 2 µs, TCE = 2 µs.
6. If THOE High < 2 µs, TOE = 2 µs.
16
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Product Specification
R
XC18V00 Series In-System Programmable Configuration PROMs
AC Characteristics Over Operating Conditions When Cascading for XC18V04 and
XC18V02
OE/RESET
CE
CLK
TCDF
TOCE
Last Bit
DATA
First Bit
TOCK
TOOE
CEO
DS026_07_020300
Symbol
TCDF
Description
CLK to data float delay(2,3)
delay(3)
TOCK
CLK to CEO
TOCE
CE to CEO delay(3)
TOOE
OE/RESET to CEO
delay(3)
Min
Max
Units
-
25
ns
-
20
ns
-
20
ns
-
20
ns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
DS026 (v4.0) June 11, 2003
Product Specification
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XC18V00 Series In-System Programmable Configuration PROMs
AC Characteristics Over Operating Conditions When Cascading for XC18V01 and
XC18V512
OE/RESET
CE
CLK
TCDF
TOCE
Last Bit
DATA
First Bit
TOCK
TOOE
CEO
DS026_07_020300
Symbol
Description
Min
Max
Units
TCDF
CLK to data float delay(2,3)
-
25
ns
TOCK
CLK to CEO delay(3)
-
20
ns
TOCE
CE to CEO delay(3)
-
20
ns
TOOE
OE/RESET to CEO delay(3)
-
20
ns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
18
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DS026 (v4.0) June 11, 2003
Product Specification
R
XC18V00 Series In-System Programmable Configuration PROMs
Ordering Information
XC18V04 VQ44 C
Device Number
Operating Range/Processing
XC18V04
XC18V02
XC18V01
XC18V512
C = (TA = –40°C to +85°C)
Package Type
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier(1)
SO20 = 20-pin Small-Outline Package(2)
PC20 = 20-pin Plastic Leaded Chip Carrier(2)
Notes:
1. XC18V04 and XC18V02 only.
2. XC18V01 and XC18V512 only.
Valid Ordering Combinations
XC18V04VQ44C
XC18V02VQ44C
XC18V01VQ44C
XC18V512VQ44C
XC18V04PC44C
XC18V02PC44C
XC18V01PC20C
XC18V512PC20C
XC18V01SO20C
XC18V512SO20C
Marking Information
44-pin Package
XC18V04 VQ44
Device Number
Operating Range/Processing
XC18V04
XC18V02
XC18V01
XC18V512
C = (TA = –40°C to +85°C)
Package Type
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Leaded Chip Carrier(1)
Notes:
1. XC18V02 and XC18V04 only.
20-pin Package(1)
Due to the small size of the serial PROM packages, the complete ordering part number cannot be marked on the
package. The XC prefix is deleted and the package code is simplified. Device marking is as follows:
18V01 S C
Device Number
Operating Range/Processing
18V01
18V512
C = (TA = –40°C to +85°C)
Package Type
S = 20-pin Small-Outline Package
J = 20-pin Plastic Leaded Chip Carrier
Notes:
1. XC18V01 and XC18V512 only.
DS026 (v4.0) June 11, 2003
Product Specification
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XC18V00 Series In-System Programmable Configuration PROMs
Revision History
The following table shows the revision history for this document.
20
Date
Version
Revision
2/9/99
1.0
First publication of this early access specification
8/23/99
1.1
Edited text, changed marking, added CF and parallel load
9/1/99
1.2
Corrected JTAG order, Security and Endurance data.
9/16/99
1.3
Corrected SelectMAP diagram, control inputs, reset polarity. Added JTAG and CF
description, 256 Kbit and 128 Kbit devices.
01/20/00
2.0
Added Q44 Package, changed XC18xx to XC18Vxx
02/18/00
2.1
Updated JTAG configuration, AC and DC characteristics
04/04/00
2.2
Removed stand alone resistor on INIT pin in Figure 5. Added Virtex-E and EM parts to
FPGA table.
06/29/00
2.3
Removed XC18V128 and updated format. Added AC characteristics for XC18V01,
XC18V512, and XC18V256 densities.
11/13/00
2.4
Features: changed 264 MHz to 264 Mb/s at 33 MHz; AC Spec.: TSCE units to ns, THCE
CE High time units to µs. Removed Standby Mode statement: “The lower power standby
modes available on some XC18V00 devices are set by the user in the programming
software”. Changed 10,000 cycles endurance to 20,000 cycles.
01/15/01
2.5
Updated Figures 5 and 6, added 4.7 resistors. Identification registers: changes ISP
PROM product ID from 06h to 26h.
04/04/01
2.6
Updated Figure 6, Virtex SelectMAP mode; added XC2V products to Compatible PROM
table; changed Endurance from 10,000 cycles, 10 years to 20,000, 20 years;
04/30/01
2.7
Updated Figure 6: removed Virtex-E in Note 2, fixed SelectMAP mode connections.
Under AC Characteristics Over Operating Conditions for XC18V04 and XC18V02,
changed TSCE from 25 ms to 25 ns.
06/11/01
2.8
AC Characteristics Over Operating Conditions for XC18V01 and XC18V512.
Changed Min values for TSCE from 20 ms to 20 ns and for THCE from 2 ms to 2 µs.
09/28/01
2.9
Changed the boundary scan order for the CEO pin in Table 1, updated the configuration
bits values in the table under Xilinx FPGAs and Compatible PROMs, and added
information to the Recommended Operating Conditions table.
11/12/01
3.0
Updated for Spartan-IIE FPGA family.
12/06/01
3.1
Changed Figure 7(c).
02/27/02
3.2
Updated Table 2 and Figure 6 for the Virtex-II Pro family of devices.
03/15/02
3.3
Updated Xilinx software and modified Figure 6 and Figure 7.
03/27/02
3.4
Made changes to pages 1-3, 5, 7-11, 13, 14, and 18. Added new Figure 8 and Figure 9.
06/14/02
3.5
Made additions and changes to Table 2.
07/24/02
3.6
Changed last bullet under Connecting Configuration PROMs, page 9.
09/06/02
3.7
Multiple minor changes throughout, plus the addition of Pinout Diagrams, page 4 and
the deletion of Figure 9.
10/31/02
3.8
Made minor change on Figure 7 (b) and changed orientation of SO20 diagram on page 5.
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1-800-255-7778
DS026 (v4.0) June 11, 2003
Product Specification
R
XC18V00 Series In-System Programmable Configuration PROMs
11/18/02
3.9
Added XC2S400E and XC2S600E to Table 2.
04/17/03
3.10
Changes to Description, External Programming, and Table 2.
06/11/03
4.0
Added alternate IDCODES to Table 5, discontinued XC18V256 density, eliminated
industrial ordering combinations, extended commercial temperature range, and added
MultiPRO Desktop Tool support. Changed THOE and THCE to 250 ns in the tables on
page 15 and page 16. Made change in capacitance values DC Characteristics Over
Operating Conditions. Added Note 3 to Table 1. Other minor edits.
DS026 (v4.0) June 11, 2003
Product Specification
www.xilinx.com
1-800-255-7778
21