0 XC9572XV High-performance CPLD R 0 5 Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC9572XV devices with equivalent XC9572XL devices in all designs as soon as possible. Recommended replacements are pin compatible, however require a VCC change to 3.3V, and a recompile of the design file. In addition, there is no 1.8V I/O support. See XCN07010 for details regarding this discontinuation, including device replacement recomendations for the XC9572XV CPLD. Features • • • • • • • • 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin VQFP (34 user I/O pins) - 100-pin TQFP (72-user I/O pins) Optimized for high-performance 2.5V systems - Low power operation - Multi-voltage operation Advanced system features - In-system programmable - Superior pin-locking and routability with Fast CONNECT™ II switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold ciruitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - 20 year data retention - ESD protection exceeding 2,000V Product Specification in a XC9500XV device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. For a general estimate of ICC, the following equation may be used: PTOTAL = PINT + PIO = ICCINT x VCCINT + PIO Separating internal and I/O power here is convenient because XC9500XV CPLDs also separate the corresponding power pins. PIO is a strong function of the load capacitance driven, so it is handled by I = CVf. ICCINT is another situation that reflects the actual design considered and the internal switching speeds. An estimation expression for ICCINT (taken from simulation) is: ICCINT(mA) = MCHS(0.122 X PTHS + 0.238) + MCLP(0.042 x PTLP + 0.171) + 0.04(MCHS + MCLP) x fMAX x MCTOG where: MCHS = # macrocells used in high speed mode MCLP = #macrocells used in low power mode PTHS = average p-terms used per high speed macrocell PTLP = average p-terms used over low power macrocell fMAX = max clocking frequency in the device MCTOG = % macrocells toggling on each clock (12% is frequently a good estimate This calculation was derived from laboratory measurements of an XC9500XV part filled with 16-bit counters and allowing a single output (the LSB) to be enabled. The actual ICC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in a graphical form. For a more detailed discussion of power consumption in this device, see Xilinx application note XAPP361, “Planning for High Speed XC9500XV Designs.” 110 90 Description The XC9572XV is a 2.5V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 5 ns. Typical I CC (mA) DS052 (v3.0) June 25, 2007 70 H P ig h erfo 50 Low 30 rma Pow nce er 10 Power Estimation Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell 0 50 100 150 Clock F requency (MHz) 200 DS052_01_041405 © 2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS052 (v3.0) June 25, 2007 Product Specification www.xilinx.com 1 R XC9572XV High-performance CPLD Figure 1: Typical ICC vs. Frequency for XC9572XV 3 JTAG Port 1 JTAG Controller In-System Programming Controller 54 18 I/O Function Block 1 Macrocells 1 to 18 I/O Fas t CONNECT II Switch Matrix I/O I/O I/O Blocks I/O I/O I/O 54 18 Function Block 2 Macrocells 1 to 18 54 18 Function Block 3 Macrocells 1 to 18 I/O 3 I/O/GCK 54 1 18 I/O/GSR I/O/GTS 2 Function Block 4 Macrocells 1 to 18 DS052_02_041200 Figure 2: XC9572XV Architecture (Function Block outputs (indicated by the bold line) drive the I/O Blocks directly) Supported I/O Standards The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS2 standard is used in 2.5V applications. Table 1: IOSTANDARD Options IOSTANDARD VCCIO LVTTL 3.3V LVCMOS2 2.5V X25TO18 1.8V XC9500XV CPLDs are also 1.8V I/O compatible. The X25TO18 setting is provided for generating 1.8V compatible outputs from a CPLD normally operating in a 2.5V environment. The default I/O Standard for pads without IOSTANDARD attributes is LVTTL for XC9500XV devices. The XC9572XV CPLD features both LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages. 2 www.xilinx.com DS052 (v3.0) June 25, 2007 Product Specification R XC9572XV High-performance CPLD Absolute Maximum Ratings Symbol Value Units Supply voltage relative to GND –0.5 to 2.7 V VCCIO Supply voltage for output drivers –0.5 to 3.6 V VIN Input voltage relative to GND(1) –0.5 to 3.6 V VTS Voltage applied to 3-state output(1) –0.5 to 3.6 V TSTG Storage temperature (ambient) –65 to +150 oC +150 oC VCC TJ Description Junction temperature Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 3. For solder specifications, see Xilinx Packaging . Recommended Operation Conditions Symbol VCCINT VCCIO Parameter Min Max Units +70oC 2.37 2.62 V Industrial TA = –40oC to +85oC 2.37 2.62 Supply voltage for output drivers for 3.3V operation 3.0 3.6 V Supply voltage for output drivers for 2.5V operation 2.37 2.62 V Supply voltage for output drivers for 1.8V operation 1.71 1.89 V Supply voltage for internal logic and input buffers Commercial TA = 0oC to VIL Low-level input voltage 0 0.8 V VIH High-level input voltage 1.7 3.6 V VO Output voltage 0 VCCIO V Quality and Reliability Characteristics Symbol Parameter Min Max Units 20 - Years TDR Data retention NPE Program/Erase cycles (endurance) 1,000 - Cycles VESD Electrostatic Discharge (ESD) 2,000 - Volts DS052 (v3.0) June 25, 2007 Product Specification www.xilinx.com 3 R XC9572XV High-performance CPLD DC Characteristics (Over Recommended Operating Conditions) Symbol VOH Parameter Test Conditions Min Max Units Output high voltage for 3.3V outputs IOH = –4.0 mA 2.4 - V Output high voltage for 2.5V outputs IOH = –1.0 mA 2.0 - V Output high voltage for 1.8V outputs IOH = –100 μA 90% VCCIO - V Output low voltage for 3.3V outputs IOL = 8.0 mA - 0.4 V Output low voltage for 2.5V outputs IOL = 1.0 mA - 0.4 V Output low voltage for 1.8V outputs IOL = 100 μA - 0.4 V IIL Input leakage current VCC = 2.62V VCCIO = 3.6V VIN = GND or 3.6V - ±10 μA IIH Input high-Z leakage current VCC = 2.62V VCCIO = 3.6V VIN = GND or 3.6V - ±10 μA VCC min < VIN < 3.6V - ±150 μA - 10 pF VOL CIN I/O capacitance VIN = GND f = 1.0 MHz ICC Operating Supply Current (low power mode, active) VI = GND, No load f = 1.0 MHz 14 mA AC Characteristics XC9572XV-5 Symbol Min Max Min Max Units - 5.0 - 7.5 ns 3.5 - 4.8 - ns TPD I/O to output valid TSU I/O setup time before GCK TH I/O hold time after GCK 0 - 0 - ns GCK to output valid - 3.5 - 4.5 ns fSYSTEM Multiple FB internal operating frequency - 222.2 - 125.0 MHz TPSU I/O setup time before p-term clock input 1.0 - 1.6 - ns TPH I/O hold time after p-term clock input 2.5 - 3.2 - ns P-term clock output valid - 6.0 - 7.7 ns TOE GTS to output valid - 4.0 - 5.0 ns TOD GTS to output disable - 4.0 - 5.0 ns TPOE Product term OE to output enabled - 7.0 - 9.5 ns TPOD Product term OE to output disabled - 7.0 - 9.5 ns TAO GSR to output valid - 10.0 - 12.0 ns TPAO P-term S/R to output valid - 10.7 - 12.6 ns TWLH GCK pulse width (High or Low) 2.2 - 4.0 - ns TPLH P-term clock pulse width (High or Low) 5.0 - 6.5 - ns Asynchronous preset/reset pulse width (High or Low) 5.0 - 6.5 - ns TCO TPCO TAPRPW 4 Parameter XC9572XV-7 www.xilinx.com DS052 (v3.0) June 25, 2007 Product Specification R XC9572XV High-performance CPLD Internal Timing Parameters VTEST R1 Output Type Device Output R2 CL VCCIO VTEST R1 R2 CL 3.3V 3.3V 320Ω 360Ω 35 pF 2.5V 2.5V 250Ω 660Ω 35 pF 1.8V 1.8V 10KΩ 14KΩ 35 pF DS051_03_0601000 Figure 3: AC Load Circuit XC9572XV-5 Symbol Parameter XC9572XV-7 Min Max Min Max Units Buffer Delays TIN Input buffer delay - 2.0 - 2.3 ns TGCK GCK buffer delay - 1.2 - 1.5 ns TGSR GSR buffer delay - 2.0 - 3.1 ns TGTS GTS buffer delay - 4.0 - 5.0 ns TOUT Output buffer delay - 2.1 - 2.5 ns TEN Output buffer enable/disable delay - 0 - 0 ns Product Term Control Delays TPTCK Product term clock delay - 1.7 - 2.4 ns TPTSR Product term set/reset delay - 0.7 - 1.4 ns TPTTS Product term 3-state delay - 5.0 - 7.2 ns - 0.2 - 1.3 ns Internal Register and Combinatorial Delays TPDI Combinatorial logic propagation delay TSUI Register setup time 2.0 - 2.6 - ns THI Register hold time 1.5 - 2.2 - ns TECSU Register clock enable setup time 2.0 - 2.6 - ns TECHO Register clock enable hold time 1.5 - 2.2 - ns TCOI Register clock to output valid time - 0.2 - 0.5 ns TAOI Register async. S/R to output delay - 5.9 - 6.4 ns TRAI Register async. S/R recover before clock TLOGI Internal logic delay - 0.7 - 1.4 ns TLOGILP Internal low power logic delay - 5.7 - 6.4 ns - 1.6 - 3.5 ns 5.0 7.5 ns Feedback Delays TF Fast CONNECT II feedback delay Time Adders TPTA Incremental product term allocator delay - 0.7 - 0.8 ns TPTA2 Adjacent macrocell p-term allocator delay - 0.3 - 0.3 ns TSLEW Slew-rate limited delay - 3.0 - 4.0 ns DS052 (v3.0) June 25, 2007 Product Specification www.xilinx.com 5 R XC9572XV High-performance CPLD XC9572XV I/O Pins Function Block Macrocell VQ44 TQ100 BScan Order Function Block Macrocell VQ44 TQ100 BScan Order 1 1 - 16 213 3 1 - 41 105 1 2 39 13 210 3 2 5 32 102 1 3 - 18 207 3 3 - 49 99 1 4 - 20 204 3 4 - 50 96 1 5 40 14 201 3 5 6 35 93 1 6 41 15 198 3 6 - 53 90 1 7 - 25 195 3 7 - 54 87 1 8 42 17 192 3 8 7 37 84 1 9 43(1) 22(1) 189 3 9 8 42 81 1 10 - 28 186 3 10 - 60 78 1 11 44(1) 23(1) 183 3 11 12 52 75 1 12 - 33 180 3 12 - 61 72 1 13 - 36 177 3 13 - 63 69 1 14 1(1) 27(1) 174 3 14 13 55 66 1 15 2 29 171 3 15 14 56 63 1 16 - 39 168 3 16 18 64 60 1 17 3 30 165 3 17 16 58 57 1 18 - 40 162 3 18 - 59 54 2 1 - 87 159 4 1 - 65 51 2 2 29 94 156 4 2 19 67 48 2 3 - 91 153 4 3 - 71 45 2 4 - 93 150 4 4 - 72 42 2 5 30 95 147 4 5 20 68 39 2 6 31 96 144 4 6 - 76 36 2 7 - 3(2) 141 4 7 - 77 33 2 8 32 97 138 4 8 21 70 30 2 9 33(1) 99(1) 135 4 9 - 66 27 2 10 - 1 132 4 10 - 81 24 2 11 34(1) 4(1) 129 4 11 22 74 21 2 12 - 6 126 4 12 - 82 18 2 13 - 8 123 4 13 - 85 15 2 14 36(3) 9(3) 120 4 14 23 78 12 2 15 37 11 117 4 15 27 89 9 2 16 - 10 114 4 16 - 86 6 2 17 38 12 111 4 17 28 90 3 2 18 - 92 108 4 18 - 79 0 Notes: 1. Global control pin. 2. GTS1 for TQ100 3. GTS1 for VQ44 6 www.xilinx.com DS052 (v3.0) June 25, 2007 Product Specification R XC9572XV High-performance CPLD XC9572XV Global, JTAG and Power Pins Pin Type VQ44 TQ100 I/O/GCK1 43 22 I/O/GCK2 44 23 I/O/GCK3 1 27 I/O/GTS1 36 3 I/O/GTS2 34 4 I/O/GSR 33 99 TCK 11 48 TDI 9 45 TDO 24 83 TMS 10 47 VCCINT 2.5V 15, 35 5, 57, 98 VCCIO 1.8/2.5V/3.3V 26 26, 38, 51, 88 GND 4, 17, 25 21, 31, 44, 62, 69, 75, 84, 100 No Connects - 2, 7, 19, 24, 34, 43, 46, 73, 80 DS052 (v3.0) June 25, 2007 Product Specification www.xilinx.com 7 R XC9572XV High-performance CPLD Device Part Marking and Ordering Combination Information R XC95xxxXV TQ144 Device Type Package 7C Speed Operating Range This line not related to device part number 1 Sample package with part marking. Notes: 1. Due to the small size of chip scale packages, part marking on these packages does not follow the above sample and the complete part number cannot be included in the marking. Part marking on chip scale packages by line: · · · · Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 95xxxXV. Line 2 = Not related to device part number. Line 3 = Not related to device part number. Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package code: C1 = CS48. Speed (pin-to-pin delay) Pkg. Symbol No. of Pins Package Type Operating Range(1) XC9572XV-5VQ44C 5 ns VQ44 44-pin Quad Flat Pack (VQFP) C XC9572XV-5TQ100C 5 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) C XC9572XV-7VQ44C 7.5 ns VQ44 44-pin Quad Flat Pack (VQFP) C XC9572XV-7TQ100C 7.5 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) C XC9572XV-7VQ44I 7.5 ns VQ44 44-pin Quad Flat Pack (VQFP) I XC9572XV-7TQ100I 7.5 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) I Device Ordering and Part Marking Number Notes: 1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C 2. Some packages available in Pb-free option. See Xilinx Packaging for more information. 8 www.xilinx.com DS052 (v3.0) June 25, 2007 Product Specification R XC9572XV High-performance CPLD Revision History Date Revision No. 02/01/00 1.1 Initial Xilinx release. Advance information specification. 01/29/01 2.0 Added -4 performance specification and VQ44 pagkage. Deleted VQ64 package. Updated ICC vs. Frequency Figure 1. 05/15/01 2.1 Updated ICC formula, Recommended Operation Conditions, -4 and -5 AC Characteristics and Internal Timing Parameters 08/27/01 2.2 Changed VCCIO 3.3V from 3.13 to 3.0 (min), 3.46 to 3.60 (max); DC characteristics: IIL - added "low" current, IIH - changed to "Input leakage high current"; Internal Timing: -5 TAOI from 6.5 to 5.9. 05/31/02 2.3 Updated ICC equation on page 1. Updated Component Availability Chart. Changed to Preliminary. Added second test condition and max measurement to IIH DC Characteristics. Added Part Marking Information to Ordering Information. Removed the -4 device. 06/18/03 2.4 Updated TSOL from 260 to 220oC. Updated Device Part Marking. 08/21/03 2.5 Updated Package Device Marking Pin 1 orientation. 04/15/05 2.6 Added TAPRPW specification to AC Characteristics. Added IOSTANDARD information. 01/16/06 2.7 Removed PC44 and CS48 packages as per XCN05020. 06/25/07 3.0 Notice of discontinuance. DS052 (v3.0) June 25, 2007 Product Specification Description www.xilinx.com 9