R DS123 (v2.6) March 14, 2005 4 2 Platform Flash In-System Programmable Configuration PROMS Preliminary Product Specification 0 Features • In-System Programmable PROMs for Configuration of Xilinx FPGAs • Low-Power Advanced CMOS NOR FLASH Process • Endurance of 20,000 Program/Erase Cycles • Operation over Full Industrial Temperature Range (–40°C to +85°C) • IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing • JTAG Command Initiation of Standard FPGA Configuration • Cascadable for Storing Longer or Multiple Bitstreams • Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ) • I/O Pins Compatible with Voltage Levels Ranging From 1.5V to 3.3V • Design Support Using the Xilinx Alliance ISE and Foundation ISE Series Software Packages • XCF01S/XCF02S/XCF04S - 3.3V supply voltage - Serial FPGA configuration interface (up to 33 MHz) - Available in small-footprint VO20 and VOG20 packages. • XCF08P/XCF16P/XCF32P - 1.8V supply voltage - Serial or parallel FPGA configuration interface (up to 33 MHz) - Available in small-footprint VO48, VOG48, FS48, and FSG48 packages - Design revision technology enables storing and accessing multiple design revisions for configuration - Built-in data decompressor compatible with Xilinx advanced compression technology Table 1: Platform Flash PROM Features Density VCCINT VCCO Range VCCJ Range Packages JTAG ISP Programming Serial Parallel Config. Config. Design Revisioning Compression XCF01S 1 Mbit 3.3V 1.8V - 3.3V 2.5V - 3.3V VO20/VOG20 √ √ XCF02S 2 Mbit 3.3V 1.8V - 3.3V 2.5V - 3.3V VO20/VOG20 √ √ XCF04S 4 Mbit 3.3V 1.8V - 3.3V 2.5V - 3.3V VO20/VOG20 √ √ XCF08P 8 Mbit 1.8V 1.5V - 3.3V 2.5V - 3.3V VO48/VOG48 FS48/FSG48 √ √ √ √ √ XCF16P 16 Mbit 1.8V 1.5V - 3.3V 2.5V - 3.3V VO48/VOG48 FS48/FSG48 √ √ √ √ √ XCF32P 32 Mbit 1.8V 1.5V - 3.3V 2.5V - 3.3V VO48/VOG48 FS48/FSG48 √ √ √ √ √ Description Xilinx introduces the Platform Flash series of in-system programmable configuration PROMs. Available in 1 to 32 Megabit (Mbit) densities, these PROMs provide an easy-to-use, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The Platform Flash PROM series includes both the 3.3V XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS version includes 4-Mbit, 2-Mbit, and 1-Mbit PROMs that support Master Serial and Slave Serial FPGA configuration modes (Figure 1). The XCFxxP version includes 32-Mbit, 16-Mbit, and 8-Mbit PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes (Figure 2). A summary of the Platform Flash PROM family members and supported features is shown in Table 1. © 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 1 R Platform Flash In-System Programmable Configuration PROMS CLK CE OE/RESET TCK Control and JTAG Interface TMS TDI Data Memory Data Address CEO Serial Interface DATA (D0) Serial Mode TDO CF ds123_01_30603 Figure 1: XCFxxS Platform Flash PROM Block Diagram FI CLK CE EN_EXT_SEL OE/RESET BUSY CLKOUT TCK TMS TDI TDO Control and JTAG Interface OSC Data Address Memory Data CF Serial or Parallel Interface Decompressor REV_SEL [1:0] CEO DATA (D0) (Serial/Parallel Mode) D[1:7] (Parallel Mode) ds123_19_050604 Figure 2: XCFxxP Platform Flash PROM Block Diagram When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. With CF High, a short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. New data is available a short access time after each rising clock edge. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are both clocked by an external clock source, or optionally, for the XCFxxP PROM only, the PROM can be used to drive the FPGA’s configuration clock. The XCFxxP version of the Platform Flash PROM also supports Master SelectMAP and Slave SelectMAP (or Slave Parallel) FPGA configuration modes. When the FPGA is in Master SelectMAP mode, the FPGA generates a configuration clock that drives the PROM. When the FPGA is in Slave SelectMAP Mode, either an external oscillator generates the configuration clock that drives the PROM and the FPGA, or optionally, the XCFxxP PROM can be used to drive the FPGA’s configuration clock. With BUSY Low and DS123 (v2.6) March 14, 2005 Preliminary Product Specification CF High, after CE and OE are enabled, data is available on the PROMs DATA (D0-D7) pins. New data is available a short access time after each rising clock edge. The data is clocked into the FPGA on the following rising edge of the CCLK. A free-running oscillator can be used in the Slave Parallel /Slave SelecMAP mode. The XCFxxP version of the Platform Flash PROM provides additional advanced features. A built-in data decompressor supports utilizing compressed PROM files, and design revisioning allows multiple design revisions to be stored on a single PROM or stored across several PROMs. For design revisioning, external pins or internal control bits are used to select the active design revision. Multiple Platform Flash PROM devices can be cascaded to support the larger configuration files required when targeting larger FPGA devices or targeting multiple FPGAs daisy chained together. When utilizing the advanced features for the XCFxxP Platform Flash PROM, such as design revisioning, programming files which span cascaded PROM devices can only be created for cascaded chains containing only XCFxxP PROMs. If the advanced XCFxxP features are www.xilinx.com 2 R Platform Flash In-System Programmable Configuration PROMS not enabled, then the cascaded chain can include both XCFxxP and XCFxxS PROMs. Table 2: Xilinx FPGAs and Compatible Platform Flash PROMs (Continued) Configuration Bitstream Platform Flash PROM (1) The Platform Flash PROMs are compatible with all of the existing FPGA device families. A reference list of Xilinx FPGAs and the respective compatible Platform Flash PROMs is given in Table 2. A list of Platform Flash PROMs and their capacities is given in Table 3. XC2V250 1,697,184 XCF02S XC2V500 2,761,888 XCF04S XC2V1000 4,082,592 XCF04S Table 2: Xilinx FPGAs and Compatible Platform Flash PROMs XC2V1500 5,659,296 XCF08P FPGA Configuration Bitstream Platform Flash PROM (1) Virtex-4 LX FPGA XC2V2000 7,492,000 XCF08P XC2V3000 10,494,368 XCF16P XC2V4000 15,659,936 XCF16P XC2V6000 21,849,504 XCF32P 29,063,072 XCF32P 630,048 XCF01S XC4VLX15 4,765,185 XCF08P XC2V8000 XC4VLX25 7,819,520 XCF08P Virtex-E XC4VLX40 12,259,328 XCF16P XCV50E XC4VLX60 17,717,248 XCF32P XCV100E 863,840 XCF01S XC4VLX80 23,290,624 XCF32P XCV200E 1,442,016 XCF02S XC4VLX100 30,711,296 XCF32P XCV300E 1,875,648 XCF02S 2,693,440 XCF04S XC4VLX160 40,346,624 XCF32P+XCF08P XCV400E XC4VLX200 48,722,432 XCF32P+XCF16P XCV405E 3,430,400 XCF04S XCV600E 3,961,632 XCF04S Virtex-4 FX XC4VFX12 4,765,184 XCF08P XC4VFX20 7,242,240 XCF08P XC4VFX40 13,550,336 XCF16P XC4VFX60 21,002,496 XCF32P XC4VFX100 33,065,024 XCF32P XC4VFX140 47,856,512 XCF32P+XCF16P XC4VSX25 9,147,264 XCF16P XC4VSX35 13,669,904 XC4VSX55 Virtex-4 SX XCV812E 6,519,648 XCF08P XCV1000E 6,587,520 XCF08P XCV1600E 8,308,992 XCF08P XCV2000E 10,159,648 XCF16P XCV2600E 12,922,336 XCF16P XCV3200E 16,283,712 XCF16P Virtex XCV50 559,200 XCF01S XCV100 781,216 XCF01S XCF16P XCV150 1,040,096 XCF01S 22,744,832 XCF32P XCV200 1,335,840 XCF02S XCV300 1,751,808 XCF02S XC2VPX20 8,214,560 XCF08P XCV400 2,546,048 XCF04S XC2VPX70 26,098,976 XCF32P XCV600 3,607,968 XCF04S XCV800 4,715,616 XCF08P 6,127,744 XCF08P Virtex-II Pro X Virtex-II Pro XC2VP2 1,305,376 XCF02S XCV1000 XC2VP4 3,006,496 XCF04S Spartan-3E XC2VP7 4,485,408 XCF08P XC3S100E 581,344 XCF01S XC2VP20 8,214,560 XCF08P XC3S250E 1,352,192 XCF02S XC2VP30 11,589,920 XCF16P XC3S500E 2,267,136 XCF04S XC2VP40 15,868,192 XCF16P XC3S1200E 3,832,320 XCF04S XC2VP50 19,021,344 XCF32P XC3S1600E 5,957,760 XCF08P XC2VP70 26,098,976 XCF32P XC2VP100 34,292,768 XCF32P (2) XC3S1000L 3,223,488 XCF04S XC3S1500L 5,214,784 XCF08P XC3S5000L 13,271,936 XCF16P Virtex-II (3) XC2V40 360,096 XCF01S XC2V80 635,296 XCF01S DS123 (v2.6) March 14, 2005 Preliminary Product Specification Spartan-3L www.xilinx.com 3 R Platform Flash In-System Programmable Configuration PROMS Table 2: Xilinx FPGAs and Compatible Platform Flash PROMs (Continued) FPGA Configuration Bitstream Platform Flash PROM (1) Spartan-3 XC3S50 439,264 XCF01S XC3S200 1,047,616 XCF01S XC3S400 1,699,136 XCF02S XC3S1000 3,223,488 XCF04S XC3S1500 5,214,784 XCF08P XC3S2000 7,673,024 XCF08P XC3S4000 11,316,864 XCF16P XC3S5000 13,271,936 XCF16P 630,048 XCF01S programming data sequence is delivered to the device using either Xilinx iMPACT software and a Xilinx download cable, a third-party JTAG development system, a JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. The iMPACT software also outputs serial vector format (SVF) files for use with any tools that accept SVF format, including automatic test equipment. During in-system programming, the CEO output is driven High. All other outputs are held in a high-impedance state or held at clamp levels during in-system programming. In-system programming is fully supported across the recommended operating voltage and temperature ranges. Spartan-IIE XC2S50E XC2S100E 863,840 XCF01S XC2S150E 1,134,496 XCF02S XC2S200E 1,442,016 XCF02S XC2S300E 1,875,648 XCF02S XC2S400E 2,693,440 XCF04S XC2S600E 3,961,632 XCF04S XC2S15 197,696 XCF01S XC2S30 336,768 XCF01S XC2S50 559,200 XCF01S XC2S100 781,216 XCF01S XC2S150 1,040,096 XCF01S XC2S200 1,335,840 XCF02S V CC GND Spartan-II (a) (a) Solder Device to PCB (b) Program Using Download Cable OE/RESET Table 3: Platform Flash PROM Capacity Configuration Bits Platform Flash PROM DS026_02_082703 Figure 3: JTAG In-System Programming Operation Notes: 1. If design revisioning or other advanced feature support is required, the XCFxxP can be used as an alternative to the XCF01S, XCF02S, or XCF04S. 2. Assumes compression used. 3. The largest possible Virtex-II bitstream sizes are specified. Refer to the Virtex-II User Guide for information on bitgen options which affect bitstream size. Platform Flash PROM (b) Configuration Bits The 1/2/4 Mbit XCFxxS Platform Flash PROMs in-system programming algorithm results in issuance of an internal device reset that causes OE/RESET to pulse Low. External Programming Xilinx reprogrammable PROMs can also be programmed by the Xilinx MultiPRO Desktop Tool or a third-party device programmer. This provides the added flexibility of using pre-programmed devices with an in-system programmable option for future enhancements and design changes. XCF01S 1,048,576 XCF08P 8,388,608 XCF02S 2,097,152 XCF16P 16,777,216 Reliability and Endurance XCF04S 4,194,304 XCF32P 33,554,432 Xilinx in-system programmable products provide a guaranteed endurance level of 20,000 in-system program/erase cycles and a minimum data retention of 20 years. Each device meets all functional, performance, and data retention specifications within this endurance limit. Programming In-System Programming In-System Programmable PROMs can be programmed individually, or two or more can be daisy-chained together and programmed in-system via the standard 4-pin JTAG protocol as shown in Figure 3. In-system programming offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. The DS123 (v2.6) March 14, 2005 Preliminary Product Specification Design Security The Xilinx in-system programmable Platform Flash PROM devices incorporate advanced data security features to fully protect the FPGA programming data against unauthorized reading via JTAG. The XCFxxP PROMs can also be pro- www.xilinx.com 4 R Platform Flash In-System Programmable Configuration PROMS grammed to prevent inadvertent writing via JTAG. Table 4 and Table 5 show the security settings available for the XCFxxS PROM and XCFxxP PROM, respectively. Read Protection The read protect security bit can be set by the user to prevent the internal programming pattern from being read or copied via JTAG. Read protection does not prevent write operations. For the XCFxxS PROM, the read protect security bit is set for the entire device, and resetting the read protect security bit requires erasing the entire device. For the XCFxxP PROM the read protect security bit can be set for individual design revisions, and resetting the read protect bit requires erasing the particular design revision. Write Protection The XCFxxP PROM device also allows the user to write protect (or lock) a particular design revision to prevent inadvertent erase or program operations. Once set, the write protect security bit for an individual design revision must be reset (using the UNLOCK command followed by ISC_ERASE command) before an erase or program operation can be performed. Table 4: XCFxxS Device Data Security Options Read Protect Read/Verify Inhibited Program Inhibited Erase Inhibited Reset (default) √ Set Table 5: XCFxxP Design Revision Data Security Options Read Protect Write Protect Reset (default) Reset (default) Reset (default) Set Read/Verify Inhibited Set Reset (default) √ Set Set √ Program Inhibited Erase Inhibited √ √ √ √ IEEE 1149.1 Boundary-Scan (JTAG) The Platform Flash PROM family is IEEE Standard 1532 in-system programming compatible, and is fully compliant with the IEEE Std. 1149.1 Boundary-Scan, also known as JTAG, which is a subset of IEEE Std. 1532 Boundary-Scan. A Test Access Port (TAP) and registers are provided to support all required boundary scan instructions, as well as many of the optional instructions specified by IEEE Std. 1149.1. In addition, the JTAG interface is used to implement in-system programming (ISP) to facilitate configuration, erasure, and verification operations on the Platform Flash PROM device. Table 6 lists the required and optional boundary-scan instructions supported in the Platform Flash PROMs. Refer to the IEEE Std. 1149.1 specification for a complete description of boundary-scan architecture and the required and optional instructions. XCFxxS Instruction Register (8 bits wide) The Instruction Register (IR) for the XCFxxS PROM is eight bits wide and is connected between TDI and TDO during an instruction scan sequence. The detailed composition of the instruction capture pattern is illustrated in Figure 4. The instruction capture pattern shifted out of the XCFxxS device includes IR[7:0]. IR[7:5] are reserved bits and are set to a logic "0". The ISC Status field, IR[4], contains logic "1" if the device is currently in In-System Configuration (ISC) mode; otherwise, it contains logic "0". The Security field, IR[3], contains logic "1" if the device has been programmed with the security option turned on; otherwise, it contains logic "0". IR[2] is unused, and is set to '0'. The remaining bits IR[1:0] are set to '01' as defined by IEEE Std. 1149.1. XCFxxP Instruction Register (16 bits wide) Instruction Register The Instruction Register (IR) for the Platform Flash PROM is connected between TDI and TDO during an instruction scan sequence. In preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction capture pattern. This pattern is shifted out onto TDO (LSB first), while an instruction is shifted into the instruction register from TDI. DS123 (v2.6) March 14, 2005 Preliminary Product Specification The Instruction Register (IR) for the XCFxxP PROM is sixteen bits wide and is connected between TDI and TDO during an instruction scan sequence. The detailed composition of the instruction capture pattern is illustrated in Figure 5. The instruction capture pattern shifted out of the XCFxxP device includes IR[15:0]. IR[15:9] are reserved bits and are set to a logic "0". The ISC Error field, IR[8:7], contains a "10" when an ISC operation is a success; otherwise a "01" when an In-System Configuration (ISC) operation fails. The Erase/Program (ER/PROG) Error field, IR[6:5], contains a "10" when an erase or program operation is a success; oth- www.xilinx.com 5 R Platform Flash In-System Programmable Configuration PROMS erwise a "01" when an erase or program operation fails. The Erase/Program (ER/PROG) Status field, IR[4], contains a logic "1" when the device is busy performing an erase or programming operation; otherwise, it contains a logic "0". The ISC Status field, IR[3], contains logic "1" if the device is currently in In-System Configuration (ISC) mode; otherwise, it contains logic "0". The DONE field, IR[2], contains logic "1" if the sampled design revision has been successfully programmed; otherwise, a logic "0" indicates incomplete programming. The remaining bits IR[1:0] are set to '01' as defined by IEEE Std. 1149.1 . Table 6: Platform Flash PROM Boundary Scan Instructions XCFxxS IR[7:0] (hex) XCFxxP IR[15:0] (hex) BYPASS FF FFFF Enables BYPASS SAMPLE/PRELOAD 01 0001 Enables boundary-scan SAMPLE/PRELOAD operation EXTEST 00 0000 Enables boundary-scan EXTEST operation CLAMP FA 00FA Enables boundary-scan CLAMP operation HIGHZ FC 00FC Places all outputs in high-impedance state simultaneously IDCODE FE 00FE Enables shifting out 32-bit IDCODE USERCODE FD 00FD Enables shifting out 32-bit USERCODE 00EE Initiates FPGA configuration by pulsing CF pin Low once. (For the XCFxxP this command also resets the selected design revision based on either the external REV_SEL[1:0] pins or on the internal design revision selection bits.) (1) Boundary-Scan Command Instruction Description Required Instructions Optional Instructions Platform Flash PROM Specific Instructions CONFIG EE Notes: 1. For more information see Initiating FPGA Configuration. TDI → IR[7:5] IR[4] IR[3] IR[2] IR[1:0] Reserved ISC Status Security 0 01 → TDO Figure 4: XCFxxS Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence TDI → IR[15:9] IR[8:7] IR[6:5] IR[4] IR[3] IR[2] IR[1:0] Reserved ISC Error ER/PROG Error ER/PROG Status ISC Status DONE 01 → TDO Figure 5: XCFxxP Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence Boundary Scan Register The boundary-scan register is used to control and observe the state of the device pins during the EXTEST, SAMPLE/PRELOAD, and CLAMP instructions. Each output pin on the Platform Flash PROM has two register stages which contribute to the boundary-scan register, while each input pin has only one register stage. The bidirectional pins have a total of three register stages which contribute to the boundary-scan register. For each output pin, the register DS123 (v2.6) March 14, 2005 Preliminary Product Specification stage nearest to TDI controls and observes the output state, and the second stage closest to TDO controls and observes the High-Z enable state of the output pin. For each input pin, a single register stage controls and observes the input state of the pin. The bidirectional pin combines the three bits, the input stage bit is first, followed by the output stage bit and finally the output enable stage bit. The output enable stage bit is closest to TDO. www.xilinx.com 6 R Platform Flash In-System Programmable Configuration PROMS See the XCFxxS/XCFxxP Pin Names and Descriptions Tables in the Pinouts and Pin Descriptions section for the boundary-scan bit order for all connected device pins, or see the appropriate BSDL file for the complete boundary-scan bit order description under the "attribute BOUNDARY_REGISTER" section in the BSDL file. The bit assigned to boundary-scan cell "0" is the LSB in the boundary-scan register, and is the register bit closest to TDO. Identification Registers USERCODE Register The USERCODE instruction gives access to a 32-bit user programmable scratch pad typically used to supply information about the device's programmed contents. By using the USERCODE instruction, a user-programmable identification code can be shifted out for examination. This code is loaded into the USERCODE register during programming of the Platform Flash PROM. If the device is blank or was not loaded during programming, the USERCODE register contains FFFFFFFFh. IDCODE Register Customer Code Register The IDCODE is a fixed, vendor-assigned value that is used to electrically identify the manufacturer and type of the device being addressed. The IDCODE register is 32 bits wide. The IDCODE register can be shifted out for examination by using the IDCODE instruction. The IDCODE is available to any other system component via JTAG. Table 7 lists the IDCODE register values for the Platform Flash PROMs. For the XCFxxP Platform Flash PROM, in addition to the USERCODE, a unique 32-byte Customer Code can be assigned to each design revision enabled for the PROM. The Customer Code is set during programming, and is typically used to supply information about the design revision contents. A private JTAG instruction is required to read the Customer Code. If the PROM is blank, or the Customer Code for the selected design revision was not loaded during programming, or if the particular design revision is erased, the Customer Code will contain all ones. The IDCODE register has the following binary format: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 where Platform Flash PROM TAP Characteristics v = the die version number f = the PROM family code a = the specific Platform Flash PROM product ID c = the Xilinx manufacturer's ID The LSB of the IDCODE register is always read as logic "1" as defined by IEEE Std. 1149.1. Table 7: IDCODES Assigned to Platform Flash PROMs Device IDCODE (1) (hex) XCF01S <v>5044093 XCF02S <v>5045093 XCF04S <v>5046093 XCF08P <v>5057093 XCF16P <v>5058093 XCF32P <v>5059093 The Platform Flash PROM family performs both in-system programming and IEEE 1149.1 boundary-scan (JTAG) testing via a single 4-wire Test Access Port (TAP). This simplifies system designs and allows standard Automatic Test Equipment to perform both functions. The AC characteristics of the Platform Flash PROM TAP are described as follows. TAP Timing Figure 6 shows the timing relationships of the TAP signals. These TAP timing characteristics are identical for both boundary-scan and ISP operations. Notes: 1. The <v> in the IDCODE field represents the device’s revision code (in hex), and may vary. DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 7 R Platform Flash In-System Programmable Configuration PROMS TCKMIN TCK TMSS TMSH TMS TDIS TDIH TDI TDOV TDO DS026_04_020300 Figure 6: Test Access Port Timing TAP AC Parameters Table 8 shows the timing parameters for the TAP waveforms shown in Figure 6. Table 8: Test Access Port Timing Parameters Symbol Description Min Max Units TCKMIN TCK minimum clock period when VCCJ = 2.5V or 3.3V 100 - ns TMSS TMS setup time when VCCJ = 2.5V or 3.3V 10 - ns TMSH TMS hold time when VCCJ = 2.5V or 3.3V 25 - ns TDIS TDI setup time when VCCJ = 2.5V or 3.3V 10 - ns TDIH TDI hold time when VCCJ = 2.5V or 3.3V 25 - ns TDOV TDO valid delay when VCCJ = 2.5V or 3.3V - 30 ns Additional Features for the XCFxxP Internal Oscillator The 8/16/32 Mbit XCFxxP Platform Flash PROMs include an optional internal oscillator which can be used to drive the CLKOUT and DATA pins on FPGA configuration interface. The internal oscillator can be enabled during device programming, and can be set to either the default frequency or to a slower frequency (AC Characteristics Over Operating Conditions When Cascading). CLKOUT The 8/16/32 Mbit XCFxxP Platform Flash PROMs include the programmable option to enable the CLKOUT signal which allows the PROM to provide a source synchronous clock aligned to the data on the configuration interface. The CLKOUT signal is derived from one of two clock sources: the CLK input pin or the internal oscillator. The input clock source is selected during the PROM programming sequence. Output data is available on the rising edge of CLKOUT. DS123 (v2.6) March 14, 2005 Preliminary Product Specification The CLKOUT signal is enabled during programming, and is active when CE is Low and OE/RESET is High. When disabled, the CLKOUT pin is put into a high-impedance state and should be pulled High externally to provide a known state. When cascading Platform Flash PROMs with CLKOUT enabled, after completing it's data transfer, the first PROM disables CLKOUT and releases the CEO pin enabling the next PROM in the PROM chain. The next PROM will begin driving the CLKOUT signal once that PROM is enabled and data is available for transfer. During high-speed parallel configuration without compression, the FPGA drives the BUSY signal on the configuration interface. When BUSY is asserted High, the PROMs internal address counter stops incrementing, and the current data value is held on the data outputs. While BUSY is High, the PROM will continue driving the CLKOUT signal to the FPGA, clocking the FPGA’s configuration logic. When the FPGA deasserts BUSY, indicating that it is ready to receive additional configuration data, the PROM will begin driving new data onto the configuration interface. www.xilinx.com 8 R Platform Flash In-System Programmable Configuration PROMS Decompression The 8/16/32 Mbit XCFxxP Platform Flash PROMs include a built-in data decompressor compatible with Xilinx advanced compression technology. Compressed Platform Flash PROM files are created from the target FPGA bitstream(s) using the iMPACT software. Only Slave Serial and Slave SelectMAP (parallel) configuration modes are supported for FPGA configuration when using a XCFxxP PROM programmed with a compressed bitstream. Compression rates will vary depending on several factors, including the target device family and the target design contents. The decompression option is enabled during the PROM programming sequence. The PROM decompresses the stored data before driving both clock and data onto the FPGA's configuration interface. If Decompression is enabled, then the Platform Flash clock output pin (CLK- OUT) must be used as the clock signal for the configuration interface, driving the target FPGA's configuration clock input pin (CCLK). Either the PROM's CLK input pin or the internal oscillator must be selected as the source for CLKOUT. Any target FPGA connected to the PROM must operate as slave in the configuration chain, with the configuration mode set to Slave Serial mode or Slave SelectMap (parallel) mode. When decompression is enabled, the CLKOUT signal becomes a controlled clock output with a reduced maximum frequency. When decompressed data is not ready, the CLKOUT pin is put into a high-Z state and must be pulled High externally to provide a known state. The BUSY input is automatically disabled when decompression is enabled. Design Revisioning Design Revisioning allows the user to create up to four unique design revisions on a single PROM or stored across multiple cascaded PROMs. Design Revisioning is supported for the 8/16/32 Mbit XCFxxP Platform Flash PROMs in both serial and parallel modes. Design Revisioning can be used with compressed PROM files, and also when the CLKOUT feature is enabled. The PROM programming files along with the revision information files (.cfi) are created using the iMPACT software. The .cfi file is required to enable design revision programming in iMPACT. A single design revision is composed of from 1 to n 8-Mbit memory blocks. If a single design revision contains less than 8 Mbits of data, then the remaining space is padded with all ones. A larger design revision can span several 8-Mbit memory blocks, and any space remaining in the last 8-Mbit memory block is padded with all ones. • • • A single 32-Mbit PROM contains four 8-Mbit memory blocks, and can therefore store up to four separate design revisions: one 32-Mbit design revision, two 16-Mbit design revisions, three 8-Mbit design revisions, four 8-Mbit design revisions, and so on. Because of the 8-Mbit minimum size requirement for each revision, a single 16-Mbit PROM can only store up to two separate design revisions: one 16-Mbit design revision, one 8-Mbit design revision, or two 8-Mbit design revisions. A single 8-Mbit PROM can store only one 8-Mbit design revision. Larger design revisions can be split over several cascaded PROMs. For example, two 32-Mbit PROMs can store up to four separate design revisions: one 64-Mbit design revision, two 32-Mbit design revisions, three 16-Mbit design revisions, four 16-Mbit design revisions, and so on. When cas- DS123 (v2.6) March 14, 2005 Preliminary Product Specification cading one 16-Mbit PROM and one 8-Mbit PROM, there are 24 Mbits of available space, and therefore up to three separate design revisions can be stored: one 24-Mbit design revision, two 8-Mbit design revisions, or three 8-Mbit design revisions. See Figure 7 for a few basic examples of how multiple revisions can be stored. The design revision partitioning is handled automatically during file generation in iMPACT. During the PROM file creation, each design revision is assigned a revision number: Revision 0 = '00' Revision 1 = '01' Revision 2 = '10' Revision 3 = '11' After programming the Platform Flash PROM with a set of design revisions, a particular design revision can be selected using the external REV_SEL[1:0] pins or using the internal programmable design revision control bits. The EN_EXT_SEL pin determines if the external pins or internal bits are used to select the design revision. When EN_EXT_SEL is Low, design revision selection is controlled by the external Revision Select pins, REV_SEL[1:0]. When EN_EXT_SEL is High, design revision selection is controlled by the internal programmable Revision Select control bits. During power up, the design revision selection inputs (pins or control bits) are sampled internally. After power up, when CE is asserted (Low) enabling the PROM inputs, the design revision selection inputs are sampled again after the rising edge of the CF pulse. The data from the selected design revision is then presented on the FPGA configuration interface. www.xilinx.com 9 R Platform Flash In-System Programmable Configuration PROMS PROM 0 PROM 0 REV 0 (8 Mbits) REV 0 (8 Mbits) PROM 0 PROM 0 PROM 0 REV 0 (8 Mbits) REV 0 (16 Mbits) REV 1 (8 Mbits) REV 1 (8 Mbits) REV 0 (32 Mbits) REV 1 (24 Mbits) REV 2 (8 Mbits) REV 2 (16 Mbits) REV 1 (16 Mbits) REV 3 (8 Mbits) 4 Design Revisions 3 Design Revisions 2 Design Revisions 1 Design Revision (a) Design Revision storage examples for a single XCF32P PROM PROM 0 PROM 0 REV 0 (16 Mbits) REV 0 (16 Mbits) PROM 0 PROM 0 PROM 0 REV 0 (16 Mbits) REV 0 (32 Mbits) REV 1 (16 Mbits) REV 1 (16 Mbits) PROM 1 PROM 1 REV 0 (32 Mbits) REV 1 (16 Mbits) PROM 1 PROM 1 PROM 1 REV 1 (32 Mbits) REV 0 (32 Mbits) REV 2 (16 Mbits) REV 2 (32 Mbits) REV 1 (32 Mbits) REV 3 (16 Mbits) 4 Design Revisions 3 Design Revisions 2 Design Revisions 1 Design Revision (b) Design Revision storage examples spanning two XCF32P PROMs ds123_20_102103 Figure 7: Design Revision Storage Examples PROM to FPGA Configuration Mode and Connections Summary The FPGA's I/O, logical functions, and internal interconnections are established by the configuration data contained in the FPGA’s bitstream. The bitstream is loaded into the FPGA either automatically upon power up, or on command, depending on the state of the FPGA's mode pins. Xilinx Platform Flash PROMs are designed to download directly to the FPGA configuration interface. FPGA configuration modes which are supported by the XCFxxS Platform Flash PROMs include: Master Serial and Slave Serial. FPGA configuration modes which are supported by the XCFxxP Platform Flash PROMs include: Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP. Below is a short summary of the supported FPGA configuration modes. See the respective FPGA data sheet for device configuration details, including which configuration modes are supported by the targeted FPGA device. DS123 (v2.6) March 14, 2005 Preliminary Product Specification FPGA Master Serial Mode In Master Serial mode, the FPGA automatically loads the configuration bitstream in bit-serial form from external memory synchronized by the configuration clock (CCLK) generated by the FPGA. Upon power-up or reconfiguration, the FPGA's mode select pins are used to select the Master Serial configuration mode. Master Serial Mode provides a simple configuration interface. Only a serial data line, a clock line, and two control lines (INIT and DONE) are required to configure an FPGA. Data from the PROM is read out sequentially on a single data line (DIN), accessed via the PROM's internal address counter which is incremented on every valid rising edge of CCLK. The serial bitstream data must be set up at the FPGA’s DIN input pin a short time before each rising edge of the FPGA's internally generated CCLK signal. www.xilinx.com 10 R Platform Flash In-System Programmable Configuration PROMS Typically, a wide range of frequencies can be selected for the FPGA’s internally generated CCLK which always starts at a slow default frequency. The FPGA’s bitstream contains configuration bits which can switch CCLK to a higher frequency for the remainder of the Master Serial configuration sequence. The desired CCLK frequency is selected during bitstream generation. • • • Connecting the FPGA device to the configuration PROM for Master Serial Configuration Mode (Figure 8): • • • • • • The DATA output of the PROM(s) drive the DIN input of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the PROM(s) The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The OE/RESET pins of all PROMs are connected to the INIT_B pins of all FPGA devices. This connection assures that the PROM address counter is reset before the start of any (re)configuration. The PROM CE input can be driven from the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of all target FPGA devices, provided that DONE is not permanently grounded. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary ICC active supply current (DC Characteristics Over Operating Conditions). The PROM CF pin is typically connected to the FPGA's PROG_B (or PROGRAM) input. For the XCFxxP only, the CF pin is a bidirectional pin. If the XCFxxP CF pin is not connected to the FPGA's PROG_B (or PROGRAM) input, then the pin should be tied High. FPGA Slave Serial Mode In Slave Serial mode, the FPGA loads the configuration bitstream in bit-serial form from external memory synchronized by an externally supplied clock. Upon power-up or reconfiguration, the FPGA's mode select pins are used to select the Slave Serial configuration mode. Slave Serial Mode provides a simple configuration interface. Only a serial data line, a clock line, and two control lines (INIT and DONE) are required to configure an FPGA. Data from the PROM is read out sequentially on a single data line (DIN), accessed via the PROM's internal address counter which is incremented on every valid rising edge of CCLK. The serial bitstream data must be set up at the FPGA’s DIN input pin a short time before each rising edge of the externally provided CCLK. Connecting the FPGA device to the configuration PROM for Slave Serial Configuration Mode (Figure 9): • • The DATA output of the PROM(s) drive the DIN input of the lead FPGA device. The PROM CLKOUT (for XCFxxP only) or an external clock source drives the FPGA's CCLK input. DS123 (v2.6) March 14, 2005 Preliminary Product Specification • The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The OE/RESET pins of all PROMs are connected to the INIT_B (or INIT) pins of all FPGA devices. This connection assures that the PROM address counter is reset before the start of any (re)configuration. The PROM CE input can be driven from the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of all target FPGA devices, provided that DONE is not permanently grounded. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary ICC active supply current (DC Characteristics Over Operating Conditions). The PROM CF pin is typically connected to the FPGA's PROG_B (or PROGRAM) input. For the XCFxxP only, the CF pin is a bidirectional pin. If the XCFxxP CF pin is not connected to the FPGA's PROG_B (or PROGRAM) input, then the pin should be tied High. Serial Daisy Chain Multiple FPGAs can be daisy-chained for serial configuration from a single source. After a particular FPGA has been configured, the data for the next device is routed internally to the FPGA’s DOUT pin. Typically the data on the DOUT pin changes on the falling edge of CCLK, although for some devices the DOUT pin changes on the rising edge of CCLK. Consult the respective device data sheets for detailed information on a particular FPGA device. For clocking the daisy-chained configuration, either the first FPGA in the chain can be set to Master Serial, generating the CCLK, with the remaining devices set to Slave Serial (Figure 10), or all the FPGA devices can be set to Slave Serial and an externally generated clock can be used to drive the FPGA's configuration interface. FPGA Master SelectMAP (Parallel) Mode(1) In Master SelectMAP mode, byte-wide data is written into the FPGA, typically with a BUSY flag controlling the flow of data, synchronized by the configuration clock (CCLK) generated by the FPGA. Upon power-up or reconfiguration, the FPGA's mode select pins are used to select the Master SelectMAP configuration mode. The configuration interface typically requires a parallel data bus, a clock line, and two control lines (INIT and DONE). In addition, the FPGA’s Chip Select, Write, and BUSY pins must be correctly controlled to enable SelectMAP configuration. The configuration data is read from the PROM byte by byte on pins [D0..D7], accessed via the PROM's internal address counter which is incremented on every valid rising edge of CCLK. The bitstream data must be set up at the FPGA’s [D0..D7] input 1. The Master SelectMAP (Parallel) FPGA configuration mode is supported only by the XCFxxP Platform Flash PROM. This mode is not supported by the XCFxxS Platform Flash PROM. www.xilinx.com 11 R Platform Flash In-System Programmable Configuration PROMS pins a short time before each rising edge of the FPGA's internally generated CCLK signal. If BUSY is asserted (High) by the FPGA, the configuration data must be held until BUSY goes Low. An external data source or external pull-down resistors must be used to enable the FPGA's active Low Chip Select (CS or CS_B) and Write (WRITE or RDWR_B) signals to enable the FPGA's SelectMAP configuration process. The Master SelectMAP configuration interface is clocked by the FPGA’s internal oscillator. Typically, a wide range of frequencies can be selected for the internally generated CCLK which always starts at a slow default frequency. The FPGA’s bitstream contains configuration bits which can switch CCLK to a higher frequency for the remainder of the Master SelectMAP configuration sequence. The desired CCLK frequency is selected during bitstream generation. After configuration, the pins of the SelectMAP port can be used as additional user I/O. Alternatively, the port can be retained using the persist option. Connecting the FPGA device to the configuration PROM for Master SelectMAP (Parallel) Configuration Mode (Figure 11): • • • • • • • The DATA outputs of the PROM(s) drive the [D0..D7] input of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the PROM(s) The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The OE/RESET pins of all PROMs are connected to the INIT_B pins of all FPGA devices. This connection assures that the PROM address counter is reset before the start of any (re)configuration. The PROM CE input can be driven from the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of all target FPGA devices, provided that DONE is not permanently grounded. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary ICC active supply current (DC Characteristics Over Operating Conditions). For high-frequency parallel configuration, the BUSY pins of all PROMs are connected to the FPGA's BUSY output. This connection assures that the next data transition for the PROM is delayed until the FPGA is ready for the next configuration data byte. The PROM CF pin is typically connected to the FPGA's PROG_B (or PROGRAM) input. For the XCFxxP only, the CF pin is a bidirectional pin. If the XCFxxP CF pin is not connected to the FPGA's PROG_B (or PROGRAM) input, then the pin should be tied High. FPGA Slave SelectMAP (Parallel) Mode(1) In Slave SelectMAP mode, byte-wide data is written into the FPGA, typically with a BUSY flag controlling the flow of DS123 (v2.6) March 14, 2005 Preliminary Product Specification data, synchronized by an externally supplied configuration clock (CCLK). Upon power-up or reconfiguration, the FPGA's mode select pins are used to select the Slave SelectMAP configuration mode. The configuration interface typically requires a parallel data bus, a clock line, and two control lines (INIT and DONE). In addition, the FPGA’s Chip Select, Write, and BUSY pins must be correctly controlled to enable SelectMAP configuration. The configuration data is read from the PROM byte by byte on pins [D0..D7], accessed via the PROM's internal address counter which is incremented on every valid rising edge of CCLK. The bitstream data must be set up at the FPGA’s [D0..D7] input pins a short time before each rising edge of the provided CCLK. If BUSY is asserted (High) by the FPGA, the configuration data must be held until BUSY goes Low. An external data source or external pull-down resistors must be used to enable the FPGA's active Low Chip Select (CS or CS_B) and Write (WRITE or RDWR_B) signals to enable the FPGA's SelectMAP configuration process. After configuration, the pins of the SelectMAP port can be used as additional user I/O. Alternatively, the port can be retained using the persist option. Connecting the FPGA device to the configuration PROM for Slave SelectMAP (Parallel) Configuration Mode (Figure 12): • • • • • • • The DATA outputs of the PROM(s) drives the [D0..D7] inputs of the lead FPGA device. The PROM CLKOUT (for XCFxxP only) or an external clock source drives the FPGA's CCLK input The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The OE/RESET pins of all PROMs are connected to the INIT_B pins of all FPGA devices. This connection assures that the PROM address counter is reset before the start of any (re)configuration. The PROM CE input can be driven from the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of all target FPGA devices, provided that DONE is not permanently grounded. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary ICC active supply current (DC Characteristics Over Operating Conditions). For high-frequency parallel configuration, the BUSY pins of all PROMs are connected to the FPGA's BUSY output. This connection assures that the next data transition for the PROM is delayed until the FPGA is ready for the next configuration data byte. The PROM CF pin is typically connected to the FPGA's 1. The Slave SelectMAP (Parallel) FPGA configuration mode is supported only by the XCFxxP Platform Flash PROMs.This mode is not supported by the XCFxxS Platform Flash PROM. www.xilinx.com 12 R Platform Flash In-System Programmable Configuration PROMS PROG_B (or PROGRAM) input. For the XCFxxP only, the CF pin is a bidirectional pin. If the XCFxxP CF pin is not connected to the FPGA's PROG_B (or PROGRAM) input, then the pin should be tied High. FPGA SelectMAP (Parallel) Device Chaining(1) Multiple Virtex-II FPGAs can be configured using the SelectMAP mode, and be made to start up simultaneously. To configure multiple devices in this way, wire the individual CCLK, DONE, INIT, Data ([D0..D7]), Write (WRITE or RDWR_B), and BUSY pins of all the devices in parallel. If all devices are to be configured with the same bitstream, readback is not being used, and the CCLK frequency selected does not require the use of the BUSY signal, the CS_B pins can be connected to a common line so all of the devices are configured simultaneously (Figure 13). With additional control logic, the individual devices can be loaded separately by asserting the CS_B pin of each device in turn and then enabling the appropriate configuration data. The PROM can also store the individual bitstreams for each FPGA for SelectMAP configuration in separate design revisions. When design revisioning is utilized, additional control logic can be used to select the appropriate bitstream by asserting the EN_EXT_SEL pin, and using the REV_SEL[1:0] pins to select the required bitstream, while asserting the CS_B pin for the FPGA the bitstream is targeting (Figure 14). For clocking the parallel configuration chain, either the first FPGA in the chain can be set to Master SelectMAP, generating the CCLK, with the remaining devices set to Slave SelectMAP, or all the FPGA devices can be set to Slave SelectMAP and an externally generated clock can be used to drive the configuration interface. Again, the respective device data sheets should be consulted for detailed information on a particular FPGA device, including which configuration modes are supported by the targeted FPGA device. Cascading Configuration PROMs When configuring multiple FPGAs in a serial daisy chain, configuring multiple FPGAs in a SelectMAP parallel chain, or configuring a single FPGA requiring a larger configuration bitstream, cascaded PROMs provide additional memory (Figure 10, Figure 13, Figure 14, and Figure 15). Multiple Platform Flash PROMs can be concatenated by using the CEO output to drive the CE input of the downstream device. The clock signal and the data outputs of all Platform Flash PROMs in the chain are interconnected. After the last data from the first PROM is read, the first PROM asserts its CEO output Low and drives its outputs to a high-impedance state. The second PROM recognizes the Low level on its CE input and immediately enables its outputs. After configuration is complete, address counters of all cascaded PROMs are reset if the PROM OE/RESET pin goes Low or CE goes High. When utilizing the advanced features for the XCFxxP Platform Flash PROM, including the clock output (CLKOUT) option, decompression option, or design revisioning, programming files which span cascaded PROM devices can only be created for cascaded chains containing only XCFxxP PROMs. If the advanced features are not used, then cascaded PROM chains can contain both XCFxxP and XCFxxS PROMs. Initiating FPGA Configuration The options for initiating FPGA configuration via the Platform Flash PROM include: 1. Automatic configuration on power up 2. Applying an external PROG_B (or PROGRAM) pulse 3. Applying the JTAG CONFIG instruction Following the FPGA’s power-on sequence or the assertion of the PROG_B (or PROGRAM) pin the FPGA’s configuration memory is cleared, the configuration mode is selected, and the FPGA is ready to accept a new configuration bitstream. The FPGA’s PROG_B pin can be controlled by an external source, or alternatively, the Platform Flash PROMs incorporate a CF pin that can be tied to the FPGA’s PROG_B pin. Executing the CONFIG instruction through JTAG pulses the CF output Low once for 300-500 ns, resetting the FPGA and initiating configuration. The iMPACT software can issue the JTAG CONFIG command to initiate FPGA configuration by setting the "Load FPGA" option. When using the XCFxxP Platform Flash PROM with design revisioning enabled, the CF pin should always be connected to the PROG_B (or PROGRAM) pin on the FPGA to ensure that the current design revision selection is sampled when the FPGA is reset. The XCFxxP PROM samples the current design revision selection from the external REV_SEL pins or the internal programmable Revision Select bits on the rising edge of CF. When the JTAG CONFIG command is executed, the XCFxxP will sample the new design revision before initiating the FPGA configuration sequence. When using the XCFxxP Platform Flash PROM without design revisioning, if the CF pin is not connected to the FPGA PROG_B (or PROGRAM) pin, then the XCFxxP CF pin should be tied High. 1. The SelectMAP (Parallel) FPGA configuration modes are supported only by the XCFxxP Platform Flash PROM.These modes are not supported by the XCFxxS Platform Flash PROM. DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 13 R Platform Flash In-System Programmable Configuration PROMS Configuration PROM to FPGA Device Interface Connection Diagrams VCCJ VCCO VCCINT VCCINT D0 4.7 kΩ 4.7 kΩ VCCO(2) (1) DIN MODE PINS (1) (2) VCCO (2) DIN VCCJ CCLK Xilinx FPGA Master Serial Platform Flash PROM DONE INIT_B PROG_B CLK CCLK CE DONE DOUT CEO OE/RESET (3) INIT_B DIN CCLK PROG_B TDI TDI TMS TMS INIT_B TCK TCK PROG_B CF DONE ...OPTIONAL Slave FPGAs with identical configurations ...OPTIONAL Daisy-chained Slave FPGAs with different configurations TDO TDO GND TDI TMS TCK TDO GND Notes: 1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate data sheet. 3 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin. ds123_11_100804 Figure 8: Configuring in Master Serial Mode DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 14 R Platform Flash In-System Programmable Configuration PROMS VCCO(2) External (3) VCCJ VCCO VCCINT VCCINT D0 4.7 kΩ 4.7 kΩ Oscillator (1) DIN MODE PINS (1) VCCO(2) (2) DIN VCCJ CCLK Xilinx FPGA Slave Serial Platform Flash PROM DONE INIT_B PROG_B (3) CCLK CE DONE CLK DOUT CEO OE/RESET (4) INIT_B DIN CCLK PROG_B TDI TDI TMS TMS INIT_B TCK TCK PROG_B CF DONE ...OPTIONAL Slave FPGAs with identical configurations ...OPTIONAL Daisy-chained Slave FPGAs with different configurations TDO TDO GND TDI TMS TCK TDO GND Notes: 1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate data sheet. 3 In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or optionally—for the XCFxxP Platform Flash PROM only—the CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used, then it must be tied to a 4.7KΩ resistor pulled up to VCCO. 4 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin. ds123_12_100804 Figure 9: Configuring in Slave Serial Mode DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 15 R Platform Flash In-System Programmable Configuration PROMS (2) VCCO VCCINT D0 VCCINT VCCO VCCO VCCJ(2) VCCJ D0 Cascaded PROM (PROM 1) First PROM (PROM 0) TMS TCK TCK MODE PINS (1) DOUT Platform Flash PROM TMS DIN MODE PINS(1) DIN (2) Platform Flash PROM TDI (1) (2) (2) TDI 4.7 kΩ VCCJ VCCO VCCINT 4.7 kΩ VCCJ VCCO VCCINT CLK CE CLK CCLK CCLK CE DONE DONE INIT_B INIT_B PROG_B PROG_B CEO CEO OE/RESET OE/RESET CF (3) TDO Xilinx FPGA Slave Serial Xilinx FPGA Master Serial CF (3) TDI TMS TDO TCK GND TDO GND TDI TDO TDI TMS TMS TCK TCK GND Notes: 1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate data sheet. 3 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin. TDO GND ds123_13_100804 Figure 10: Configuring Multiple Devices Master/Slave Serial Mode DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 16 R Platform Flash In-System Programmable Configuration PROMS (2) VCCJ VCCO VCCINT VCCINT D[0:7] 4.7 kΩ 4.7 kΩ VCCO (1) D[0:7] MODE PINS (2) RDWR_B (2) CS_B VCCO VCCJ XCFxxP Platform Flash PROM Xilinx FPGA Master SelectMAP CLK CCLK CE DONE TDI TDI TMS TMS TCK I/O 1KΩ 1KΩ CCLK INIT_B CF (5) PROG_B BUSY (4) BUSY(4) DONE INIT_B PROG_B TCK BUSY TDO TDO GND (3) D[0:7] CEO OE/RESET I/O(3) (1) ...OPTIONAL Slave FPGAs with identical configurations (4) TDI TMS TCK TDO GND Notes: 1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate data sheet. 3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown. 4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet. 5 For the XCFxxP the CF pin is a bidirectional pin. ds123_14_100804 Figure 11: Configuring in Master SelectMAP Mode DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 17 R Platform Flash In-System Programmable Configuration PROMS (2) VCCO VCCJ VCCO VCCINT VCCINT D[0:7] 4.7 kΩ 4.7 kΩ External (5) Oscillator (1) D[0:7] MODE PINS (2) RDWR_B (2) CS_B VCCO VCCJ XCFxxP Platform Flash PROM Xilinx FPGA Slave SelectMAP (5) CCLK CE DONE CLK I/O(3) (1) I/O 1KΩ 1KΩ D[0:7] CEO OE/RESET TDI TDI TMS TMS TCK CCLK INIT_B CF (6) PROG_B BUSY (4) BUSY(4) DONE INIT_B PROG_B TCK BUSY TDO TDO GND (3) ...OPTIONAL Slave FPGAs with identical configurations (4) TDI TMS TCK TDO GND Notes: 1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate data sheet. 3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown. 4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet. 5 If the XCFxxP Platform Flash PROM is not used with CLKOUT enabled to drive CCLK, then an external clock is required for Slave SelectMAP (or Slave Parallel) modes. If CLKOUT is used, then it must be tied to a 4.7KΩ resistor pulled up to VCCO. 6 For the XCFxxP the CF pin is a bidirectional pin. ds123_15_100804 Figure 12: Configuring in Slave SelectMAP Mode DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 18 R Platform Flash In-System Programmable Configuration PROMS VCCINT VCCJ D[0:7] VCCINT (2) VCCO (2) VCCJ VCCO 4.7 kΩ VCCO(2) VCCJ VCCO VCCINT 4.7 kΩ VCCJ VCCO VCCINT (1) D[0:7] D[0:7] MODE PINS CLK CCLK CCLK CE DONE DONE CEO INIT_B INIT_B (5) PROG_B PROG_B (4) BUSY OE/RESET OE/RESET TDI TDI CF (5) CF TMS TMS BUSY(4) BUSY TCK TCK TDO TDO (4) (4) BUSY TDI TDO TMS TCK GND Xilinx FPGA Slave SelectMAP 1KΩ CEO First PROM (PROM 0) (3) I/O CS_B 1KΩ CE CS_B Xilinx FPGA Master SelectMAP I/O(3) RDWR_B I/O 1KΩ XCFxxP Platform Flash PROM CLK MODE PINS (3) RDWR_B 1KΩ Cascaded PROM (PROM 1) (1) D[0:7] I/O(3) (2) XCFxxP Platform Flash PROM (1) (2) TDO GND TDI TDI TMS TMS TCK TCK GND GND TDO Notes: 1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate data sheet. 3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown. 4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet. 5 For the XCFxxP the CF pin is a bidirectional pin. ds123_16_100804 Figure 13: Configuring Multiple Devices with Identical Patterns in Master/Slave SelectMAP Mode DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 19 R Platform Flash In-System Programmable Configuration PROMS VCCJ VCCO VCCINT (2) VCCJ VCCO VCCINT VCCO External (3) Oscillator 4.7 kΩ D0 VCCINT VCCINT D0 VCCO VCCJ (2) VCCJ XCFxxP Platform Flash PROM XCFxxP Platform Flash PROM (3) CLK CE CEO First PROM (PROM 0) OE/RESET TMS TMS TCK TCK DOUT (1) MODE PINS DIN (2) Cascaded PROM (PROM 1) TDI (1) MODE PINS DIN (2) VCCO(2) TDI 4.7 kΩ (1) TDO TDO (3) CCLK CCLK CE DONE DONE CLK CEO INIT_B INIT_B CF PROG_B PROG_B TDO TDI TDI TMS TMS TCK TCK OE/RESET (4) (4) CF Xilinx FPGA Slave Serial Xilinx FPGA Slave Serial TDI TMS TCK EN_EX_SEL EN_EX_SEL REV_SEL[1:0] REV_SEL[1:0] GND GND GND TDO GND EN_EXT_SEL Design Revision Control Logic REV_SEL[1:0] DONE CF / PROG_B 1. For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate data sheet. 3 In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or optionally the CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used, then it must be tied to a 4.7KΩ resistor pulled up to VCCO. 4 For the XCFxxP the CF pin is a bidirectional pin. ds123_17_100804 Figure 14: Configuring Multiple Devices with Design Revisioning in Slave Serial Mode DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 20 R VCCJ Platform Flash In-System Programmable Configuration PROMS VCCO VCCINT VCCJ VCCO VCCINT VCCO (2) VCCINT (2) VCCJ VCCJ XCFxxP Platform Flash PROM Cascaded PROM (PROM 1) CLK (5) CE CEO TCK TCK CF D[0:7] MODE PINS I/O(3) Xilinx FPGA Slave SelectMAP CCLK CCLK DONE DONE INIT_B INIT_B PROG_B PROG_B (3) CEO (6) (4) BUSY I/O CS_B (5) CF (4) Xilinx FPGA Slave SelectMAP (1) RDWR_B CE CLK OE/RESET (6) TDO (1) CS_B First PROM (PROM 0) OE/RESET TDI TMS MODE PINS RDWR_B XCFxxP Platform Flash PROM TMS D[0:7] VCCO (2) TDI D[0:7] (2) VCCO(2) 1KΩ D[0:7] (1) 1KΩ VCCINT 4.7 kΩ 4.7 kΩ External (5) Oscillator BUSY BUSY (4) BUSY (4) TDI TMS TDO TCK EN_EX_SEL EN_EX_SEL REV_SEL[1:0] REV_SEL[1:0] GND TDO TDI TDO TDI TMS TMS TCK TCK TDO GND GND GND EN_EXT_SEL Design REV_SEL[1:0] Revision CF Control DONE Logic PROG_B CS_B[1:0] Notes: 1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate data sheet. 3 RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown. 4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet. 5 In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or optionally the CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used, then it must be tied to a 4.7KΩ resistor pulled up to VCCO. 6 For the XCFxxP the CF pin is a bidirectional pin. ds123_18_100804 Figure 15: Configuring Multiple Devices with Design Revisioning in Slave SelectMAP Mode DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 21 R Platform Flash In-System Programmable Configuration PROMS Reset and Power-On Reset Activation At power up, the device requires the VCCINT power supply to monotonically rise to the nominal operating voltage within the specified VCCINT rise time. If the power supply cannot meet this requirement, then the device might not perform power-on reset properly. During the power-up sequence, OE/RESET is held Low by the PROM. Once the required supplies have reached their respective POR (Power On Reset) thresholds, the OE/RESET release is delayed (TOER minimum) to allow more margin for the power supplies to stabilize before initiating configuration. The OE/RESET pin is connected to an external 4.7kΩ pull-up resistor and also to the target FPGA's INIT pin. For systems utilizing slow-rising power supplies, an additional power monitoring circuit can be used to delay the target configuration until the system power reaches minimum operating voltages by holding the OE/RESET pin Low. When OE/RESET is released, the FPGA’s INIT pin is pulled High allowing the FPGA's configuration sequence to begin. If the power drops below the power-down threshold (VCCPD), the PROM resets and OE/RESET is again held Low until the after the POR threshold is reached. OE/RESET polarity is not programmable. These power-up requirements are shown graphically in Figure 16. For a fully powered Platform Flash PROM, a reset occurs whenever OE/RESET is asserted (Low) or CE is deasserted (High). The address counter is reset, CEO is driven High, and the remaining outputs are placed in a high-impedance state. Notes: 1. The XCFxxS PROM only requires VCCINT to rise above its POR threshold before releasing OE/RESET. 2. The XCFxxP PROM requires both VCCINT to rise above its POR threshold and for VCCO to reach the recommended operating voltage level before releasing OE/RESET. Recommended Operating Range VCCINT Delay or Restart Configuration 200 µs ramp 50 ms ramp VCCPOR VCCPD A slow-ramping VCCINT supply may still be below the minimum operating voltage when OE/RESET is released. In this case, the configuration sequence must be delayed until both VCCINT and VCCO have reached their recommended operating conditions. TOER TOER TIME (ms) TRST ds123_21_103103 Figure 16: Platform Flash PROM Power-Up Requirements I/O Input Voltage Tolerance and Power Sequencing The I/Os on each re-programmable Platform Flash PROM are fully 3.3V-tolerant. This allows 3V CMOS signals to connect directly to the inputs without damage. The core power supply (VCCINT), JTAG pin power supply (VCCJ), output power supply (VCCO), and external 3V CMOS I/O signals can be applied in any order. Additionally, for the XCFxxS PROM only, when VCCO is supplied at 2.5V or 3.3V and VCCINT is supplied at 3.3V, the I/Os are 5V-tolerant. This allows 5V CMOS signals to connect directly to the inputs on a powered XCFxxS PROM without damage. Failure to power the PROM correctly while supplying a 5V input signal may result in damage to the XCFxxS device. DS123 (v2.6) March 14, 2005 Preliminary Product Specification Standby Mode The PROM enters a low-power standby mode whenever CE is deasserted (High). In standby mode, the address counter is reset, CEO is driven High, and the remaining outputs are placed in a high-impedance state regardless of the state of the OE/RESET input. For the device to remain in the low-power standby mode, the JTAG pins TMS, TDI, and TDO must not be pulled Low, and TCK must be stopped (High or Low). When using the FPGA DONE signal to drive the PROM CE pin High to reduce standby power after configuration, an external pull-up resistor should be used. Typically a 330Ω pull-up resistor is used, but refer to the appropriate FPGA data sheet for the recommended DONE pin pull-up value. If the DONE circuit is connected to an LED to indicate FPGA www.xilinx.com 22 R Platform Flash In-System Programmable Configuration PROMS configuration is complete, and is also connected to the PROM CE pin to enable low-power standby mode, then an external buffer should be used to drive the LED circuit to ensure valid transitions on the PROM’s CE pin. If low-power standby mode is not required for the PROM, then the CE pin should be connected to ground. Table 9: Truth Table for XCFxxS PROM Control Inputs Control Inputs OE/RESET CE High Low Low X (1) Outputs Internal Address DATA CEO ICC If address < TC (2) : increment Active High Active If address = High-Z Low Reduced TC (2) : don't change Low Held reset High-Z High Active High Held reset High-Z High Standby Notes: 1. X = don’t care. 2. TC = Terminal Count = highest address value. TC + 1 = address 0. Table 10: Truth Table for XCFxxP PROM Control Inputs Outputs Control Inputs OE/RESET CE CF BUSY(5) Internal Address DATA CEO CLKOUT ICC If address < and address < EA (3) : increment Active High Active Active If address < TC (2) and address = EA (3) : don't change High-Z High High-Z Reduced Else If address = TC (2) : don't change High-Z Low High-Z Reduced Active and Unchanged High Active Active TC (2) High Low High Low High Low High High Unchanged High Low ↑ X (1) Reset (4) Active High Active Active Low Low X X Held reset (4) High-Z High High-Z Active X High X X Held reset (4) High-Z High High-Z Standby Notes: 1. X = don’t care. 2. TC = Terminal Count = highest address value. TC + 1 = address 0. 3. For the XCFxxP with Design Revisioning enabled, EA = end address (last address in the selected design revision). 4. For the XCFxxP with Design Revisioning enabled, Reset = address reset to the beginning address of the selected bank. If Design Revisioning is not enabled, then Reset = address reset to address 0. 5. The BUSY input is only enabled when the XCFxxP is programmed for parallel data output and decompression is not enabled. DC Electrical Characteristics This data sheet is a Preliminary data sheet. The DC characteristics are based on characterization rather than simulation. Further characteristic changes are not expected. •Absolute Maximum Ratings, page 24 •Supply Voltage Requirements for Power-On Reset and Power-Down, page 24 •Recommended Operating Conditions, page 25 •Quality and Reliability Characteristics, page 25 •DC Characteristics Over Operating Conditions, page 26 DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 23 R Platform Flash In-System Programmable Configuration PROMS AC Electrical Characteristics This data sheet is a Preliminary data sheet. The AC characteristics are based on characterization rather than simulation. Further characteristic changes are not expected. •AC Characteristics Over Operating Conditions, page 28 •AC Characteristics Over Operating Conditions When Cascading, page 32 Absolute Maximum Ratings Symbol Description XCF01S, XCF02S, XCF04S XCF08P, XCF16P, XCF32P Units VCCINT Internal supply voltage relative to GND –0.5 to +4.0 –0.5 to +2.7 V VCCO I/O supply voltage relative to GND –0.5 to +4.0 –0.5 to +4.0 V VCCJ JTAG I/O supply voltage relative to GND –0.5 to +4.0 –0.5 to +4.0 V –0.5 to +3.6 V Input voltage with respect to GND VCCO < 2.5V –0.5 to +3.6 VIN VCCO ≥ 2.5V –0.5 to +5.5 –0.5 to +3.6 V –0.5 to +3.6 V Voltage applied to High-Z output VCCO < 2.5V –0.5 to +3.6 VTS VCCO ≥ 2.5V –0.5 to +5.5 –0.5 to +3.6 V TSTG Storage temperature (ambient) –65 to +150 –65 to +150 °C TJ Junction temperature +125 +125 °C Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins can undershoot to –2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability. 3. For soldering guidelines, see the information on "Packaging and Thermal Characteristics" at www.xilinx.com. Supply Voltage Requirements for Power-On Reset and Power-Down XCF01S, XCF02S, XCF04S Symbol Description TVCC VCCINT rise time from 0V to nominal voltage (2) VCCPOR POR threshold for the VCCINT supply POR (3) TOER OE/RESET release delay following VCCPD Power-down threshold for VCCINT supply TRST Time required to trigger a device reset when the VCCINT supply drops below the maximum VCCPD threshold XCF08P, XCF16P, XCF32P Min Max Min Max Units 0.2 50 0.2 50 ms 1 - 0.5 - V 0.5 3 0.5 30 ms - 1 - 0.5 V 10 - 10 - ms Notes: 1. VCCINT, VCCO, and VCCJ supplies may be applied in any order. 2. At power up, the device requires the VCCINT power supply to monotonically rise to the nominal operating voltage within the specified TVCC rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See Figure 16, page 22. 3. If the VCCINT and VCCO supplies do not reach their respective recommended operating conditions before the OE/RESET pin is released, then the configuration data from the PROM will not be available at the recommended threshold levels. The configuration sequence must be delayed until both VCCINT and VCCO have reached their recommended operating conditions. DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 24 R Platform Flash In-System Programmable Configuration PROMS Recommended Operating Conditions Symbol VCCINT VCCO VCCJ VIL VIH XCF01S, XCF02S, XCF04S XCF08P, XCF16P, XCF32P Min Typ Max Min Typ Max Units 3.0 3.3 3.6 1.65 1.8 2.0 V 3.3V Operation 3.0 3.3 3.6 3.0 3.3 3.6 V 2.5V Operation 2.3 2.5 2.7 2.3 2.5 2.7 V 1.8V Operation 1.7 1.8 1.9 1.7 1.8 1.9 V 1.5V Operation - - - TBD 1.5 TBD V 3.3V Operation 3.0 3.3 3.6 3.0 3.3 3.6 V 2.5V Operation 2.3 2.5 2.7 2.3 2.5 2.7 V 3.3V Operation 0 - 0.8 0 - 0.8 V 2.5V Operation 0 - 0.8 0 - 0.8 V 1.8V Operation - - 20% VCCO - - 20% VCCO V 1.5V Operation - - - 0 - TBD V 3.3V Operation 2.0 - 5.5 2.0 - 3.6 V 2.5V Operation 1.7 - 5.5 1.7 - 3.6 V 1.8V Operation 70% VCCO - 3.6 70% VCCO - 3.6 V 1.5V Operation - - - TBD - 3.6 V time(1) - - 500 - - 500 ns 0 - VCCO 0 - VCCO V –40 - 85 –40 - 85 °C Min Max Units 20 - Years Description Internal voltage supply Supply voltage for output drivers Supply voltage for JTAG output drivers Low-level input voltage High-level input voltage TIN Input signal transition VO Output voltage TA Operating ambient temperature Notes: 1. Input signal transition time measured between 10% VCCO and 90% VCCO . Quality and Reliability Characteristics Symbol Description TDR Data retention NPE Program/erase cycles (Endurance) 20,000 - Cycles VESD Electrostatic discharge (ESD) 2,000 - Volts DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 25 R Platform Flash In-System Programmable Configuration PROMS DC Characteristics Over Operating Conditions XCF01S, XCF02S, XCF04S Symbol Test Conditions Min Max Test Conditions Min Max Units High-level output voltage for 3.3V outputs IOH = –4 mA 2.4 - IOH = –4 mA 2.4 - V High-level output voltage for 2.5V outputs IOH = –500 µA VCCO – 0.4 - IOH = –500 µA VCCO – 0.4 - V High-level output voltage for 1.8V outputs IOH = –50 µA VCCO – 0.4 - IOH = –50 µA VCCO – 0.4 - V High-level output voltage for 1.5V outputs - - - IOH = TBD TBD - V Low-level output voltage for 3.3V outputs IOL = 4 mA - 0.4 IOL = 4 mA - 0.4 V Low-level output voltage for 2.5V outputs IOL = 500 µA - 0.4 IOL = 500 µA - 0.4 V Low-level output voltage for 1.8V outputs IOL = 50 µA - 0.4 IOL = 50 µA - 0.4 V Low-level output voltage for 1.5V outputs - - - IOL = TBD - TBD V Internal voltage supply current, active mode 33 MHz - 10 33 MHz - 10 mA Output driver supply current, active serial mode 33 MHz - 10 33 MHz - 10 mA - - - 33 MHz - 40 mA Description VOH VOL ICCINT ICCO (1) XCF08P, XCF16P, XCF32P Output driver supply current, active parallel mode ICCJ JTAG supply current, active mode Note (2) - 5 Note (2) - 5 mA ICCINTS Internal voltage supply current, standby mode Note (3) - 5 Note (3) - 5 mA ICCOS Output driver supply current, standby mode Note (3) - 1 Note (3) - 1 mA ICCJS JTAG supply current, standby mode Note (3) - 1 Note (3) - 1 mA IILJ JTAG pins TMS, TDI, and TDO pull-up current VCCJ = max VIN = GND - 100 VCCJ = max VIN = GND - 100 µA –10 10 µA –10 10 µA - 100 µA -100 - µA VCCINT = max VCCINT = max IIL VCCO = max Input leakage current IIH Input and output High-Z leakage current IILP Source current through internal pull-ups on EN_EXT_SEL, REV_SEL0, REV_SEL1 –10 10 VCCO = max VIN = GND or VCCO VIN = GND or VCCO VCCINT = max VCCINT = max VCCO = max –10 10 VIN = GND or VCCO VCCO = max VIN = GND or VCCO VCCINT = max - - - VCCO = max VIN = GND or VCCO VCCINT = max IIHP Sink current through internal pull-down on BUSY DS123 (v2.6) March 14, 2005 Preliminary Product Specification - - - VCCO = max VIN = GND or VCCO www.xilinx.com 26 R Platform Flash In-System Programmable Configuration PROMS XCF01S, XCF02S, XCF04S Symbol Description Test Conditions XCF08P, XCF16P, XCF32P Min Max Test Conditions Min Max Units CIN Input capacitance VIN = GND f = 1.0 MHz - 8 VIN = GND f = 1.0 MHz - 8 pF COUT Output capacitance VIN = GND f = 1.0 MHz - 14 VIN = GND f = 1.0 MHz - 14 pF Notes: 1. Output driver supply current specification based on no load conditions. 2. TDI/TMS/TCK non-static (active). 3. CE High, OE Low, and TMS/TDI/TCK static. DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 27 R Platform Flash In-System Programmable Configuration PROMS AC Characteristics Over Operating Conditions TSCE CE THCE THOE OE/RESET TLC THC TCYC CLK TCLKO CLKOUT (optional) TCEC TSB TOEC BUSY (optional) TOE THB TOH TCAC TCDD TCOH TDF TCE DATA TOH CF EN_EXT_SEL TSXT THXT TSRV REV_SEL[1:0] THRV ds123_22_110403 XCF01S, XCF02S, XCF04S Min Max Min Max Units - 10 - 25 ns OE/RESET to data delay (6) when VCCO = 1.8V - 30 - 25 ns CE to data delay (5) when VCCO = 3.3V or 2.5V - 15 - 25 ns - 30 - 25 ns CLK to data delay (7) when VCCO = 3.3V or 2.5V - 15 - 25 ns CLK to data delay (7) when VCCO = 1.8V - 30 - 25 ns Data hold from CE, OE/RESET, or CLK when VCCO = 3.3V or 2.5V 0 - 5 - ns Data hold from CE, OE/RESET, or CLK when VCCO = 1.8V 0 - 5 - ns CE or OE/RESET to data float delay (2) when VCCO = 3.3V or 2.5V - 25 - 45 ns CE or OE/RESET to data float delay (2) when VCCO = 1.8V - 30 - 45 ns 30 - 25 - ns 67 - 25 - ns Clock period (7) (parallel mode) when VCCO = 3.3V or 2.5V - - 30 - ns Clock period (7) (parallel mode) when VCCO = 1.8V - - 30 - ns Symbol Description OE/RESET to data TOE TCE TCAC TOH TDF CE to data delay (5) delay (6) when VCCO = 3.3V or 2.5V when VCCO = 1.8V Clock period (7) (serial mode) when VCCO = 3.3V or 2.5V Clock TCYC XCF08P, XCF16P, XCF32P period (7) (serial mode) when VCCO = 1.8V DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 28 R Platform Flash In-System Programmable Configuration PROMS XCF01S, XCF02S, XCF04S Min Max Min Max Units 10 - 12 - ns 15 - 12 - ns 10 - 12 - ns CLK High time (3) when VCCO = 1.8V 15 - 12 - ns CE setup time to CLK (guarantees proper counting) (3) when VCCO = 3.3V or 2.5V 20 - 30 - ns CE setup time to CLK (guarantees proper counting) (3) when VCCO = 1.8V 30 30 - ns CE hold time (guarantees counters are reset) (5) when VCCO = 3.3V or 2.5V 250 - 2000 - ns CE hold time (guarantees counters are reset) (5) when VCCO = 1.8V 250 - 2000 - ns OE/RESET hold time (guarantees counters are reset) (6) when VCCO = 3.3V or 2.5V 250 - 2000 - ns OE/RESET hold time (guarantees counters are reset) (6) when VCCO = 1.8V 250 - 2000 - ns BUSY setup time to CLK when VCCO = 3.3V or 2.5V - - 12 - ns BUSY setup time to CLK when VCCO = 1.8V - - 12 - ns BUSY hold time to CLK when VCCO = 3.3V or 2.5V - - 8 - ns BUSY hold time to CLK when VCCO = 1.8V - - 8 - ns CLK input to CLKOUT output delay when VCCO = 3.3V or 2.5V - - - 35 ns CLK input to CLKOUT output delay when VCCO = 1.8V - - - 35 ns CLK input to CLKOUT output delay when VCCO = 3.3V or 2.5V with decompression (12) - - - 35 ns CLK input to CLKOUT output delay when VCCO = 1.8V with decompression (12) - - - 35 ns CE to CLKOUT delay (8) with CLKOUT sourced from internal oscillator, when VCCO = 3.3V or 2.5V - - 0 1 µs CE to CLKOUT delay (8) with CLKOUT sourced from internal oscillator, when VCCO = 1.8V - - 0 1 µs CE to CLKOUT delay (8) with CLKOUT sourced from external CLK input, when VCCO = 3.3V or 2.5V - - 0 2 CLK cycles - CE to CLKOUT delay (8) with CLKOUT sourced from external CLK input, when VCCO = 1.8V - - 0 2 CLK cycles - OE/RESET to CLKOUT delay (8) with CLKOUT sourced from internal oscillator, when VCCO = 3.3V or 2.5V - - 0 1 µs OE/RESET to CLKOUT delay (8) with CLKOUT sourced from internal oscillator, when VCCO = 1.8V - - 0 1 µs OE/RESET to CLKOUT delay (8) with CLKOUT sourced from external CLK input , when VCCO = 3.3V or 2.5V 0 2 CLK cycles - OE/RESET to CLKOUT delay (8) with CLKOUT sourced from external CLK input, when VCCO = 1.8V 0 2 CLK cycles - Symbol Description CLK Low TLC TSCE THCE THOE TSB THB TCLKO TCEC TOEC time (3) when VCCO = 3.3V or 2.5V CLK Low time (3) when VCCO = 1.8V CLK High THC XCF08P, XCF16P, XCF32P time (3) when VCCO = 3.3V or 2.5V DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 29 R Platform Flash In-System Programmable Configuration PROMS XCF01S, XCF02S, XCF04S Min Max Min Max Units - - - 22 ns CLKOUT to data delay when VCCO = 1.8V(9) - - - 22 ns Data setup time to CLKOUT when VCCO = 3.3V or 2.5V with decompression (9)(12) - - 5 ns Data setup time to CLKOUT when VCCO = 1.8V with decompression (9)(12) - - 5 ns Data hold from CLKOUT when VCCO = 3.3V or 2.5V - - 3 - ns Data hold from CLKOUT when VCCO = 1.8V - - 3 - ns Data hold from CLKOUT when VCCO = 3.3V or 2.5V with decompression (12) - - 3 - ns Data hold from CLKOUT when VCCO = 1.8V with decompression (12) - - 3 - ns EN_EXT_SEL setup time to CF (rising edge) when VCCO = 3.3V or 2.5V - - 300 - ns EN_EXT_SEL setup time to CF (rising edge) when VCCO = 1.8V - - 300 - ns EN_EXT_SEL hold time from CF (rising edge) when VCCO = 3.3V or 2.5V - - 300 - ns EN_EXT_SEL hold time from CF (rising edge) when VCCO = 1.8V - - 300 - ns REV_SEL setup time to CF (rising edge) when VCCO = 3.3V or 2.5V - - 300 - ns REV_SEL setup time to CF (rising edge) when VCCO = 1.8V - - 300 - ns REV_SEL hold time from CF (rising edge) when VCCO = 3.3V or 2.5V - - 300 - ns REV_SEL hold time from CF (rising edge) when VCCO = 1.8V - - 300 - ns CLKOUT default (fast) frequency (10) - - 25 50 MHz CLKOUT default (fast) frequency with decompression (12) - - 12.5 25 MHz Symbol TCDD TDDC TCOH TSXT THXT TSRV THRV FF XCF08P, XCF16P, XCF32P Description CLKOUT to data delay when VCCO = 3.3V or DS123 (v2.6) March 14, 2005 Preliminary Product Specification 2.5V(9) www.xilinx.com 30 R Platform Flash In-System Programmable Configuration PROMS XCF01S, XCF02S, XCF04S Symbol Description CLKOUT alternate (slower) FS frequency (11) CLKOUT alternate (slower) frequency with decompression (12) XCF08P, XCF16P, XCF32P Min Max Min Max Units - - 12.5 25 MHz - - 6 12.5 MHz Notes: 1. AC test load = 50 pF for XCF01S/XCF02S/XCF04S; 30pF for XCF08P/XCF16P/XCF32P. 2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady-state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 5. If THCE High < 2 µs, TCE = 2 µs. 6. If THOE Low < 2 µs, TOE = 2 µs. 7. This is the minimum possible TCYC. Actual TCYC = TCAC + FPGA Data setup time. Example: With the XCF32P in serial mode with VCCO at 3.3V, if FPGA Data setup time = 15 ns, then the actual TCYC = 25 ns +15 ns = 40 ns. 8. The delay before the enabled CLKOUT signal begins clocking data out of the device is dependent on the clocking configuration. The delay before CLKOUT is enabled will increase if decompression is enabled. 9. Slower CLK frequency option may be required to meet the FPGA data sheet setup time. 10. Typical CLKOUT default (fast) period = 25 ns (40 MHz) 11. Typical CLKOUT alternate (slower) period = 50 ns (20 MHz) 12. When decompression is enabled, the CLKOUT signal becomes a controlled clock output. When decompressed data is available, CLKOUT will toggle at ½ the source clock frequency (either ½ the selected internal clock frequency or ½ the external CLKIN frequency). When decompressed data is not available, CLKOUT remains High. DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 31 R Platform Flash In-System Programmable Configuration PROMS AC Characteristics Over Operating Conditions When Cascading OE/RESET CE CLK CLKOUT (optional) TCDF TCODF DATA Last Bit First Bit TOCE TOOE TOCK TCOCE CEO ds123_23_102203 XCF01S, XCF02S, XCF04S Min Max Min Max Units CLK to output float delay (2,3) when VCCO = 2.5V or 3.3V - 25 - 20 ns CLK to output float delay (2,3) when VCCO = 1.8V - 35 - 20 ns CLK to CEO delay (3,5) when VCCO = 2.5V or 3.3V - 20 - 20 ns - 35 - 20 ns - 20 - 80 ns - 35 - 80 ns - 20 - 80 ns - 35 - 80 ns CLKOUT to CEO delay when VCCO = 2.5V or 3.3V - - - 20 ns CLKOUT to CEO delay when VCCO = 1.8V - - - 20 ns CLKOUT to output float delay when VCCO = 2.5V or 3.3V - - - 25 ns CLKOUT to output float delay when VCCO = 1.8V - - - 25 ns Symbol TCDF TOCK TOCE TOOE TCOCE TCODF XCF08P, XCF16P, XCF32P Description CLK to CEO delay (3,5) when VCCO = 1.8V CE to CEO delay (3,6) when VCCO = 2.5V or 3.3V CE to CEO delay (3,6) when VCCO = 1.8V OE/RESET to CEO delay (3) when VCCO = 2.5V or 3.3V OE/RESET to CEO delay (3) when VCCO = 1.8V Notes: 1. AC test load = 50 pF for XCF01S/XCF02S/XCF04S; 30 pF for XCF08P/XCF16P/XCF32P. 2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 5. For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins are set to persist as configuration pins, the minimum period is increased based on the CLK to CEO and CE to data propagation delays: - TCYC minimum = TOCK + TCE + FPGA Data setup time. - TCAC maximum = TOCK + TCE 6. For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins become general I/O pins after configuration; to allow for the disable to propagate to the cascaded PROMs and to avoid contention on the data lines following configuration, the minimum period is increased based on the CE to CEO and CE to data propagation delays: - TCYC minimum = TOCE + TCE - TCAC maximum = TOCK + TCE DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 32 R Platform Flash In-System Programmable Configuration PROMS Pinouts and Pin Descriptions The XCFxxS Platform Flash PROM is available in the VO20 and VOG20 packages. The XCFxxP Platform Flash PROM is available in the VO48, VOG48, FS48, and FSG48 packages. This section includes: • • • • • • Table 11, XCFxxS Pin Names and Descriptions, page 33 Figure 17, VO20/VOG20 Pinout Diagram (Top View) with Pin Names, page 34 Table 12, XCFxxP Pin Names and Descriptions, page 35 Figure 18, VO48/VOG48 Pinout Diagram (Top View) with Pin Names, page 36 Table 13, FS48/FSG48 Pin Number/Name Reference, page 38 Figure 19, FS48/FSG48 Pinout Diagram (Top View), page 38 Notes: 1. VO20/VOG20 denotes a 20-pin (TSSOP) Plastic Thin Shrink Small Outline Package 2. VO48/VOG48 denotes a 48-pin (TSOP) Plastic Thin Small Outline Package. 3. FS48/FSG48 denotes a 48-pin (TFBGA) Plastic Thin Fine Pitch Ball Grid Array (0.8 mm pitch). XCFxxS Pinouts and Pin Descriptions Table 11 provides a list of the pin names and descriptions for the XCFxxS 20-pin VO20/VOG20 package. Table 11: XCFxxS Pin Names and Descriptions Pin Name Boundary Scan Order Boundary Scan Function 4 Data Out 3 Output Enable 0 Data In 20 Data In 19 Data Out 18 Output Enable 15 Data In 22 Data Out 21 Output Enable 12 Data Out D0 CLK OE/RESET CE CF CEO 11 Output Enable TMS Mode Select TCK Clock DS123 (v2.6) March 14, 2005 Preliminary Product Specification Pin Description 20-pin TSSOP (VO20/VOG20) D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. The D0 output is set to a high-impedance state during ISPEN (when not clamped). 1 Configuration Clock Input. Each rising edge on the CLK input increments the internal address counter if the CLK input is selected, CE is Low, and OE/RESET is High. 3 Output Enable/Reset (Open-Drain I/O). When Low, this input holds the address counter reset and the DATA output is in a high-impedance state. This is a bidirectional open-drain pin that is held Low while the PROM is reset. Polarity is not programmable. 8 Chip Enable Input. When CE is High, the device is put into low-power standby mode, the address counter is reset, and the DATA pins are put in a high-impedance state. 10 Configuration Pulse (Open-Drain Output). Allows JTAG CONFIG instruction to initiate FPGA configuration without powering down FPGA. This is an open-drain output that is pulsed Low by the JTAG CONFIG command. 7 Chip Enable Output. Chip Enable Output (CEO) is connected to the CE input of the next PROM in the chain. This output is Low when CE is Low and OE/RESET input is High, AND the internal address counter has been incremented beyond its Terminal Count (TC) value. CEO returns to High when OE/RESET goes Low or CE goes High. 13 JTAG Mode Select Input. The state of TMS on the rising edge of TCK determines the state transitions at the Test Access Port (TAP) controller. TMS has an internal 50KΩ resistive pull-up to VCCJ to provide a logic "1" to the device if the pin is not driven. 5 JTAG Clock Input. This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics. 6 www.xilinx.com 33 R Platform Flash In-System Programmable Configuration PROMS Table 11: XCFxxS Pin Names and Descriptions (Continued) Pin Name Boundary Scan Order Boundary Scan Function Pin Description 20-pin TSSOP (VO20/VOG20) Data In JTAG Serial Data Input. This pin is the serial input to all JTAG instruction and data registers. TDI has an internal 50KΩ resistive pull-up to VCCJ to provide a logic "1" to the device if the pin is not driven. 4 Data Out JTAG Serial Data Output. This pin is the serial output for all JTAG instruction and data registers. TDO has an internal 50KΩ resistive pull-up to VCCJ to provide a logic "1" to the system if the pin is not driven. 17 VCCINT +3.3V Supply. Positive 3.3V supply voltage for internal logic. 18 VCCO +3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V supply voltage connected to the output voltage drivers and input buffers. 19 VCCJ +3.3V, 2.5V, or 1.8V JTAG I/O Supply. Positive 3.3V, 2.5V, or 1.8V supply voltage connected to the TDO output voltage driver and TCK, TMS, and TDI input buffers. 20 GND Ground 11 DNC Do not connect. (These pins must be left unconnected.) TDI TDO 2, 9, 12, 14, 15, 16 XCFxxS Pinout Diagram D0 1 20 VCCJ (DNC) 2 19 VCCO CLK 3 18 VCCINT TDI 4 17 TDO TMS 5 TCK 6 CF VO20/VOG20 16 Top View (DNC) 15 (DNC) 7 14 (DNC) OE/RESET 8 13 CEO (DNC) 9 12 (DNC) 10 11 CE GND ds123_02_071304 Figure 17: VO20/VOG20 Pinout Diagram (Top View) with Pin Names DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 34 R Platform Flash In-System Programmable Configuration PROMS XCFxxP Pinouts and Pin Descriptions Table 12 provides a list of the pin names and descriptions for the XCFxxP 48-pin VO48/VOG48 and 48-pin FS48/FSG48 packages. Table 12: XCFxxP Pin Names and Descriptions Pin Name Boundary Scan Order Boundary Scan Function 28 Data Out 27 Output Enable 26 Data Out 25 Output Enable 24 Data Out 23 Output Enable 22 Data Out 21 Output Enable 20 Data Out 19 Output Enable 18 Data Out 17 Output Enable 16 Data Out 15 Output Enable 14 Data Out 13 Output Enable 48-pin TSOP (VO48/ VOG48) 48-pin TFBGA (FS48/ FSG48) 28 H6 29 H5 32 E5 33 D5 43 C5 44 B5 47 A5 48 A6 Configuration Clock Input. An internal programmable control bit selects between the internal oscillator and the CLK input pin as the clock source to control the configuration sequence. Each rising edge on the CLK input increments the internal address counter if the CLK input is selected, CE is Low, OE/RESET is High, BUSY is Low (parallel mode only), and CF is High. 12 B3 Output Enable/Reset (Open-Drain I/O). When Low, this input holds the address counter reset and the DATA and CLKOUT outputs are placed in a high-impedance state. This is a bidirectional open-drain pin that is held Low while the PROM is reset. Polarity is not programmable. 11 A3 Chip Enable Input. When CE is High, the device is put into low-power standby mode, the address counter is reset, and the DATA and CLKOUT outputs are placed in a high-impedance state. 13 B4 Configuration Pulse (Open-Drain I/O). As an output, this pin allows the JTAG CONFIG instruction to initiate FPGA configuration without powering down the FPGA. This is an open-drain signal that is pulsed Low by the JTAG CONFIG command. As an input, on the rising edge of CF, the current design revision selection is sampled and the internal address counter is reset to the start address for the selected revision. If unused, the CF pin should be pulled High using an external 4.7KΩ pull-up to VCCO. 6 D1 Pin Description D0 D1 D2 D3 D4 D5 D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. D0-D7 are the DATA output pins to provide parallel data for configuring a Xilinx FPGA in SelectMap (parallel) mode. The D0 output is set to a high-impedance state during ISPEN (when not clamped). The D1-D7 outputs are set to a high-impedance state during ISPEN (when not clamped) and when serial mode is selected for configuration. The D1-D7 pins can be left unconnected when the PROM is used in serial mode. D6 D7 CLK OE/RESET CE CF 01 Data In 04 Data In 03 Data Out 02 Output Enable 00 Data In 11 Data In 10 Data Out 09 Output Enable DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 35 R Platform Flash In-System Programmable Configuration PROMS Table 12: XCFxxP Pin Names and Descriptions (Continued) Pin Name Boundary Scan Order Boundary Scan Function 06 Data Out CEO 05 Output Enable EN_EXT_SEL 31 Data In REV_SEL0 30 Data In REV_SEL1 29 Data In BUSY 12 08 Data In Data Out CLKOUT 07 Output Enable TMS Mode Select TCK Clock TDI DS123 (v2.6) March 14, 2005 Preliminary Product Specification Data In 48-pin TSOP (VO48/ VOG48) 48-pin TFBGA (FS48/ FSG48) Chip Enable Output. Chip Enable Output (CEO) is connected to the CE input of the next PROM in the chain. This output is Low when CE is Low and OE/RESET input is High, AND the internal address counter has been incremented beyond its Terminal Count (TC) value. CEO returns to High when OE/RESET goes Low or CE goes High. 10 D2 Enable External Selection Input. When this pin is Low, design revision selection is controlled by the Revision Select pins. When this pin is High, design revision selection is controlled by the internal programmable Revision Select control bits. EN_EXT_SEL has an internal 50KΩ resistive pull-up to VCCO to provide a logic "1" to the device if the pin is not driven. 25 H4 26 G3 27 G4 Busy Input. The BUSY input is enabled when parallel mode is selected for configuration. When BUSY is High, the internal address counter stops incrementing and the current data remains on the data pins. On the first rising edge of CLK after BUSY transitions from High to Low, the data for the next address is driven on the data pins. When serial mode or decompression is enabled during device programming, the BUSY input is disabled. BUSY has an internal 50KΩ resistive pull-down to GND to provide a logic "0" to the device if the pin is not driven. 5 C1 Configuration Clock Output. An internal Programmable control bit enables the CLKOUT signal, which is sourced from either the internal oscillator or the CLK input pin. Each rising edge of the selected clock source increments the internal address counter if data is available, CE is Low, and OE/RESET is High. Output data is available on the rising edge of CLKOUT. CLKOUT is disabled if CE is High or OE/RESET is Low. If decompression is enabled, CLKOUT is disabled when decompressed data is not ready. When CLKOUT is disabled, the CLKOUT pin is put into a high-Z state. If CLKOUT is used, then it must be pulled High externally using a 4.7KΩ pull-up to VCCO. 9 C2 JTAG Mode Select Input. The state of TMS on the rising edge of TCK determines the state transitions at the Test Access Port (TAP) controller. TMS has an internal 50KΩ resistive pull-up to VCCJ to provide a logic "1" to the device if the pin is not driven. 21 E2 JTAG Clock Input. This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics. 20 H3 JTAG Serial Data Input. This pin is the serial input to all JTAG instruction and data registers. TDI has an internal 50KΩ resistive pull-up to VCCJ to provide a logic "1" to the device if the pin is not driven. 19 G1 Pin Description Revision Select[1:0] Inputs. When the EN_EXT_SEL is Low, the Revision Select pins are used to select the design revision to be enabled, overriding the internal programmable Revision Select control bits. The Revision Select[1:0] inputs have an internal 50KΩ resistive pull-up to VCCO to provide a logic "1" to the device if the pins are not driven. www.xilinx.com 36 R Platform Flash In-System Programmable Configuration PROMS Table 12: XCFxxP Pin Names and Descriptions (Continued) 48-pin TSOP (VO48/ VOG48) 48-pin TFBGA (FS48/ FSG48) JTAG Serial Data Output. This pin is the serial output for all JTAG instruction and data registers. TDO has an internal 50KΩ resistive pull-up to VCCJ to provide a logic "1" to the system if the pin is not driven. 22 E6 VCCINT +1.8V Supply. Positive 1.8V supply voltage for internal logic. 4, 15, 34 B1, E1, G6 VCCO +3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V supply voltage connected to the output voltage drivers and input buffers. 8, 30, 38, 45 B2, C6, D6, G5 VCCJ +3.3V, 2.5V, or 1.8V JTAG I/O Supply. Positive 3.3V, 2.5V, or 1.8V supply voltage connected to the TDO output voltage driver and TCK, TMS, and TDI input buffers. 24 H2 Ground 2, 7, 17, 23, 31, 36, 46 A1, A2, B6, F1, F5, F6, H1 Do Not Connect. (These pins must be left unconnected.) 1, 3, 14, 16, 18, 35, 37, 39, 40, 41, 42 A4, C3, C4, D3, D4, E3, E4, F2, F3, F4, G2 Pin Name Boundary Scan Order TDO Boundary Scan Function Data Out GND DNC Pin Description XCFxxP Pinout Diagrams DNC GND DNC VCCINT BUSY CF GND VCCO CLKOUT CEO OE/RESET CLK CE DNC VCCINT DNC GND DNC TDI TCK TMS TDO GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VO48/VOG48 Top View 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 D7 D6 VCCJ GND VCCO D5 D4 DNC DNC DNC DNC VCCO DNC GND DNC VCCINT D3 D2 GND VCCO D1 D0 REV_SEL1 REV_SEL0 EN_EXT_SEL Figure 18: VO48/VOG48 Pinout Diagram (Top View) with Pin Names DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 37 R Platform Flash In-System Programmable Configuration PROMS Table 13: FS48/FSG48 Pin Number/Name Reference Table 13: FS48/FSG48 Pin Number/Name Reference Pin Name Pin Number Pin Name Pin Number Pin Name E1 VCCINT D1 CF H1 GND GND E2 TMS D2 CEO H2 VCCJ A3 OE/RESET E3 DNC D3 DNC H3 TCK A4 DNC E4 DNC D4 DNC H4 EN_EXT_SEL A5 D6 E5 D2 D5 D3 H5 D1 A6 D7 E6 TDO D6 VCCO H6 D0 B1 VCCINT F1 GND B2 VCCO F2 DNC B3 CLK F3 DNC B4 CE F4 DNC B5 D5 F5 GND B6 GND F6 GND A C1 BUSY G1 TDI B C2 CLKOUT G2 DNC C C3 DNC G3 REV_SEL0 D C4 DNC G4 REV_SEL1 E C5 D4 G5 VCCO C6 VCCO G6 VCCINT Pin Number Pin Name Pin Number A1 GND A2 FS48/FSG48 Top View 1 2 3 4 5 6 F G H ds121_01_071604 DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 38 R Platform Flash In-System Programmable Configuration PROMS Ordering Information XCF04S VO20 C Device Number XCF01S XCF02S XCF04S Operating Range/Processing C = (TA = –40°C to +85°C) Package Type VO20 = 20-pin TSSOP Package VOG20 = 20-pin TSSOP Package, Pb-free XCF32P FS48 C Device Number XCF08P XCF16P XCF32P Operating Range/Processing C = (TA = –40°C to +85°C) Package Type VO48 = 48-pin TSOP Package VOG48 = 48-pin TSOP Package, Pb-free FS48 = 48-pin TFBGA Package FSG48 = 48-pin TFBGA Package, Pb-free Valid Ordering Combinations XCF01SVO20 C XCF08PVO48 C XCF08PFS48 C XCF01SVOG20 C XCF08PVOG48 C XCF08PFSG48 C XCF02SVO20 C XCF16PVO48 C XCF16PFS48 C XCF02SVOG20 C XCF16PVOG48 C XCF16PFSG48 C XCF04SVO20 C XCF32PVO48 C XCF32PFS48 C XCF04SVOG20 C XCF32PVOG48 C XCF32PFSG48 C Marking Information XCF04S-V Device Number XCF01S XCF02S XCF04S XCF08P XCF16P XCF32P Operating Range/Processing C = (TA = –40°C to +85°C) Package Type V = 20-pin TSSOP Package (VO20) VG = 20-pin TSSOP Package, Pb-free (VOG20) VO48 = 48-pin TSOP Package (VO48) VOG48 = 48-pin TSOP Package, Pb-free (VOG48) F48 = 48-pin TFBGA Package (FS48) FG48 = 48-pin TFBGA Package, Pb-free (FSG48) DS123 (v2.6) March 14, 2005 Preliminary Product Specification www.xilinx.com 39 R Platform Flash In-System Programmable Configuration PROMS Revision History The following table shows the revision history for this document. Date Version Revision 04/29/03 1.0 Xilinx Initial Release. 06/03/03 1.1 Made edits to all pages. 11/05/03 2.0 Major revision. 11/18/03 2.1 Pinout corrections as follows: • Table 12: - For VO48 package, removed 38 from VCCINT and added it to VCCO. - For FS48 package, removed pin D6 from VCCINT and added it to VCCO. • Table 13 (FS48 package): - For pin D6, changed name from VCCINT to VCCO. - For pin A4, changed name from GND to DNC. • Figure 18 (VO48 package): For pin 38, changed name from VCCINT to VCCO. 12/15/03 2.2 • • 05/07/04 2.3 • • • • • • • • • • • • DS123 (v2.6) March 14, 2005 Preliminary Product Specification Added specification (4.7kΩ) for recommended pull-up resistor on OE/RESET pin to section Reset and Power-On Reset Activation, page 22. Added paragraph to section Standby Mode, page 22, concerning use of a pull-up resistor and/or buffer on the DONE pin. Section Features, page 1: Added package styles and 33 MHz configuration speed limit to itemized features. Section Description, page 1 and following: Added state conditions for CF and BUSY to the descriptive text. Table 2, page 3: Updated Virtex-II configuration bitstream sizes. Section Design Revisioning, page 9: Rewritten. Section PROM to FPGA Configuration Mode and Connections Summary, page 10 and following, five instances: Added instruction to tie CF High if it is not tied to the FPGA’s PROG_B (PROGRAM) input. Figure 8, page 14, through Figure 15, page 21: Added footnote indicating the directionality of the CF pin in each configuration. Section I/O Input Voltage Tolerance and Power Sequencing, page 22: Rewritten. Table 10, page 23: Added CF column to truth table, and added an additional row to document the Low state of CF. Section Absolute Maximum Ratings, page 24: Revised VIN and VTS for ’P’ devices. Section Supply Voltage Requirements for Power-On Reset and Power-Down, page 24: - Revised footnote callout number on TOER from Footnote (4) to Footnote (3). - Added Footnote (2) callout to TVCC. Section Recommended Operating Conditions, page 25: - Added Typical (Typ) parameter columns and parameters for VCCINT and VCCO/VCCJ. - Added 1.5V operation parameter row to VIL and VIH, ’P’ devices. - Revised VIH Min, 2.5V operation, from 2.0V to 1.7V. - Added parameter row TIN and Max parameters (Continued on next page) www.xilinx.com 40 R 05/07/04 (cont’d) Platform Flash In-System Programmable Configuration PROMS 2.3 (cont’d) • • • 07/20/04 2.4 • Table 12, page 35: - Added additional state conditions to CLK description. - Added function of resetting the internal address counter to CF description. • • Added Pb-free package options VOG20, FSG48, and VOG48. Figure 8, page 14, and Figure 9, page 15: Corrected connection name for FPGA DOUT (OPTIONAL Daisy-chained Slave FPGAs with different configurations) from DOUT to DIN. Section Absolute Maximum Ratings, page 24: Removed parameter TSOL from table. (TSOL information can be found in Package User Guide.) • 10/18/04 2.5 • Table 2, page 3: Removed reference to XC2VP125 FPGA. • Table 1, page 1: Broke out VCCO / VCCJ into two separate columns. • • Table 7, page 7: Added clarification of ID code die revision bits. Table 8, page 8: Deleted TCKMIN2 (bypass mode) and renamed TCKMIN1 to TCKMIN. • Table Recommended Operating Conditions, page 25: Separated VCCO and VCCJ parameters. Table DC Characteristics Over Operating Conditions, page 26: - Added most parameter values for XCF08P, XCF16P, XCF32P devices. - Added Footnote (1) to ICCO specifying no-load conditions. Table AC Characteristics Over Operating Conditions, page 28: - Added most parameter values for XCF08P, XCF16P, XCF32P devices. - Expanded Footnote (1) to include XCF08P, XCF16P, XCF32P devices. - Added Footnote (8) through (11) relating to CLKOUT conditions for various parameters. - Added rows to TCYC specifying parameters for parallel mode. - Added rows specifying parameters with decompression for TCLKO, TCOH, TFF, TSF. - Added TDDC (setup time with decompression). Table AC Characteristics Over Operating Conditions When Cascading, page 32: - Added most parameter values for XCF08P, XCF16P, XCF32P devices. - Separated Footnote (5) into Footnotes (5) and (6) to specify different derivations of TCYC, depending on whether dual-purpose configuration pins persist as configuration pins, or become general I/O pins after configuration. • • • DS123 (v2.6) March 14, 2005 Preliminary Product Specification Section DC Characteristics Over Operating Conditions, page 26: - Added parameter row and parameters for parallel configuration mode, ’P’ devices, to ICCO . - Added Footnote (1) and Footnote (2) with callouts in the Test Conditions column for ICCJ, ICCINTS, ICCOS, and ICCJS, to define active and standby mode requirements. Section AC Characteristics Over Operating Conditions, page 28: - Corrected description for second TCAC parameter line to show parameters for 1.8V VCCO . - Revised Footnote (7) to indicate VCCO = 3.3V. - Applied Footnote (7) to second TCYC parameter line. Section AC Characteristics Over Operating Conditions When Cascading, page 32: Revised Footnote (5)TCYC Min and TCAC Min formulas. www.xilinx.com 41 R 03/14/05 Platform Flash In-System Programmable Configuration PROMS 2.6 • • • • • • • • • • DS123 (v2.6) March 14, 2005 Preliminary Product Specification Added Virtex-4 LX/FX/SX configuration data to Table 2. Corrected Virtex-II configuration data in Table 2. Corrected Virtex-II Pro configuration data in Table 2. Added Spartan-3L configuration data to Table 2. Added Spartan-3E configuration data to Table 2. Paragraph added to FPGA Master SelectMAP (Parallel) Mode (1), page 11. Changes to DC Characteristics - TOER changed, page 26. - IOL changed for VOL, page 26. - VCCO added to test conditions for IIL , IILP, IIHP,and IIH, page 26. Values modified for IILP and IIHP. Changes to AC Characteristics - TLC and THC modified for 1.8V, page 29. - New rows added for TCEC and TOEC, page 29. Minor changes to grammar and punctuation. Add explanation of "Preliminary" to DC and AC Electrical Characteristics. www.xilinx.com 42