U62256A Standard 32K x 8 SRAM Features Description ! 32768x8 bit static CMOS RAM ! Access times 70 ns, 100 ns ! Common data inputs and The U62256A is a static RAM manufactured using a CMOS process technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6-transistor cell. data outputs ! Three-state outputs ! Typ. operating supply current 70 ns: 50 mA 100 ns: 40 mA ! TTL/CMOS-compatible ! Automatical reduction of power dissipation in long Read Cycles ! Power supply voltage 5 V + 10 % ! Operating temperature ranges 0 to 70 °C -40 to 85 °C -40 to 125 °C ! QS 9000 Quality Standard ! ESD protection > 2000 V (MIL STD 883C M3015.7) ! Latch-up immunity >100 mA ! Packages: PDIP28 (600 mil) SOP28 (330 mil) The circuit is activated by the falling edge of E. The address and control inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. In a Read cycle, the data outputs are activated by the falling edge of G, afterwards the data word read will be available at the outputs DQ0-DQ7. After the address change, the data outputs go High-Z until the new information read is available. The data outputs have not preferred state. The Read cycle is finished by the Pin Configuration Pin Description A14 1 28 VCC A12 2 27 W A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 A2 8 PDIP SOP 21 G A1 9 20 A0 10 19 E DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 VSS 14 15 DQ3 A10 Top View April 20, 2004 falling edge of W, or by the rising edge of E, respectively. Data retention is guaranteed down to 2 V. With the exception of E, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. 1 Signal Name Signal Description A0 - A14 Address Inputs DQ0 - DQ7 Data In/Out E Chip Enable G Output Enable W VCC Write Enable Power Supply Voltage VSS Ground U62256A Row Decoder Memory Cell Array 512 Rows x 64 x 8 Columns Column Decoder DQ0 Sense Amplifier/ Write Control Logic Address Change Detector Clock Generator DQ1 Common Data I/O A0 A1 A2 A3 A4 A5 Column Address Inputs A6 A7 A8 A9 A10 A11 A12 A13 A14 Row Address Inputs Block Diagram DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC VSS E W G Truth Table Operating Mode E W G DQ0 - DQ7 Standby/not selected H * * High-Z Internal Read L H H High-Z Read L H L Data Outputs Low-Z Write L L * Data Inputs High-Z * H or L 2 April 20, 2004 U62256A Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured ±200 mV from steady-state voltage. Absolute Maximum Ratings a Symbol Min. Max. Unit VCC -0.5 7 V Input Voltage VI -0.5 VCC + 0.5 b V Output Voltage VO -0.5 VCC + 0.5 b V Power Dissipation PD - 1 W Power Supply Voltage Operating Temperature C-Type K-Type A-Type Ta 0 -40 -40 70 85 125 °C Storage Temperature C/K-Type A-Type Tstg -65 -65 125 150 °C 200 mA Output Short-Circuit Current at VCC = 5 V and VO = 0 V c a b c d | IOS | Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Maximum voltage is 7 V Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s. Recommended Operating Conditions Symbol Power Supply Voltage Conditions Min. Max. Unit VCC 4.5 5.5 V Input Low Voltage d VIL -0.3 0.8 V Input High Voltage VIH 2.2 VCC + 0.3 V -2 V at Pulse Width 10 ns April 20, 2004 3 U62256A Electrical Characteristics Supply Current - Operating Mode Symbol ICC(OP) Conditions VCC VIL VIH tcW tcW = = = = = VCC VE C-Type K-Type A-Type = 5.5 V = VCC - 0.2 V ICC(SB)1 VCC VE = 5.5 V = 2.2 V Output High Voltage VOH Output Low Voltage VOL VCC IOH VCC IOL = 4.5 V = -1.0 mA = 4.5 V = 3.2 mA VCC VIH VCC VIL = 5.5 V = 5.5 V = 5.5 V = 0V VCC VOH VCC VOL = = = = VCC VOH VCC VOL = 5.5 V = 5.5 V = 5.5 V = 0V Supply Current - Standby Mode (CMOS level) Supply Current - Standby Mode (TTL level) ICC(SB) Input High Leakage Current IIH Input Low Leakage Current IIL Output High Current IOH Output Low Current IOL Output Leakage Current High at Three-State Outputs IOHZ Low at Three-State Outputs IOLZ 4 Min. 5.5 V 0.8 V 2.2 V 70 ns 100 ns 4.5 V 2.4 V 4.5 V 0.4 V Max. Unit 70 65 mA mA 5 10 50 µA µA µA 1 mA 2.4 V 0.4 V 2 µA -2 µA -1 3,2 mA 1 -1 mA µA µA April 20, 2004 U62256A Switching Characteristics Read Cycle Symbol 07 10 IEC Min. Read Cycle Time tRC tcR 70 Address Access Time to Data Valid tAA ta(A) 70 100 ns Chip Enable Access Time to Data Valid tACE ta(E) 70 100 ns Output Enable Access Time to Data Valid tOE ta(G) 35 45 ns E HIGH to Output in High-Z tHZCE tdis(E) 25 35 ns G HIGH to Output in High-Z tHZOE tdis(G) 25 35 ns E LOW to Output in Low-Z tLZCE ten(E) 5 5 ns G LOW to Output in Low-Z tLZOE ten(G) 0 0 ns tOH tv(A) 5 5 ns Output Hold Time from Address Change Switching Characteristics Write Cycle Symbol Max. Min. Max. Unit Alt. 100 07 ns 10 IEC Min. Write Cycle Time tWC tcW 70 100 ns Write Pulse Width tWP tw(W) 55 70 ns Write Pulse Width Setup Time tWP tsu(W) 55 70 ns Address Setup Time tAS tsu(A) 0 0 ns Address Valid to End of Write tAW tsu(A-WH) 65 80 ns Chip Enable Setup Time tCW tsu(E) 65 80 ns Pulse Width Chip Enable to End of Write tCW tw(E) 65 80 ns Data Setup Time tDS tsu(D) 30 35 ns Data Hold Time tDH th(D) 0 0 ns Address Hold from End of Write tAH th(A) 0 0 ns W LOW to Output in High-Z tHZWE tdis(W) 25 35 ns G HIGH to Output in High-Z tHZOE tdis(G) 25 35 ns W HIGH to Output in Low-Z tLZWE ten(W) 0 0 ns G LOW to Output in Low-Z tLZOE ten(G) 0 0 ns April 20, 2004 5 Max. Min. Max. Unit Alt. U62256A Data Retention Mode E-Controlled VCC 4.5 V VCC(DR) ≥ 2 V 2.2 V tDR Data Retention trec 2.2 V E 0V VCC(DR) - 0.2 V ≤ V E(DR) ≤ VCC(DR) + 0.3 V Data Retention Characteristics Symbol Alt. IEC Data Retention Supply Voltage VCC(DR) Data Retention Supply Current ICC(DR) Data Retention Setup Time Operating Recovery Time tCDR tsu(DR) tR trec Conditions Min. Typ. 2 VCC(DR) = 3 V VE = VCC(DR) - 0.2 V C-Type K-Type A-Type See Data Retention Waveforms (above) Max. Unit 5.5 V 3 6 30 µA µA µA 0 ns tcR ns Test Configuration for Functional Check E W G e VCC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Simultaneous measurement of all 8 output pins VIL relevant test measurement VIH Input level according to the 5V A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 960 VO 30 pF e 510 VSS In measurement of tdis(E), tdis(W), tdis(G), ten(E), ten(W), ten(G) the capacitance is 5 pF. 6 April 20, 2004 U62256A Capacitance Input Capacitance Output Capacitance Conditions VCC VI f Ta Symbol Min. Max. Unit CI - 7 pF 7 pF = 5.0 V = VSS = 1 MHz = 25 °C CO - All pins not under test must be connected with ground by capacitors. Ordering Code Example U62256A S2 K 07 LL Type Leadfree Option blank = Standard Package G1 = Leadfree Green Package f Package D = PDIP28 (600 mil, only C/K-Type and 70 ns) S2 = SOP28 (330 mil) Type 2 Operating Temperature Range C = 0 to 70 °C K = -40 to 85 °C A = -40 to 125 °C f Power Consumption blank = Standard (only A-Type) LL = Very Low Power (C/K-Type) Access Time 07 = 70 ns 10 = 100 ns (only C/K-Type) on special request Device Marking (example) Product specification Assembly location and trace code ZMD U62256AS2K 07LL C 0425 1 ZZ G1 Internal Code April 20, 2004 Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package 7 U62256A Read Cycle 1: Ai-controlled (during Read Cycle : E = G = VIL, W = VIH) tcR Ai Address Valid ta(A) DQi Previous Data Valid Output Output Data Valid tv(A) Read Cycle 2: G-, E-controlled (during Read Cycle: W = VIH) tcR Ai E Address Valid tsu(A) ten(E) G DQi ten(G) tdis(E) ta(E) ta(G) High-Z tdis(G) Output Data Valid Output 8 April 20, 2004 U62256A Write Cycle1: W-controlled tcW Ai Address Valid tsu(E) th(A) E W tsu(A-WH) tw(W) tsu(A) tsu(D) DQi Input th(D) Input Data Valid ten(W) High-Z tdis(W) DQi Output G Write Cycle 2: E-controlled tcW Ai E Address Valid tsu(A) th(A) tw(E) tsu(W) W tsu(D) DQi Input Input Data Valid ten(E) tdis(W) DQi Output th(D) High-Z tdis(G) G undefined L- to H-level H- to L-level The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and rights to change design reserved. April 20, 2004 9 U62256A LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and conditions of sale. ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. April 20, 2004 Zentrum Mikroelektronik Dresden AG Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: [email protected] • http://www.zmd.de