DRF100 ® 15V, 8A, 30MHz High Speed MOSFET Driver The DRF100 is a High-Speed Power MOSFET driver with a unique anti-ring function. It is intended to drive the gate of a power MOSFET ≥3nF, gate capacitance to an 18V maximum, at frequencies up to 30MHz. It can produce output currents ≥8A RMS, while dissipating 100W. VDD VDD TYPICAL APPLICATIONS FEATURES • Switching Frequency: DC TO 30MHz • MOSFET Drivers • Switching Speeds 3-4ns 50Ω Load • Switch Mode Power Ampliﬁers • Low Pulse Width Distortion • Digital Output Ampliﬁers • Single Power Supply • Pulse Generators • 3V CMOS Schmitt Trigger Input 1V Hysteresis • Laser Diode Drivers • Output Capable of ≥ 8A RMS • Ultrasound Transducer Drivers • Power Dissipation Capability >100W • Acoustic Optical Modulators Absolute Maximum Ratings Symbol Parameter Unit Ratings VDD Supply Voltage 18 VIN Input Single Voltage 5.5 V Speciﬁcations Symbol Parameter VDD Supply Voltage IOUT 5 Output Current VIN Input Voltage Rising Edge VIN(F) 6 Input Voltage Falling Edge Max Output Current Coss Output Capacitance Ciss Input Capacitance VIL Input Low VIH Input High VDLY Max 18 8 1.8 8 Quiescent Current IO Typ 3 Input Voltage VIN(R) 6 IDDQ Min 8 2.2 1.2 Time Delay (throughput) ns µA A 200 8 2500 3 0.8 1.9 Unit V A V pF 1.0 2.2 V ns 38 Min Characteristic Junction to Case Thermal Resistance TJ Operating Junction Temperature PD Maximum Power Dissipation Total Power Dissipation @ TC = 25°C PDC APT Website - http://www.advancedpower.com Typ Max 0.71 175 >100 210 Unit °C/W °C W Rev A RθJC 050-4912 Symbol 2-2006 Thermal Characteristics Driver Speciﬁcations TJ = 25°C unless otherwise speciﬁed DRF100 Typical Symbol Parameter Test Conditions tr Rise Time 2,3 15VDD 3.1 7.5 tf Fall Time 2,3 15VDD 2.8 7.5 15V 33 TD Prop. Delay 2,4 Symmetry 1 15VDD 3 Driver Output Characteristics Symbol Min Min Cout Output Capacitance 2,5 Rout Output Resistance 2,5 Lout Output Inductance 2,5 FMAX Operating Frequency CL Max 38 % Typ Max 2500 1 2 Unit ns 1.2 TJ = 25°C unless otherwise speciﬁed Parameter RL 3 4 30 Unit pF Ω nH MHz Test curcuit show on page 3. All measurements were made with the Anti-Ring circuit activated unless noted. 1. Symmetry is the percent difference in high and low FWHM times with a 50% duty cycle square wave input. 2 RL = 50Ω, CL = 3000pF 3 10% - 90% See Test Circuit 4 50% - 50%, see Test Circuit 5 VDD = 18V, CL = 3000pF, F = 10MHz 6 Performance speciﬁed with this input. APT reserves the right to change, without notice, the speciﬁcations and information contained herein. 050-4912 Rev A 2-2006 Figure 1, DRF100 Simpliﬁed Ciruit Diagram A Simpliﬁed DRF100 Circuit Diagram is illustrated above. By including the driver high speed by-pass capacitors (C1C8), their contribution to the internal parasitic loop inductance of the driver output is greatly reduced. This, coupled with the tight geometry of the hybrid, allows optimum drive to the gate of the MOSFET. This low parasitic approach, coupled with the Schmitt trigger input, Kelvin signal ground (4,5) and the Anti-Ring Function, provide improved stability and control in Kilowatt to Multi-Kilowatt, High Frequency applications The IN pin (4) is applied to a Schmitt Trigger. The signal is then applied to the intermediate drivers and level shifters; this section contains proprietary circuitry designed speciﬁcally for ring abatement. The P channel and N channel power drivers provide the high current to the OUT pin (9). The FUNCTION, FN, pin (3) is used to disable the Anti-Ring function. It is recommended that the device be operated with this function enabled. Func. = Hi (+5V or Float) Anti-Ring on, Func. = Low (0V or GND.) Anti-ring off. Driver Control Logic In (4) HIGHDriver Output (9) LOW In (4) LOWDriver Output (9) HIGH DRF100 Figure 2, Test Circuit The Test Circuit illustrated above was used to evaluate the DRF100 (available as an evaluation Board DRF-100EVAL). The input control signal is applied to the DRF100 via the IN(4) and SG(5) pins via RG188. This provides excellent noise immunity and control of the signal ground currents. The FN pin is off and unwanted signals can cause erratic behavior, Therefore FN pin is heavily by-passed on the Evaluation board, see FN (3) above. 050-4912 Rev A 2-2006 The +Vcc inputs (2,6) are heavily By-Passed (C1-C3, C5-C7), this is in addition to the internal bypassing mentioned previously. The capacitors used for this function must be capable of supporting the RMS currents and frequency of the load. DRF100 Figure 3, Leading Edge throughput Delay ~ = 32ns Figure 4, Trailing Edge throughput Delay ~ = 33ns Figure 5, 30MHz Output into 50Ω Figure 6, Output Rise Time = 2.8ns All waveforms on this page, Figures 3 thru 7, were taken using the test circuit of Figure 1, with the following test conditions: 050-4912 Rev A 2-2006 1. +VDD = 15V 2. Control input 5.0V/50Ω 3. Load = 50Ω Figure 7, Output Fall Time = 2.0ns DRF100 Figure 8, Leading Edge throughput Delay ~ = 37ns Figure 9, Trailing Edge throughput Delay ~ = 37ns Figure 10, Output Rise Time = 7.2ns Figure 11, Output Fall Time = 7.2ns Figure 12, DRF-100 Output @ 30MHz in to 50Ω +3nF 050-4912 Rev A 4. +VDD = 15V 5. Control input 5.0V/50Ω 6. Load = 50Ω+3nF 2-2006 All waveforms on this page, Figures 8 thru 12, were taken using the test circuit of Figure 3, with the following test conditions: DRF100 Figure 13, Anti-Ring ON Figure 14, Anit-RIng OFF The output waveform with the Anti-Ring function ON is illustrated in Figure 13 and the Anti-Ring function OFF is illustrated in Figure 14. The load is 50Ω with no load capacitance, other than the output capacitance of the driver. 050-4912 Rev A 2-2006 Figure 15, Anti-Ring ON Figure 16, Anit-RIng OFF The output waveform with the Anti-Ring function ON is illustrated in Figure 15 and the Anti-Ring function OFF is illustrated in Figure 16. The load is 50Ω + 3nF of capacitance. The ring amplitude in Figure 15 is clearly above the 2-4V threshold voltage of most power MOSFETs, while In Figure 16 we see that the ring peak is at ~ =2V, also see Figure 13. It is most likely that the wave form of Figure 16 will cause a cross conduction in a Bridge or push pull topology. T1 T2 T3 A T4 The real time gating of the FN function is illustrated in Figure 17. At T1 the FN trace (C) is deactivated and at T4 it is reactivated. B The output is shown as trace (B), There is signiﬁcant ringing on both the leading and tailing edges. Trace (A) is the input control signal C Figure 17 T1 T2 T3 T4 A In Figure 18, trace (B) shows the antiring function active during the pulse. In trace (B) we see the output with a greatly reduced ring amplitude. B Note: load = 50Ω + 3nF, series inductance is estimated at 3nH. A typical MOSFET can exceed this value. 050-4912 Figure 18 Rev A 2-2006 C T1 T2 T3 T4 A B C In Figure 19, we see the anti-ring function FN active for the leading edge only, T2. Figure 20, illustrates the anti-ring function active on the trailing edge only. Figure 19 Note: load = 50Ω + 3nF, series inductance is estimated at 3 nH, A typical MOSFET can exceed this value. T1 T2 T3 A B 050-4912 Rev A 2-2006 C Figure 20 T4 DRF100 VDD VDD 050-4912 Rev A 2-2006 Figure 21, DRF100 Mechanical Outline DRF100 +VDD By-Pass LF +VDD By-Pass HF This Section Configured by User R2 50Ω Input Termination FN Input Figure 22, DRF100 Eval Board 050-4912 Rev A 2-2006 The DFR100 is a high power device and must have adequate cooling for full power operation Evaluation Boards are provided to facilitate the circuit design process by allowing the end user to quickly evaluate the performance of our components under a speciﬁc and single set of conditions. They are not intended to be used as a sub assembly in any ﬁnal product(s). Care has been taken to insure that the Evaluation Boards are assembled to correctly represent the test circuit included in the component data sheet. There is no warranty of these Evaluation Boards beyond workmanship and materials. DRF100 5.25 4 holes .150 dia. 4.936 Advanced Power Technology DRF100 0.900 3.50 3.196 1.7 RE 12/06/05 revD 1.425 .716 See DRF100 mechanical drawing for physical dimension details PCB material - .062 FR4 050-4912 Rev A 2-2006 Figure 23, DRF100 Eval Board Mechanical DRF100 Mounting instructions for Flangeless Packages Heat sink mounting of any device in the Flangeless Package family follows the same process details outlined in this document. 2. The BeO surface of the device must be free of any foreign objects or material. 3. The BeO surface must be coated with a thin and uniform ﬁlm of thermal compound. 4. For commercial manufacturing the suggested method for thermal compound application is to apply the compound using a screen printer. This process insures consistent and repeatable performance with minimum effort. Figure 24, Top and Side View of a T3 device 050-4912 Rev A 2-2006 Heat Sink Surface: 1. The heat sink surface should be smooth, free of nicks and burs; in addition it should be ﬂat to ≤.001in./in TIR, (Total Indicator Run out) and be ﬁnished to ~ 68µ CLA, (Center Line Average). 2. Must be free of solder balls, metal shavings and any foreign objects or material. Figure 25, Stress Relief bend Device Preparation: 1. The leads should be prepared with an “s” bend, as shown in Figure 25 prior to mounting on the heat sink. Mechanical Attachment: 1. The four screws (1-2-3-4), as shown in Figure 24, should be installed and seated, then torqued to one-half the speciﬁcation, in the sequence shown. First screw 1 then screw 2, 3 and 4. 2. Then complete the process by tightening to the full speciﬁcation in the same manner. 3. The torque spec is 8in.lb. ± 1lb. (0.9Nm) Lead Attachment: 1. The leads may now be soldered to the PCB 2. Maximum lead temperature must not exceed 300oC for 10s. 3. For lead free use 96.5 % tin, 3% silver, and 0.5% copper. 4. Non-lead Free use 2% Silver, 62% Tin, 36% lead (sn62).