DRF1200 ® 15V, 13A, 30MHz MOSFET Driver Hybrid The DRF1200 MOSFET driver hybrid. This hybrid includes a high power gate driver and the power MOSFET. It was designed to provide the system designer increased flexibility and lowered cost over a non-integrated solution. DRIVER FEATURES TYPICAL APPLICATIONS MOSFET FEATURES • Switching Frequency: DC TO 30MHz • Switching Frequency: DC TO 30MHz • Class C, D and E RF Generators • Low Pulse Width Distortion • Switching Speed 3-4ns • Switch Mode Power Amplifiers • Single Power Supply • BVds = 1kV • Pulse Generators • 3V CMOS Schmitt Trigger Input 1V • Ids = 13A avg. • Ultrasound Transducer Drivers • Rds(on) ≤ 1 Ohm • Acoustic Optical Modulators Hysteresis • PD = 350W • Drivers > 3nF Driver Absolute Maximum Ratings Symbol Parameter Unit Ratings VDD Supply Voltage 18 VIN Input Single Voltage 5.5 V Driver Specifications Input Voltage VIN(R) 6 Input Voltage Rising Edge VIN(F) 6 Input Voltage Falling Edge IDDQ Max Output Current Coss Output Capacitance Ciss Input Capacitance VIL Input Low VIH Input High Max 18 3 1.8 0.8 2.2 1.2 Quiescent Current IO TDLY Typ Driver Specifications Typical Symbol Parameter Test Conditions tr Rise Time 2,3 15VDD 3.1 7.5 tf Fall Time 2,3 15VDD 2.8 7.5 15V 33 38 TD Prop. Delay Symmetry 1 2,4 15VDD 3 APT Website - http://www.advancedpower.com Min RL CL 1.2 V ns 38 TJ = 25°C unless otherwise specified ns pF 1.0 2.2 Time Delay (throughput) V µA A 200 8.5 2500 3 0.8 1.9 Unit Max Unit ns % 2-2006 Supply Voltage VIN Min 8 Rev A Parameter VDD 050-4913 Symbol MOSFET Absolute Maxumum Ratings Symbol VDSS ID RDS(on) DRF1200 Min Parameter Drain-Source Voltage Typ Max Unit V A Ω Max Unit 1000 Continuos Drain Current THS = 25°C 13 Drain-Source On State Resistance 0.90 Dynamic Characteristics Symbol Min Parameter Typ Ciss Input Capacitance 2000 Coss Output Resistance 165 Crss Reverse Transfer Capacitance 75 pF Thermal Characteristics Symbol RθJC 1. 2 3 4 5 6 Junction to Case Thermal Resistance TJ Operating and Storage Junction Temperature PD Maximum Power Dissipation Total Power Dissipation @ TC = 25°C PDC Ratings 0.13 175 >100 1050 Characteristic Unit °C/W °C W Test curcuit show on page 3. All measurements were made with the Anti-Ring circuit activated unless noted. Symmetry is the percent difference in high and low FWHM times with a 50% duty cycle square wave input. RL = 50Ω, CL = 3000pF 10% - 90% See Test Circuit 50% - 50%, see Test Circuit VDD = 18V, CL = 3000pF, F = 10MHz Performance specified with this input. APT reserves the right to change, without notice, the specifications and information contained herein. Figure 1, DRF1200 Simplified Ciruit Diagram 050-4913 Rev A 2-2006 A Simplified DRF1200 Circuit Diagram is illustrated above. By including the driver high speed by-pass capacitors (C1-C8), their contribution to the internal parasitic loop inductance of the driver output is greatly reduced. This, coupled with the tight geometry of the hybrid, allows optimal the gate drive to the MOSFET. This low parasitic approach, coupled with the Schmitt trigger input, Kelvin signal ground and the Anti-Ring Function, Provide improved stability and control in Kilowatt to Multi-Kilowatt, High Frequency applications. The IN pin is the input for the control signal and is applied to a Schmitt Trigger. The signal is then applied to the intermediate drivers and level shifters; this section contains proprietary circuitry designed specifically for ring abatement. The P channel and N channel power drivers provide the high current to the gate of the MOSFET and the MOSFET drain is attached to the OUT pin (9). Driver Control Logic In (4) HIGH Driver In (4) LOW Driver Driver Output LOW Driver Output HIGH MOSFET OFF Drain (9) HIGH MOSFET ON Drain (9) LOW The FUNCTION, FN, pin (3) is used to disable the Anti-Ring function. It is recommended that the device be operated with this function enabled. Func. = Hi (+5V or Float) Anti-Ring on, Func. = Low (0V or GND.) Anti-ring off. On the Output side are the POWER GROUND connections pin 8 and pin 10. The DRAIN connection is pin 9. It is suggested that output currents be restricted to these pins by design. DRF1200 Figure 2, Test Circuit The Test Circuit illustrated above was used to evaluate the DRF1200 (available as an evaluation Board DRF1200 EVAL). The input control signal is applied to the DRF1200 via IN(4) and SG(5) pins using RG188. This provides excellent noise immunity and control of the signal ground currents. The FN pin is very sensitive and unwanted signals can cause erratic behavior, Therefore FN pin is heavily by-passed on the Evaluation board, see FN (3) above. 050-4913 Rev A 2-2006 The +VDD inputs (2,6) are By-Passed (C1-C3, C5-C7), this is in addition to the internal bypassing mentioned previously. The capacitors used for this function must be capable of supporting the RMS currents and frequency of the gate load. A 50Ω (R4) load is used evaluate the output performance of the DRF1200. DRF1200 Figure 3, Drain & Current Waveforms Figure 4, Drain Fall Time In Figure 3 we see a drain voltage fall of 800V and the current rise of 13.6A in a 50Ω Load. The drain voltage fall time is 3.4ns 10% to 90% as shown in Figure 4. Figure 6, Typical Maximum Safe Operating Area 050-4913 Rev A 2-2006 Figure 5, Typical Capacitance vs. Drain-to-Source Voltage Figure 7, Maximum Effective Transient Thermal Impedance, Junction-to -Case vs. Pulse Duration DRF1200 0.200 0.369 0.200 10 9 8 SOURCE GND DRAIN SOURCE GND 0.275 .090 Gap Typ. .115 in. Clear 4 Places 0.300 APT DRF1200 0.750 1.00 5600 5600 5600 5600 5600 5600 5600 .050 Gap Typ. 0.300 GND +VDD 0.06 3 +VDD FN 4 5 6 IN SG +VDD 7 .005in. Typ. Half Hard Copper Gold Plated 0.040 GND 0.04 1.25 0.300 1.500 Figure 8, DRF1200 Mechanical Outline 2-2006 2 1 0.100 Rev A 5600 050-4913 0.275 DRF1200 Vds Monitor HV By-Pass Capacitors FN By-Pass Load Resistors +Vdd By-Pass Capacitors This Section Configured by User Control In 50Ω Terminator Control In +Vdd By-Pass Capacitors Decoupling Resistors Figure 9, DRF1200 Eval Board 050-4913 Rev A 2-2006 The DFR1200 is a high power device and must have adequate cooling for full power operation Evaluation Boards are provided to facilitate the circuit design process by allowing the end user to quickly evaluate the performance of our components under a specific and single set of conditions. They are not intended to be used as a sub assembly in any final product(s). Care has been taken to insure that the Evaluation Boards are assembled to correctly represent the test circuit included in the component data sheet. There is no warranty of these Evaluation Boards beyond workmanship and materials. DRF1200 5.5 4 holes .150 dia. 5.196 Advanced Power Technology DRF1200 0.900 3.50 3.196 1.7 RE 12/06/05 revD 1.425 1.145 See DRF1200 mechanical drawing for physical dimension details PCB material - .062 FR4 050-4913 Rev A 2-2006 Figure 10, DRF1200 Eval Board Mechanical DRF1200 Mounting instructions for Flangeless Packages Heat sink mounting of any device in the Flangeless Package family follows the same process details outlined in this document. 3 2 T3 Package 1 4 Torque screws in 1 -2-3-4 Sequence 4-40 Socket head SS Screws . Torque to 8in.lb. Stress Relief “S” Bend On all leads #4 Flat Washer PCB PCB Thermal Compound Figure 11, Top and Side View of a T3 device Heat Sink Surface: 1. The heat sink surface should be smooth, free of nicks and burs; in addition it should be flat to ≤.001in./in TIR, (Total Indicator Run out) and be finished to ~ 68µ CLA, (Center Line Average). 2. Must be free of solder balls, metal shavings and any foreign objects or material. Stress Relief “S” Bend On all leads 050-4913 Rev A 2-2006 PCB Figure 12, Stress Relief bend Device Preparation: 1. The leads should be prepared with an “s” bend, as shown in Figure 10 prior to mounting on the heat sink 2. The BeO surface of the device must be free of any foreign objects or material. 3. The BeO surface must be coated with a thin and uniform film of thermal compound. 4. For commercial manufacturing the suggested method for thermal compound application is to apply the compound using a screen printer. This process insures consistent and repeatable performance with minimum effort. Mechanical Attachment: 1. The four screws (1-2-3-4), as shown in Figure 11, should be installed and seated, then torqued to one-half the specification, in the sequence shown. First screw 1 then screw 2, 3 and 4. 2. Then complete the process by tightening to the full specification in the same manner. 3. The torque spec is 8in.lb. ±1lb. (0.9Nm) Lead Attachment: 1. The leads may now be soldered to the PCB 2. Maximum lead temperature must not exceed 300°C for 10s. 3. For lead free use 96.5 % tin, 3% silver, and 0.5% copper. 4. Non-lead Free use 2% Silver, 62% Tin, 36% lead (sn62).