AGERE FW323061394A

Data Sheet, Rev. 1
December 2005
™
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Features
„
128-pin TQFP lead-free package
„
1394a-2000 OHCI link and PHY core function in a single
device:
— Single-chip link and PHY enable smaller, simpler,
more efficient motherboard and add-in card designs
— Enables lower system costs
— Leverages proven 1394a-2000 PHY core design
— Demonstrated compatibility with current Microsoft
Windows ® drivers and common applications
— Demonstrated interoperability with existing, as well as
older, 1394 consumer electronics and peripherals
products
— Feature-rich implementation for high performance in
common applications
— Supports low-power system designs (CMOS implementation, power management features)
— Provides LPS, LKON, and CNA outputs to support
legacy power management implementations
„
OHCI:
— Complies with the 1394 OHCI 1.1 Specification
— OHCI 1.0 backwards compatible—configurable via
EEPROM to operate in either OHCI 1.0 or OHCI 1.1
mode
— Complies with Microsoft Windows logo program
system and device requirements
— Listed on Windows hardware compatibility list
http://www.microsoft.com/hcl/results.asp
— Compatible with Microsoft Windows and MacOS ®
operating systems
— 4 Kbyte isochronous transmit FIFO
— 2 Kbyte asynchronous transmit FIFO
— 4 Kbyte isochronous receive FIFO
— 2 Kbyte asynchronous receive FIFO
— Dedicated asynchronous and isochronous descriptorbased DMA engines
— Eight isochronous transmit contexts
— Eight isochronous receive contexts
— Prefetches isochronous transmit data
— Supports posted write transactions
— Supports parallel processing of incoming physical
read and write requests
— Supports notification (via interrupt) of a failed register
access
— May be used without an EEPROM when the system
BIOS is programmed with the EEPROM contents.
„
1394a-2000 PHY core:
— Compliant with IEEE ® 1394a-2000, Standard for a
High Performance Serial Bus (Supplement)
— Three fully compliant cable ports, each supporting
400 Mbits/s, 200 Mbits/s, and 100 Mbits/s traffic
— Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders
— While unpowered and connected to the bus, will not
drive TPBIAS on a connected port even if receiving
incoming bias voltage on that port
— Does not require external filter capacitor for PLL
— Supports link-on as a part of the internal
PHY core-link interface
— 25 MHz crystal oscillator and internal PLL provide a
50 MHz internal link-layer controller clock as well as
transmit/receive data at 100 Mbits/s, 200 Mbits/s, and
400 Mbits/s
— Interoperable across 1394 cable with 1394 physical
layers (PHY core) using 5 V supplies
— Provides node power-class information signaling for
system power management
— Supports ack-accelerated arbitration and fly-by
concatenation
— Supports arbitrated short bus reset to improve
utilization of the bus
— Fully supports suspend/resume
— Supports connection debounce
— Supports multispeed packet concatenation
— Supports PHY pinging and remote PHY access
packets
— Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V
„
Link:
— Cycle master and isochronous resource manager
capable
— Supports 1394a-2000 acceleration features
„
PCI:
— Revision 2.2 compliant
— 33 MHz/32-bit operation
— Programmable burst size thresholds for PCI data
transfer
— Supports optimized memory read line, memory read
multiple, and memory write invalidate burst
commands
— Supports PCI Bus Power Management Interface
Specification v.1.1, including D3cold wakeups
— Supports CLKRUN# protocol per PCI Mobile Design
Guide
— Supports Mini PCI Specification v1.0, including Mini
PCI power requirements
— Global byte swap function
— CardBus support per PC Card Standard Release 8.0,
including 128 bytes of on-chip tuple memory.
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Table of Contents
Contents
Page
Features .................................................................................................................................................................. 1
Other Features .................................................................................................................................................. 6
FW323 Functional Overview ................................................................................................................................... 6
FW323 Functional Description ................................................................................................................................ 6
PCI Core ........................................................................................................................................................... 7
OHCI Data Transfer .......................................................................................................................................... 8
OHCI Isochronous Data Transfer ..................................................................................................................... 8
Isochronous Register Access ........................................................................................................................... 9
OHCI Asynchronous Data Transfer .................................................................................................................. 9
Asynchronous Register Access ........................................................................................................................ 9
Link Core ......................................................................................................................................................... 11
PHY Core ........................................................................................................................................................ 13
Pin Information ...................................................................................................................................................... 15
Internal Registers .................................................................................................................................................. 22
PCI Configuration Registers ........................................................................................................................... 22
Vendor ID Register ......................................................................................................................................... 24
Device ID Register .......................................................................................................................................... 24
PCI Command Register .................................................................................................................................. 25
PCI Status Register ........................................................................................................................................ 26
Class Code and Revision ID Registers ........................................................................................................... 27
Latency Timer and Cache Line Size Register ................................................................................................. 28
Header Type and BIST Register ..................................................................................................................... 28
OHCI Base Address Register ......................................................................................................................... 29
CardBus Base Address Register .................................................................................................................... 30
CIS Pointer ...................................................................................................................................................... 30
PCI Subsystem Identification Register ............................................................................................................ 31
PCI Power Management Capabilities Pointer Register ................................................................................... 31
Interrupt Line and Pin Register ....................................................................................................................... 32
MIN_GNT and MAX_LAT Register ................................................................................................................. 32
PCI OHCI Control Register ............................................................................................................................. 33
Capability ID and Next Item Pointer Register ................................................................................................. 33
Power Management Capabilities Register ...................................................................................................... 34
Power Management Control and Status Register ........................................................................................... 35
Power Management CSR PCI-to-PCI Bridge Support Extensions ................................................................. 36
Power Management Data ............................................................................................................................... 36
CardBus Function Registers (CardBusN = 0) ................................................................................................. 36
OHCI Registers ............................................................................................................................................... 37
OHCI Version Register ................................................................................................................................... 40
GUID ROM Register ....................................................................................................................................... 41
Asynchronous Transmit Retries Register ........................................................................................................ 41
CSR Data Register ......................................................................................................................................... 42
CSR Compare Register .................................................................................................................................. 42
CSR Control Register ..................................................................................................................................... 42
Configuration ROM Header Register .............................................................................................................. 43
Bus Identification Register .............................................................................................................................. 44
Bus Options Register ...................................................................................................................................... 44
GUID High Register ........................................................................................................................................ 45
GUID Low Register ......................................................................................................................................... 45
Configuration ROM Mapping Register ............................................................................................................ 46
Posted Write Address Low Register ............................................................................................................... 47
Posted Write Address High Register .............................................................................................................. 47
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Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Table of Contents (continued)
Contents
Page
Vendor ID Register ..........................................................................................................................................
Host Controller Control Register .....................................................................................................................
SelfID Buffer Pointer Register .........................................................................................................................
SelfID Count Register .....................................................................................................................................
Isochronous Receive Multiple Channel Mask High (IRMultiChanMaskHi) Register .......................................
Isochronous Receive Multiple Channel Mask Low (IRMultiChanMaskLo) Register .......................................
Interrupt Event (IntEvent) Register ..................................................................................................................
Interrupt Mask (IntMask) Register ...................................................................................................................
Isochronous Transmit Interrupt Event (isoXmitIntMask) Register ...................................................................
Isochronous Transmit Interrupt Mask (isoXmitIntMask) Register ...................................................................
Isochronous Receive Interrupt Event (isoRecvIntEvent) Register ..................................................................
Isochronous Receive Interrupt Mask (isoRecvIntMask) Register ...................................................................
Fairness Control Register ...............................................................................................................................
Link Control Register .......................................................................................................................................
Node Identification Register ............................................................................................................................
PHY Core Layer Control Register ...................................................................................................................
Isochronous Cycle Timer Register ..................................................................................................................
Asynchronous Request Filter High Register ...................................................................................................
Asynchronous Request Filter Low Register ....................................................................................................
Physical Request Filter High Register .............................................................................................................
Physical Request Filter Low Register .............................................................................................................
Asynchronous Context Control Register .........................................................................................................
Asynchronous Context Command Pointer Register ........................................................................................
Isochronous Transmit Context Control (IT DMA ContextControl) Register .....................................................
Isochronous Transmit Context Command Pointer Register ............................................................................
Isochronous Receive Context Control (IR DMA ContextControl) Register .....................................................
Isochronous Receive Context Command Pointer Register .............................................................................
Isochronous Receive Context Match (IR DMA ContextMatch) Register .........................................................
FW323 Vendor-Specific Registers ..................................................................................................................
Isochronous DMA Control ...............................................................................................................................
Asynchronous DMA Control ............................................................................................................................
Link Options ....................................................................................................................................................
Internal Register Configuration ..............................................................................................................................
PHY Core Register Map ..................................................................................................................................
PHY Core Register Fields ...............................................................................................................................
Crystal Selection Considerations ...........................................................................................................................
Load Capacitance ...........................................................................................................................................
Adjustment to Crystal Loading ........................................................................................................................
Crystal/Board Layout .......................................................................................................................................
Serial EEPROM Interface ......................................................................................................................................
ac Characteristics of Serial EEPROM Interface Signals ........................................................................................
NAND Tree Testing ................................................................................................................................................
Solder Reflow and Handling ..................................................................................................................................
Absolute Maximum Voltage/Temperature Ratings .................................................................................................
Electrical Characteristics .......................................................................................................................................
Timing Characteristics ...........................................................................................................................................
Outline Diagrams ...................................................................................................................................................
128-Pin TQFP .................................................................................................................................................
Ordering Information ..............................................................................................................................................
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FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Table of Contents (continued)
Figure
Page
Figure 1. FW323 Conceptual Block Diagram ........................................................................................................... 6
Figure 2. PCI Core Block Diagram ........................................................................................................................... 7
Figure 3. OHCI Core Block Diagram ........................................................................................................................ 8
Figure 4. Link Core Block Diagram ......................................................................................................................... 11
Figure 5. The PHY Core Block Diagram ................................................................................................................. 12
Figure 6. Pin Assignments for the FW323 06 ......................................................................................................... 15
Figure 7. Crystal Circuitry ....................................................................................................................................... 81
Figure 8. Bus Timing .............................................................................................................................................. 83
Figure 9. Write Cycle Timing .................................................................................................................................. 83
Figure 10. Data Validity .......................................................................................................................................... 83
Figure 11. Start and Stop Definition ....................................................................................................................... 84
Figure 12. Output Acknowledge ............................................................................................................................. 84
Figure 13. Nand Tree Logic Structure .................................................................................................................... 86
Table
Page
Table 1. Pin Descriptions ....................................................................................................................................... 16
Table 2. Bit-Field Access Tag Description ............................................................................................................. 22
Table 3a. PCI Configuration Register Map, CardBusN = 1 ................................................................................... 22
Table 3b. PCI Configuration Register Map, CardBusN = 0 ................................................................................... 23
Table 4. PCI Command Register Description ........................................................................................................ 25
Table 5. PCI Status Register ................................................................................................................................. 26
Table 6. Class Code and Revision ID Register Description .................................................................................. 27
Table 7. Latency Timer and Class Cache Line Size Register Description ........................................................... 28
Table 8. Header Type and BIST Register Description .......................................................................................... 28
Table 9. OHCI Base Address Register Description ............................................................................................... 29
Table 10. CardBus Base Address Register Description ........................................................................................ 30
Table 11. PCI Subsystem Identification Register Description ............................................................................... 31
Table 12. Interrupt Line and Pin Register Description ........................................................................................... 32
Table 13. MIN_GNT and MAX_LAT Register Description ..................................................................................... 32
Table 14. PCI OHCI Control Register Description ................................................................................................. 33
Table 15. Capability ID and Next Item Pointer Register Description ..................................................................... 33
Table 16. Power Management Capabilities Register Description ......................................................................... 34
Table 17. Power Management Control and Status Register Description .............................................................. 35
Table 18. Power Management Data Register Description .................................................................................... 36
Table 19. OHCI Register Map ............................................................................................................................... 37
Table 20. OHCI Version Register Description ....................................................................................................... 40
Table 21. GUID ROM Register Description ........................................................................................................... 41
Table 22. Asynchronous Transmit Retries Register Description ........................................................................... 41
Table 23. CSR Data Register Description ............................................................................................................. 42
Table 24. CSR Compare Register Description ...................................................................................................... 42
Table 25. CSR Control Register Description ........................................................................................................ 42
Table 26. Configuration ROM Header Register Description ................................................................................. 43
Table 27. Bus Identification Register Description.................................................................................................. 44
Table 28. Bus Options Register Description .......................................................................................................... 44
Table 29. GUID High Register Description ............................................................................................................ 45
Table 30. GUID Low Register Description ............................................................................................................. 45
Table 31. Configuration ROM Mapping Register Description ................................................................................ 46
Table 32. Posted Write Address Low Register Description ................................................................................... 47
Table 33. Posted Write Address High Register Description .................................................................................. 47
Table 34. Vendor ID Register Description ............................................................................................................. 47
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Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Table of Contents (continued)
Table
Page
Table 35. Host Controller Control Register Description ......................................................................................... 48
Table 36. SelfID Buffer Pointer Register Description ............................................................................................ 50
Table 37. SelfID Count Register Description ......................................................................................................... 50
Table 38. Isochronous Receive Channel Mask High Register Description ........................................................... 51
Table 39. Isochronous Receive Channel Mask Low Register Description ............................................................ 51
Table 40. Interrupt Event Register Description ...................................................................................................... 52
Table 41. Interrupt Mask Register Description ...................................................................................................... 54
Table 42. Isochronous Transmit Interrupt Event Register Description .................................................................. 56
Table 43. Isochronous Transmit Interrupt Event Description ................................................................................ 57
Table 44. Isochronous Receive Interrupt Event Description ................................................................................. 58
Table 45. Fairness Control Register Description ................................................................................................... 59
Table 46. Link Control Register Description ......................................................................................................... 60
Table 47. Node Identification Register Description ............................................................................................... 61
Table 48. PHY Core Layer Control Register Description ...................................................................................... 62
Table 49. Isochronous Cycle Timer Register Description ..................................................................................... 62
Table 50. Asynchronous Request Filter High Register Description ....................................................................... 63
Table 51. Asynchronous Request Filter Low Register Description ....................................................................... 63
Table 52. Physical Request Filter High Register Description ................................................................................ 64
Table 53. Physical Request Filter Low Register Description ................................................................................. 64
Table 54. Asynchronous Context Control Register Description ........................................................................... 65
Table 55. Asynchronous Context Command Pointer Register Description ........................................................... 66
Table 56. Isochronous Transmit Context Control Register Description ................................................................ 67
Table 57. Isochronous Transmit Context Command Pointer Register Description ............................................... 68
Table 58. Isochronous Receive Context Control Register Description .................................................................. 69
Table 59. Isochronous Receive Context Command Pointer Register Description ................................................ 70
Table 60. Isochronous Receive Context Match Register Description ................................................................... 71
Table 61. FW323 Vendor-Specific Registers Description ..................................................................................... 72
Table 62. Isochronous DMA Control Registers Description .................................................................................. 72
Table 63. Asynchronous DMA Control Registers Description ............................................................................... 73
Table 64. Link Options Register Description ......................................................................................................... 74
Table 65. PHY Core Register Map ........................................................................................................................ 75
Table 66. PHY Core Register Fields ..................................................................................................................... 76
Table 67. PHY Core Register Page 0: Port Status Page ...................................................................................... 78
Table 68. PHY Core Register Port Status Page Fields ........................................................................................ 79
Table 69. PHY Core Register Page 1: Vendor Identification Page ....................................................................... 80
Table 70. PHY Core Register Vendor Identification Page Fields .......................................................................... 80
Table 71. ac Characteristics of Serial EEPROM Interface Signals ....................................................................... 82
Table 72. NAND Tree Testing ............................................................................................................................... 85
Table 73. Absolute Maximum Ratings ................................................................................................................... 87
Table 74. Analog Characteristics ........................................................................................................................... 88
Table 75. Driver Characteristics ............................................................................................................................ 89
Table 76. Device Characteristics ........................................................................................................................... 89
Table 77. Switching Characteristics ...................................................................................................................... 90
Table 78. Clock Characteristics ............................................................................................................................. 90
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FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Features (continued)
Other Features
„
I2C serial ROM interface
„
CMOS process
„
3.3 V operation, 5 V tolerant inputs
„
NAND tree test mode
FW323 Functional Overview
The FW323 is a high-performance, PCI bus-based open host controller designed by Agere Systems Inc. for implementation of IEEE 1394a-2000 compliant systems and devices. Link-layer functions are handled by the FW323, utilizing the on-chip 1394a-2000 compliant link core and physical layer core. A high-performance and cost-effective
solution for connecting and servicing multiple IEEE 1394 (both 1394-1995 and 1394a-2000) peripheral devices can
be realized using this PHY/link OHCI device.
OHCI
ASYNCHRONOUS
DATA
TRANSFER
PCI
BUS
PCI
CORE
OHCI
ISOCHRONOUS
DATA
TRANSFER
CABLE PORT 2
LINK
CORE
PHY
CORE
CABLE PORT 1
CABLE PORT 0
ROM
I/F
5-6250 (F).f
Figure 1. FW323 Conceptual Block Diagram
FW323 Functional Description
The FW323 is comprised of four major functional sections (see Figure 1): PCI core, OHCI isochronous and
asynchronous data transfer, link core, and PHY core. The following is a general description of each of the major
sections.
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Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
FW323 Functional Description (continued)
SLAVE
CONTROL
PCI SLAVE
MASTER
CONTROL
PCI MASTER
ADDRESS/DATA
MUX
PCI BUS
PCI
CONFIGURATION
Figure 2. PCI Core Block Diagram
PCI Core
The PCI core (shown in Figure 2) serves as the interface to the PCI bus. It contains the state machines that allow
the FW323 to respond properly when it is the target of the transaction. Also, during 1394 packet transmission or
reception, the PCI core arbitrates for the PCI bus and enables the FW323 to become the bus master for reading the
different buffer descriptors and management of the actual data transfers to/from host system memory.
The PCI core also supports the PCI Bus Power Management Interface Specification v.1.1. Included in this support
is a standard power management register interface accessible through the PCI configuration space. Through this
register interface, software is able to transition the FW323 into four distinct power consumption states (D0, D1, D2,
and D3hot). This permits software to selectively increase/decrease the power consumption of the FW323 for
reasons such as periods of system inactivity or power conservation. In addition, the FW323 also includes support
for waking up the system through the generation of a power management event (PME).
The FW323 supports generation of a power management event (PME) while in the D0, D1, D2, D3hot, and D3cold
power states. To facilitate PME generation from the D3cold power state, the FW323 supports the detection of an
auxiliary power supply. If an auxiliary power supply is not present, PME generation from the D3cold power state is
disabled. Refer to the FW322 06/FW323 06 D3cold Application Note for specific implementation details of enabling
and supporting the generation of a PME wakeup event while the FW323 is in the D3cold power state.
The PCI core will support CardBus applications, per the PC Card Standard v8.0, when the CARDBUSN pin is low.
This support includes the CardBus I/O electrical requirements, the CIS (Card Information Structure) pointer,
128 bytes of memory in PCI configuration space for user-defined tuples, an additional Base Address register dedicated to CardBus registers, a serial EEPROM format to load the CIS into PCI configuration space, and the CardBus Function Event registers. The FW323 will also support the CardBus implementation of PCI power
management, including support for the CSTSCHG (CardBus status change) signal. Refer to the Application Note,
Using the FW322 06/FW323 06 in CardBus Applications, for more information.
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FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
FW323 Functional Description (continued)
ASYNCHRONOUS DATA TRANSFER
SELFID DMA
ASYNC_RX
DMA
PCI32 INTERFACE
ASYNC
REGISTER
ACCESS
PCI SLAVE
REGISTER
SELECT
PHYSICAL
REQUEST/
RESPONSE
DMA
ASYNC_TX
DMA
OHCI
INTERRUPT
HANDLER
AR FIFO
AT FIFO
ASYNC
TX
ADMIN
ISOCHRONOUS DATA TRANSFER
ISOCH
REGISTER
ACCESS
PCI MASTER
ASYNC
RX
ADMIN
ISOCH
RECEIVE
DMA
IR FIFO
ARBITER
ISOCH
TRANSMIT
DMA
IT FIFO
Figure 3. OHCI Core Block Diagram
OHCI Data Transfer
The OHCI core consists of the three blocks shown in Figure 3: the PCI interface (PCI32_interface), the isochronous
data transfer, and the asynchronous data transfer blocks. The PCI interface provides an interface between the
OHCI blocks and the PCI core. It contains an arbiter to select the appropriate OHCI data engine to gain access to
the PCI core. In addition, the PCI interface includes a register select function to decode slave accesses to the
OHCI core and select data from appropriate sources. The PCI interface also has an OHCI interrupt handler to service OHCI generated interrupts, which are ultimately translated into PCI interrupts.
OHCI Isochronous Data Transfer
The isochronous data transfer logic, which is incorporated into the OHCI core, handles the transfer of isochronous
data between the link core and the PCI interface module. It consists of the Isochronous register access module, the
isochronous transmit DMA module, the isochronous receive DMA module, the isochronous transmit (IT) FIFO, and
the isochronous receive (IR) FIFO.
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Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 Functional Description (continued)
Isochronous Register Access
The Isochronous register access module services PCI
slave accesses to OHCI registers within the isochronous block. The module also maintains the status of
interrupts generated within the isochronous block and
sends the isochronous interrupt status to the OHCI
interrupt handler block.
Isochronous Transmit DMA (ITDMA)
The isochronous transmit DMA (ITDMA) module
moves data from host memory to the link core, which
will then send the data via the PHY core to the 1394
bus. This module consists of eight isochronous
transmit contexts, each of which is independently
configurable by software, and is capable of sending
data on a separate 1394 isochronous channel.
During each 1394 isochronous cycle, the ITDMA
module will service each of the contexts and attempt to
process one 1394 packet for each active context. While
processing an active context, ITDMA will request
access to the PCI bus. When granted PCI access, a
descriptor block is fetched from host memory. This data
is decoded by ITDMA to determine how much data is
required and where in host memory the data resides.
ITDMA initiates another PCI access to fetch this data,
which is placed into the isochronous transmit FIFO for
processing by the link core. If the context is not active,
it is skipped by ITDMA for the current cycle.
After processing each context, ITDMA writes a cycle
marker word in the transmit FIFO to indicate to the link
core that there is no more data for this isochronous
cycle. As a summary, the major steps for the FW323
ITDMA to transmit a packet are the following:
1. Fetch a descriptor block from host memory.
2. Fetch data specified by the descriptor block from
host memory and place it into the isochronous
transmit FIFO.
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
When IRDMA detects that the link core has placed
data into the receive FIFO, it immediately reads out the
first word in the FIFO, which makes up the header of
the isochronous packet. IRDMA extracts the channel
number for the packet and packet filtering controls from
the header. This information is compared with the
Control registers for each context to determine if any
context is to process this packet.
If a match is found, IRDMA will request access to the
PCI bus. When granted PCI access, a descriptor block
is fetched from host memory. The descriptor provides
information about the host memory block allocated for
the incoming packet. IRDMA then reads the packet
from the receive FIFO and writes the data to host
memory via the PCI bus.
If no match is found, IRDMA will read the remainder of
the packet from the receive FIFO, but not process the
data in any way.
OHCI Asynchronous Data Transfer
The asynchronous data transfer block within the OHCI
core is functionally partitioned into blocks responsible
for processing incoming SelfID packet streams, transmitting and receiving asynchronous 1394 packets, processing incoming physical request packets and
outgoing physical response packets, and servicing
accesses to OHCI registers within the respective asynchronous blocks.
Asynchronous Register Access
The Asynchronous register access module operates on
PCI slave accesses to OHCI registers within the asynchronous block. The module also maintains the status
of interrupts generated within the asynchronous block
and sends the asynchronous interrupt status to the
OHCI interrupt handler block.
3. Data in FIFO is read by the link and sent to the PHY
core device interface.
Isochronous Receive DMA (IRDMA)
The isochronous receive DMA (IRDMA) module moves
data from the isochronous receive FIFO to host
memory. It consists of eight isochronous contexts, each
of which is independently controlled by software.
Normally, each context can process data on a single
1394 isochronous channel. However, software can
select one context to receive data on multiple channels.
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FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
FW323 Functional Description (continued)
The header of the received packet is processed to
determine, among other things, the following:
Asynchronous Transmit DMA (ASYNC_TX DMA,
ASYNC_TX_ADMIN)
1. The type of packet received.
2. The source and destinations.
3. The data and size, if any.
4. Any required operation, for example, compare and
swap operation.
The ASYNC_TX DMA and ASYNC_TX_ADMIN blocks
of the FW323 manage the asynchronous transmission
of either request or response packets. The mechanism
for asynchronous transmission of requests and
responses is similar. The only difference is the system
memory location of the buffer descriptor list when
processing the two contexts. Therefore, the discussion
below, which pertains to asynchronous transmit
requests, parallels that of asynchronous transmit
responses.
The FW323 asynchronous transmission of packets
involves the following steps:
1. Fetch complete buffer descriptor block from host
memory.
2. Get data from system memory and store into
asynchronous transmit (AT) FIFO.
3. Request transfer of data from FIFO to the link core.
4. Handle retries, if any.
5. Handle errors in steps 1 to 4.
6. End the transfer if there are no errors.
Asynchronous Receive DMA (ASYNC_RX DMA,
ASYNC_RX_ADMIN)
The ASYNC_RX DMA and ASYNC_RX_ADMIN blocks
of the FW323 manage the processing of received
packets. Data packets are parsed and stored in a
dedicated asynchronous receive (AR) FIFO. Command
descriptors are read through the PCI interface to
determine the disposition of the data arriving through
the 1394 link.
10
The asynchronous data transfer block also handles
DMA transfers of SelfID packets during the 1394 bus
initialization phase and block transactions associated
with physical requests.
Physical Request/Response DMA
The Physical DMA block within the FW323 is responsible for processing incoming physical requests and outgoing physical responses. When an incoming
asynchronous packet is received, the FW323 will process the packet automatically without software intervention if the packet meets a set of criteria defined
within the OHCI specification. When the criteria are
met, the asynchronous packet is reclassified as a physical packet. Requests that do not meet the criteria
remain asynchronous packets and are processed as
described above in the Asynchronous Receive DMA
section. Processing packets as physical requests/
responses allows the FW323 to either receive or transmit an asynchronous packet without the use of DMA
descriptors. Instead, the FW323 directly writes or reads
data to/from memory using the address defined within
the packet header. Since physical packets can be processed independently of the system’s software and
CPU, processing a packet as physical results in a system performance optimization.
SelfID DMA
The SelfID DMA block within the FW323 is responsible
for receiving SelfID packets during the bus initialization
process. The received SelfID packets are written into a
software-defined host memory buffer.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
FW323 Functional Description (continued)
ISOCH
CONTROL
TIMER
AT FIFO
TX
IT FIFO
PHYDATA
CRC
DATAMUX
AR FIFO
PHY - LINK
INTERFACE
PHYCTL
RX
IR FIFO
ADDRESS
DECODER
PCI SLAVE
LINK CONTROL
STATE
MACHINE
PHYLREQ
INTERFACE
CONTROL
Figure 4. Link Core Block Diagram
Link Core
The link core shown in Figure 4 consists of the following blocks:
„
Link Control State Machine: main link state machine that controls all other link core modules.
„
Transmit (TX): reads from the AT and IT FIFOs and forms 1394 packets for transmit.
„
Receive (RX): pipes incoming 1394 packet data to appropriate FIFO (if any).
„
Address Decoder: decodes the destination ID of an incoming 1394 packet to determine if an acknowledge is
needed.
„
CRC: calculates and checks CRC on outgoing and incoming packets.
„
Isochronous Control Timer: contains the logic for the 1394 cycle timer.
„
DataMUX: pipes 1394 data to and from various modules.
„
Interface Control: contains interrupt and registers for the link core. Interfaces with the slave control block of the
PCI core.
„
PHY-Link Interface: interfaces with the 1394 physical layer.
Agere Systems Inc.
11
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
FW323 Functional Description (continued)
It is the responsibility of the link to ascertain if a
received packet is to be forwarded to the OHCI for
processing. If so, the packet is directed to a proper
inbound FIFO for either the isochronous block or the
asynchronous block to process. The link is also
responsible for CRC generation on outgoing packets
and CRC checking on received packets.
Data Sheet, Rev. 1
December 2005
To become aware of data to be sent outbound on the
1394 bus, the link must monitor the OHCI FIFOs looking for packets in need of transmission. Based on data
received from the OHCI block, the link will form packet
headers for the 1394 bus. The link will alert the PHY
core regarding the availability of the outbound data. It is
the link’s function to generate CRC for the outbound
data. The link also provides PHY core register access
for the OHCI.
RECEIVED
DATA
DECODER/
RETIMER
CPS
LPS
SYSCLK
LREQ
BIAS
VOLTAGE
AND
CURRENT
GENERATOR
R0
R1
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
LKON
PC0
PC1
PC2
LINK
INTERFACE
I/O
TPA0+
TPA0–
ARBITRATION
AND
CONTROL
STATE
MACHINE
LOGIC
TPBIAS0
CABLE PORT 0
TPB0+
TPB0–
CONTENDER
SE
SM
RESETN
TRANSMIT
DATA
ENCODER
CABLE PORT 1
TPA1+
TPA1–
TPBIAS1
TPB1+
TPB1–
CABLE PORT 2
TPA2+
TPA2–
TPBIAS2
TPB2+
TPB2–
CRYSTAL
OSCILLATOR,
PLL SYSTEM,
AND
CLOCK
GENERATOR
XI
XO
5-5459.i(F) R.01
Figure 5. The PHY Core Block Diagram
12
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 Functional Description (continued)
PHY Core
The PHY core in Figure 5 on the preceding page, provides the analog physical layer functions needed to
implement a three-port node in a cable-based IEEE
1394-1995 and IEEE 1394a-2000 network.
Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor
the line conditions as needed for determining connection status, for initialization and arbitration, and for
packet reception and transmission. The PHY core
interfaces with the link core.
The PHY core requires either an external 24.576 MHz
crystal or crystal oscillator. The internal oscillator
drives an internal phase-locked loop (PLL), which generates the required 393.216 MHz reference signal. The
393.216 MHz reference signal is internally divided to
provide the 49.152 MHz, 98.304 MHz, and
196.608 MHz clock signals that control transmission of
the outbound encoded strobe and data information.
The 49.152 MHz clock signal is also supplied to the
associated link layer controller (LLC) for synchronization of the link with the PHY core and is used for
resynchronization of the received data.
The PHY/link interface is a direct connection and does
not provide isolation.
Data bits to be transmitted through the cable ports are
received from the LLC on two, four, or eight data lines
(D[0:7]), and are latched internally in the PHY in synchronization with the 49.152 MHz system clock. These
bits are combined serially, encoded, and transmitted at
98.304 Mbits/s, 196.608 Mbits/s, or 393.216 Mbits/s as
the outbound data-strobe information stream. During
transmission, the encoded data information is transmitted differentially on the TPA and TPB cable pair(s).
During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled, and the
receivers for that port are enabled. The encoded data
information is received on the TPA and TPB cable pair.
The received data strobe information is decoded to
recover the receive clock signal and the serial data
bits. The serial data bits are split into two (for S100),
four (for S200), or eight (for S400) parallel streams,
resynchronized to the local system clock, and sent to
the associated LLC. The received data is also transmitted (repeated) out of the other active (connected) cable
ports.
Agere Systems Inc.
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Both the TPA and TPB cable interfaces incorporate
differential comparators to monitor the line states during initialization and arbitration. The outputs of these
comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors
the incoming cable common-mode voltage. The value
of this common-mode voltage is used during arbitration to set the speed of the next packet transmission.
In addition, the TPB channel monitors the incoming
cable common-mode voltage for the presence of the
remotely supplied twisted-pair bias voltage. This
monitor is called bias-detect.
The TPBIAS circuit monitors the value of incoming
TPA pair common-mode voltage when local TPBIAS is
inactive. Because this circuit has an internal current
source and the connected node has a current sink, the
monitored value indicates the cable connection status.
The monitor is called connect-detect.
Both the TPB bias-detect monitor and TPBIAS
connect-detect monitor are used in suspend/resume
signaling and cable connection detection.
The PHY core provides a 1.86 V nominal bias voltage
for driver load termination. This bias voltage, when
seen through a cable by a remote receiver, indicates
the presence of an active connection. The value of this
bias voltage has been chosen to allow interoperability
between transceiver chips operating from 5 V or 3 V
nominal supplies. This bias voltage source should be
stabilized by using an external filter capacitor of
approximately 0.33 µF.
The port transmitter circuitry and the receiver circuitry
are disabled when the port is disabled, suspended, or
disconnected.
The line drivers in the PHY core operate in a highimpedance current mode and are designed to work
with external 112 Ω line-termination resistor networks.
One network is provided at each end of each twistedpair cable. Each network is composed of a pair of
series-connected 56 Ω resistors. The midpoint of the
pair of resistors that is directly connected to the
twisted-pair A (TPA) signals is connected to the
TPBIAS voltage signal. The midpoint of the pair of
resistors that is directly connected to the twisted-pair B
(TPB) signals is coupled to ground through a parallel
RC network with recommended resistor and capacitor
values of 5 kΩ and 220 pF, respectively. The values of
the external resistors are specified to meet the 1394a2000 Specification when connected in parallel with the
internal receiver circuits.
13
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
FW323 Functional Description (continued)
An external resistor sets the driver output current,
along with other internal operating currents. This
resistor is connected between the R0 and R1 signals
and has a value of 2.49 kΩ ± 1%.
Four signals are used as inputs to set four
configuration status bits in the self-identification
(SelfID) packet. These signals are hardwired high or
low as a function of the equipment design. PC[0:2] are
the three signals that indicate either the need for
power from the cable or the ability to supply power to
the cable. The fourth signal (CONTENDER), as an
input, indicates whether a node is a contender for bus
manager. When the CONTENDER signal is asserted,
it means the node is a contender for bus manager.
When the signal is not asserted, it means that the
node is not a contender. The contender bit
corresponds to the c field (bit 20) in the SelfID packet.
PC[0:2] corresponds to the pwr field of the SelfID
packet in the following manner: PC0 corresponds to bit
21, PC1 corresponds to bit 22, and PC2 corresponds
to bit 23 (see SelfID packets table in Section 4.3.4.1 of
the IEEE 1394-1995 and 1394a-2000 standards for
additional details). As an example, for a Power_Class
value of 001, PC0 = 0, PC1 = 0, and PC2 = 1.
When the power supply of the PHY core is removed
while the twisted-pair cables are connected, the PHY
core transmitter and receiver circuitry has been
designed to present a high impedance to the cable in
order to not load the TPBIAS signal voltage on the
other end of the cable.
Data Sheet, Rev. 1
December 2005
Note: All gap counts on all nodes of a 1394 bus must
be identical. The software accomplishes this by
issuing PHY core configuration packets (see
Section 4.3.4.3 of IEEE 1394-1995 and 1394a2000 standards) or by issuing two bus resets,
which resets the gap counts to the maximum
level (3Fh).
The internal link power status (LPS) signal works with
the internal LKON signal to manage the LLC power
usage of the node. The LPS signal indicates if the LLC
of the node is powered up or down. If LPS is inactive
for more than 1.2 µs and less than 25 µs, the internal
PHY/link interface is reset.
If LPS is inactive for greater than 25 µs, the PHY will
disable the internal PHY/link interface to save power.
The FW323 continues its repeater function even when
the PHY/link interface is disabled. If the PHY then
receives a link-on packet, the internal LKON signal is
activated to output a 6.114 MHz signal, which can be
used by the LLC to power itself up. Once the LLC is
powered up, the internal LPS signal communicates this
to the PHY and the internal PHY/link interface is
enabled. The internal LKON signal is turned off when
the LCtrl bit is set. (For more information on this bit,
refer to the Table 66 on PHY Core Register Fields in
this data sheet.)
Three of the FW323 pins are used to set up various
test conditions used only during the device
manufacturing process. These pins are SE, SM, and
PTEST.
Whenever the TPA±/TPB± signals are wired to a
connector, they must be terminated using the normal
termination network. This is required for reliable
operation. For those applications when one or more of
the FW323 ports are not wired to a connector, those
unused ports may be left unconnected without normal
termination. When a port does not have a cable
connected, internal connect-detect circuitry will keep
the port in a disconnected state.
14
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
VAUX_PRESENT
NU
SE
SM
PTEST
RESETN
XO
XI
PLLVSS
PLLVDD
R1
R0
VDDA
VSSA
TPBIAS0
TPA0+
TPA0–
TPB0+
TPB0–
TPBIAS1
TPA1+
TPA1–
TPB1+
TPB1–
VDDA
VSSA
Pin Information
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VSSA
TPBIAS2
TPA2+
TPA2–
TPB2+
TPB2–
VDDA
VSSA
CPS
VDD
MPCIACTN
LPS
LKON
PC0
PC1
PC2
CONTENDER
PCI_VIOS
PCI_AD[0]
PCI_AD[1]
VDD
VSS
PCI_AD[2]
PCI_AD[3]
PCI_AD[4]
VSS
PCI_AD[5]
PCI_AD[6]
PCI_AD[7]
PCI_CBEN[0]
VDD
VSS
PCI_AD[8]
PCI_AD[9]
PCI_AD[10]
PCI_AD[11]
VSS
PCI_AD[12]
PCI_AD[21]
PCI_AD[20]
PCI_AD[19]
PCI_AD[18]
VDD
VSS
PCI_AD[17]
PCI_AD[16]
PCI_CBEN[2]
PCI_FRAMEN
VDD
VSS
PCI_IRDYN
PCI_TRDYN
PCI_DEVSELN
PCI_STOPN
VDD
VSS
PCI_PERRN
PCI_SERRN
PCI_PAR
PCI_CBEN[1]
VSS
PCI_AD[15]
PCI_AD[14]
PCI_AD[13]
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VDD
VSS
CARDBUSN
NU
CNA
NANDTREE
TEST1
ROM_CLK
ROM_AD
TEST0
VDD
VSS
CLKRUNN
PCI_INTAN
PCI_RSTN
PCI_GNTN
PCI_REQN
PCI_PMEN/CSTSCHG
VDD
PCI_CLK
VSS
PCI_AD[31]
PCI_AD[30]
PCI_AD[29]
PCI_AD[28]
VDD
VSS
PCI_AD[27]
PCI_AD[26]
PCI_AD[25]
PCI_AD[24]
VSS
PCI_CBEN[3]
PCI_IDSEL
PCI_AD[23]
PCI_AD[22]
VDD
VSS
5-7838 (F)a R.03
Note: Active-low signals within this document are indicated by an N following the symbol names.
Figure 6. Pin Assignments for the FW323 06
Agere Systems Inc.
15
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Pin Information (continued)
Table 1. Pin Descriptions
Pin
Symbol*
Type
Description
1
2
3
VDD
VSS
CARDBUSN
—
—
I
4
5
NU
CNA
—
O
6
NANDTREE
O
7
TEST1
I
8
9
10
ROM_CLK
ROM_AD
TEST0
I/O
I/O
I
11
12
13
VDD
VSS
CLKRUNN
—
—
I/O
14
15
16
17
18
PCI_INTAN
PCI_RSTN
PCI_GNTN
PCI_REQN
PCI_PMEN/CSTSCHG
O
I
I
O
O
19
20
21
22
23
24
25
26
VDD
PCI_CLK
VSS
PCI_AD[31]
PCI_AD[30]
PCI_AD[29]
PCI_AD[28]
VDD
—
I
—
I/O
I/O
I/O
I/O
—
Digital Power.
Digital Ground.
CardBusN (Active-Low). Selects mode of operation for PCI output
buffers. Connect this pin to ground for CardBus operation; connect to
VDD for PCI operation.
Not Usable. No external connections to this pin are allowed.
Cable Not Active. CNA output is provided for use in legacy power
management systems. CNA is asserted high when none of the PHY
ports is receiving an incoming bias voltage. This circuit remains
active during the powerdown mode. The CNA pin is TTL-compatible.
This pin can source and sink up to a 6 mA load.
NAND Tree Test Output. When the chip is placed into the NAND
tree test mode, the pin is the output of the NAND tree logic. This pin
is not used during normal operation.
Test. Used by Agere for device manufacturing testing. Tie to VSS for
normal operation.
ROM Clock.
ROM Address/Data.
Test. Used by Agere for device manufacturing testing. Tie to VSS for
normal operation.
Digital Power.
Digital Ground.
CLKRUNN (Active-Low). Optional signal for PCI mobile computing
environment. If not used, CLKRUNN pin needs to be pulled down to
VSS for correct operation.
PCI Interrupt (Active-Low).
PCI Reset (Active-Low).
PCI Grant Signal (Active-Low).
PCI Request Signal (Active-Low).
PCI Power Management Event (Active-Low)/CardBus Status
Changed (Active-High). When the CARDBUSN signal is high (i.e.,
when the FW323 is communicating directly with the PCI bus and not
the CardBus), a PCI power management event will be indicated if this
signal is low. When the CARDBUSN signal is low (indicating the
FW323 is in CardBus mode), this pin signals that the CardBus status
has changed when it is active-high. (See PC Card Standard, v. 8.0,
Volume 2, Section 5.2.11 for more information regarding CSTSCHG.)
Digital Power.
PCI Clock Input. 33 MHz.
Digital Ground.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Digital Power.
* Active-low signals within this document are indicated by an N following the symbol names.
16
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol*
Type
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
VSS
PCI_AD[27]
PCI_AD[26]
PCI_AD[25]
PCI_AD[24]
VSS
PCI_CBEN[3]
PCI_IDSEL
PCI_AD[23]
PCI_AD[22]
VDD
VSS
PCI_AD[21]
PCI_AD[20]
PCI_AD[19]
PCI_AD[18]
VDD
VSS
PCI_AD[17]
PCI_AD[16]
PCI_CBEN[2]
PCI_FRAMEN
VDD
VSS
PCI_IRDYN
PCI_TRDYN
PCI_DEVSELN
PCI_STOPN
VDD
VSS
PCI_PERRN
PCI_SERRN
PCI_PAR
PCI_CBEN[1]
VSS
PCI_AD[15]
PCI_AD[14]
PCI_AD[13]
PCI_AD[12]
VSS
PCI_AD[11]
PCI_AD[10]
PCI_AD[9]
—
I/O
I/O
I/O
I/O
—
I/O
I
I/O
I/O
—
—
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
Description
Digital Ground.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Digital Ground.
PCI Command/Byte Enable (Active-Low).
PCI ID Select.
PCI Address/Data Bit.
PCI Address/Data Bit.
Digital Power.
Digital Ground.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Digital Power.
Digital Ground.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Command/Byte Enable Signal (Active-Low).
PCI Frame Signal (Active-Low).
Digital Power.
Digital Ground.
PCI Initiator Ready Signal (Active-Low).
PCI Target Ready Signal (Active-Low).
PCI Device Select Signal (Active-Low).
PCI Stop Signal (Active-Low).
Digital Power.
Digital Ground.
PCI Parity Error Signal (Active-Low).
PCI System Error Signal (Active-Low).
PCI Parity Signal.
PCI Command/Byte Enable Signal (Active-Low).
Digital Ground.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Digital Ground.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
* Active-low signals within this document are indicated by an N following the symbol names.
Agere Systems Inc.
17
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol*
Type
Description
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
PCI_AD[8]
VSS
VDD
PCI_CBEN[0]
PCI_AD[7]
PCI_AD[6]
PCI_AD[5]
VSS
PCI_AD[4]
PCI_AD[3]
PCI_AD[2]
VSS
VDD
PCI_AD[1]
PCI_AD[0]
PCI_VIOS
I/O
—
—
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
—
—
I/O
I/O
—
86
CONTENDER
I
87
88
89
PC2
PC1
PC0
I
90
LKON
O
91
LPS
O
92
MPCIACTN
O
93
VDD
—
PCI Address/Data Bit.
Digital Ground.
Digital Power.
PCI Command/Byte Enable Signal (Active-Low).
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Digital Ground.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Address/Data Bit.
Digital Ground.
Digital Power.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Signaling Indicator. For PCI applications that use a universal
expansion board (see PCI Local Bus Specification, Rev. 2.2, Section 4.1.1), connect this pin to the VI/O pin. For Cardbus applications, connect this pin to 3.3 V. For other cases, connect this pin to
3.3 V for PCI buses using 3.3 V signaling or to 5 V for PCI buses
using 5 V signaling.
Contender. On hardware reset (RESETN), this input sets the
default value of the CONTENDER bit indicated during SelfID. This
bit can be tied to VDD (high), so it will be considered for bus
manager or to ground (low) to not be considered for bus manager.
Power-Class Indicators. On hardware reset (RESETN), these
inputs set the default value of the power class indicated during
SelfID. These bits can be tied to VDD (high) or to ground (low) as
required for particular power consumption and source characteristics. In SelfID packet (see Section 4.3.4.1 of the 1394a-2000 Specification), PC0, the most significant bit of this 3-bit field,
corresponds to bit 21, PC1 corresponds to bit 22, and PC2 corresponds to bit 23. As an example, for a Power_Class value of 001,
PC0 = 0, PC1 = 0, and PC2 = 1.
Link On. Signal from the internal PHY core to the internal link core.
This signal is provided as an output for use in legacy power
management systems.
Link Power Status. Signal from the internal link core to the internal
PHY core. LPS is provided as an output for use in legacy power
management systems.
Mini PCI Function Active. An active-low output used only in Mini
PCI applications. A low indicates that the FW323 requires full
system performance. If MPCIACTN is low, the FW323 requires that
the system not be in a low-power state.
Digital Power.
* Active-low signals within this document are indicated by an N following the symbol names.
18
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol*
Type
Description
94
CPS
I
95
VSSA
—
96
VDDA
—
97
TPB2–
Analog I/O
98
TPB2+
99
TPA2–
100
TPA2+
101
TPBIAS2
Analog I/O
102
VSSA
—
103
VSSA
—
104
VDDA
—
105
TPB1–
Analog I/O
106
TPB1+
Cable Power Status. CPS is normally connected to the cable
power through a 400 kΩ resistor. This circuit drives an internal
comparator that detects the presence of cable power. This information is maintained in one internal register and is available to the
LLC by way of a register read (see IEEE 1394a-2000, Standard for
a High Performance Serial Bus, Sections 4.2.2.7 and 5B.1).
Note: This pin can be left unconnected for applications that do not
use 1394 bus power (VP). When this pin is grounded, the
PWR_FAIL bit in PHY register 01012 will set.
Analog Circuit Ground. All VSSA signals should be tied together to
a low-impedance ground plane.
Analog Circuit Power. VDDA supplies power to the analog portion
of the device.
Port 2, Port Cable Pair B. TPB2± is the port B connection to the
twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as
possible to the external load resistors and to the cable connector.
When the FW323’s 1394 port pins are not wired to a connector, the
unused port pins may be left unconnected. Internal connect-detect
circuitry will keep the port in a disconnected state.
Port 2, Port Cable Pair A. TPA2± is the port A connection to the
twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as
possible to the external load resistors and to the cable connector.
When the FW323’s 1394 port pins are not wired to a connector, the
unused port pins may be left unconnected. Internal connect-detect
circuitry will keep the port in a disconnected state.
Port 2, Twisted-Pair Bias. TPBIAS2 provides the 1.86 V nominal
bias voltage needed for proper operation of the twisted-pair cable
drivers and receivers and for sending a valid cable connection signal
to the remote nodes. When the FW323’s 1394 port pins are not
wired to a connector, the unused port pins may be left unconnected.
Internal connect-detect circuitry will keep the port in a disconnected
state.
Analog Circuit Ground. All VSSA signals should be tied together to
a low-impedance ground plane.
Analog Circuit Ground. All VSSA signals should be tied together to
a low-impedance ground plane.
Analog Circuit Power. VDDA supplies power to the analog portion of
the device.
Port 1, Port Cable Pair B. TPB1± is the port B connection to the
twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as
possible to the external load resistors and to the cable connector.
When the FW323’s 1394 port pins are not wired to a connector, the
unused port pins may be left unconnected. Internal connect-detect
circuitry will keep the port in a disconnected state.
Analog I/O
* Active-low signals within this document are indicated by an N following the symbol names.
Agere Systems Inc.
19
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol*
Type
Description
107
TPA1–
Analog I/O
108
TPA1+
109
TPBIAS1
Analog I/O
110
TPB0–
Analog I/O
111
TPB0+
112
TPA0–
113
TPA0+
114
TPBIAS0
Analog I/O
115
VSSA
—
116
VDDA
—
117
R0
I
118
R1
119
PLLVDD
—
120
PLLVSS
—
Port 1, Port Cable Pair A. TPA1± is the port A connection to the
twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as
possible to the external load resistors and to the cable connector.
When the FW323’s 1394 port pins are not wired to a connector, the
unused port pins may be left unconnected. Internal connect-detect
circuitry will keep the port in a disconnected state.
Port 1, Twisted-Pair Bias. TPBIAS1 provides the 1.86 V nominal
bias voltage needed for proper operation of the twisted-pair cable
drivers and receivers and for sending a valid cable connection signal
to the remote nodes. When the FW323’s 1394 port pins are not
wired to a connector, the unused port pins may be left unconnected.
Internal connect-detect circuitry will keep the port in a disconnected
state.
Port 0, Port Cable Pair B. TPB0± is the port B connection to the
twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as
possible to the external load resistors and to the cable connector.
When the FW323’s 1394 port pins are not wired to a connector, the
unused port pins may be left unconnected. Internal connect-detect
circuitry will keep the port in a disconnected state.
Port 0, Port Cable Pair A. TPA0± is the port A connection to the
twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as
possible to the external load resistors and to the cable connector.
When the FW323’s 1394 port pins are not wired to a connector, the
unused port pins may be left unconnected. Internal connect-detect
circuitry will keep the port in a disconnected state.
Port 0, Twisted-Pair Bias. TPBIAS0 provides the 1.86 V nominal
bias voltage needed for proper operation of the twisted-pair cable
drivers and receivers and for sending a valid cable connection signal
to the remote nodes. When the FW323’s 1394 port pins are not
wired to a connector, the unused port pins may be left unconnected.
Internal connect-detect circuitry will keep the port in a disconnected
state.
Analog Circuit Ground. All VSSA signals should be tied together to
a low-impedance ground plane.
Analog Circuit Power. VDDA supplies power to the analog portion of
the device.
Current Setting Resistor. An internal reference voltage is applied to
a resistor connected between R0 and R1 to set the operating current
and the cable driver output current. A low temperature-coefficient
resistor (TCR) with a value of 2.49 kΩ ± 1% should be used to meet
the IEEE 1394-1995 standard requirements for output voltage limits.
Power for PLL Circuit. PLLVDD supplies power to the PLL circuitry
portion of the device.
Ground for PLL Circuit. PLLVSS is tied to a low-impedance ground
plane.
Analog I/O
* Active-low signals within this document are indicated by an N following the symbol names.
20
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol*
Type
Description
121
XI
Analog I/O
122
XO
123
RESETN
I
124
PTEST
I
125
SM
I
126
SE
I
127
128
NU
VAUX_PRESENT
—
I
Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel
resonant fundamental mode crystal. Although when a 24.576 MHz
clock source is used, it can be connected to XI with XO left unconnected. The optimum values for the external shunt capacitors are
dependent on the specifications of the crystal used. It is necessary to
add an external series resistor to the XO pin. The value of the resistor
is nominally 400 Ω. For more details, refer to the Crystal Selection
Considerations section in this data sheet. Note that it is very important to place the crystal as close as possible to the XO and XI pins,
i.e., within 0.5 in./1.27 cm. For more important details regarding the
crystal, refer to the FW323/FW322 Hardware Implementation Design
Guideline Application Note.
Reset (Active-Low). When RESETN is asserted low (active), a 1394
bus reset condition is set on the active cable port and the FW323 is
reset to the reset start state. To guarantee that the PHY will reset,
this pin must be held low for at least 2 ms. An internal pull-up resistor,
connected to VDD, is provided, so only an external delay capacitor
(0.1 µF) and resistor (510 kΩ), in parallel, are required to connect this
pin to ground. This circuitry will ensure that the capacitor will be
discharged when PHY power is removed. The input is a standard
logic buffer and can also be driven by an open-drain logic output
buffer. Do not leave this pin unconnected. This pin is also used with
the EEPROM interface. It is the powerup reset pin. This pin is
asserted low (active) to indicate a powerup reset. Refer to the FW322
06/FW323 06 EEPROM Interface and Start-up Behavior Application
Note sections titled Initiation of EEPROM Load and Initial Powerup.
Test. Used by Agere for device manufacturing testing. Tie to VSS for
normal operation.
Test Mode Control. SM is used during Agere’s manufacturing test
and should be tied to VSS for normal operation.
Test Mode Control. SE is used during Agere’s manufacturing test
and should be tied to VSS for normal operation.
Not Usable. No external connections to this pin are allowed.
3.3 Vaux Present. An active-high input indicating whether the
FW323 is powered via an auxiliary power supply (e.g., PCI 3.3 Vaux).
An internal pull-down resistor connected to VSS is provided, so an
external pull-up is only required when the device is being powered by
an auxiliary power supply. Note that VAUX_PRESENT is not an
actual power supply pin to the device. Rather, this pin is an indicator
of whether the FW323 is powered via an auxiliary power supply
(VAUX_PRESENT = 1) or the regular PCI power supply
(VAUX_PRESENT = 0). This input is used by the FW323 to properly
support the D3cold power management functionality.
* Active-low signals within this document are indicated by an N following the symbol names.
Note: For those applications when one or more FW323 ports are not wired to a connector, those unused ports may be left unconnected without
normal termination. When a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected
state.
Agere Systems Inc.
21
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers
This section provides a summary of the internal registers within the FW323, including both PCI Configuration registers and OHCI registers. Register default values, registers, bits that have not been implemented in the FW323, and
other information specific to the FW323 will be noted.
Please refer to the PCI Local Bus Specification v.2.2, PCI Bus Power Management Interface Specification, v.1.1,
1394 OHCI specification v.1.1, and the IEEE standard 1394a-2000 Specification for further details concerning these
registers.
Table 2 describes the field access tags that are designated in the Type column of the register tables in this
document.
Table 2. Bit-Field Access Tag Description
Access Tag
Name
R
W
S
C
U
Read
Write
Set
Clear
Update
Description
Field may be read by software.
Field may be written by software to any value.
Field may be set by a write of 1. Writes of 0 have no effect.
Field may be cleared by a write of 1. Writes of 0 have no effect.
Field may be autonomously updated by the FW323.
PCI Configuration Registers
Table 3a and Table 3b illustrates the PCI configuration header that includes both the predefined portion of the
configuration space and the user-definable registers. Note that there are two mutually exclusive versions of this
header: one for PCI applications (CardBusN = 1) and one for CardBusN applications (CardBusN = 0).
Table 3a. PCI Configuration Register Map, CardBusN = 1
Register Name [default]
Offset
Device ID [5811h]
Vendor ID [11C1h]
00h
Status [02901h]
Command [0000h]
04h
Class Code [0C0010h]
BIST [00h]
Header Type [00h]
Latency Timer† [00h]
Revision ID [6xh]*
08h
Cache Line Size†
[00h]
0Ch
OHCI Base Address Register [0000 0000h]
10h
Reserved
14h
Reserved
18h
Reserved
1Ch
Reserved
20h
Reserved
24h
CardBus CIS Pointer [0000 0000h]
28h
Subsystem ID† [0000h]
Subsystem Vendor ID† [0000h]
Reserved
Reserved
30h
PCI Power Management Capabilities
Pointer [44h]
Reserved
Latency†
Maximum
[18h]
Grant†
Minimum
[0Ch]
Interrupt Pin [01h]
2Ch
34h
38h
Interrupt Line [00h]
3Ch
* x is a minor revision number of the FW323 06 and may be any value from 0 hex to F hex.
† Values for this register can be loaded from a serial EEPROM during the powerup sequence.
22
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Table 3a. PCI Configuration Register Map, CardBusN = 1 (continued)
Register Name [default]
Offset
Register † [0000
PCI OHCI Control
Power Management Capabilities †, ‡ [FFC2h]
Pm Data † [00h]
Pmcsr_bse [00h]
0000h]
Next Item Pointer
Capability ID [01h]
[00h]
Power Management CSR‡ [0000h]
Reserved
40h
44h
48h
4C—FCh
† Values for this register can be loaded from a serial EEPROM during the powerup sequence.
‡ Value for this register is affected by the state of the VAUX_PRESENT input pin.
Table 3b. PCI Configuration Register Map, CardBusN = 0
Register Name [default]
Offset
Device ID [5811h]
Vendor ID [11C1h]
00h
Status [02901h]
Command [0000h]
04h
Class Code [0C0010h]
BIST [00h]
Header Type [00h]
Latency Timer † [00h]
Revision ID [6xh] *
08h
Cache Line Size†
[00h]
0Ch
OHCI Base Address Register [0000 0000h]
10h
CardBus Base Address Register [0000 0000h]
14h
Reserved
18h
Reserved
1Ch
Reserved
20h
Reserved
24h
CardBus CIS Pointer [0000 0080h]
28h
Subsystem ID† [0000h]
Subsystem Vendor ID† [0000h]
Reserved
Reserved
30h
PCI Power Management Capabilities
Pointer [44h]
Reserved
Latency †
2Ch
Grant †
34h
38h
Minimum
Interrupt Pin [01h]
Interrupt Line [00h]
[0Ch]
PCI OHCI Control Register † [0000 0000h]
Power Management Capabilities †, ‡ [FFC2h]
Next Item Pointer
Capability ID [01h]
[00h]
Pm Data † [00h]
Pmcsr_bse [00h]
Power Management CSR ‡ [0000h]
3Ch
Reserved
CIS†
4C—7Ch
80—FCh
Maximum
[18h]
40h
44h
48h
* x is a minor revision number of the FW323 06 and may be any value from 0 hex to F hex.
† Values for this register can be loaded from a serial EEPROM during the powerup sequence.
‡ Value for this register is affected by the state of the VAUX_PRESENT input pin.
Agere Systems Inc.
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FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Vendor ID Register
The Vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the device. The
vendor ID assigned to Agere is 11C1h.
Offset:
Default:
Type:
Reference:
00h
11C1h
Read only
PCI Local Bus Specification, Rev. 2.2, Section 6.2.1
Device ID Register
The Device ID register contains a value assigned to the FW323 by Agere. The device identification for the FW323
is 5811h.
Offset:
Default:
Type:
Reference:
24
02h
5811h
Read only
PCI Local Bus Specification, Rev. 2.2, Section 6.2.1
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
PCI Command Register
The Command register provides control over the FW323 interface to the PCI bus. All bit functions adhere to the
definitions in the PCI Local Bus Specification, as in the following bit descriptions.
Offset:
Default:
Type:
Reference:
04h
0000h
Read/write
PCI Local Bus Specification, Rev. 2.2, Section 6.2.2 and 1394 Open Host Controller Interface
Specification, Rev. 1.1, Section A.3.1
Table 4. PCI Command Register Description
Bit
Field Name
Type
Description
15:10
9
Reserved
FBB_ENB
R
R
8
SERR_ENB
RW
7
STEP_ENB
R
6
PERR_ENB
RW
5
VGA_ENB
R
4
MWI_ENB
RW
3
SPECIAL
R
2
MASTER_ENB
RW
1
MEMORY_ENB
RW
0
IO_ENB
R
Reserved. Bits 15:10 return 0s when read.
Fast Back-to-Back Enable. The FW323 does not generate fast back-toback transactions; thus, this bit returns 0 when read.
SERR Enable. When this bit is set, the FW323 SERR driver is enabled.
PCI_SERRN can be asserted after detecting an address parity error on
the PCI bus.
Address/Data Stepping Control. The FW323 does not support
address/data stepping; thus, this bit is hardwired to 0.
Parity Error Enable. When this bit is set, the FW323 is enabled to drive
PERR response to parity errors through the PCI_PERRN signal.
VGA Palette Snoop Enable. The FW323 does not feature VGA palette
snooping. This bit returns 0 when read.
Memory Write and Invalidate Enable. When this bit is set, the FW323
is enabled to generate MWI PCI bus commands. If this bit is reset, then
the FW323 generates memory write commands instead.
Special Cycle Enable. The FW323 function does not respond to special
cycle transactions. This bit returns 0 when read.
Bus Master Enable. When this bit is set, the FW323 is enabled to
initiate cycles on the PCI bus.
Memory Response Enable. Setting this bit enables the FW323 to
respond to memory cycles on the PCI bus. This bit must be set to access
OHCI registers.
I/O Space Enable. The FW323 does not implement any I/O mapped
functionality; thus, this bit returns 0 when read.
Agere Systems Inc.
25
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
PCI Status Register
The Status register provides status information for PCI bus related events. All bit functions adhere to the
definitions in the PCI Local Bus Specification, v.2.2, Table 6.2.
Offset:
Default:
Type:
Reference:
06h
0290h
Read/write
PCI Local Bus Specification, Rev. 2.2, Section 6.2.3 and 1394 Open Host Controller Interface
Specification, Rev. 1.1, Section A.3.2
Table 5. PCI Status Register
Bit
Field
Name
Type
15
PAR_ERR
RCU
14
SYS_ERR
RCU
13
MABORT
RCU
12
TABORT_REC
RCU
11
TABORT_SIG
RCU
10:9
PCI_SPEED
R
8
DATAPAR
RCU
7
FBB_CAP
R
6
5
Reserved
66MHZ
R
R
4
CAPLIST
R
3:0
Reserved
R
26
Description
Detected Parity Error. This bit must be set by the device whenever it
detects a parity error, even if parity error handling is disabled.
Signaled System Error. This bit must be set whenever the device
asserts SERR#.
Received Master Abort. This bit must be set by a master device
whenever its transaction (except for special cycle) is terminated with
master-abort.
Received Target Abort. This bit must be set by a master device
whenever its transaction is terminated with target-abort.
Signaled Target Abort. This bit must be set by a target device
whenever it terminates a transaction with target-abort.
DEVSEL Timing. Bits 9 and 10 encode the timing of DELSEL# (see
Section 3.6.1 of the PCI Specification). These bits must indicate the
slowest time that a device asserts DEVSEL# for any bus command
except configuration read and configuration write. The default timing is
01 (medium).
Master Data Parity Error. See Table 6-2 of the PCI Specification for
more information.
Fast Back-to-Back Capable. Indicates whether or not the target is
capable of accepting fast back-to-back transactions when the
transactions are not to the same agent. The FW323 does not support
back-to-back transactions.
Reserved.
66 MHz Capable. Indicates whether or not this device is capable of
running at 66 MHz as defined in Chapter 7 of the PCI Specification. The
FW323 reports a value of zero in this field indicating that 66 MHz
functionality is not supported.
Capabilities List. Indicates whether or not this device implements the
pointer for a New Capabilities linked list at offset 34h. A value of zero
indicates that no New Capabilities linked list is available. A value of one
indicates that the value read at offset 34h is a point in Configuration
Space to a linked list of new capabilities. (See Section 6.7 of the PCI
Specification for more details.)
Reserved.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Class Code and Revision ID Registers
The Class Code register and Revision ID register categorize the FW323 as a serial bus controller (0Ch),
controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the chip revision is
indicated in the lower byte.
Offset:
Default:
Type:
Reference:
08h
0C00 106xh*
Read only
PCI Local Bus Specification, Rev. 2.2, Section 6.2.1 and 1394 Open Host Controller Interface
Specification, Rev. 1.1, Section A.3.3 and A.3.4.
Table 6. Class Code and Revision ID Register Description
Bit
Field Name
Type
Description
31:24
BASECLASS
R
23:16
SUBCLASS
R
15:8
PGMIF
R
7:0
CHIPREV
R
Base Class. This field returns 0Ch when read, which classifies the function as a serial bus controller.
Subclass. This field returns 00h when read, which specifically classifies
the function as an IEEE 1394 serial bus controller.
Programming Interface. This field returns 10h when read, indicating
that the programming model is compliant with the 1394 Open Host
Controller Interface Specification.
Silicon Revision. This field returns 6xh* when read, indicating the
silicon revision of the FW323.
* x is a minor revision number of the FW323 06 and may be any value from 0 hex to F hex.
Agere Systems Inc.
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FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Latency Timer and Cache Line Size Register
The Latency Timer and Class Cache Line Size register is programmed by host BIOS to indicate system cache line
size and the latency timer associated with the FW323. If a serial EEPROM is detected, then the contents of this
register are loaded from the serial EEPROM interface after a PCI reset. If no serial EEPROM is detected, then this
register returns a default value of 0000h.
Offset:
Default:
Type:
Reference:
0Ch
0000h
Read/write
PCI Local Bus Specification, Rev. 2.2, Section 6.2.4
Table 7. Latency Timer and Class Cache Line Size Register Description
Bit
Field Name
Type
Description
15:8
LATENCY_TIMER
RW
7:0
CACHELINE_SZ
RW
PCI Latency Timer. The value in this register specifies the latency
timer, in units of PCI clock cycles, for the FW323. When the FW323 is
a PCI bus initiator and asserts FRAME, the latency timer begins
counting from zero. If the latency timer expires before the FW323
transaction has terminated, then the FW323 terminates the transaction when its PCI_GNTN is deasserted.
Cache Line Size. This value is used by the FW323 during memory
write and invalidate, memory read line, and memory read multiple
transactions.
Header Type and BIST Register
The Header Type and BIST register indicates the FW323 PCI header type.
Offset:
Default:
Type:
Reference:
0Eh
0000h
Read only
PCI Local Bus Specification, Rev. 2.2, Sections 6.2.1 and 6.2.4
Table 8. Header Type and BIST Register Description
28
Bit
Field Name
Type
Description
15:8
BIST
R
7:0
HEADER_TYPE
R
Built-In Self-Test. The FW323 does not include a built-in self-test;
thus, this field returns 00h when read.
PCI Header Type. The FW323 includes the standard PCI header, and
this is communicated by returning 00h when this field is read.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
OHCI Base Address Register
The OHCI Base Address register is programmed with a base address referencing the memory-mapped OHCI control. When BIOS writes all 1s to this register, the value read back is FFFF F000h, indicating that 4 Kbytes of memory address space are required for the OHCI registers.
Offset:
Default:
Type:
Reference:
10h
0000 0000h
Read/write
PCI Local Bus Specification, Rev. 2.2, Sections 6.2.5 and 1394 Open Host Controller Interface
Specification, Rev. 1.1, Section A.3.5
Table 9. OHCI Base Address Register Description
Bit
Field Name
Type
Description
31:12
OHCIREG_PTR
RW
11:4
OHCI_SZ
R
3
OHCI_PF
R
2:1
OHCI_MEMTYPE
R
0
OHCI_MEM
R
OHCI Register Pointer. Specifies the upper 20 bits of the 32-bit OHCI
base address.
OHCI Register Size. This field returns 0s when read, indicating that
the OHCI registers require a 4 Kbyte region of memory.
OHCI Register Prefetch. This bit returns 0 when read, indicating that
the OHCI registers are not prefetchable.
OHCI Memory Type. This field returns 0s when read, indicating that
the OHCI Base Address register is 32 bits wide and mapping can be
done anywhere in the 32-bit memory space.
OHCI Memory Indicator. This bit returns 0 when read, indicating that
the OHCI registers are mapped into system memory space.
Agere Systems Inc.
29
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
CardBus Base Address Register
The CardBus Base Address register is programmed with a base address referencing the memory-mapped
Function Event registers. When BIOS writes all 1s to this register, the value read back is FFFF FF00h, indicating
that 256 bytes of memory address space are required for the CardBus Function Event registers.
Offset:
Default:
Type:
Reference:
14h
0000 0000h
Read/write
PC Card Standard Rev 8, volume 2, Section 5.4.2.1.7
Table 10. CardBus Base Address Register Description
Bit
Field Name
Type
Description
31:8
CBREG_PTR
RW
7:4
CB_SZ
R
3
CB_PF
R
2:1
CB_MEMTYPE
R
0
CB_MEM
R
CardBus Register Pointer. Specifies the upper 24 bits of the 32-bit
CardBus base address.
CardBus Register Size. This field returns 0s when read, indicating
that the CardBus registers require a 256 byte region of memory.
CardBus Register Prefetch. This bit returns 0 when read, indicating
that the CardBus Function Event registers do not have support for
prefetchable memory.
CardBus Memory Type. This field returns 0s when read, indicating
that the CardBus Base Address register is 32 bits wide and mapping
can be done anywhere in the 32-bit memory space.
CardBus Memory Indicator. This bit returns 0 when read, indicating
that the CardBus registers are mapped into system memory space.
CIS Pointer
The CIS Pointer indicates the starting point of the card information structure (CIS). The CIS may begin in any one
of the following spaces:
„
Configuration space: must begin in device-dependent space at or after location 40h.
„
Memory space: may be in any of the memory spaces.
„
Expansion ROM space: may be in any of the images.
The FW323 will only support the first, configuration space starting at location 80h.
Offset:
Default (CardBusN = 1):
Default (CardBusN = 0):
Type:
Reference:
30
28h
0000 0000h
0000 0080h
Read only
PCI Card Standard, Rev. 8, volume 2, Section 5.4.2.1.8
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
PCI Subsystem Identification Register
The PCI Subsystem Identification register is used to uniquely identify the card or system in which the FW323
resides. If a serial EEPROM is present, these values are loaded from the EEPROM during the powerup sequence.
Subsystem vendor IDs can be obtained from the PCI SIG. Values for the subsystem ID are vendor specific.
By default, the PCI Subsystem ID and PCI Subsystem Vendor ID registers are read only. However, if a serial
EEPROM is not interfaced to the FW323 06, bit 0 (SubSystemWriteEn) of the PCI Config register, offset 4Ch can
be set to enable writes to the PCI Subsystem ID and PCI Subsystem Vendor ID so that these registers can be
customized to the correct ID values. After the IDs have been written, the SubSystemWriteEn bit should be reset to
protect the data from being overwritten.
Offset:
Default:
Type:
Reference:
2Ch
0000 0000h
Read/write
PCI Local Bus Specification, Rev. 2.2, Section 6.2.4
Table 11. PCI Subsystem Identification Register Description
Bit
Field Name
Type
Description
31:16
15:0
SSID
SSVID
RU
RU
Subsystem ID. This field indicates the subsystem ID.
Subsystem Vendor ID. This field indicates the subsystem vendor ID.
PCI Power Management Capabilities Pointer Register
The PCI Power Management Capabilities Pointer register provides a pointer into the PCI configuration header
where the PCI Power Management register block resides. The FW323 configuration words at offsets 44h and 48h
provide the Power Management registers. This register is read only and returns 44h when read.
Offset:
Default:
Type:
Reference:
34h
44h
Read only
PCI Local Bus Specification, Rev. 2.2, Section 6.2.4 and 6.7 and 1394 Open Host Controller
Interface Specification, Rev. 1.1, Section A.3.6.
Agere Systems Inc.
31
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Interrupt Line and Pin Register
The Interrupt Line and Pin register is used to communicate interrupt line routing information.
Offset:
Default:
Type:
Reference:
3Ch
0100h
Read only
PCI Local Bus Specification, Rev. 2.2, Section 6.2.4 and 6.7
Table 12. Interrupt Line and Pin Register Description
Bit
Field Name
Type
Description
15:8
INTR_PIN
R
7:0
INTR_LINE
RW
Interrupt Pin Register. This register returns 01h when read, indicating that the FW323 PCI function signals interrupts on the INTA pin.
Interrupt Line Register. This register is programmed by the system
and indicates to software to which interrupt line the FW323 INTA is
connected.
MIN_GNT and MAX_LAT Register
The MIN_GNT and MAX_LAT register is used to communicate to the system the desired setting of the Latency
Timer register. If a serial EEPROM is detected, then the contents of this register are loaded from the serial
EEPROM interface after a PCI reset. If no serial EEPROM is detected, then this register returns a default value
that corresponds to the MIN_GNT = 0Ch, MAX_LAT = 18h.
Offset:
Default:
Type:
Reference:
3Eh
180Ch
Read only
PCI Local Bus Specification, Rev. 2.2, Section 6.2.4
Table 13. MIN_GNT and MAX_LAT Register Description
32
Bit
Field Name
Type
Description
15:8
MAX_LAT
RU
7:0
MIN_GNT
RU
Maximum Latency. The contents of this register may be used by host
BIOS to assign an arbitration priority level to the FW323. The default
for this register (18h) indicates that the FW323 may need to access
the PCI bus as often as every 0.25 µs; thus, an extremely high-priority
level is requested. The contents of this field may also be loaded from
the serial ROM.
Minimum Grant. The contents of this register may be used by host
BIOS to assign a Latency Timer register value to the FW323. The
default (0Ch) for this register indicates that the FW323 may need to
sustain burst transfers for nearly 64 µs; thus, requesting a large value
be programmed in the FW323 Latency Timer register. The contents of
this field may also be loaded from the serial ROM.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
PCI OHCI Control Register
The PCI OHCI Control register is defined in Section A.3.7 of the 1394 Open Host Controller Interface
Specification and provides a bit for big endian PCI support. Note that the GLOBAL_SWAP bit is loaded from the
serial EEPROM on powerup.
Offset:
Default:
Type:
Reference:
40h
0000 0000h
Read/write
1394 Open Host Controller Interface Specification, Rev. 1.1, Section A.3.7
Table 14. PCI OHCI Control Register Description
Bit
Field Name
Type
31:1
0
Reserved
GLOBAL_SWAP
R
RW
Description
Reserved. Bits 31:1 return 0s when read.
When this bit is set, all quadlets read from the FW323 as well as any
data written to the PCI bus by the FW323 is byte swapped. This
excludes PCI Config registers and CardBus Function Event registers
(they are not swapped under any circumstances). However, OHCI
registers are byte swapped when this bit is set.
Capability ID and Next Item Pointer Register
The Capability ID and Next Item Pointer register identifies the linked list capability item and provides a pointer to
the next capability item.
Offset:
Default:
Type:
Reference:
44h
0001h
Read only
PCI Local Bus Specification, Rev. 2.2, Sections 6.8.1.1, 6.8.1.2 and 1394 Open Host Controller
Interface Specification, Rev. 1.1, Sections A.3.8.1 and A.3.8.2
Table 15. Capability ID and Next Item Pointer Register Description
Bit
Field Name
Type
Description
15:8
NEXT_ITEM
R
7:0
CAPABILITY_ID
R
Next Item Pointer. The FW323 supports only one additional capability
that is communicated to the system through the extended capabilities
list; thus, this field returns 00h when read.
Capability Identification. This field returns 01h when read, which is
the unique ID assigned by the PCI SIG for PCI power management
capability.
Agere Systems Inc.
33
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Power Management Capabilities Register
The Power Management Capabilities register indicates the capabilities of the FW323 related to PCI power management. The default value of this register is dependent on the state of the VAUX_PRESENT input pin. If
VAUX_PRESENT is asserted when the FW323 comes out of powerup reset, then the default value of this register
will be FFC2h. If the VAUX_PRESENT input pin is deasserted when the FW323 comes out of powerup reset, then
the default value of this register will be 7E02h. In addition, the default value of this register can be selectively programmed by the serial EEPROM. Note, however, that if VAUX_PRESENT is deasserted, then the D3cold and
AUX_PWR fields will both be set to 0h regardless of the serial EEPROM settings.
Offset:
Default:
Type:
Reference:
46h
FFC2h (if VAUX_PRESENT = 1)
7E02h (if VAUX_PRESENT = 0)
Read only
PCI Bus Power Management Interface Specification, Rev. 1.1, Section 3.2.3 and 1394 Open Host
Controller Interface Specification, Rev. 1.1, Section A.3.8.3
Table 16. Power Management Capabilities Register Description
34
Bit
Field Name
Type
Description
15
PME_D3COLD
R
14
PME_D3HOT
R
13
PME_D2
R
12
PME_D1
R
11
PME_D0
R
10
D2_SUPPORT
R
9
D1_SUPPORT
R
8:6
AUX_PWR
R
5
DSI
R
4
3
Reserved
PME_CLK
R
R
2:0
PM_VERSION
R
PME Support from D3cold. Indicates whether the FW323 can
generate a PME event while in the D3cold state (see description
above for default setting).
PME Support from D3hot. Set to 1, indicating that the FW323 can
generate a PME event in the D3hot state.
PME Support from D2. Set to 1, indicating that the FW323 can
generate a PME in D2.
PME Support from D1. Set to 1, indicating that the FW323 can
generate a PME in D1.
PME Support from D0. Set to 1, indicating that the FW323 can
generate a PME in D0.
D2 Support. This bit returns a 1 when read, indicating that the FW323
supports the D2 power state.
D1 Support. This bit returns a 1 when read, indicating that the FW323
supports the D1 power state.
Auxiliary Power Source. This field reports the Vaux power requirements for the Open HCI function (see description above for default
setting).
Device-Specific Initialization. This bit returns 0 when read, indicating that the FW323 does not require special initialization beyond
the standard PCI configuration header before a generic class driver is
able to use it.
Reserved. Bit returns 0 when read.
PME Clock. This bit returns 0 when read, indicating that no host bus
clock is required for the FW323 to generate PME.
Power Management Version. This field returns 010b when read, indicating that the FW323 is compatible with the registers described in the
PCI Power Management Interface Specification, Rev.1.1.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Power Management Control and Status Register
The Power Management Control and Status register implements the control and status of the PCI power management function. This register is not affected by the internally generated reset caused by the transition from the D3hot
to D0 state. The value of this register after a PCI reset is dependent on whether the FW323 is enabled to generate
a PME event while in the D3cold state. If the PME_D3cold bit within the Power Management Capabilities register is
asserted, then the PME_STS and PME_ENB bits within this register will not be reset by a PCI reset, i.e., these bits
will become sticky bits. Otherwise these bits, along with all the other bits within this register, will be reset by a PCI
reset.
Offset:
Default:
Type:
Reference:
48h
0000h (If PME_D3cold is deasserted)
XX00h (If PME_D3cold is asserted)
Read/write
PCI Bus Power Management Interface Specification, Rev. 1.1, Section 3.2.4 and 1394 Open Host
Controller Interface Specification, Rev. 1.1, Section A.3.8.4
Table 17. Power Management Control and Status Register Description
Bit
Field Name
Type
15
PME_STS
RC
14:13
DATA_SCALE
12:9
DATA_SELECT
8
PME_ENB
7:5
4
Reserved
DYN_DATA
3:2
1:0
Reserved
PWR_STATE
Description
This bit is set when the FW323 would normally be asserting the PME
signal, independent of the state of the PME_ENB bit. This bit is
cleared by a writeback of 1, and this also clears the PME signal driven
by the FW323. Writing a 0 to this bit has no effect. This bit is implemented as sticky when PME_D3cold is asserted in the Power
Management Capabilities register.
R This 2-bit field indicates a scaling factor that is to be used when interpreting the value of the PM_DATA register within the Power Management Extension register. The value and meaning of this field will vary
depending on the value that has been selected by the DATA_SELECT
field.
R This 4-bit field is used to select which data values are to be reported
through the PM_DATA field in the Power Management Extension
register and the DATA_SCALE fields. Valid values are 0—7, which
map to power consumption/dissipation ratings for the FW323 within
the PM_DATA/DATA_SCALE fields.
RW PME Enable. This bit enables the function to assert PME. If this bit is
cleared, then assertion of PME is disabled. This bit is implemented as
sticky when PME_D3cold is asserted in the Power Management
Capabilities register.
R Reserved. Bits 7:5 return 0s when read.
R Dynamic Data. This bit returns 0 when read, since the FW323 does
not report dynamic data.
R Reserved. Bits 3:2 return 0s when read.
RW Power State. This 2-bit field is used to set the FW323 device power
state and is encoded as follows:
00 = current power state is D0.
01 = current power state is D1.
10 = current power state is D2.
11 = current power state is D3.
Agere Systems Inc.
35
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Power Management CSR PCI-to-PCI Bridge Support Extensions
This register returns 00h when read since the FW323 does not provide PCI-to-PCI bridging.
Offset:
Default:
Type:
Reference:
4Ah
00h
Read only
PCI Bus Power Management Interface Specification, Rev. 1.1, Section 3.2.5 and 1394 Open Host
Controller Interface Specification, Rev. 1.1, Section A.3.8.5 and A.3.8.6
Power Management Data
The Power Management (PM) Data register set is comprised of 16 eight-bit registers, providing more detailed power
management information about the device. All 16 registers will return 00h by default. The first eight registers are
assigned to single function devices, and the second eight are reserved for use by multifunction devices (see Table
18). The FW323 supports programmability, via the serial EEPROM, of the first eight registers in the PM data complex. Software uses the DATA_SELECT and DATA_SCALE fields within the Power Management Control and Status
register to select and scale the desired PM data entry. Note that if the serial EEPROM is used to program nonzero
values into PM DATA, then the AUX_PWR field should be programmed to a zero value via the serial EEPROM and
vice versa. This is to comply with the PCI Specification, which states that these two functions must be implemented
mutually exclusive of one another. The FW323 does not enforce this, and therefore, it is up to the creator of the serial
EEPROM image to ensure that these two fields are used mutually exclusive of one another.
Offset:
Default:
Type:
Reference:
4Bh
00h
Read Only
PCI Bus Power Management Interface Specification, Rev. 1.1, Section 3.2.6 and 1394 Open Host
Controller Interface Specification, Rev. 1.1, Section A.3.8.5 and A.3.8.6
Table 18. Power Management Data Register Description
(Derived from Table 10 of the PCI Power Management Interface Specification, Revision 1.1.)
Value in
Data_Select
Data Reported
Data_Scale
Interpretation
Units/Accuracy
0
1
2
3
4
5
6
7
8—15
D0 Power Consumed
D1 Power Consumed
D2 Power Consumed
D3 Power Consumed
D0 Power Dissipated
D1 Power Dissipated
D2 Power Dissipated
D3 Power Dissipated
Reserved (unused by FW323
and will return 00h when read)
0 = Unknown
Watts
1 = 0.1x
2 = 0.01x
3 = 0.001x
Reserved
TBD
CardBus Function Registers (CardBusN = 0)
The FW323 06, when used in a CardBus application, provides a set of four 32-bit registers: Function Event, Function
Event Mask, Function Present State, and Function Force Event. These registers are located in memory space starting at the location given by the CISTPL_CONFIG_CB tuple in the CIS and the CardBus Base Address register.
These registers support status changed notification through the CSTSCHG (PCI_PMEN) signal and functional interrupt notification using the CINTN (PCI_INTAN) signal. The Function Event registers are only visible when
CardBusN = 0. For more information, refer to the Application Note Using the FW322 06/FW323 06 in CardBus Applications.
36
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
OHCI Registers
The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory mapped into a
2 Kbyte region of memory pointed to by the OHCI Base Address register located at offset 10h in PCI configuration
space. These registers are the primary interface for controlling the FW323 IEEE 1394 OHCI function. This section
provides a summary of the registers within this interface and a description of the individual bit fields within each
register. For more details regarding these registers and bits, please refer to the 1394 Open Host Controller Interface Specification, Rev. 1.1.
In addition to regular read/write registers, there are several pairs of set and clear registers implemented within the
OHCI register interface. For each pair of set and clear registers, there are two addresses that correspond to individual set/clear registers: RegisterSet and RegisterClear. Refer to Table 20 for a listing of these registers. A 1 bit written to RegisterSet causes the corresponding bit in the register to be set, while a 0 bit leaves the corresponding bit
unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the register to be reset, while a 0 bit
leaves the corresponding bit unaffected. Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register. However, in some instances, reading the RegisterClear provides a masked version
of the set or clear register. The Interrupt Event register is an example of this behavior.
The following FW323 OHCI register definitions are based on version 1.1 of the 1394 Open Host Controller
Specification.
Table 19. OHCI Register Map
DMA
Context
—
Register Name
Abbreviation
Offset
OHCI Version
Global Unique ID ROM
Asynchronous Transmit Retries
CSR Data
CSR Compare Data
CSR Control
Configuration ROM Header
Bus Identification
Bus Options
Global Unique ID High
Global Unique ID Low
Reserved
Reserved
Configuration ROM Map
Posted Write Address Low
Posted Write Address High
Vendor Identification
Reserved
Host Controller Control
Version
GUID_ROM
ATRetries
CSRData
CSRCompareData
CSRControl
ConfigROMhdr
BusID
BusOptions
GUIDHi
GUIDLo
—
—
ConfigROMmap
PostedWriteAddressLo
PostedWriteAddressHi
VendorID
—
HCControlSet
HCControlClear
—
—
—
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
Reserved
50h
54h
58h
5Ch
60h
Reserved
Reserved
Reserved
Agere Systems Inc.
OHCI
Specification
Reference
5.2
5.3
5.4
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
—
—
5.5.6
13.2.8.1
5.6
—
5.7
—
—
—
37
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Table 19. OHCI Register Map (continued)
DMA
Context
SelfID
—
Abbreviation
Offset
SelfID Buffer
SelfID Count
Reserved
Isochronous Receive Channel Mask High
SelfIDBuffer
SelfIDCount
—
IRChannelMaskHiSet
IRChannelMaskHiClear
IRChannelMaskLoSet
IRChannelMaskLoClear
IntEventSet
IntEventClear
IntMaskSet
IntMaskClear
IsoXmitIntEventSet
IsoXmitIntEventClear
64h
68h
6Ch
70h
74h
78h
7Ch
80h
84h
88h
8Ch
90h
94h
11.1
11.2
—
10.4.1.1
IsoXmitIntMaskSet
IsoXmitIntMaskClear
IsoRecvIntEventSet
IsoRecvIntEventClear
IsoRecvIntMaskSet
IsoRecvIntMaskClear
InitialBandwidthAvailable
InitialChannelsAvailableHi
InitialChannelsAvailableLo
—
FairnessControl
LinkControlSet
LinkControlClear
NodeID
PhyControl
IsoCycTimer
—
AsyncRequestFilterHiSet
AsyncRequestFilterHiClear
AsyncRequestFilterLoSet
AsyncRequestFilterloClear
PhysicalRequestFilterHiSet
PhysicalRequestFilterHiClear
PhysicalRequestFilterLoSet
PhysicalRequestFilterloClear
PhysicalUpperBound
—
98h
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
B8h
BCh:D8h
DCh
E0h
E4h
E8h
ECh
F0h
F4h:FCh
100h
104h
108h
10Ch
110h
114h
118h
11Ch
120h
124h:17Ch
6.3.2
Isochronous Receive Channel Mask Low
Interrupt Event
Interrupt Mask
Isochronous Transmit
Interrupt Event
Isochronous Transmit
Interrupt Mask
—
Isochronous Receive
Interrupt Event
Isochronous Receive
Interrupt Mask
Bus Management CSR Initialization
Reserved
Fairness Control
Link Control
Node Identification
PHY Core Layer Control
Isochronous Cycle Timer
Reserved
Asynchronous Request Filter High
Asynchronous Request Filter Low
Physical Request Filter High
Physical Request Filter Low
Physical Upper Bound
Reserved
38
OHCI
Specification
Reference
Register Name
6.1
6.2
6.3.1
6.4.1
6.4.2
5.8
—
5.9
5.10
5.11
5.12
5.13
—
5.14.1
5.4.2
5.15
—
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Table 19. OHCI Register Map (continued)
DMA Context
Register Name
Abbreviation
Offset
Asynchronous
Request Transmit
[ATRQ]
Context Control
ContextControlSet
ContextControlClear
—
CommandPtr
—
ContextControlSet
ContextControlClear
—
CommandPtr
—
ContextControlSet
ContextControlClear
—
CommandPtr
—
ContextControlSet
ContextControlClear
—
CommandPtr
—
ContextControlSet
ContextControlClear
—
CommandPtr
ContextControlSet
ContextControlClear
—
CommandPtr
ContextMatch
—
180h
184h
188h
18Ch
190h:19Ch
1A0h
1A4h
1A8h
1ACh
1B0h:1BCh
1C0h
1C4h
1C8h
1CCh
1D0h:1DFh
1E0h
1E4h
1E8h
1ECh
1F0h:1FFh
200h + 16 * n
204h + 16 * n
208h + 16 * n
20Ch + 16 * n
400h + 32 * n
404h + 32 * n
408h + 32 * n
40Ch + 32 * n
410h + 32 * n
414h + 32 * n –
41Ch+ 32 * n
Asynchronous
Response
Transmit
[ATRS]
Asynchronous
Request
Receive
[ARRQ]
Asynchronous
Response
Receive
[ARRS]
Isochronous
Transmit
Context n
n = 0:7
Isochronous
Receive
Context n
n = 0:7
Agere Systems Inc.
Reserved
Command Pointer
Reserved
Context Control
Reserved
Command Pointer
Reserved
Context Control
Reserved
Command Pointer
Reserved
Context Control
Reserved
Command Pointer
Reserved
Context Control
Reserved
Command Pointer
Context Control
Reserved
Command Pointer
Context Match
Reserved
OHCI
Specification
Reference
3.1, 7.2.2
—
3.1.2, 7.2.1
—
3.1, 7.2.2
—
3.1.2, 7.2.1
—
3.1, 8.3.2
—
3.1.2, 8.3.1
—
3.1, 8.3.2
—
3.1.2, 8.3.1
—
3.1, 9.2.2
—
3.1.2, 9.2.1
3.1, 10.3.2
—
3.1.2, 10.3.1
10.3.3
—
39
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
OHCI Version Register
This register indicates the OHCI version supported, and whether or not the serial EEPROM is present. To support
backwards compatibility with existing hardware and software, the version and revision fields default to 8’h01 and
8’h00 respectively. These values denote compatibility with version 1.0 of the OHCI specification. However, both the
version and revision fields are programmable via the serial EEPROM. This functionality allows these fields to be
optionally updated to 8’h01 and 8’h10 respectively to indicate compatibility with version 1.1 of the OHCI
specification. Note that if the version and revision fields are programmed with OHCI 1.1 values, then the
LinkOptions register (see FW323 Vendor-Specific Registers on page 72) should also be programmed to properly
enable OHCI 1.1 features within the FW323.
Offset:
Default:
Type:
Reference:
00h
0X01 0000h
Read/write
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.2
Table 20. OHCI Version Register Description
40
Bit
Field Name
Type
Description
31:25
24
23:16
Reserved
GUID_ROM
Version
R
R
R
15:8
7:0
Reserved
Revision
R
R
Reserved.
The FW323 sets this bit if the serial EEPROM is detected.
Major Version of the OHCI. The FW323 is compliant with both
version 1.0 and version 1.1 of the 1394 Open Host Controller Interface
Specification. This field defaults to 01h, but can be reconfigured via
the serial EEPROM.
Reserved.
Minor Version of the OHCI. The FW323 is compliant with both
version 1.0 and version 1.1 of the 1394 Open Host Controller Interface
Specification. This field defaults to 00h, but can be reconfigured via
the serial EEPROM.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
GUID ROM Register
The GUID ROM register is used to access the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the
OHCI Version register is set.
Offset:
Default:
Reference:
04h
00XX 0000h
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.3
Table 21. GUID ROM Register Description
Bit
Field Name
Type
Description
31
addrReset
RWU
30:26
25
Reserved
rdStart
R
RWU
24
23:16
Reserved
rdData
R
RU
15:8
7:0
Reserved
miniROM
R
R
Software sets this bit to reset the GUID ROM address to 0. When the
FW323 completes the reset, it clears this bit.
Reserved. Bits 30:26 return 0s when read.
A read of the currently addressed byte is started when this bit is set.
This bit is automatically cleared when the FW323 completes the read
of the currently addressed GUID ROM byte.
Reserved. Bit 24 returns 0 when read.
This field represents the data read from the GUID ROM and is only
valid when rdStart = 0.
Reserved. Bits 15:8 return 0s when read.
Indicates the first byte location of the miniROM image in the GUID
ROM. A value of 0 is returned if no miniROM is implemented.
Asynchronous Transmit Retries Register
The Asynchronous Transmit Retries register indicates the number of times the FW323 attempts a retry for
asynchronous DMA request transmit and for asynchronous physical and DMA response transmit.
Offset:
Default:
Reference:
08h
0000 0000h
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.4
Table 22. Asynchronous Transmit Retries Register Description
Bit
Field Name
Type
Description
31:29
secondLimit
R
28:16
cycleLimit
R
15:12
11:8
Reserved
maxPhysRespRetries
R
RW
7:4
maxATRespRetries
RW
3:0
maxATReqRetries
RW
The second limit field returns 0s when read, since outbound dualphase retry is not implemented.
The cycle limit field returns 0s when read, since outbound dualphase retry is not implemented.
Reserved. Bits 15:12 return 0s when read.
This field tells the physical response unit how many times to
attempt to retry the transmit operation for the response.
This field tells the asynchronous transmit DMA response unit how
many times to attempt to retry the transmit operation for the
response.
This field tells the asynchronous transmit DMA request unit how
many times to attempt to retry the transmit operation for the
response.
Agere Systems Inc.
41
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued
CSR Data Register
The CSR Data register is used to access the bus management CSR registers from the host through compare-swap
operations. This register contains the data to be stored in a CSR if the compare is successful.
Offset:
Default:
Reference:
0Ch
XXXX XXXXh
1394 Open Host Controller Interface Specification, Rev. 1.1, Sections 5.5.1.
Table 23. CSR Data Register Description
Bit
Field Name
Type
31:0
csrData
RWU
Description
At start of operation, the data to be stored if the compare is
successful.
CSR Compare Register
The CSR Compare register is used to access the bus management CSR registers from the host through compareswap operations. This register contains the data to be compared with the existing value of the CSR resource.
Offset:
Default:
Reference:
10h
XXXX XXXXh
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.1
Table 24. CSR Compare Register Description
Bit
Field Name
Type
31:0
csrCompare
RW
Description
The data to be compared with the existing value of the CSR
resource.
CSR Control Register
The CSR Compare register is used to access the bus management CSR registers from the host through compareswap operations. Bits in this register are used to initiate a compare-and-swap operation on a selected resource and
signal when that operation is complete.
Offset:
Default:
Reference:
14h
8000 000Xh
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.1
Table 25. CSR Control Register Description
Bit
Field Name
Type
31
csrDone
RU
30:2
1:0
Reserved
csrSel
R
RW
Description
This bit is set by the FW323 when a compare-swap operation is
complete. It is reset whenever this register is written.
Reserved. Bits 30:2 return 0s when read.
This field selects the CSR resource as follows:
00 = BUS_MANAGER_ID
01 = BANDWIDTH_AVAILABLE
10 = CHANNELS_AVAILABLE_HI
11 = CHANNELS_AVAILABLE_LO
42
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Configuration ROM Header Register
The Configuration ROM Header register externally maps to the first quadlet of the 1394 configuration ROM, offset
48’hFFFF_F000_0400.
Offset:
Default:
Reference:
18h
0000 0000h
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.2
Table 26. Configuration ROM Header Register Description
Bit
Field Name
Type
Description
31:24
info_length
RW
23:16
crc_length
RW
15:0
rom_crc_value
RW
IEEE 1394 Bus Management Field. Must be valid when bit 17 (linkEnable) of the Host Controller Control register is set (see Table 35).
IEEE 1394 Bus Management Field. Must be valid when bit 17 (linkEnable) of the Host Controller Control register is set (see Table 35).
IEEE 1394 Bus Management Field. Must be valid at any time bit 17
(linkEnable) of the Host Controller Control register is set (see Table 35).
Agere Systems Inc.
43
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Bus Identification Register
The Bus Identification register externally maps to the first quadlet in the Bus_Info_Block and is addressable at
FFFF_F000_0404. This register is read locally at the offset specified below.
Offset:
Default:
Reference:
1Ch
3133 3934h
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.3
Table 27. Bus Identification Register Description
Bit
Field Name
Type
Description
31—0
busID
R
Contains the constant 32’h31333934, which is the ASCII value for
1394.
Bus Options Register
The Bus Options register externally maps to the second quadlet of the Bus_Info_Block and is 1394 addressable
at FFFF_F000_0408.
Offset:
Default:
Reference:
20h
0000 A002h
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.4
Table 28. Bus Options Register Description
44
Bit
Field Name
31:16
Reserved
15:12
max_rec
11:3
2:0
Reserved
Lnk_spd
Type
Description
R or RW Reserved. Bits return 0s when read; 23:16 and 31:27 are RW and
undefined.
RW
IEEE 1394 Bus Management Field. Hardware initializes this field
to indicate the maximum number of bytes in a block request packet
that is supported by the implementation. This value,
max_rec_bytes, must be 512 or greater and is calculated by
2(max_rec + 1). Software may change this field; however, this field
must be valid at any time bit 17 (linkEnable) of the Host Controller
Control register is set. A received block write request packet with a
length greater than max_rec_bytes may generate an
ack_type_error. This field is not affected by a soft reset, and
defaults to value indicating 2048 bytes on a hard reset.
R
Reserved. Bits 11:3 return 0s when read.
R
Link Speed. This field returns 010, indicating that the link speeds
of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s are supported.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
GUID High Register
The GUID High register represents the upper quadlet in a 64-bit global unique ID (GUID), which maps to the third
quadlet in the Bus_Info_Block 1394, addressable at FFFF_F000_0410. This register contains node_vendor_ID
and chip_ID_hi fields. This register initializes to 0s on a hardware reset, which is an illegal GUID value. If a serial
EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a
PCI reset. If no serial EEPROM is detected, then the contents of this register can be loaded with a single PCI
write to either of two configuration registers, executed after a PCI reset. The two configuration registers are
located at offset 0x70, for all CardBus and new PCI applications, and offset 0x80, for backward compatibility with
FW323 05 PCI applications only. After one of these load mechanisms has completed, this register becomes
read only.
Offset:
Default:
Reference:
24h
0000 0000h
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.5
Table 29. GUID High Register Description
Bit
Field Name
Type
Description
31:8
node_vendor_ID
RWU
7:0
chip_ID_hi
RWU
IEEE 1394 Bus Management Fields. Firmware or hardware must
ensure that this register is valid whenever HCCControl.linkEnable
bit is set.
Firmware or hardware must ensure that this register is valid whenever HCCControl.linkEnable bit is set.
GUID Low Register
The GUID Low register represents the lower quadlet in a 64-bit global unique ID (GUID), which maps to
chip_ID_lo in the Bus_Info_Block 1394, addressable at FFFF_F000_0414. This register initializes to 0s on a
hardware reset and behaves identical to the GUID High register. If no serial EEPROM is detected, then the
contents of this register can be loaded with a PCI configuration write to either offset 0x74 or 0x84, as described
above.
Offset:
Default:
Reference:
28h
0000 0000h
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.5
Table 30. GUID Low Register Description
Bit
Field Name
Type
Description
31:0
chip_ID_lo
R
IEEE 1394 Bus Management Fields. Firmware or hardware must
ensure that this register is valid whenever HCCControl.linkEnable
bit is set.
Agere Systems Inc.
45
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Configuration ROM Mapping Register
The Configuration ROM Mapping register contains the start address within system memory that maps to the start
address of 1394 configuration ROM for this node.
Offset:
Default:
Reference:
34h
0000 0000h
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.6
Table 31. Configuration ROM Mapping Register Description
46
Bit
Field Name
Type
31:10
configROMaddr
RW
9:0
Reserved
R
Description
If a quadlet read request to 1394 offset 48’hFFFF_F000_0400
through offset 48’hFFFF_F000_07FF is received, then the loworder 10 bits of the offset are added to this register to determine
the host memory address of the read request.
Reserved. Bits 9:0 return 0s when read.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Posted Write Address Low Register
The Posted Write Address Low register is used to communicate error information if a write request is posted and
an error occurs while writing the posted data packet.
Offset:
Default:
Reference:
38h
XXXX XXXXh
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 13.2.8.1.
Table 32. Posted Write Address Low Register Description
Bit
Field Name
Type
Description
31:0
offsetLo
RU
The lower 32 bits of the 1394 destination offset of the write request
that was posted and failed.
Posted Write Address High Register
The Posted Write Address High register is used to communicate error information if a write request is posted and
an error occurs while writing the posted data packet.
Offset:
Default:
Reference:
3Ch
XXXX XXXXh
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 13.2.8.1.
Table 33. Posted Write Address High Register Description
Bit
Field Name
Type
Description
31:16
sourceID
RU
15:0
offsetHi
RU
This field is the bus and node number of the node that issued the
write request that was posted and failed.
The upper 16 bits of the 1394 destination offset of the write
request that was posted and failed.
Vendor ID Register
The Vendor ID register holds the company ID of an organization that specifies any vendor-unique registers.
Offset:
Default:
Reference:
40h
0000 0000h
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.6
Table 34. Vendor ID Register Description
Bit
Field Name
Type
31:24
vendorUnique
R
23:0
vendorCompanyID
R
Agere Systems Inc.
Description
Returns 0 when read, since the FW323 does not specify any
vendor unique registers.
Returns 0 when read, since the FW323 does not specify any
vendor unique registers.
47
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Host Controller Control Register
The Host Controller Control set/clear register pair provides flags for controlling the OHCI portion of the FW323.
Offset:
Default:
Reference:
50h set register
54h clear register
X00X 0000h
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.7
Table 35. Host Controller Control Register Description
48
Bit
Field Name
Type
Description
31
BIBimageValid
RSU
30
noByteSwapData
RSC
29
ackTardyEnable
RSC
28:24
23
Reserved
programPhyEnable
R
RC
22
aPhyEnhanceEnable
RSC
21:20
19
Reserved
LPS
R
RSU
18
postedWriteEnable
RSC
This bit is used to enable both OHCI response to block read
requests to host configuration ROM and the OHCI mechanism for
automatically updating configuration ROM. When this bit is 0, the
OHCI returns a ack_type_error on block read requests to configuration ROM and does not update the configROMmap register or
ConfigROMheader and BusOptions registers when a 1394 bus
reset occurs. When this bit is 1, the physical response unit handles
block reads of host configuration ROM and the mechanism for
automatically updating configuration ROM is enabled.
This bit is used to control byte swapping during host bus accesses
involving the data portion of 1394 packets. Data is swapped if
equal to 0, not swapped when equal to 1.
This bit is used to control the acknowledgment of ack_tardy. When
this bit is set to one, ack_tardy may be returned as an acknowledgement to configuration ROM accesses from 1394 to OHCI
including accesses to the bus_info_block. The host controller will
return ack_tardy to all other asynchronous packets addressed to
the OHCI node.
Reserved. Bits 28:24 return 0s when read.
This bit informs upper-level software that lower-level software has
consistently configured the 1394a-2000 enhancements in the link
and PHY core. When this bit is 1, generic software such as the
OHCI driver is responsible for configuring 1394a-2000 enhancements in the PHY core and bit 22 (aPhyEnhanceEnable) in the
FW323. When this bit is 0, the generic software may not modify the
1394a-2000 enhancements in the FW323 and cannot interpret the
setting of bit 22 (aPhyEnhanceEnable). This bit is initialized from
serial EEPROM.
When bits 23 (programPhyEnable) is 1 and 17 (linkEnable) is 0,
the OHCI driver can set this bit to use all 1394a-2000 enhancements. When bit 23 (programPhyEnable) is set to 0, the software
does not change PHY enhancements or this bit.
Reserved. Bits 21:20 return 0s when read.
Link Power Status. This bit drives the LPS signal to the PHY core
within the FW323 (see Section 5.7 of the OHCI 1.1 Specification
for additional details).
This bit is used to enable (1) or disable (0) posted writes. Software
should change this bit only when bit 17 (linkEnable) is 0.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Table 35. Host Controller Control Register Description (continued)
Bit
Field Name
Type
Description
17
linkEnable
RSU
16
SoftReset
RSU
15:0
Reserved
R
This bit is cleared to 0 by either a hardware or software reset. Software must set this bit to 1 when the system is ready to begin operation and then force a bus reset. This bit is necessary to keep
other nodes from sending transactions before the local system is
ready. When this bit is cleared, the FW323 is logically and immediately disconnected from the 1394 bus, no packets are received or
processed, and no packets transmitted.
When this bit is set, all FW323 states are reset, all FIFOs are
flushed, and all OHCI registers are set to their hardware reset
values unless otherwise specified. PCI registers are not affected
by this bit. This bit remains set while the softReset is in progress
and reverts back to 0 when the reset has completed.
Reserved. Bits 15:0 return 0s when read.
Agere Systems Inc.
49
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
SelfID Buffer Pointer Register
The SelfID Buffer Pointer register points to the 2 Kbyte aligned base address of the buffer in host memory where
the SelfID packets are stored during bus initialization. Bits 31:11 are read/write accessible.
Offset:
Default:
Reference:
64h
XXXX XX00h
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 11.1
Table 36. SelfID Buffer Pointer Register Description
Bit
Field Name
Type
31:11
SelfIDBufferPtr
RW
10:0
Reserved
R
Description
Contains the 2 Kbyte aligned base address of the buffer in host
memory where received SelfID packets are stored.
Reserved.
SelfID Count Register
The SelfID Count register keeps a count of the number of times the SelfID process has occurred. The register
also flags any SelfID errors and maintains a count of the amount of SelfID data in the SelfID buffer.
Offset:
Default:
Reference:
68h
X0XX 0000h
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 11.2
Table 37. SelfID Count Register Description
50
Bit
Field Name
Type
Description
31
selfIDError
RU
30:24
23:16
Reserved
selfIDGeneration
R
RU
15:11
10:2
Reserved
selfIDSize
R
RU
1:0
Reserved
R
When this bit is 1, an error was detected during the most recent
SelfID packet reception. The contents of the SelfID buffer are
undefined. This bit is cleared after a SelfID reception in which no
errors are detected. Note that an error can be a hardware error or
a host bus write error.
Reserved. Bits 30:24 return 0s when read.
The value in this field increments each time a bus reset is
detected. This field rolls over to 0 after reaching 255.
Reserved. Bits 15:11 return 0s when read.
This field indicates the number of quadlets that have been written
into the SelfID buffer for the current bits 23:16 (SelfIDGeneration
field). This includes the header quadlet and the SelfID data. This
field is cleared to 0 when the SelfID reception begins.
Reserved. Bits 1:0 return 0s when read.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Isochronous Receive Multiple Channel Mask High (IRMultiChanMaskHi) Register
The Isochronous Receive Multiple Channel Mask High set/clear register is used to enable packet receives from
the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of
the Isochronous Receive Multiple Channel Mask High register.
Offset:
Default:
Reference:
70h set register
74h clear register
XXXX XXXXh
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 10.4.1.1
Table 38. Isochronous Receive Channel Mask High Register Description
Bit
Field Name
31:0 isoChannel(N + 32)
Type
RSC
Description
If bit N (where N = a bit number 0—31) is set, iso
channel number (N + 32) is enabled.
Isochronous Receive Multiple Channel Mask Low (IRMultiChanMaskLo) Register
The Isochronous Receive Channel Mask Low set/clear register is used to enable packet receives from the lower
32 isochronous data channels.
Offset:
Default:
Reference:
78h set register
7Ch clear register
XXXX XXXXh
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 10.4.1.
Table 39. Isochronous Receive Channel Mask Low Register Description
Bit
Field Name
Type
31:0
isoChannel N
RSC
Agere Systems Inc.
Description
If bit N (where N = a bit number 0—31) is set, iso
channel number N is enabled.
51
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Interrupt Event (IntEvent) Register
The Interrupt Event set/clear register reflects the state of the various FW323 interrupt sources. The interrupt bits
are set by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the
set register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear
register. Reading the IntEventSet register returns the current state of the IntEvent register. Reading the
IntEventClear register returns the masked version of the IntEvent register, i.e., the bit-wise AND function of
IntEvent and IntMask.
Offset:
Default:
Reference:
80h set register
84h clear register
XXXX 0XXXh
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 6.1.
Table 40. Interrupt Event Register Description
Bit
Field Name
Type
31
30
Reserved
vendorSpecific
R
RSCU
29
SoftInterrupt
RSC
28
27
Reserved
ack_Tardy
R
RSCU
Description
Reserved. Bit 31 returns 0 when read.
This vendor-specific interrupt event is reported when serial EEPROM
read is complete.
Soft Interrupt. This bit may be used by software to generate a host
controller interrupt for its own use.
Reserved. Bit 28 returns 0 when read.
This bit will be set when the ackTardyEnable bit of the HC Control
register (see Table 35) is set to 1 and any of the following conditions
occur:
a. Data is present in a FIFO that is to be delivered to the host.
b. The physical response unit is busy processing requests or sending
responses.
52
26
phyRegRcvd
RSCU
25
cycleTooLong
RSCU
24
unrecoverableError
RSCU
23
cycleInconsistent
RSCU
22
cycleLost
RSCU
c. The host controller sent an ack_tardy acknowledgment.
The FW323 has received a PHY Core register data byte, which can be
read from the PHY Core Layer Control register.
If bit 21 (cycleMaster) of the Link Control register (see Table 46) is set,
then this indicates that over 125 µs have elapsed between the start of
sending a cycle start packet and the end of a subaction gap. The Link
Control register bit 21 (cycleMaster) is cleared by this event.
This event occurs when the FW323 encounters any error that forces it
to stop operations on any or all of its subunits, for example, when a
DMA context sets its dead bit. While this bit is set, all normal interrupts
for the context(s) that caused this interrupt are blocked from being set.
A cycle start was received that had values for cycleSeconds and
cycleCount fields that are different from the values in bits 31:25 (cycleSeconds field) and bits 24:12 (cycleCount field) of the Isochronous
Cycle Timer register (see Table 49).
A lost cycle is indicated when no cycle_start packet is sent/received
between two successive cycleSynch events. A lost cycle can be
predicted when a cycle_start packet does not immediately follow the
first subaction gap after the cycleSynch event or if an arbitration reset
gap is detected after a cycleSynch event without an intervening cycle
start. This bit may be set either when it occurs or when logic predicts
that it will occur.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Table 40. Interrupt Event Register Description (continued)
Bit
Field Name
Type
Description
21
cycle64Seconds
RSCU
20
cycleSynch
RSCU
19
18
PHY
regAccessFail
RSCU
RSCU
17
16
busReset
selfIDcomplete
RSCU
RSCU
15
SelfIDcomplete2
RSCU
14:10
9
Reserved
lockRespErr
R
RSCU
8
postedWriteErr
RSCU
7
isochRx
RU
6
isochTx
RU
5
RSPkt
RSCU
4
RQPkt
RSCU
3
ARRS
RSCU
2
ARRQ
RSCU
1
respTxComplete
RSCU
0
reqTxComplete
RSCU
Indicates that the seventh bit of the cycleSeconds (see Table 49)
counter has changed.
Indicates that a new isochronous cycle has started. This bit is set when
the low-order bit of the cycleCount (see Table 49) toggles.
Indicates the PHY core requests an interrupt through a status transfer.
Indicates that an OHCI register access failed due to a missing SCLK
clock signal from the PHY. When a register access fails, this bit will be
set before the next register access.
Indicates that the PHY core chip has entered bus reset mode.
A SelfID packet stream has been received. It is generated at the end of
the bus initialization process. This bit is turned off simultaneously when
bit 17 (busReset) is turned on.
Secondary indication of the end of a SelfID packet stream. This bit will
be set by the OHCI when it sets SelfIDcomplete, and will retain state
independent of the busReset bit of this register.
Reserved. Bits 14:10 return 0s when read.
Indicates that the FW323 sent a lock response for a lock request to a
serial bus register, but did not receive an ack_complete.
Indicates that a host bus error occurred while the FW323 was trying to
write a 1394 write request, which had already been given an
ack_complete, into system memory.
Isochronous Receive DMA Interrupt. Indicates that one or more
isochronous receive contexts have generated an interrupt. This is not a
latched event; it is the ORing of all bits in the Isochronous Receive
Interrupt Event and Isochronous Receive Interrupt Mask registers. The
Isochronous Receive Interrupt Event register (see Table 44) indicates
which contexts have interrupted.
Isochronous Transmit DMA Interrupt. Indicates that one or more
isochronous transmit contexts have generated an interrupt. This is not
a latched event; it is the ORing of all bits in the Isochronous Transmit
Interrupt Event (see Table 42) and Isochronous Transmit Interrupt
Mask (see Table 43) registers. The Isochronous Transmit Interrupt
Event register indicates which contexts have interrupted.
Indicates that a packet was sent to an asynchronous receive response
context buffer and the descriptor’s xferStatus and resCount fields have
been updated.
Indicates that a packet was sent to an asynchronous receive request
context buffer and the descriptor’s xferStatus and resCount fields have
been updated.
Asynchronous Receive Response DMA Interrupt. This bit is conditionally set upon completion of an ARRS DMA context command
descriptor.
Asynchronous Receive Request DMA Interrupt. This bit is conditionally set upon completion of an ARRQ DMA context command
descriptor.
Asynchronous Response Transmit DMA Interrupt. This bit is conditionally set upon completion of an ATRS DMA command.
Asynchronous Request Transmit DMA Interrupt. This bit is conditionally set upon completion of an ATRQ DMA command.
Agere Systems Inc.
53
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Interrupt Mask (IntMask) Register
The Interrupt Mask set/clear register is used to enable/disable the various FW323 interrupt sources. Reads from
either the set register or the clear register always return the contents of the Interrupt Mask register. In all cases
except masterIntEnable (bit 31), the enables for each interrupt event align with the Interrupt Event (IntEvent)
register bits (see Table 40). A one bit in the IntMask register enables the corresponding IntEvent register bit to
generate a processor interrupt. A zero bit in IntMask disables the corresponding IntEvent register bit from
generating a processor interrupt. A bit is set in the IntMask register by writing a one to the corresponding bit in the
IntMaskSet address and cleared by writing a one to the corresponding bit in the IntMaskClear address.
Offset:
Default:
Reference:
88h set register
8Ch clear register
XXXX 0XXXh
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 6.2.
Table 41. Interrupt Mask Register Description
54
Bit
Field Name
Type
Description
31
masterIntEnable
RSCU
30
vendorSpecific
RSC
29
softInterrupt
RSC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14:10
Reserved
ack_Tardy
phyRegRcvd
cycleTooLong
unrecoverableError
cycleInconsistent
cycleLost
cycle64Seconds
cycleSynch
PHY
regAccessFail
busReset
selfIDcomplete
SelfIDcomplete2
Reserved
R
RSCU
Master Interrupt Enable. If this bit is set, then external interrupts
are generated in accordance with the Interrupt Mask register. If this
bit is cleared, then external interrupts are not generated, regardless
of the Interrupt Mask register settings. The value of masterIntEnable
has no effect on the value returned by reading the IntEventClear.
When this bit is set, this vendor-specific interrupt mask enables
interrupt generation when bit 30 (vendorSpecific) of the Interrupt
Event register (Table 40) is set.
Soft Interrupt. This bit may be used by software to generate a host
controller interrupt for its own use. When set, this bit enables the
corresponding IntEvent register bit to generate a processor interrupt.
Reserved. Bit 28 returns 0 when read.
A one bit enables the corresponding IntEvent register bit to
generate a processor interrupt. A zero bit disables the
corresponding IntEvent register bit from generating a processor
interrupt.
R
Reserved. Bits 14:10 return 0s when read.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Table 41. Interrupt Mask Register Description (continued)
Bit
Field Name
Type
Description
9
8
7
6
5
4
3
2
1
0
lockRespErr
postedWriteErr
isochRx
isochTx
RSPkt
RQPkt
ARRS
ARRQ
respTxComplete
reqTxComplete
RSCU
When set, these bits enable the corresponding IntEvent register bits
to generate a processor interrupt.
Agere Systems Inc.
55
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Isochronous Transmit Interrupt Event (isoXmitIntMask) Register
The Isochronous Transmit Interrupt Event (isoXmitIntMask) set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an
OUTPUT_LAST command completes and its interrupt bits are set. Upon determining that the Interrupt Event register isochTx (bit 6) (see Table 40) interrupt has occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set by an asserting edge of the corresponding interrupt signal, or
by writing a 1 in the corresponding bit in the set register. The only mechanism to clear the bits in this register is to
write a 1 to the corresponding bit in the clear register.
Reading the isoXmitIntEventSet register returns the current state of the isoXmitIntEvent register. Reading the
isoXmitIntEventClear register returns the masked version of the isoXmitIntEvent register, i.e., the bit-wise AND
function of isoXmitIntEvent and isoXmitIntMask.
Offset:
Default:
Reference:
90h
set register
94h
clear register
0000 00XXh
1394 Open Host Controller Specification, Rev. 1.1, Section 6.3
Table 42. Isochronous Transmit Interrupt Event Register Description
Bit
Field Name
31:8
7
Reserved
isoXmit7
6
isoXmit6
5
isoXmit5
4
isoXmit4
3
isoXmit3
2
isoXmit2
1
isoXmit1
0
isoXmit0
56
Type
Description
R
Reserved. Bits 31:8 return 0s when read.
RSCU Isochronous transmit channel 7 caused the interrupt event register bit 6 (isochTx)
interrupt.
RSCU Isochronous transmit channel 6 caused the interrupt event register bit 6 (isochTx)
interrupt.
RSCU Isochronous transmit channel 5 caused the interrupt event register bit 6 (isochTx)
interrupt.
RSCU Isochronous transmit channel 4 caused the interrupt event register bit 6 (isochTx)
interrupt.
RSCU Isochronous transmit channel 3 caused the interrupt event register bit 6 (isochTx)
interrupt.
RSCU Isochronous transmit channel 2 caused the interrupt event register bit 6 (isochTx)
interrupt.
RSCU Isochronous transmit channel 1 caused the interrupt event register bit 6 (isochTx)
interrupt.
RSCU Isochronous transmit channel 0 caused the interrupt event register bit 6 (isochTx)
interrupt.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Isochronous Transmit Interrupt Mask (isoXmitIntMask) Register
The Isochronous Transmit Interrupt Mask set/clear register is used to enable the isochTx interrupt source on a
per-channel basis. Reads from either the set register or the clear register, always return the contents of the
Isochronous Transmit Interrupt Mask register. In all cases, the enables for each interrupt event align with the
event register bits detailed in Table 42.
Offset:
Default:
Reference:
98h set register
9Ch clear register (returns IsoXmitEvent and IsoXmitMask when read)
0000 00XXh
1394 Open Host Controller Specification, Rev. 1.1, Section 6.3
Table 43. Isochronous Transmit Interrupt Event Description
Bit
Field Name
Type
Description
31:8
7:0
Reserved
isoXmit7:isoXmit0
R
RSCU
Reserved. Bits 31:8 return 0s when read.
Setting one of these bits enables the corresponding interrupt
event in the isoXmitIntEvent register. Clearing a bit in this register
disables the corresponding interrupt event in the isoXmitIntEvent
register.
Agere Systems Inc.
57
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Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Isochronous Receive Interrupt Event (isoRecvIntEvent) Register
The Isochronous Receive Interrupt Event set/clear register reflects the interrupt state of the isochronous receive
contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes
and its interrupt bits are set. Upon determining that the interrupt event register isochRx (bit 7) interrupt has
occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are
set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set
register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register.
The isoRecvIntMask register is ANDed with the isoRecvIntEvent register to enable selected bits to generate processor interrupts. Reading the isoRecvIntEventSet register returns the current state of the isoRecvIntEvent register. Reading isoRecvIntEventClear register returns the masked version of the isoRecvIntEvent register, i.e., the bitwise AND function of isoRecvtIntEvent and isoRecvtIntMask.
Offset:
Default:
Reference:
A0h set register
A4h clear register
0000 0000h
1394 Open Host Controller Specification, Rev. 1.1, Section 6.4
Table 44. Isochronous Receive Interrupt Event Description
Bit
Field Name
Type
Description
31:8
Reserved
isoRecv7
R
RSCU
isoRecv6
RSCU
isoRecv5
RSCU
isoRecv4
RSCU
isoRecv3
RSCU
isoRecv2
RSCU
isoRecv1
RSCU
isoRecv0
RSCU
Reserved. Bits 31:8 return 0s when read.
Isochronous receive context 7 caused the interrupt event register bit 7
(isochRx) interrupt.
Isochronous receive context 6 caused the interrupt event register bit 7
(isochRx) interrupt.
Isochronous receive context 5 caused the interrupt event register bit 7
(isochRx) interrupt.
Isochronous receive context 4 caused the interrupt event register bit 7
(isochRx) interrupt.
Isochronous receive context 3 caused the interrupt event register bit 7
(isochRx) interrupt.
Isochronous receive context 2 caused the interrupt event register bit 7
(isochRx) interrupt.
Isochronous receive context 1 caused the interrupt event register bit 7
(isochRx) interrupt.
Isochronous receive context 0 caused the interrupt event register bit 7
(isochRx) interrupt.
7
6
5
4
3
2
1
0
58
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Isochronous Receive Interrupt Mask (isoRecvIntMask) Register
The Isochronous Receive Interrupt Mask set/clear register is used to enable the isochRx interrupt source on a
per-channel basis. Reads from either the set register or the clear register always return the contents of the
Isochronous Transmit Interrupt Mask register. In all cases, the enables for each interrupt event correspond to the
isoRecvIntEvent register bits. Setting a bit in this register enables the corresponding interrupt event in the
isoRecvIntEvent register. Clearing a bit in this register disables the corresponding interrupt event in the
isoRecvIntEvent register.
Offset:
Default:
Reference:
A8h set register
ACh clear register
0000 000Xh
1394 Open Host Controller Specification, Rev. 1.1, Section 6.4
Fairness Control Register
The Fairness Control register provides a mechanism by which software can direct the host controller to transmit
multiple asynchronous requests during a fairness interval, as specified by the IEEE-1394a Specification.
Offset:
Default:
Reference:
DCh
0000 0000h
1394 Open Host Controller Specification, Rev. 1.1, Section 5.9
Table 45. Fairness Control Register Description
Bit
31:8
7:0
Field Name Type
Reserved
pri_req
Agere Systems Inc.
R
RW
Description
Reserved. Bits 31:8 return 0s when read.
This field specifies the maximum number of priority arbitration requests for asynchronous request packets that the link is permitted to make of the PHY core during
the fairness interval.
59
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Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Link Control Register
The Link Control register provides flags to enable and configure the link core cycle timer and receiver portions of
the FW323.
Offset:
Default:
Reference:
E0h set register
E4h clear register
00X0 0X00h
1394 Open Host Controller Specification, Rev. 1.1, Section 5.10
Table 46. Link Control Register Description
60
Bit
Field Name
Type
Description
31:23
22
Reserved
cycleSource
R
RSC
21
cycleMaster
RSCU
20
CycleTimerEnable
RSC
19:11
10
Reserved
RcvPhyPkt
R
RSC
9
RcvSelfID
RSC
8:7
6
Reserved
tag1SyncFilterLock
R
RS
5:0
Reserved
R
Reserved. Bits 31:23 return 0s when read.
Set to 0, since the FW323 does not support an external cycle
timer.
When this bit is set, and the FW323 PHY core has notified the
OHCI core that it is root, the OHCI generates a cycle start packet
every time the cycle timer rolls over, based on the setting of bit 22.
When this bit is cleared, the OHCI accepts received cycle start
packets to maintain synchronization with the node that is sending
them. This bit is automatically reset when bit 25 (cycleTooLong) of
the Interrupt Event register (see Table 40) is set and cannot be set
until bit 25 (cycleTooLong) is cleared.
When this bit is set, the cycle timer offset counts cycles of the
24.576 MHz clock and rolls over at the appropriate time based on
the settings of the above bits. When this bit is cleared, the cycle
timer offset does not count.
Reserved. Bits 19:11 return 0s when read.
When this bit is set, the receiver accepts incoming PHY core
packets into the AR request context if the AR request context is
enabled. This does not control receipt of self-identification packets
received outside of the SelfID phase of bus initialization.
When this bit is set, the receiver accepts incoming self-identification packets. Before setting this bit to 1, software must ensure that
the SelfID Buffer Pointer register contains a valid address.
Reserved.
When this bit is set, the tag1SyncFilter bit of the IR Context Match
register (see Table 60) equals one for all IR contexts. When this bit
is cleared, the tag1SynchFilter bit has read/write access. A hardware reset clears this bit to 0. A soft reset has no effect.
Reserved. Bits 5:0 return 0s when read.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Node Identification Register
The Node Identification register contains the address of the node on which the OHCI resides, and indicates the
valid node number status. The 16-bit combination of the busNumber field (bits 15:6) and the NodeNumber field
(bits 5:0) is referred to as the node ID.
Offset:
Default:
Reference:
E8h
0000 FFXXh
1394 Open Host Controller Specification, Rev. 1.1, Section 5.11
Table 47. Node Identification Register Description
Bit
Field Name
Type
31
iDValid
RU
30
29:28
27
26:16
15:6
5:0
Description
This bit indicates whether or not the FW323 has a valid node number. It is cleared
when a 1394 bus reset is detected and set when the FW323 receives a new node
number from the PHY core.
root
RU This bit is set during the bus reset process if the attached PHY core is root.
Reserved
R
Reserved. Bits 29:28 return 0s when read.
CPS
RU Set if the PHY core is reporting that cable power status is OK.
Reserved
R
Reserved. Bits 26:16 return 0s when read.
busNumber RWU This number is used to identify the specific 1394 bus to which the FW323 belongs
when multiple 1394-compatible buses are connected via a bridge.
NodeNumber RU This number is the physical node number established by the PHY core during
self-identification. It is automatically set to the value received from the PHY core
after the self-identification phase. If the PHY core sets the nodeNumber to 63,
then software should not set the run bit of the ContextControl register for either of
the AT DMA contexts (see Table 54).
Agere Systems Inc.
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Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
PHY Core Layer Control Register
The PHY Core Layer Control register is used to read or write a PHY Core register.
Offset:
Default:
Reference:
ECh
0000 0000h
1394 Open Host Controller Specification, Rev. 1.1, Section 5.12
Table 48. PHY Core Layer Control Register Description
Bit
Field Name
Type
31
rdDone
RU
30:28
27:24
23:16
15
Reserved
rdAddr
rdData
rdReg
14
wrReg
13:12
11:8
7:0
Reserved
regAddr
wrData
Description
This bit is cleared to 0 by the FW323 when either bit 15 (rdReg) or bit 14 (wrReg)
is set. This bit is set when a register transfer is received by the OHCI core from
the PHY core and rdData is updated.
R
Reserved. Bits 30:28 return 0s when read.
RU This is the address of the register most recently received from the PHY core.
RU This field is the contents of a PHY Core register, which have been read at rdAddr.
RWU This bit is set by software to initiate a read request to a PHY Core register and is
cleared by hardware when the request has been sent. Bit 14 (wrReg) must not be
set when bit 15 (rdReg) is set.
RWU This bit is set by software to initiate a write request to a PHY Core register and is
cleared by hardware when the request has been sent. Bit 15 (rdReg) must not be
set when bit 14 (wrReg) is set.
R
Reserved. Bits 13:12 return 0s when read.
RW This field is the address of the PHY Core register to be written or read.
RW This field is the data to be written to a PHY Core register and is ignored for reads.
Isochronous Cycle Timer Register
The Isochronous Cycle Timer register indicates the current cycle number and offset. When the FW323 is cycle
master, this register is transmitted with the cycle start message. When the FW323 is not cycle master, this register
is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the
fields can continue incrementing on their own (if programmed) to maintain a local time reference.
Offset:
Default:
Reference:
F0h
XXXX XXXXh
1394 Open Host Controller Specification, Rev. 1.1, Section 5.13
Table 49. Isochronous Cycle Timer Register Description
62
Bit
Field Name
31:25
cycleSeconds
24:12
cycleCount
11:0
cycleOffset
Type
Description
RWU This field counts seconds [rollovers from bits 24:12 (cycleCount field)]
modulo 128.
RWU This field counts cycles [rollovers from bits 11:0 (cycleOffset field)] modulo
8000.
RWU This field counts 24.576 MHz clocks modulo 3072, i.e., 125 ms. If an
external 8 kHz clock configuration is being used, then this bit must be set to
0 at each tick of the external clock.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Asynchronous Request Filter High Register
The Asynchronous Request Filter High set/clear register is used to enable asynchronous receive requests on a
per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context
or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set in this register, then the packet is not acknowledged and the request is not queued. The node ID comparison is done if the
source node is on the same bus as the FW323. All nonlocal bus-sourced packets are not acknowledged unless
bit 31 in this register is set.
Offset:
Default:
Reference:
100h set register
104h clear register
0000 0000h
1394 Open Host Controller Specification, Rev. 1.1, Section 5.14
Table 50. Asynchronous Request Filter High Register Description
Bit
Field Name
Type
Description
31
asynReqResourceAll RSCU If this bit is set, then all asynchronous requests received by the FW323 from
nonlocal bus nodes are accepted and the values of all asynReqResourceN
bits will be ignored. Set/Clear operations to this register while the
IntEvent.busReset bit (see Table 40) is asserted will have no effect. A bus
reset will not affect the value of the asynReqResourceAll bit.
30:0 asynReqResourceN RSCU If this bit is set, then asynchronous requests received from node N (where
N = the bit number + 32) on local bus are accepted by FW323. All asynReqResourceN bits will be cleared to zero when a bus reset occurs. Set/
Clear operations to this register while the IntEvent.busReset bit (see Table
40) is asserted will have no effect.
Asynchronous Request Filter Low Register
The Asynchronous Request Filter Low set/clear register is used to enable asynchronous receive requests on a
per-node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves
identically to the Asynchronous Request Filter High register.
Offset:
Default:
Reference:
108h set register
10Ch clear register
0000 0000h
1394 Open Host Controller Specification, Rev. 1.1, Section 5.14
Table 51. Asynchronous Request Filter Low Register Description
Bit
Field Name
Type
Description
31:0 asynReqResourceN RSCU If this bit is set for local bus node number N (where N = the bit number from
0 to 31), then asynchronous requests received by the FW323 from that node
are accepted. All asynReqResourceN bits will be cleared to zero when a bus
reset occurs. Set/Clear operations to this register while the
IntEvent.busReset bit (see Table 40) is asserted will have no effect.
Agere Systems Inc.
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Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Physical Request Filter High Register
The Physical Request Filter High set/clear register is used to enable physical receive requests on a per-node
basis and handle the upper-node IDs. When a packet is destined for the physical request context and the node ID
has been compared against the ARRQ registers, then the comparison is done again with this register. If the bit
corresponding to the node ID is not set in this register, then the request is handled by the ARRQ context instead
of the physical request context.
Offset:
Default:
Reference:
110h set register
114h clear register
0000 0000h
1394 Open Host Controller Specification, Rev. 1.1, Section 5.14.2
Table 52. Physical Request Filter High Register Description
Bit
Field Name
Type
Description
31
physReqResourceAllBuses
RSC
30:0
physReqResourceN
RSC
If this bit is set, then all asynchronous requests received by the FW323
from nonlocal bus nodes are accepted. Set/Clear operations to this
register while the IntEvent.busReset bit (see Table 40) is asserted will
have no effect. A bus reset will not affect the value of the physReqResourceAllBuses bit.
If this bit is set, requests received by the FW323 from local bus node N
(where N = bit number + 32) will be handled through the physical
request context. Set/Clear operations to this register while the
IntEvent.busReset bit (see Table 40) is asserted will have no effect. All
physReqResourceN bits will be cleared to zero when a bus reset
occurs.
Physical Request Filter Low Register
The Physical Request Filter Low set/clear register is used to enable physical receive requests on a per-node
basis and handle the lower-node IDs. When a packet is destined for the physical request context and the node ID
has been compared against the Asynchronous Request Filter registers, then the node ID comparison is done
again with this register. If the bit corresponding to the node ID is not set in this register, then the request is
handled by the asynchronous request context instead of the physical request context.
Offset:
Default:
Reference:
118h set register
11Ch clear register
0000 0000h
1394 Open Host Controller Specification, Rev. 1.1, Section 5.14.2
Table 53. Physical Request Filter Low Register Description
Bit
Field Name
31:0 physReqResourceN
64
Type
Description
RSC
If this bit is set, requests received by the FW323 from local bus node N
(where N = bit number) will be handled through the physical request context.
Set/Clear operations to this register while the IntEvent.busReset bit (see
Table 40) is asserted will have no effect. All physReqResourceN bits will be
cleared to zero when a bus reset occurs.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Asynchronous Context Control Register
The Asynchronous Context Control set/clear register controls the state and indicates status of the DMA context.
Offset:
Default:
Reference:
180h
set register (ATRQ)
184h
clear register (ATRQ)
1A0h
set register (ATRS)
1A4h
clear register (ATRS)
1C0h
set register (ARRQ)
1C4h
clear register (ARRQ)
1E0h
set register (ARRS)
1E4h
clear register (ARRS)
0000 X0XXh
1394 Open Host Controller Specification, Rev. 1.1, Section 7.22, 8.3.2, 3.1.1
Table 54. Asynchronous Context Control Register Description
Bit
Field Name
Type
Description
31:16
15
Reserved
run
R
RSCU
14:13
12
Reserved
wake
R
RSU
11
dead
RU
10
9:8
7:5
active
Reserved
spd
(Note: These bits are
reserved, undefined
for the ATRQ and
ATRS contexts.)
RU
R
RU
Reserved. Bits 31:16 return 0s when read.
This bit is set by software to enable descriptor processing for the
context and cleared by software to stop descriptor processing. The
FW323 changes this bit (i.e., sets it to 0) only on a hardware or software reset.
Reserved. Bits 14:13 return 0s when read.
Software sets this bit to cause the FW323 to continue or resume
descriptor processing. The FW323 clears this bit on every descriptor
fetch.
The FW323 sets this bit when it encounters a fatal error and clears the
bit when software resets bit 15 (run).
The FW323 sets this bit to 1 when it is processing descriptors.
Reserved. Bits 9:8 return 0s when read.
This field indicates the speed at which a packet was received or transmitted, and only contains meaningful information for receive contexts.
This field is encoded as:
4:0
eventcode
Agere Systems Inc.
000 = 100 Mbits/s.
001 = 200 Mbits/s.
010 = 400 Mbits/s.
RU
All other values are reserved. Software should not attempt to interpret
the contents of this field while the active or wake bits are set.
This field holds the acknowledge sent by the link core for this packet or
an internally generated error code if the packet was not transferred
successfully.
65
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Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Asynchronous Context Command Pointer Register
The Asynchronous Context Command Pointer register contains a pointer to the address of the first descriptor block
that the FW323 accesses when software enables the context by setting the Asynchronous Context Control register
bit 15 (run).
Offset:
Default:
Reference:
18Ch (ATRQ)
1ACh (ATRS)
1CCh (ARRQ)
1ECh (ARRS)
XXXX XXXXh
1394 Open Host Controller Specification, Rev. 1.1, Sections 3.1.2, 7.2.1, 8.3.1
Table 55. Asynchronous Context Command Pointer Register Description
66
Bit
Field Name
Type
Description
31:4
descriptorAddress
RWU
3:0
Z
RWU
Contains the upper 28 bits of the address of a 16-byte aligned
descriptor block.
Indicates the number of contiguous descriptors at the address pointed
to by the descriptor address. If Z is 0, then it indicates that the descriptorAddress field (bits 31:4) is not valid. Valid values for z are context
specific. Refer to the OHCI specification for more details.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Isochronous Transmit Context Control (IT DMA ContextControl) Register
The Isochronous Transmit Context Control set/clear register controls options, state, and status for the
isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number
(n = 0:7).
Offset:
Default:
Reference:
200h + (16 * n) set register
204h + (16 * n) clear register
XXXX X0XXh
1394 Open Host Controller Specification, Rev. 1.1, Sections 9.2, 3.1.1
Table 56. Isochronous Transmit Context Control Register Description
Bit
Field Name
Type
Description
31
cycleMatchEnable
RSCU
30:16
cycleMatch
RSC
15
run
RSCU
14:13
12
Reserved
wake
R
RSU
11
dead
RU
10
9:5
4:0
active
Reserved
event code
RU
R
RU
When this bit is set to 1, processing occurs such that the packet
described by the context’s first descriptor block is transmitted in the
cycle whose number is specified in the cycleMatch field (bits 30:16).
The cycleMatch field (bits 30:16) must match the low-order 2 bits of
cycleSeconds and the 13-bit cycleCount field in the cycle start packet
that is sent or received immediately before isochronous transmission
begins. Since the isochronous transmit DMA controller may work
ahead, the processing of the first descriptor block may begin slightly in
advance of the actual cycle in which the first packet is transmitted. The
effects of this bit, however, are impacted by the values of other bits in
this register and are explained in the 1394 Open Host Controller Interface Specification. Once the context has become active, hardware
clears this bit.
Contains a 15-bit value, corresponding to the low-order 2 bits of the bus
isochronous Cycle Time register cycleSeconds field (bits 31: 25) and
the cycleCount field (bits 24:12) (see Table 49). If bit 31
(cycleMatchEnable) is set, then this isochronous transmit DMA context
becomes enabled for transmits when the low-order 2 bits of the bus
Isochronous Cycle Timer register cycleSeconds field (bits 31:25) and
the cycleCount field (bits 24:12) value equal this field’s (cycleMatch)
value.
This bit is set by software to enable descriptor processing for the
context and cleared by software to stop descriptor processing. The
FW323 changes this bit only on a hardware or software reset.
Reserved. Bits 14:13 return 0s when read.
Software sets this bit to cause the FW323 to continue or resume
descriptor processing. The FW323 clears this bit on every descriptor
fetch.
The FW323 sets this bit when it encounters a fatal error and clears the
bit when software resets bit 15 (run).
The FW323 sets this bit to 1 when it is processing descriptors.
Reserved. Bits 9:5 return 0s when read.
Following an OUTPUT_LAST* command, the error code is indicated in
this field. Possible values are ack_complete, evt_descriptor_read,
evt_data_read, and evt_unknown.
Agere Systems Inc.
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Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Isochronous Transmit Context Command Pointer Register
The Isochronous Transmit Context Command Pointer register contains a pointer to the address of the first descriptor block that the FW323 accesses when software enables an isochronous transmit context by setting the Isochronous Transmit Context Control register bit 15 (run). The n value in the following register addresses indicates the
context number (n = 0:7).
Offset:
Default:
Reference:
20Ch + (16 * n)
XXXX XXXXh
1394 Open Host Controller Specification, Rev. 1.1, Sections 9.2.1, 3.1.2
Table 57. Isochronous Transmit Context Command Pointer Register Description
68
Bit
Field Name
Type
Description
31:4
descriptorAddress
RWU
3:0
Z
RWU
Address of the context program, which will be executed when a DMA
context is started. All descriptors are 16-byte aligned, so the four least
significant bits of any descriptor address must be zero.
Indicates how many physically contiguous descriptors are pointed to by
descriptorAddress.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Isochronous Receive Context Control (IR DMA ContextControl) Register
The Isochronous Receive Context Control set/clear register controls options, state, and status for the isochronous
receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0:7).
Offset:
Default:
Reference:
400h + (32 * n) set register
404h + (32 *n) clear register
X000 X0XXh
1394 Open Host Controller Specification, Rev. 1.1, Sections 10.3, 3.1.2
Table 58. Isochronous Receive Context Control Register Description
Bit
Field Name
Type
Description
31
bufferFill
RSC
30
isochHeader
RSC
29
cycleMatchEnable
RSCU
28
multiChanMode
RSC
27
dualBufferMode
RSC
26:16
Reserved
R
When this bit is set, received packets are placed back-to-back to completely fill each receive buffer. When this bit is cleared, each received
packet is placed in a single buffer. If bit 28 (multiChanMode) is set to 1,
then this bit must also be set to 1. The value of this bit must not be
changed while bit 10 (active) or bit 15 (run) is set.
When this bit is 1, received isochronous packets include the complete
4-byte isochronous packet header seen by the link layer. The end of the
packet is marked with an xferStatus in the first doublet, and a 16-bit
timeStamp indicating the time of the most recently received (or sent)
cycleStart packet. When this bit is cleared, the packet header is stripped
off of received isochronous packets. The packet header, if received,
immediately precedes the packet payload. The value of this bit must not
be changed while bit 10 (active) or bit 15 (run) is set.
When this bit is set, the context begins running only when the 15-bit
cycleMatch field (bits 26:12) in the IRContext Match register (see Table
60) matches the two low-order bits of the CycleSeconds field and the
13-bit CycleCount field in the CycleTimer register. The effects of this bit,
however, are impacted by the values of other bits in this register. Once
the context has become active, hardware clears this bit. The value of this
bit must not be changed while bit 10 (active) or bit 15 (run) is set.
When this bit is set, the corresponding isochronous receive DMA context
receives packets for all isochronous channels enabled in the Isochronous Receive Channel Mask High and Isochronous Receive Channel
mask Low registers. The isochronous channel number specified in the
isochronous receive DMA Context Match register is ignored. When this
bit is cleared, the isochronous receive DMA context receives packets for
the channel number specified in the Context Match register. Only one
isochronous receive DMA context may use the Isochronous Receive
Channel Mask registers. If more than one Isochronous Receive Context
Control register has this bit set, then results are undefined. The value of
this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1.
When this bit is set, received packets are separated into first and second
payload and streamed independently to the first buffer series and second
buffer series (see OHCI v.1.1, 10.2.3). Both multiChanMode and buffer
fill must be programmed to zero when this bit is set. The value of
dualBufferMode will not be changed while active or run is set.
Reserved. Bits 26:16 return 0s when read.
Agere Systems Inc.
69
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Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Table 58. Isochronous Receive Context Control Register Description (continued)
Bit
Field Name
Type
Description
15
run
RSCU
14:13
12
Reserved
wake
R
RSU
11
dead
RU
10
9:8
7:5
active
Reserved
spd
RU
R
RU
This bit is set by software to enable descriptor processing for the context
and cleared by software to stop descriptor processing. The FW323
changes this bit only on a hardware or software reset.
Reserved. Bits 14:13 return 0s when read.
Software sets this bit to cause the FW323 to continue or resume descriptor processing. The FW323 clears this bit on every descriptor fetch.
The FW323 sets this bit when it encounters a fatal error and clears the
bit when software resets bit 15 (run).
The FW323 sets this bit to 1 when it is processing descriptors.
Reserved. Bits 9:8 return 0s when read.
This field indicates the speed at which the packet was received.
000 = 100 Mbits/s.
001 = 200 Mbits/s.
010 = 400 Mbits/s.
4:0
event code
RU
All other values are reserved.
Following an INPUT_* command, the error or status code is indicated in
this field (see OHCI v.1.1, 10.3.2 and Table 3-2).
Isochronous Receive Context Command Pointer Register
The Isochronous Receive Context Command Pointer register contains a pointer to the address of the first
descriptor block that the FW323 accesses when software enables an isochronous receive context by setting the
Isochronous Receive Context Control register bit 15 (run). The n value in the following register addresses
indicates the context number (n = 0:7).
Offset:
Default:
Reference:
40Ch + (32 * n)
XXXX XXXXh
1394 Open Host Controller Specification, Rev. 1.1, Sections 10.3, 3.1.2
Table 59. Isochronous Receive Context Command Pointer Register Description
70
Bit
Field Name
Type
Description
31:4
descriptorAddress
RWU
3:0
Z
RWU
Address of the context program which will be executed when a DMA
context is started.
Indicates how many physically contiguous descriptors are pointed to by
descriptor address. In buffer full mode, Z will be either one or zero. In
packet-per-buffer mode, Z will be from zero to eight.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Isochronous Receive Context Match (IR DMA ContextMatch) Register
The Isochronous Receive Context Match register is used to control on which isochronous cycle the context should
start. The register is also used to control which packets are accepted by the context.
Offset:
Default:
Reference:
410Ch + (32 * n)
XXXX XXXXh
1394 Open Host Controller Specification, Rev. 1.1, Section 10.3. 3.
Table 60. Isochronous Receive Context Match Register Description
Bit
Field Name
Type
Description
31
tag3
RW
30
tag2
RW
29
tag1
RW
28
tag0
RW
27
26:12
Reserved
cycleMatch
R
RW
11:8
sync
RW
7
6
Reserved
tag1SyncFilter
R
RW
5:0
channelNumber
RW
If this bit is set, then this context matches on iso receive packets with a
tag field of 11b.
If this bit is set, then this context matches on iso receive packets with a
tag field of 10b.
If this bit is set, then this context matches on iso receive packets with a
tag field of 01b.
If this bit is set, then this context matches on iso receive packets with a
tag field of 00b.
Reserved. Bit 27 returns a 0 when read.
Contains a 15-bit value, corresponding to the low-order 2 bits of cycleSeconds and the 13-bit cycleCount field in the cycleStart packet. If Isochronous Receive Context Control register bit 29 (cycleMatchEnable)
is set, then this context is enabled for receives when the 2 low-order
bits of the Bus Isochronous Cycle Timer register cycleSeconds field
(bits 31:25) and cycleCount field (bits 24:12) value equal this field’s
(cycleMatch) value.
This field contains the 4-bit field, which is compared to the sync field of
each isochronous packet for this channel when the command descriptor’s w field is set to 11b.
Reserved. Bit 7 returns 0 when read.
If this bit and bit 29 (tag1) are set, then packets with tag2’b01 are
accepted into the context if the two most significant bits of the packets
sync field are 00b. Packets with tag values other than 01b are filtered
according to tag0, tag2, and tag3 (bits 28, 30, and 31, respectively)
without any additional restrictions. If this bit is cleared, then this context
matches on isochronous receive packets as specified in bits 28:31
(tag0:tag3) with no additional restrictions. If the tag1SyncFilterLock bit
of the Link Control register is set, then this bit is read only and is set to
one by the OHCI.
This 6-bit field indicates the isochronous channel number for which this
isochronous receive DMA context accepts packets.
Agere Systems Inc.
71
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
FW323 Vendor-Specific Registers
The FW323 contains a number of vendor-defined registers used for diagnostics and control of low-level hardware
functionality. These registers are addressable in the upper 2K of the 4K region defined by PCI Base Address
register 0 (registers defined by the OHCI specification reside in the lower 2K of this region). These registers are
also programmable via the serial EEPROM. These control registers should not be changed when the link is
enabled.
Table 61. FW323 Vendor-Specific Registers Description
Offset
Register Name
Description
12’h800
IsoDMACtrl
12’h808
AsyDMACtrl
12’h840
LinkOptions
Controls PCI access for the isochronous DMA engines. Initial values
are loaded from serial EEPROM, if present (see Table 62 of this data
sheet).
Controls PCI access and AT FIFO threshold for the asynchronous DMA
engines. Initial values are loaded from serial EEPROM, if present (see
Table 63 of this data sheet).
Controls low-level functionality of the link core. Initial values are loaded
from serial EEPROM, if present (see Table 64 of this data sheet).
Isochronous DMA Control
The fields in this register control when the isochronous DMA engines access the PCI bus and how much data they
will attempt to move in a single PCI transaction. The actual PCI burst sizes will also be affected by 1394 packet size,
host memory buffer size, FIFO constraints, and the PCI cache line size.
Offset:
Default:
800h
0000 7373h
Table 62. Isochronous DMA Control Registers Description
Bits
15:12
11:8
7:4
3:0
72
Field
Description
IT Maximum Burst The maximum number of quadlets that will be fetched by the IT DMA in
one PCI transaction. The maximum burst is 16 * (n + 1) quadlets;
n defaults to 7 (128 quadlets). Max value of n is 0xf.
IT Threshold
This field defines the amount of available space that is needed in the IT
FIFO, before the IT DMA will request access to the PCI bus. The
threshold is 16 * (n + 1) quadlets; n defaults to 3 (64 quadlets). Note,
however, that the IT DMA may request access to the PCI bus sooner if
the amount of data to be fetched from memory is less than the amount
of space available in the IT FIFO. Max value of n is 0xf.
IR Maximum Burst The maximum number of quadlets that will be written by the IR DMA in
one PCI transaction. The maximum burst is 16 * (n + 1) quadlets;
n defaults to 7 (128 quadlets). Max value of n is 0xf.
IR Threshold
This field defines the amount of available data that is needed in the IR
FIFO, before the IR DMA will request access to the PCI bus. The
threshold is 16 * (n + 1) quadlets; n defaults to 0 (16 quadlets). Note,
however, that the IR DMA may request access to the PCI bus sooner if
the amount of data available in the FIFO exceeds the space remaining in
the current host memory buffer or a complete packet resides in the
FIFO. Max value of n is 0xf.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Asynchronous DMA Control
The fields in this register control the functionality within the asynchronous and physical DMA engines. Accesses to
the PCI bus and how much data the DMA engines will attempt to move in a single PCI transaction can be controlled. The actual PCI burst sizes will also be affected by 1394 packet size, host memory buffer size, FIFO constraints, and the PCI cache line size.
Offset:
Default:
808h
0010 7373h
Table 63. Asynchronous DMA Control Registers Description
Bits
Field
24
Retry Threshold
Max. Enable
23:16
15:12
11:8
7:4
3:0
Description
When this bit is set, a packet being retried, e.g., due to an ack_busy on the
initial attempt, will behave as if the AT FIFO threshold value was set to the
maximum (n = 0x20). The purpose of this feature is to prevent a packet that
previously experienced a FIFO underrun on the initial transmit attempt from
failing again due to a FIFO underrun on the retry attempt. If this bit is not set,
retried packets will use the same AT FIFO threshold as the initial transmit
attempt. The default value of this field is 0x0.
AT FIFO Threshold This field defines the number of quadlets of packet data that must be available
in the AT FIFO before the link will be notified that there is an asynchronous
packet to be transmitted. (The link will also be signaled that a packet is available
for transmission if the entire packet is in the FIFO, regardless of its size.) The
threshold is 16 * n quadlets; n defaults to a value of 0x10 (256 quadlets). Max
size of n is 0x20 (512 quadlets).
AT Maximum Burst The maximum number of quadlets that will be fetched by the AT or physical read
response DMAs in one PCI transaction. The maximum burst is 16 * (n + 1)
quadlets; n defaults to 7 (128 quadlets). Max value of n is 0xf.
AT Threshold
This field defines the amount of available space that is needed in the AT FIFO,
before the AT or physical read response units will request access to the PCI
bus. The threshold is 16 * (n + 1) quadlets; n defaults to 0 (16 quadlets). Note,
however, that the AT or physical DMAs may request access to the PCI bus
sooner if the amount of data to be fetched from memory is less than the amount
of space available in the AT FIFO. Max value of n is 0xf.
AR Maximum Burst The maximum number of quadlets that will be written by the AR and physical
write DMAs in one PCI transaction. The maximum burst is 16 * (n + 1) quadlets;
n defaults to 7 (128 quadlets). Max value of n is 0xf.
AR Threshold
This field defines the amount of available data that is needed in the AR FIFO,
before the AR DMA will request access to the PCI bus. The threshold is
16 * (n + 1) quadlets; n defaults to 0 (16 quadlets). However, the AR DMA may
request access to the PCI bus sooner if the amount of data available in the
FIFO exceeds the space remaining in the current host memory buffer or a
complete packet resides in the FIFO. Max value of n is 0xf.
Agere Systems Inc.
73
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Registers (continued)
Link Options
The values in this register provide low-level control of configurable features within the FW323 that are beyond
those stated in 1394 and OHCI specifications.
Offset:
Default:
840h
0000 0020h
Table 64. Link Options Register Description
Bits
Field
Description
31
OHCI1.1En
Enables general features of OHCI 1.1 that are not covered by any of the bits below.
30
Reserved
29
RegAccessFailEn
28
InitBMEnable
27
RetryEnable
26
25
Reserved for internal use by the FW323. Must be set to 0x0.
Enables RegAccessFailEn interrupt for SCLK register accesses that fail.
Enables usage of initial registers for loading Bus Management registers on a bus
reset.
Enables retry processing as defined in OHCI 1.1.
ConfigROMEnable Enables config ROM management, including config ROM block reads, as defined in
OHCI 1.1.
DualBufferEnable Enables IR dual-buffer mode processing as defined in OHCI 1.1
Enables skip and FIFO underrun processing in the IT context as defined in
OHCI 1.1.
Reserved for internal use by the FW323. Must be set to 0x0.
24
ITChangeEnable
23
Reserved
22
Reserved
21
Reserved
Read-only status bit. Reserved for internal use by the FW323. Will read back as
0x0.
Reserved for internal use by the FW323. Must be set to 0x0.
20
19:6
Reserved
Reserved for internal use by the FW323. Must be set to 0x0.
5:3
2:0
Reserved
Posted Writes
Cycle Timer
Control
Reserved for internal use by the FW323. Must be set to 0x0.
Number of physical posted writes the link is allowed to queue in the asynchronous
receive FIFO. These three bits [5:3] default to 100b, which is the maximum value.
Values greater than 100b will disable all physical posted writes.
Selects the value the FW323 will use for its isochronous cycle period when the
FW323 is the root node. This value is for debugging purposes only and should not
be set to any value other than its default value in a real 1394 network. This value
defaults to 0.
If 0, cycle = 125 µs.
If 1, cycle = 62.5 µs.
If 2, cycle = 31.25 µs.
If 3, cycle = 15.625 µs.
If 4, cycle = 7.8125 µs.
74
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Register Configuration
PHY Core Register Map
The PHY Core register map is shown below in Table 65.
Reference:
IEEE Standard 1394a-2000, Annex J2
Table 65. PHY Core Register Map
Address
Contents
Bit 0
Bit 1
00002
00012
Bit 2
Bit 3
Bit 4
Bit 5
Physical_ID
RHB
IBR
00102
Extended (7)
00112
Max_speed
Bit 6
Bit 7
R
PS
Gap_count
XXXXX
XXXXX
Total_ports
Delay
01002
LCtrl
Contender
01012
Watchdog
ISBR
01102
01112
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
Page_select
Port_select
XXXXX
10002
Register 0 Page_select
11112
Register 7 Page_select
Jitter
Loop
REQUIRED
Agere Systems Inc.
Pwr_fail
XXXXX
Pwr_class
Timeout
Port_event Enab_accel Enab_multi
RESERVED
75
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Register Configuration (continued)
PHY Core Register Fields
Table 66. PHY Core Register Fields
Field
Size
Type
Power
(In Bits)
Reset Value
Physical_ID
6
R
000000
R
PS
1
1
R
R
0
—
RHB
1
RW
0
IBR
1
RW
0
Gap_count
6
RW
3F16
Extended
3
R
7
Total_ports
4
R
3
Max_speed
3
R
0102
Description
The address of this node is determined during self-identification. A
value of 63 indicates a misconfigured bus; therefore, the link will not
transmit any packets.
When set to one, indicates that this node is the root.
Cable Power Active. The PHY core sets this bit when cable power
measured at the connector is at least 7.5 V. The PHY core clears
this bit when the detectable voltage is below this value.
Root Hold-Off Bit. When set to one, the force_root variable is
TRUE. This instructs the PHY core to attempt to become the root
during the next tree identify process.
Initiate Bus Reset. When set to one, instructs the PHY core to set
ibr TRUE and reset_time to RESET_TIME. These values, in turn,
cause the PHY core to initiate a bus reset without arbitration; the
reset signal is asserted for 166 µs. This bit is self-clearing.
Used to configure the arbitration timer setting to optimize gap times
according to the topology of the bus. See Section 4.3.6 of IEEE
Standard 1394a-2000 for the encoding of this field.
This field has a constant value of seven, which indicates the
extended PHY Core register map.
The number of ports implemented by this PHY core. This count
reflects the number.
Indicates the speed(s) this PHY core supports:
0002 =
0012 =
0102 =
0112 =
1002 =
Delay
4
R
LCtrl
1
RW
Contender
1
RW
Jitter
3
R
Pwr_class
3
RW
76
98.304 Mbits/s.
98.304 and 196.608 Mbits/s.
98.304, 196.608, and 393.216 Mbits/s.
98.304, 196.608, 393.216, and 786.43 Mbits/s.
98.304, 196.608, 393.216, 786.432, and
1,572.864 Mbits/s.
1012 = 98.304, 196.608, 393.216, 786.432, 1,572.864, and
3,145.728 Mbits/s.
All other values are reserved for future definition.
0000
Worst-case repeater delay; total worst-case repeater delay = [144 +
(delay * 20)] ns.
1
Link Active. Cleared or set by software to control the value of the L
bit transmitted in the node’s SelfID packet 0, which will be the logical AND of this bit and LPS active.
See
Cleared or set by software to control the value of the C bit transmitted in the SelfID packet. Powerup reset value is set by the FW323’s
description
CONTENDER pin.
000
The difference between the fastest and slowest repeater data delay
= [(Jitter + 1) * 20] ns.
Power Class. Controls the value of the pwr field transmitted in the
See
SelfID packet. See Section 4.3.4.1 of IEEE Standard 1394a-2000
description
for the encoding of this field. The PC0, PC1, and PC2 pins determine the power reset value.
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Register Configuration (continued)
Table 66. PHY Core Register Fields (continued)
Field
Size Type Power Reset Value
Watchdog
1
RW
0
ISBR
1
RW
0
Loop
Pwr_fail
1
1
RW
RW
0
1
Timeout
1
RW
0
Port_event
1
RW
0
Enab_accel
1
RW
0
Enab_multi
1
RW
0
Page_select
3
RW
000
Port_select
4
RW
0000
Agere Systems Inc.
Description
When set to one, the PHY core will set Port_event to one if
resume operations commence for any port.
Initiate Short (Arbitrated) Bus Reset. A write of one to this bit
instructs the PHY core to set ISBR true and reset_time to
SHORT_RESET_TIME. These values, in turn, cause the PHY
core to arbitrate and issue a short bus reset. This bit is selfclearing.
Loop Detect. A write of one to this bit clears it to zero.
Cable Power Failure Detect. Set to one when the PS bit
changes from one to zero. A write of one to this bit clears it to
zero.
Arbitration State Machine Time-Out. A write of one to this bit
clears it to zero (see MAX_ARB_STATE_TIME).
Port Event Detect. The PHY core sets this bit to one if any of
connected, bias, disabled, or fault change for a port whose
Int_enable bit is one. The PHY core also sets this bit to one if
resume operations commence for any port and watchdog bit is
one. A write of one to this bit clears it to zero.
Enable Arbitration Acceleration. When set to one, the PHY
core will use the enhancements specified in clause 4.4 of
1394a-2000 Specification. PHY core behavior is unspecified if
the value of Enab_accel is changed while a bus request is
pending.
Enable Multispeed Packet Concatenation. When set to one,
the link will signal the speed of all packets to the PHY core.
Selects which of eight possible PHY Core register pages are
accessible through the window at PHY Core register addresses
10002 through 11112, inclusive.
If the page selected by Page_select presents per-port information, this field selects which port’s registers are accessible
through the window at PHY Core register addresses 10002
through 11112, inclusive. Ports are numbered monotonically
starting at zero, p0.
77
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Internal Register Configuration (continued)
The port status page is used to access configuration and status information for each of the PHY core’s ports. The
port is selected by writing zero to Page_select and the desired port number to Port_select in the PHY Core register
at address 01112. The format of the port status page is illustrated by Table 67 below; reserved fields are shown as
XXXXX. The meanings of the register fields in the port status page are defined as type RSC.
Table 67. PHY Core Register Page 0: Port Status Page
Address
Contents
Bit 0
Bit 1
Bit 2
10002
AStat
10012
Negotiated_speed
10102
10112
11002
11012
11102
11112
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
Bit 4
Bit 5
Bit 6
Bit 7
Child
Connected
Bias
Disabled
Int_enable
Fault
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
RESERVED
BStat
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
REQUIRED
78
Bit 3
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Register Configuration (continued)
The meaning of the register fields in the port status page are defined by Table 68 below.
Table 68. PHY Core Register Port Status Page Fields
Field
AStat
Size Type
2
R
Power Reset
Value
—
BStat
Child
2
1
R
R
—
0
Connected
Bias
Disabled
Negotiated_speed
1
1
1
3
R
R
RW
R
0
0
0
000
Int_enable
1
RW
0
Fault
1
RW
0
Agere Systems Inc.
Description
TPA line state for the port:
002 = invalid.
012 = 1.
102 = 0.
112 = Z.
TPB line state for the port (same encoding as AStat).
If this bit is equal to one, the port is a child; otherwise, a parent. The meaning of this bit is undefined from the time a bus
reset is detected until the PHY core transitions to state T1:
child handshake during the tree identify process (see Section
4.4.2.2 in IEEE Standard 1394a-2000).
If equal to one, the port is connected.
If equal to one, incoming TPBIAS is detected.
If equal to one, the port is disabled.
Indicates the maximum speed negotiated between this PHY
core port and its immediately connected port; the encoding is
the same as for the PHY Core register Max_speed field (see
Table 66).
Enable Port Event Interrupts. When set to one, the PHY
core will set Port_event to one if any of connected, bias, disabled, or fault (for this port) change state.
Set to one if an error is detected during a suspend or resume
operation. A write of one to this bit clears it to zero.
79
FW323 06 1394a
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Data Sheet, Rev. 1
December 2005
Internal Register Configuration (continued)
The vendor identification page is used to identify the PHY core’s vendor and compliance level. The page is selected
by writing one to Page_select in the PHY Core register at address 01112. The format of the vendor identification
page is shown in Table 69; reserved fields are shown as XXXXX.
Table 69. PHY Core Register Page 1: Vendor Identification Page
Address
Contents
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
10002
Compliance_level
10012
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
10102
10112
Vendor_ID
11002
11012
11102
Product_ID
11112
REQUIRED
XXXXX
RESERVED
Note: The meaning of the register fields within the vendor identification page are defined by Table 70.
Table 70. PHY Core Register Vendor Identification Page Fields
Field
Compliance_level
Size Type
8
r
Vendor_ID
24
r
Product_ID
24
r
Description
Standard to which the PHY core implementation complies:
0 = not specified
1 = IEEE 1394a-2000
Agere’s FW323 compliance level is 1.
All other values reserved for future standardization.
The company ID or organizationally unique identifier (OUI) of the manufacturer of
the PHY core. Agere’s vendor ID is 00601Dh. This number is obtained from the
IEEE registration authority committee (RAC). The most significant byte of
Vendor_ID appears at PHY Core register location 10102 and the least significant
at 11002.
The meaning of this number is determined by the company or organization that
has been granted Vendor_ID. Agere’s FW323 PHY core product ID is 03236x16*.
The most significant byte of Product_ID appears at PHY Core register location
11012 and the least significant at 11112.
* ’x’ is a minor revision number of the FW323 06 and may be any value from 0 hex to F hex.
Note: The vendor-dependent page provides access to information used in the manufacturing test of the FW323.
80
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Crystal Selection Considerations
The FW323 is designed to use an external 24.576 MHz parallel resonant fundamental mode crystal connected
between the XI and XO terminals to provide the reference for an internal oscillator circuit. The IEEE 1394a-2000
standard requires that FW323 have less than ±100 ppm total variation from the nominal data rate, which is directly
influenced by the crystal. To achieve this, it is recommended that an oscillator with a nominal 50 ppm or less frequency tolerance be used.
The total frequency variation must be kept below ±100 ppm from nominal with some allowance for error introduced
by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the
total frequency variation is less than ±100 ppm.
Load Capacitance
The frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant
mode crystal circuits. Total load capacitance (CL) is a function of not only the discrete load capacitors, but also
capacitances from the FW323 board traces and capacitances of the other FW323 connected components. The values for load capacitors (CA and CB) should be calculated using this formula:
CA = CB = (CL – Cstray) × 2
CA
XI
RL
CB
XO
A
Where:
CL = load capacitance specified by the crystal manufacturer.
Cstray = capacitance of the board and the FW323, typically 2 pF—3 pF.
RL = load resistance; nominal value is 400 Ω; the best value to be used can be determined by customer testing.
Figure 7. Crystal Circuitry
Adjustment to Crystal Loading
The resistor (RL) in Figure 7 is recommended for fine-tuning the crystal circuit. The nominal value for this resistor is
approximately 400 Ω. A more precise value for this resistor is dependent on the specific crystal used. Please refer to
the crystal manufacturer’s data sheet and application notes to determine an appropriate value for RL. A more precise value for this resistor can be obtained by placing different values of RL on a production board and using an
oscilloscope to view the resultant clock waveform at node A for each resistor value. The desired waveform should
have the following characteristics: the waveform should be sinusoidal, with an amplitude as large as possible, but not
greater than 3.3 V or less than 0 V.
Crystal/Board Layout
The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency and minimizing
noise introduced into the FW323 PLL. The crystal and two load capacitors (CA + CB) should be considered as a unit
during layout. They should be placed as close as possible to one another, while minimizing the loop area created by
the combination of the three components. Minimizing the loop area minimizes the effect of the resonant current that
flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possible
to the PHY XI and XO terminals to minimize trace lengths. Vias should not be used to route the XI and XO signals.
Agere Systems Inc.
81
FW323 06 1394a
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Data Sheet, Rev. 1
December 2005
Serial EEPROM Interface
The FW323 features an I 2C compliant serial ROM interface that allows for the connection of an external serial
EEPROM. The interface provides a mechanism to store configurable data such as the global unique identification
(GUID) within an external EEPROM.
The interface consists of the ROM_AD and ROM_CLK pins. ROM_CLK is an output clock provided by the FW323
to the external EEPROM. ROM_AD is bidirectional and is used for serial data/control transfers between the FW323
and the external EEPROM.
The FW323 uses this interface to read the contents of the serial EEPROM in response to the first PCI reset after
powerup. The FW323 also makes the serial ROM interface visible to software through the OHCI defined GUID
ROM register. When the FW323 is operational, the GUID ROM register allows software to initiate reads to the
external EEPROM.
The FW323 EEPROM interface has a number of new and updated features that were not present in earlier
revisions of the chip:
1. Improved external interface timing.
2. OHCI soft reset and D3-to-D0 device state transition will not initiate an EEPROM load.
3. Retry of PCI/OHCI/vendor register accesses during an EEPROM load.
4. Load failure and quick EEPROM detection.
5. EEPROM cache.
6. Automatic update of the OHCI 1394 MiniROM field of the GUID_ROM register.
7. CardBus CIS support.
8. Additional EEPROM image formats, including a CardBus format.
For additional detail, refer to the FW322/FW323 06 EEPROM Interface and Start-Up Behavior Application Note.
ac Characteristics of Serial EEPROM Interface Signals
Table 71. ac Characteristics of Serial EEPROM Interface Signals
Symbol
fROM_CLK
tPW_LOW
tPW_HIGH
Parameter
Frequency of Serial Clock
Width of Serial Clock Pulse Low
Width of Serial Clock Pulse High
tDATA_VALID Time from When Serial Clock Transitions Low Until EEPROM
Returns Valid Data
tFREE
Time I 2C Bus Must be Idle Before a New Transaction Can Be
Started
tHOLD_START FW323 Hold Time for a Valid Start Condition
tSETUP_START FW323 Setup Time for a Valid Start Condition
tHOLD_DATA Data Out Hold Time for the FW323
tSETUP_DATA Data Out Setup Time for the FW323
tRISE_TIME
Rise Time for Serial Clock and Data Out from the FW323
Fall Time for Serial Clock and Data Out from the FW323
tFALL_TIME
tSETUP_STOP FW323 Setup Time for a Valid Stop Condition
tHOLD_EEPROM Data Out Hold Time for EEPROM
82
Min
Max
Unit
—
4.7
4.0
0.1
100
—
—
4.5
kHz
µs
µs
µs
4.7
—
µs
4.0
4.7
0
200
—
—
4.7
100
—
—
—
—
1.0
300
—
—
µs
µs
µs
ns
µs
ns
µs
ns
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
ac Characteristics (continued)
tPW_LOW
tPW_HIGH
tFALL_TIME
tRISE_TIME
tPW_LOW
ROM_CLK
tHOLD_START
tSETUP_START
tSETUP_STOP
tHOLD_DATA
tSETUP_DATA
ROM_AD IN
tDATA_VALID
tFREE
tHOLD_EEPROM
ROM_AD OUT
ROM_CLK: serial clock, ROM_AD: serial data I/O.
1313 (F) R.02
Figure 8. Bus Timing
ROM_CLK
ROM_AD
8TH BIT
ACK
WORD n
tWR(1)
STOP
START
ROM_CLK: serial clock, ROM_AD: serial data I/O.
1314 (F) R.02
Figure 9. Write Cycle Timing
ROM_AD
ROM_CLK
STABLE
STABLE
CHANGE
ROM_CLK: serial clock, ROM_AD: serial data I/O.
1310 (F) R.02
Figure 10. Data Validity
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PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
ac Characteristics (continued)
ROM_AD
ROM_CLK
START
STOP
ROM_CLK: serial clock, ROM_AD: serial data I/O.
1311 (F) R.02
Figure 11. Start and Stop Definition
ROM_CLK
1
8
9
DATA IN
DATA OUT
START
ACK
ROM_CLK: serial clock.
1312 (F) R.02
Figure 12. Output Acknowledge
84
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
NAND Tree Testing
The FW323 can be placed into a NAND tree mode of operation to enable board-level production testing. The
NAND tree mode is designed to allow board-level contact testing of the digital pins of the FW323. To place the
FW323 into NAND tree mode, pins 10 (TEST0), 7 (TEST1), and 124 (PTEST) should all be forced high. (Note: In
normal mode, these inputs are forced low.) The output for NAND tree is pin 6. No clocks are required for NAND tree
testing. When NAND tree is enabled, the NAND tree logic follows the signal ordering in the following table.
To run the test, force all of the inputs in the table below high. At this point, the NAND tree output should be verified
to be high. In the order listed below, force each input low, while keeping previously tested inputs low. After each
input is forced low, the NAND tree output should be verified, and the correct value should be the opposite of the
previous value. Therefore, after forcing the first input low, the NAND tree output should be low, after forcing the second input low (and keeping the first input low), NAND tree output should be high, etc.
Table 72. NAND Tree Testing
Input
Order
Pin #
1
3
2
5
3
Input
Order
Pin #
CARDBUSN
26
67
PCI_AD[11]
CNA
27
65
PCI_AD[12]
128
VAUX_PRESENT
28
64
PCI_AD[13]
4
126
SE
29
63
PCI_AD[14]
5
125
SM
30
62
PCI_AD[15]
6
123
RESETN
31
60
PCI_CBEN[1]
7
92
MPCIACTN
32
59
PCI_PAR
8
91
LPS
33
58
PCI_SERRN
9
90
LKON
34
57
PCI_PERRN
10
89
PC0
35
54
PCI_STOPN
11
88
PC1
36
53
PCI_DEVSELN
12
87
PC2
37
52
PCI_TRDYN
13
86
CONTENDER
38
51
PCI_IRDYN
14
84
PCI_AD[0]
39
48
PCI_FRAMEN
15
83
PCI_AD[1]
40
47
PCI_CBEN[2]
16
80
PCI_AD[2]
41
46
PCI_AD[16]
17
79
PCI_AD[3]
42
45
PCI_AD[17]
18
78
PCI_AD[4]
43
42
PCI_AD[18]
19
76
PCI_AD[5]
44
41
PCI_AD[19]
20
75
PCI_AD[6]
45
40
PCI_AD[20]
21
74
PCI_AD[7]
46
39
PCI_AD[21]
22
73
PCI_CBEN[0]
47
36
PCI_AD[22]
23
70
PCI_AD[8]
48
35
PCI_AD[23]
24
69
PCI_AD[9]
49
34
PCI_IDSEL
25
68
PCI_AD[10]
50
33
PCI_CBEN[3]
Agere Systems Inc.
Pin
Name
Pin
Name
85
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
NAND Tree Testing (continued)
Table 72. NAND Tree Testing (continued)
Input
Order
Pin #
51
31
52
Pin
Name
Input
Order
Pin #
Pin
Name
PCI_AD[24]
60
17
PCI_REQN
30
PCI_AD[25]
61
16
PCI_GNTN
53
29
PCI_AD[26]
62
15
PCI_RSTN
54
28
PCI_AD[27]
63
14
PCI_INTAN
55
25
PCI_AD[28]
64
13
CLKRUNN
56
24
PCI_AD[29]
65
9
ROM_AD
57
23
PCI_AD[30]
66
8
ROM_CLK
58
22
PCI_AD[31]
Output
6
NANDTREE
59
20
PCI_CLK
CARDBUSN
VDD
CNA
VAUX_PRESENT
SE
ROM_AD
NANDTREE
ROM_CLK
5-7276a.r2
Figure 13. Nand Tree Logic Structure
86
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Solder Reflow and Handling
The FW323 has a moisture sensitivity classification of 3, which is determined in accordance with the standard IPC/
JEDEC J-STD-020, Revision A, titled Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. Handling of this device should be in accordance with standard IPC/JEDEC J-STD-033, titled
Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices.
Up to three reflows may be performed using a temperature profile that meets the requirements of Table 3 in standard IPC/JEDEC J-STD-020. The requirements of IPC/JEDEC J-STD-033 must be met. The maximum allowable
body temperature for the FW323 is 220 °C —225 °C. This is the actual tolerance that Agere uses to test the devices
during preconditioning.
Absolute Maximum Voltage/Temperature Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Table 73. Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
VDD
3.0
3.6
V
Input Voltage Range
VI
−0.5
VDD + 0.5
V
Output Voltage Range at Any Output
VO
−0.5
VDD + 0.5
V
Operating Free Air Temperature*
TA
0
70
°C
Tstg
–65
150
°C
Supply Voltage Range
Storage Temperature Range
* External leads can be bonded and soldered safely at temperatures of:
— Up to 300 °C on non-lead-free parts.
— Up to 350 °C on lead-free parts.
Agere Systems Inc.
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FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Electrical Characteristics
Table 74. Analog Characteristics
Parameter
Supply Voltage
Differential Input Voltage
Common-mode Voltage
Source Power Mode
Common-mode Voltage
Nonsource Power Mode*
Receive Input Jitter
Receive Input Skew
Positive Arbitration
Comparator Input
Threshold Voltage
Negative Arbitration
Comparator Input
Threshold Voltage
Speed Signal Input
Threshold Voltage
Output Current
TPBIAS Output Voltage
Current Source for
Connect Detect Circuit
Test Conditions
Symbol
Min
Typ
Max
Unit
Source power node
Cable inputs, 100 Mbits/s operation
Cable inputs, 200 Mbits/s operation
Cable inputs, 400 Mbits/s operation
Cable inputs, during arbitration
TPB cable inputs,
speed signaling off
TPB cable inputs,
S100 speed signaling on
TPB cable inputs,
S200 speed signaling on
TPB cable inputs,
S400 speed signaling on
TPB cable inputs,
speed signaling off
TPB cable inputs,
S100 speed signaling on
TPB cable inputs,
S200 speed signaling on
TPB cable inputs,
S400 speed signaling on
TPA, TPB cable inputs,
100 Mbits/s operation
TPA, TPB cable inputs,
200 Mbits/s operation
TPA, TPB cable inputs,
400 Mbits/s operation
Between TPA and TPB cable inputs,
100 Mbits/s operation
Between TPA and TPB cable inputs,
200 Mbits/s operation
Between TPA and TPB cable inputs,
400 Mbits/s operation
—
VDD—SP
VID—100
VID—200
VID—400
VID—ARB
VCM
3.0
142
132
100
168
1.165
3.3
—
—
—
—
—
3.6
260
260
260
265
2.515
V
mV
mV
mV
mV
V
VCM—SP—100
1.165
—
2.515
V
VCM—SP—200
0.935
—
2.515
V
VCM—SP—400
0.532
—
2.515
V
VCM
1.165
—
2.015
V
VCM—NSP—100
1.165
—
2.015
V
VCM—NSP—200
0.935
—
2.015
V
VCM—NSP—400
0.532
—
2.015
V
—
—
—
1.08
ns
—
—
—
0.5
ns
—
—
—
0.315
ns
—
—
—
0.8
ns
—
—
—
0.55
ns
—
—
—
0.5
ns
VTH+
89
—
168
mV
—
VTH−
–168
—
–89
mV
200 Mbits/s
400 Mbits/s
TPBIAS outputs
At rated I/O current
—
VTH—S200
VTH—S400
IO
VO
ICD
45
266
–5
1.665
—
—
—
—
—
—
139
445
2.5
2.015
76
mV
mV
mA
V
µA
* For a node that does not source power (see Section 4.2.2.2 in IEEE 1394-1995 Standard).
88
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Electrical Characteristics (continued)
Table 75. Driver Characteristics
Parameter
Differential Output Voltage
Off-state Common-mode Voltage
Driver Differential Current,
TPA+, TPA−, TPB+, TPB−
Common-mode Speed Signaling
Current, TPB+, TPB−
Test Conditions
Symbol
Min
Typ
Max
Unit
56 Ω load
Drivers disabled
Driver enabled,
speed signaling off*
200 Mbits/s speed
signaling enabled
400 Mbits/s speed
signaling enabled
VOD
VOFF
IDIFF
172
—
−1.05
—
—
—
265
20
1.05
mV
mV
mA
ISP
−2.53
—
−4.84
mA
ISP
−8.1
—
−12.4
mA
* Limits are defined as the algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− as the algebraic sum of driver
currents.
Table 76. Device Characteristics
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Supply Current:
D0, 3 Ports Active
D0, 2 Ports Active
D0, 1 Port Active
D0, No Ports Active
VDD = 3.3 V
VDD = 3.3 V
VDD = 3.3 V
VDD = 3.3 V
IDD
IDD
IDD
IDD
—
—
—
—
126
112
97
78
—
—
—
—
mA
mA
mA
mA
System Off (D3cold)
VDD = 3.3 Vaux
IDD
—
560*
—
µA
VDD = 3.0 V PCI or
VDD = 3.3 Vaux
VDD = 3.3 Vaux
IDD
—
30
—
mA
IDD
—
1.3
—
mA
IOH max, VDD = min
IOL min, VDD = max
CMOS inputs
CMOS inputs
VI = 0 V
VOH
VOL
VIH
VIL
II
VDD – 0.4
—
0.7 VDD
—
11
—
—
—
—
—
—
0.4
—
0.2 VDD
32
V
V
V
V
µA
System in Standby
(suspend mode = S1)
System in Hibernate
(suspend mode = S1 or S3) or
System in Standby
(suspend mode = S3)
High-level Output Voltage
Low-level Output Voltage
High-level Input Voltage
Low-level Input Voltage
Pull-up Current,
RESETN Input
* This IDD value may differ depending on the system board into which the FW323 06 PCI add-in card is inserted.
Agere Systems Inc.
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PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
Timing Characteristics
Table 77. Switching Characteristics
Symbol
Parameter
Measured
Test Conditions
Min
Typ
Max
Unit
—
—
—
—
—
—
0.15
±0.1
ns
ns
RI = 56 Ω,
CI = 10 pF
RI = 56 Ω,
CI = 10 pF
—
—
1.2
ns
—
—
1.2
ns
—
—
Jitter, Transmit
Transmit Skew
tr
Rise Time, Transmit (TPA/TPB)
TPA, TPB
Between
TPA and TPB
10% to 90%
tf
Fall Time, Transmit (TPA/TPB)
90% to 10%
Table 78. Clock Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
External Clock Source Frequency
f
24.5735
24.5760
24.5785
MHz
90
Agere Systems Inc.
Data Sheet, Rev. 1
December 2005
FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Outline Diagrams
128-Pin TQFP
Dimensions are in millimeters.
16.00 ± 0.20
14.00 ± 0.20
PIN #1 IDENTIFIER ZONE
128
103
1
1.00 REF
102
0.25
GAGE PLANE
SEATING PLANE
0.45/0.75
20.00
± 0.20
DETAIL A
22.00
± 0.20
38
65
0.106/0.200
39
64
0.19/0.27
0.08
DETAIL A
DETAIL B
M
1.40 ± 0.05
DETAIL B
1.60 MAX
SEATING PLANE
0.50 TYP
0.08
0.05/0.15
5-4427r.2 (F)
Ordering Information
Device Code
Package
Comcode
FW323 06
L-FW323-06-DB*†
128-Pin TQFP
128-Pin TQFP
700005872
700060370
* Tape and reel part numbers.
† Lead free: No intentional addition of lead, and less than 1000 ppm.
‡ Agere Systems lead-free devices are fully compliant with the Restriction of Hazardous Substances (RoHS) directive that restricts the content
of six hazardous substances in electronic equipment in the European Union. Beginning July 1, 2006, electronic equipment sold in the European Union must be manufactured in accordance with the standards set by the RoHS directive.
Agere Systems Inc.
91
Microsoft and Windows are registered trademarks of Microsoft Corporation.
The FireWire logo is a trademark and MacOS is a registered trademark of Apple Computer, Inc.
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
Home: http://www.agere.com Sales: http://www.agere.com/sales
E-MAIL:
docmaster@agere.com
N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA:
CHINA: (86) 21-54614688 (Shanghai), (86) 755-25881122 (Shenzhen), (86) 10-65391096 (Beijing)
JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6741-9855, TAIWAN: (886) 2-2725-5858 (Taipei)
EUROPE:
Tel. (44) 1344 296 400
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Agere, Agere Systems, and the Agere logo are registered trademarks of Agere Systems Inc.
Copyright © 2005 Agere Systems Inc.
All Rights Reserved
December 2005
DS05-074CMPR-1 (Replaces DS05-074CMPR)