Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Allows wide range of applications for SONET network termination application as well as generic data moving for high-speed backplane data transfer. Clock/data recovery (CDR) function for high-speed serial backplane data transfer. CDR function uses Agere Systems Inc. proven 622 Mbits/s serial interface core. Two-channel CDR function provides 622 Mbits/s serial interface per channel for a total chip bandwidth of 1.24 Gbits/s (full duplex). Low-voltage differential signaling (LVDS) I/Os for CDR and reference clock signals. 8:1 data multiplexing/demultiplexing (MUX/ deMUX) for 77.76 MHz byte-wide data processing. CDR meets B jitter tolerance specification of ITU-T recommendation G.958. Powerdown option of CDR receiver on a perchannel basis. Pseudo-SONET protocol including A1/A2 framing. SONET scrambling and descrambling for required ones density (optional). Selected transport overhead (TOH) bytes insertion and detection for interdevice communication via the TOH serial link. Streamlined pointer processor (pointer mover) for 8 kHz frame alignment. FIFOs for alignment of incoming data to reference clock. FIFOs optionally align incoming data across all two channels for synchronous transport signal STS-24 operation (in dual STS-12 format). Independent data stream enables in pseudoSONET processor. Supports STS-12/STS-24 redundancy by either software or hardware control for protection switching applications. ■ Low-power 3.3 V supply. ■ –40 °C to +125 °C industrial temperature range. ■ 272-pin ball grid array (PBGA) package. Description The TTSV02622 can support a 1.24 Gbits/s interface for backplane connections. The 1.24 Gbits/s interface is implemented as dual 622 Mbits/s LVDS links. The HSI macrocell is used for clock/data recovery (CDR) and MUX/deMUX between 77.76 MHz bytewide internal data buses and the 622 Mbits/s external serial links. Each 622 Mbits/s serial link uses a pseudo-SONET protocol. SONET A1/A2 framing is used on the link for locating the 8 kHz frame location. The link is also scrambled using the standard SONET scrambler definition to ensure proper transitions on the link for improved CDR performance. Selectable transport overhead (TOH) bytes are insertable in the transmit direction. All bytes can be transparently passed through the device, or all bytes can be inserted via the TOH serial link. In addition, certain microprocessor unit (MPU) selectable bytes can be passed through transparently while in insert mode. Elastic buffers (FIFOs) are used to align each incoming STS-12 link to the core 77.76 MHz clock and 8 kHz frame. These FIFOs will absorb delay variations between 622 Mbits/s links due to timing skews between cards and along backplane traces. For greater variations, a streamlined pointer processor (pointer mover) within the device will align the 8 kHz frames regardless of their incoming frame position. The TTSV02622 supports dual STS-12 mode of operation on the input/output ports. STS-24 is also supported, but it must be received in the dual STS-12 format. When operating in dual STS-12 mode, each of the independent byte streams carries an entire STS-12 within it. Figure 1 on page 2 reveals the byte ordering of the individual STS-12 streams. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Description (continued) 12 9 6 3 11 8 5 2 10 7 4 1 STS-12 #1 24 21 18 15 23 20 17 14 22 19 16 13 STS-12 #2 STS-24 IN DUAL STS-12 FORMAT 1, 12 1, 9 1, 6 1, 3 1, 11 1, 8 1, 5 1, 2 1, 10 1, 7 1, 4 1, 1 STS-12 #1 2, 12 2, 9 2, 6 2, 3 2, 11 2, 8 2, 5 2, 2 2, 10 2, 7 2, 4 2, 1 STS-12 #2 DUAL STS-12 Figure 1. Byte Ordering on Input/Output Interface in STS-12 Mode 2 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Table of Contents Contents Page Features ................................................................................................................................................................... 1 Description................................................................................................................................................................ 1 Pin Information ......................................................................................................................................................... 6 Synchronization ...................................................................................................................................................... 17 HSI Block Interface................................................................................................................................................. 17 Line Interface.......................................................................................................................................................... 17 Architecture ............................................................................................................................................................ 17 Powerdown Mode................................................................................................................................................... 19 Supervisory Features ............................................................................................................................................. 20 Test Features ......................................................................................................................................................... 21 Transmit Direction (Line to Backplane) .................................................................................................................. 22 Transport Overhead Serial Link ........................................................................................................................... 23 A1/A2 Frame Insert and Corruption ..................................................................................................................... 23 B1 Calculation and Insertion ................................................................................................................................ 23 Stream Disable .................................................................................................................................................... 23 Scrambler............................................................................................................................................................. 23 Receiver Block........................................................................................................................................................ 24 Framer Subblock (Backplane to Line).................................................................................................................. 24 B1 Calculate and Descramble (Backplane to Line) ............................................................................................. 27 Internal Parity Generation .................................................................................................................................... 27 FIFO Subblock (Backplane to Line) ..................................................................................................................... 28 Pointer Mover Subblock (Backplane to Line)....................................................................................................... 28 Miscellaneous Functions ........................................................................................................................................ 31 K1/K2, A1/A2 Handling ........................................................................................................................................ 31 SPE C1J1 Outputs............................................................................................................................................... 31 Registers ................................................................................................................................................................ 32 Definition of Register Types................................................................................................................................. 32 Register Map........................................................................................................................................................ 33 Register Descriptions ............................................................................................................................................. 36 Absolute Maximum Ratings.................................................................................................................................... 48 Handling Precautions ............................................................................................................................................. 48 Recommended Operating Conditions .................................................................................................................... 48 Thermal Characteristics.......................................................................................................................................... 49 Power Consumption (Advance).............................................................................................................................. 49 Electrical Characteristics ........................................................................................................................................ 49 Propagation Delay Specifications........................................................................................................................... 49 LVDS I/O ................................................................................................................................................................ 50 LVDS Receiver Buffer Capabilities ...................................................................................................................... 52 Clock and Data Recovery (CDR)............................................................................................................................ 54 Input Data ............................................................................................................................................................ 54 Jitter Tolerance .................................................................................................................................................... 54 Generated Output Jitter ....................................................................................................................................... 54 PLL....................................................................................................................................................................... 54 Input Reference Clock ......................................................................................................................................... 54 Timing Characteristics ............................................................................................................................................ 55 CPU Interface Timing........................................................................................................................................... 61 Outline Diagram...................................................................................................................................................... 63 272-Pin PBGA...................................................................................................................................................... 63 Ordering Information............................................................................................................................................... 64 Agere Systems Inc. 3 TTSV02622 STS-24 Backplane Transceiver Data Sheet June 2003 List of Figures Contents Page Figure 1. Byte Ordering on Input/Output Interface in STS-12 Mode ........................................................................ 2 Figure 2. Pin Diagram of 272-Pin PBGA (Bottom View)........................................................................................... 6 Figure 3. Suggested Schematic for 1.0 V and 1.4 V Reference Voltages.............................................................. 16 Figure 4. Alignment of Two STS-12 Streams ......................................................................................................... 17 Figure 5. Interior View of TTSV02622 .................................................................................................................... 18 Figure 6. Interconnect of Streams for FIFO Alignment........................................................................................... 19 Figure 7. Transmitter Block .................................................................................................................................... 22 Figure 8. Receiver Block ........................................................................................................................................ 24 Figure 9. Framer State Machine............................................................................................................................. 26 Figure 10. Pointer Mover State Machine ................................................................................................................ 30 Figure 11. LVDS Driver and Receiver and Associated Internal Components ........................................................ 51 Figure 12. LVDS Driver and Receiver .................................................................................................................... 51 Figure 13. LVDS Driver .......................................................................................................................................... 51 Figure 14. Input Parallel Port Timing ...................................................................................................................... 55 Figure 15. Transmitter Transport Delay.................................................................................................................. 56 Figure 16. Output Parallel Port Timing ................................................................................................................... 57 Figure 17. Protection Switch Timing....................................................................................................................... 58 Figure 18. Input Serial Port Timing......................................................................................................................... 59 Figure 19. Output Serial Port Timing ...................................................................................................................... 60 Figure 20. Write Transaction .................................................................................................................................. 61 Figure 21. Read Transaction .................................................................................................................................. 62 4 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver List of Tables Contents Page Table 1. Pin Assignments for 272-Pin PBGA by Pin Number Order ........................................................................ 7 Table 2. Pin Assignments for 272-Pin PBGA by Signal Name............................................................................... 10 Table 3. Pin Descriptions ....................................................................................................................................... 12 Table 4. Valid Starting Positions for a STS-MC...................................................................................................... 29 Table 5. SPE and C1J1 Functionality..................................................................................................................... 31 Table 6. Register Map ............................................................................................................................................ 33 Table 7. Register Description ................................................................................................................................. 36 Table 8. Absolute Maximum Ratings...................................................................................................................... 48 Table 9. Handling Precautions ............................................................................................................................... 48 Table 10. Recommended Operating Conditions .................................................................................................... 48 Table 11. Thermal Resistance—Junction to Ambient ............................................................................................ 49 Table 12. Power Consumption (Advance).............................................................................................................. 49 Table 13. LVTTL Electrical Characteristics ............................................................................................................ 49 Table 14. LVDS Receiver dc Data* ........................................................................................................................ 52 Table 15. LVDS Receiver ac Data* ........................................................................................................................ 52 Table 16. LVDS Driver dc Data*............................................................................................................................. 53 Table 17. LVDS Driver ac Data*............................................................................................................................. 53 Table 18. LVDS Driver Reference Data ................................................................................................................. 53 Table 19. Jitter Tolerance....................................................................................................................................... 54 Table 20. Input Parallel Port Timing Requirements................................................................................................ 55 Table 21. Transmitter Transport Delay Timing Requirements................................................................................ 56 Table 22. Output Parallel Port Timing Requirements ............................................................................................. 57 Table 23. Protection Switch Timing Requirements................................................................................................. 58 Table 24. Input Serial Port Timing Requirements................................................................................................... 59 Table 25. Output Serial Port Timing Requirements................................................................................................ 60 Table 26. Write Transaction Timing Requirements ................................................................................................ 61 Table 27. Read Transaction Timing Requirements ................................................................................................ 62 Agere Systems Inc. 5 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Pin Information 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 A1 BALL PAD CORNER 1 A B C D E F G H J K L M N P R T U V W Y Figure 2. Pin Diagram of 272-Pin PBGA (Bottom View) 6 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 1. Pin Assignments for 272-Pin PBGA by Pin Number Order Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 VSS TCK TDI TMS DXP NC PROT_SWITCH_A TOH_INA NC NC TOH_OUTA NC NC NC DOUTA7 DOUTA4 DOUTA0 DOUTA_C1J1 DOUTB7 DOUTB6 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 TDO TRSTN TSTMD SCANEN NC DXN PROT_SWITCH_C TOH_INB NC NC TOH_OUTB NC NC NC DOUTA6 DOUTA3 DOUTA_PAR DOUTB5 DOUTB4 DOUTB3 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 NC NC LVDS_EN NC NC NC NC TX_TOH_CKEN TOH_CLK NC RX_TOH_CKEN RX_TOH_FP NC NC DOUTA5 DOUTA2 DOUTA_SPE DOUTB2 DOUTB1 DOUTB0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 NC NC NC VSS NC VDD NC VSS NC NC VDD NC VSS NC VDD DOUTA1 VSS DOUTB_PAR DOUTB_SPE DOUTB_C1J1 Note: NC refers to no connect. Do not connect pins so designated. Agere Systems Inc. 7 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 1. Pin Assignments for 272-Pin PBGA by Pin Number Order (continued) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name E1 E2 E3 E4 E17 E18 E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H4 STS_INA_P STS_INA_N CTAP_REFA NC NC NC NC NC STS_INB_P STS_INB_N CTAP_REFB VDD VDD NC NC NC NC NC NC NC NC NC NC NC NC NC NC VSS H17 H18 H19 H20 J1 J2 J3 J4 J9 J10 J11 J12 J17 J18 J19 J20 K1 K2 K3 K4 K9 K10 K11 K12 K17 K18 K19 K20 VSS NC NC NC STS_OUTA_P STS_OUTA_N NC NC VSS VSS VSS VSS NC NC NC NC PLL REF PLL_VDDA PLL_VSSA VDD VSS VSS VSS VSS NC NC NC NC L1 L2 L3 L4 L9 L10 L11 L12 L17 L18 L19 L20 M1 M2 M3 M4 M9 M10 M11 M12 M17 M18 M19 M20 N1 N2 N3 N4 STS_OUTB_P STS_OUTB_N NC NC VSS VSS VSS VSS VDD NC NC NC REF10 REF14 LVDS_RESH LVDS_RESL VSS VSS VSS VSS SYS_CLK SYS_FP LINE_FP NC NC NC NC VSS N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 T20 VSS DINA7 DINA6 DINA5 NC NC NC NC DINA4 DINA3 DINA2 DINA1 NC NC NC VDD VDD DINB7 DINA0 DINA_PAR TSTMODE BYPASS RESETRN RESETTN DINB6 DINB5 DINB4 DINB3 Note: NC refers to no connect. Do not connect pins so designated. 8 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 1. Pin Assignments for 272-Pin PBGA by Pin Number Order (continued) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 TSTCLK TSTSHFTLD ETOGGLE VSS TSTMUX3S VDD CPU_ADDR6 VSS CS_N VDD CPU_DATA7 CPU_DATA3 VSS NC VDD DIND4 VSS DINB2 DINB1 DINB0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 MRESET ECSEL LOOPBKEN TSTMUX6S TSTMUX2S NC CPU_ADDR5 CPU_ADDR2 RD_WRN INT_N CPU_DATA6 CPU_DATA2 NC NC NC NC NC NC NC DINB_PAR W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 EXDNUP TSTPHASE TSTMUX8S TSTMUX5S TSTMUX1S NC CPU_ADDR4 CPU_ADDR1 RST_N NC CPU_DATA5 CPU_DATA1 NC NC NC NC NC NC NC NC Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 NC NC TSTMUX7S TSTMUX4S TSTMUX0S NC CPU_ADDR3 CPU_ADDR0 HIZ_N NC CPU_DATA4 CPU_DATA0 NC NC NC NC NC NC NC NC Note: NC refers to no connect. Do not connect pins so designated. Agere Systems Inc. 9 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 2. Pin Assignments for 272-Pin PBGA by Signal Name Signal Name Pin Signal Name Pin Signal Name Pin Signal Name Pin BYPASS CPU_ADDR0 CPU_ADDR1 CPU_ADDR2 CPU_ADDR3 CPU_ADDR4 CPU_ADDR5 CPU_ADDR6 CPU_DATA0 CPU_DATA1 CPU_DATA2 CPU_DATA3 CPU_DATA4 CPU_DATA5 CPU_DATA6 CPU_DATA7 CS_N CTAP_REFA CTAP_REFB DINA_PAR DINA0 DINA1 DINA2 DINA3 DINA4 DINA5 DINA6 DINA7 DINB_PAR DINB0 DINB1 DINB2 DINB3 DINB3 T2 Y8 W8 V8 Y7 W7 V7 U7 Y12 W12 V12 U12 Y11 W11 V11 U11 U9 E3 F3 R20 R19 P20 P19 P18 P17 N20 N19 N18 V20 U20 U19 U18 T20 T20 DINB4 DINB5 DINB6 DINB7 DIND4 DOUTA_C1J1 DOUTA_PAR DOUTA_SPE DOUTA0 DOUTA1 DOUTA2 DOUTA3 DOUTA4 DOUTA5 DOUTA6 DOUTA7 DOUTB_C1J1 DOUTB_PAR DOUTB_SPE DOUTB0 DOUTB1 DOUTB2 DOUTB3 DOUTB4 DOUTB5 DOUTB6 DOUTB7 DXN DXP ECSEL ETOGGLE EXDNUP HIZ_N INT_N T19 T18 T17 R18 U16 A18 B17 C17 A17 D16 C16 B16 A16 C15 B15 A15 D20 D18 D19 C20 C19 C18 B20 B19 B18 A20 A19 B6 A5 V2 U3 W1 Y9 V10 LINE_FP LOOPBKEN LVDS_EN LVDS_RESH LVDS_RESL MRESET NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC M19 V3 C3 M3 M4 V1 A6 A9 A10 A12 A13 A14 B5 B9 B10 B12 B13 B14 C1 C2 C4 C5 C6 C7 C10 C13 C14 D1 D2 D3 D5 D7 D9 D10 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC D12 D14 E4 E17 E18 E19 E20 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H18 H19 H20 J3 J4 J17 J18 J19 J20 K17 K18 K19 K20 Note: NC refers to no connect. Do not connect pins so designated. 10 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 2. Pin Assignments for 272-Pin PBGA by Signal Name (continued) Signal Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC — Pin Signal Name Pin L3 NC W20 L4 NC Y1 L18 NC Y2 L19 NC Y6 L20 NC Y10 M20 NC Y13 N1 NC Y14 N2 NC Y15 N3 NC Y16 P1 NC Y17 P2 NC Y18 P3 NC Y19 P4 NC Y20 R1 PLL REF K1 R2 PLL_VDDA K2 R3 PLL_VSSA K3 U14 PROT_SWITCH_A A7 V6 PROT_SWITCH_C B7 V13 RD_WRN V9 V14 REF10 M1 V15 REF14 M2 V16 RESETRN T3 V17 RESETTN T4 V18 RST_N W9 V19 RX_TOH_CKEN C11 W6 RX_TOH_FP C12 W10 SCANEN B4 W13 STS_INA_N E2 W14 STS_INA_P E1 W15 STS_INB_N F2 W16 STS_INB_P F1 W17 STS_OUTA_N J2 W18 STS_OUTA_P J1 W19 STS_OUTB_N L2 — — — Signal Name Pin Signal Name Pin STS_OUTB_P SYS_CLK SYS_FP TCK TDI TDO TMS TOH_CLK TOH_INA TOH_INB TOH_OUTA TOH_OUTB TRSTN TSTCLK TSTMD TSTMODE TSTMUX0S TSTMUX1S TSTMUX2S TSTMUX3S TSTMUX4S TSTMUX5S TSTMUX6S TSTMUX7S TSTMUX8S TSTPHASE TSTSHFTLD TX_TOH_CKEN VDD VDD VDD VDD VDD VDD — L1 M17 M18 A2 A3 B1 A4 C9 A8 B8 A11 B11 B2 U1 B3 T1 Y5 W5 V5 U5 Y4 W4 V4 Y3 W3 W2 U2 C8 D6 D11 D15 F4 F17 K4 — VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS L17 R4 R17 U6 U10 U15 A1 D4 D8 D13 D17 H4 H17 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 N4 N17 U4 U8 U13 U17 Note: NC refers to no connect. Do not connect pins so designated. Agere Systems Inc. 11 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 3. Pin Descriptions Pin Symbol Type I/O N18, N19, N20, P17, P18, P19, P20, R19 R20 DINA[7:0] TTL I/ Pull-up Input parallel bus of transmitter #1. DINA_PAR TTL Parity for input bus of transmitter #1. DINB[7:0] TTL I/ Pull-up I/ Pull-up DINB_PAR TTL I/ Pull-up O/ HI-Z/ Pull-up O/ HI-Z/ Pull-up O/ HI-Z/ Pull-up O/ HI-Z/ Pull-up O/ HI-Z/ Pull-up O/ HI-Z/ Pull-up O/ HI-Z/ Pull-up O/ HI-Z/ Pull-up I/ Pull-up I/ Pull-up I/ Pull-up I/ Pull-up O/ HI-Z/ Pull-up Parity for input bus of transmitter #2. R18, T17, T18, T19, T20, U18, U19, U20 V20 12 A15, B15, C15, A16, B16, C16, D16, A17 B17 DOUTA[7:0] TTL DOUTA_PAR TTL C17 DOUTA_SPE TTL A18 DOUTA_C1J1 TTL A19, A20, B18, B19, B20, C18, C19, C20 D18 DOUTB[7:0] TTL DOUTB_PAR TTL D19 DOUTB_SPE TTL D20 DOUTB_C1J1 TTL C9 TOH_CLK TTL A8 TOH_INA TTL B8 TOH_INB TTL C8 TX_TOH_CKEN TTL A11 TOH_OUTA TTL Description Input parallel bus of transmitter #2. Output parallel bus of receiver #1. Parity for output parallel bus of receiver #1. SPE signal for output parallel bus of receiver #1. C1J1 signal for output parallel bus of receiver #1. Output parallel bus of receiver #2. Parity for output parallel bus of receiver #2. SPE signal for output parallel bus of receiver #2. C1J1 signal for output parallel bus of receiver #2. Tx and Rx TOH serial links clock (25 MHz— 77.76 MHz). TOH serial link input for transmitter #1. TOH serial link input for transmitter #2. Tx TOH serial link clock enable. TOH serial link output for receiver #1. Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 3. Pin Descriptions (continued) Pin Symbol Type I/O B11 TOH_OUTB TTL C11 RX_TOH_CKEN TTL C12 RX_TOH_FP TTL E1 E2 F1 F2 J1 J2 L1 L2 E3 F3 U11, V11, W11, Y11, U12, V12, W12, Y12 U7, V7, W7, Y7, V8, W8, Y8 V9 U9 STS_INA_P STS_INA_N STS_INB_P STS_INB_N STS_OUTA_P STS_OUTA_N STS_OUTB_P STS_OUTB_N CTAP_REFA CTAP_REFB CPU_DATA[7:0] LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS — — TTL CPU_ADDR[6:0] TTL RD_WRN CS_N TTL TTL M18 SYS_FP TTL M19 LINE_FP TTL M17 SYS_CLK TTL A7 PROT_SW_A TTL B7 PROT_SW_C TTL V10 INT_N TTL W9 RST_N TTL O/ HI-Z/ Pull-up O/ HI-Z/ Pull-up O/ HI-Z/ Pull-up I I I I O O O O — — I/ O/ Pull-up I/ Pull-up I/Pull-Up I/ Pull-up SCHMITT I/ Pull-up I/ Pull-up I/ Pull-up I/ Pull-up I/ Pull-up O/ Open Drain I/ Pull-down/ SCHMITT Agere Systems Inc. Description TOH serial link output for receiver #2. Rx TOH serial link clock enable. Rx TOH serial link frame pulse. LVDS input receiver #1. LVDS input receiver #1. LVDS input receiver #2. LVDS input receiver #2. LVDS output transmitter #1. LVDS output transmitter #1. LVDS output transmitter #2. LVDS output transmitter #2. LVDS input center tap (Rx #1) (use 0.01 µF to GND). LVDS input center tap (Rx #2) (use 0.01 µF to GND). Central processing unit (CPU) interface data bus. CPU interface address bus. CPU interface read/write. Chip select. System frame pulse for transmitter section. Line frame pulse for receiver section. System clock (77.76 MHz). Protection switching control signal. Protection switching control signal. Interrupt output. Global reset. 13 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 3. Pin Descriptions (continued) 14 Pin Symbol Type Y9 HIZ_N TTL K1 M1 PLL_REF REF10 — — M2 REF14 — M3 LVDS_RESH — M4 LVDS_RESL — A5 B6 K2 K3 A2 DXP DXN PLL_VDDA PLL_VSSA TCLK — — — — TTL A3 TDI TTL A4 TMS TTL B1 B2 TDO TRSTN TTL TTL B3 TSTMD TTL B4 SCANEN TTL C3 LVDS_EN — T1 TSTMODE — T2 BYPASS — U1 TSTCLK — V1 MRESET — T3 RESETRN — T4 RESETTN — U2 TSTSHFTLD — I/O Description I/ Global 3-state control. Pull-up/ SCHMITT — Reference for PLL (10 kΩ to GND). I 1.0 V reference for LVDS reference block. See Figure 3 on page 16. I 1.4 V reference for LVDS reference block. See Figure 3 on page 16. — Resistance high input (use 100 Ω to LVDS_RESL input). — Resistance low input (use 100 Ω to LVDS_RESH input). — Temperature-sensing diode (anode +). — Temperature-sensing diode (cathode –). — PLL analog VDD (3.3 V). — PLL analog VSS (GND). I/ JTAG clock input. Pull-up I/ JTAG data input. Pull-up I/ JTAG mode select input. Pull-up O JTAG data output. I/ JTAG reset input. Pull-up I/ Scan test mode input. Pull-up I/ Scan mode enable input. Pull-Up I/ LVDS enable used during boundary scan (B-S). Pull-up I/ Enables CDR test mode. Pull-down I/ Enables bypassing of the 622 MHz clock synthesis Pull-down with TSTCLK. I/ Test clock for emulation of 622 MHz clock during PLL Pull-down bypass. I/ Test mode reset. Pull-down I/ Resets receiver clock division counter. Pull-up I/ Resets transmitter clock division counter. Pull-up I/ Enables the test mode control register for shifting-in Pull-down selected tests by a serial port. Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 3. Pin Descriptions (continued) Pin Symbol Type I/O Description V2 ECSEL — W1 EXDNUP — Enables external test control of 622 MHz clock phase selection. Direction of phase change. U3 ETOGGLE — V3 LOOPBKEN — W2 TSTPHASE — — I/ Pull-down I/ Pull-down I/ Pull-down I/ Pull-Down I/ Pull-down O — — — — — — W3, Y3, V4, W4, TSTMUX[8:0]S Y4, U5, V5, W5, Y5 VSS A1, D4, D8, D13, D17, H4, H17, N4, N17, U4, U8, U13, U17, J9, J10, J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11, M12 D6, D11, D15, F4, VDD F17, K4, L17, R4, R17, U6, U10, U15 Agere Systems Inc. Moves 622.08 MHz clock selection on phase per positive pulse. Enables 622 Mbits/s loopback mode. Controls bypass of 16 PLL-generated phases with 16 low-speed phases. Test mode output port. 15 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) 3.3 V 3.3 V 2.32 kΩ 1% 1.91 kΩ 1% 1 kΩ 1% 1.43 kΩ 1% REF10 REF14 10 nF 10 nF Figure 3. Suggested Schematic for 1.0 V and 1.4 V Reference Voltages 16 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Synchronization The incoming data from the high-speed interface (HSI) can be separated into two STS-12 channels per slice (A and B). Example of TTSV02622 alignment. STREAM A STREAM B STREAM A STREAM B Figure 4. Alignment of Two STS-12 Streams There is also a provision to allow certain streams to be disabled (i.e., not producing interrupts or affecting synchronization). These streams can be enabled at a later time without disrupting other streams. HSI Block Interface The HSI block should provide two independent 77.76 MHz interfaces. Each interface will consist of a byte-wide data stream and its recovered clock. There is no requirement for bit alignment since SONET type framing will take place inside the TTSV02622 device. Line Interface The line side will receive/transmit frame-aligned streams of STS-12 data. All frames transmitted to the line will be aligned to the line frame pulse, which will be provided to the TTSV02622. All frames received from the line will be aligned to the system frame pulse, which will be supplied to the TTSV02622. Architecture The TTSV02622 is composed of transmit (Tx) and receive (Rx) sections. The device (see Figure 1 on page 2) receives two byte-wide data streams at 77.76 MHz (STS-12 rate) and the associated clock. The incoming streams are framed, and descrambled before they are then written into a FIFO that absorbs phase and delay variations and allows the shift to system clock. The TOH is then extracted and sent out on the two serial ports. The pointer interpreter will then put the synchronous transport signal (STS) synchronous payload envelopes (SPEs) into a small elastic store from which the pointer generator will produce two byte-wide STS-12 streams of data that are aligned to the line timing pulse. Agere Systems Inc. 17 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Architecture (continued) TOH CLK TX TOH CLK ENA TOH INPUT #1 1 TO RX TOH PROC. 1 DUAL CHANNEL TRANSMITTER LINE LBPK (SOFT CTL) 1 TX TOH PROCESSOR INPUT BUS #1 DATA(8) PARITY(1) TOH INPUT #2 1 TX TOH PROCESSOR INPUT BUS #2 DATA(8) PARITY(1) LINE FRAME PROT SWITCH A/B TX CH#1 (MACRO) 2 LVDS OUT #1 FRAME PROC. TX CH#2 (MACRO) 2 LVDS OUT #2 2 LVDS IN #1 2 LVDS IN #2 77.76 MHz 1 1 1 1 SOFT CTL SOFT CTL DATA(8)/PARITY(1) SPE(1) C1J1(1) 77.76 MHz FRAME CLOCK 622 MHz /8 FDBK PLL REF CH#1 SYSTEM FRAME SYSTEM CLOCK (77.76 MHz) FRAME PROC. 622 MHz CLKs RX CH#1 77.76 (MACROCELL) MHz OUTPUT BUS #1 CH#2 SOFT CTL DATA(8)/PARITY(1) SPE(1) C1J1(1) OUTPUT BUS #2 POINTER MOVER STS-24 77.76 MHz RX CH#2 (MACROCELL) FIFO LVDS LPBK (SOFT CTL) SOFT CTL TOH CLK SOFT CTL TOH OUTPUT #1 TOH OUTPUT #2 CH#1 1 CH#2 1 SOFT CTL RX TOH PROCESSOR DUAL CHANNEL RECEIVER SOFT CTL RX TOH CLK ENA RX TOH FRAME 1 1 CPU INTERFACE (ASYNC) LINE SIDE 1 HIZ_N 1 RST_N (HARD RST) 1 CS_N 1 RD/WR_N 7 ADDR 8 DATA 1 LVDS SIDE INT_N Figure 5. Interior View of TTSV02622 18 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Architecture (continued) The alignment FIFO allows the transfer of all data to the system clock. The FIFO sync block allows the system to be configured to allow the frame alignment of multiple slightly varying data streams (see the FIFO Sync Subblock (Backplane to Line) section on page 28). STS-12 STREAM A STS-12 STREAM B FIFO SYNC Figure 6. Interconnect of Streams for FIFO Alignment The pointer mover (see the Pointer Mover Subblock (Backplane to Line) section on page 28) is responsible for mapping incoming frames to line frames. The pointer mover is a pseudo SONET implementation which is streamlined wherever possible to minimize gate count and complexity. As a result, it is only capable of correcting single bit, nonrepeating pointer errors. This pointer mover (i.e., interpreter, elastic store, and generator) will be capable of handling intra STS-12 concatenation as well as inter STS-12 concatenation as long as the STS-12 streams are frame aligned. Powerdown Mode Powerdown mode should be entered when the corresponding channel is disabled. Channels can be independently enabled or disabled under software control. Note: The EXT PROT SW FUNC is low for STS-12 mode. When a channel is disabled, the disabled channel of the clock and data recovery module is powered down, as well as the LVDS buffers and TTL buffers for that channel. When all channels are powered down, PLL in the CDR module is also powered down. In addition, a pin has been added to enable the LVDS pins during boundary scan. This pin should be pulled high on the board for functional operation. Agere Systems Inc. 19 TTSV02622 STS-24 Backplane Transceiver Data Sheet June 2003 Supervisory Features ■ Parallel bus integrity: — Parity error checking is implemented on each of the four parallel input buses. Even and odd parity is supported as controlled from the CPU interface (per device control). Upon detection of an error, an interrupt is raised. This feature is on a per-channel basis. Note: On parallel output ports, parity is calculated over the 8-bit data bus and not on the SPE and C1J1 lines. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ TOH serial port integrity: — There is even parity generation on each of the four TOH serial output ports. There is even parity error checking on each of the four TOH serial input ports. There is one parity bit imbedded in the TOH frame. It occupies the most significant bit location of A1 byte of STS-1. Upon detection of an error, an interrupt is raised. This feature is on a per-channel basis. LVDS link integrity: — There is B1 parity generation on each of the four LVDS output channels. There is also performance monitoring on each of the four LVDS input channels, implemented as B1 parity error checking. Upon detection of an error, a counter is incremented (one count per errored bit) and an interrupt is raised. The counter is 7 bits wide plus one overflow indicator bit. This feature is on a per-channel basis. Framer monitor: — The framer in the receive direction will report loss of frame (LOF) as an interrupt, as well as a LOF count and errored frame count. The LOF interrupt must not be clearable as long as the channel is in the LOF state. In addition, the errored frame count must represent errored frames, and should not increment more than once per frame even if there are multiple errors. Receiver internal path integrity: — There is even parity generation in the receiver section (after descrambler). There is also even parity error checking in the receiver section (before output). Upon detection of an error, an interrupt is raised. This feature is on a per-channel basis. Pointer mover performance monitoring: — There is pointer mover performance monitoring in the receiver section. Alarm indication signal path (AIS-P) and concatenation is reported, as well as elastic store overflows. AIS-P is implemented as a per STS-1 interrupt. In case of concatenated payload, only the interrupt associated with the head of the group will be active. Concatenation is reported as a per STS-1 status, and is high when STS-1 is concatenated; and low when not concatenated. Elastic store overflow will generate an interrupt on a per STS-1 basis. FIFO aligner monitoring: — There is monitoring of the FIFO aligner operating point, and upon deviating from the nominal operating point of the FIFO by more than user-programmable threshold values (min and max threshold values), an interrupt is raised. Threshold values are defined per device, flags are per channel. Frame offset monitoring: — There is monitoring of the frame offset between all enabled channels (disabled channels must not interfere with the monitoring). Monitoring is performed continuously. Upon exceeding the maximum allowed frame offset (18 bytes) between all enabled channels, an interrupt is raised. CPU interface monitoring: — There is monitoring of potential write cycles that may occur when operating in write protect mode. Upon detecting a write access to the application specific integrated circuit (ASIC) when the device is in write protect mode, an interrupt is raised (W-LOCK flag). 20 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Test Features ■ ■ ■ ■ ■ ■ ■ Line loopback: — There is a line loopback feature allowing the user to perform a loopback on the line side (per device control). The line frame signal used by the pointer mover is automatically replaced by the system frame signal when operating in line loopback mode. LVDS loopback: — There is a LVDS loopback feature allowing the user to perform a loopback on the LVDS side (per device control). A1/A2 error insert: — There is a frame error inject feature, in the transmitter section, allowing the user to replace framing bytes A1/A2 (only last A1 byte and first A2 byte) with a selectable A1/A2 byte value for a selectable number of consecutive frames. The number of consecutive frames to alter is specified by a 4-bit field, while A1/A2 value is specified by two 8-bit fields. The error insert feature is on a per-channel basis, A1/A2 values and 4-bit frame count value are on a per-device basis. B1 error insert: — There is a B1 error insert feature, in the transmitter section, allowing the user to insert errors on user selectable bits in the B1 byte. Errors are created by simply inverting bit values. Bits to invert will be specified through an 8-bit register (each bit is associated with one of the eight B1 bits). To insert an error, software will first set the bits in the transmitter B1 error insert mask. Then, on a per-channel basis, software will write a one to the b1 error insert command. The insertion circuitry performs a rising edge detect on the bit, and will issue a corruption signal for the next frame, for one frame only. This feature is on a per-channel basis. TOH serial output port parity error insert: — There is a parity error inject feature, in the receive section, allowing the user to invert the parity bit of each serial output port. This feature inserts a single error. This feature is on a per-channel basis. Parallel output bus parity error insert: — There is a parity error inject feature, in the receive section, allowing the user to invert parity lines associated with each output parallel buses. This feature inserts a single error. This feature is on a per-channel basis. This feature supports both even and odd parities. Scrambler/descrambler disable: — There is a scrambler/descrambler disable feature, allowing the user to disable the scrambler of the transmitter and the descrambler of the receiver. The B1 is calculated (in transmitter and receiver) on the nonscrambled data stream. This feature is per device. Agere Systems Inc. 21 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Transmit Direction (Line to Backplane) Each TOH insert block receives two byte-wide 77.76 MHz data from the line, which nominally represents two STS-12 streams (A and B). Transport overhead bytes are then optionally inserted into these streams and the streams are forwarded to the HSI. All byte timing pulses required to isolate individual overhead bytes (e.g., A1, A2, B1, D1—D12, etc.) are generated internally based on a Frame_Sync received from the system (SYS_FP). ■ A1 and A2 insertion and optional corruption. ■ H1, H2, and H3 pass through transparently. ■ B1 calculation (after scrambling), insertion and optional corruption (before scrambling). ■ Optional K1 and K2 insert. ■ Optional S1/M0 insert. ■ Optional E1/F1/E2 insert. ■ Optional section and line data communication channel (DCC, D1—D12) insertion (for intercard communications channel). ■ Scrambling of outgoing data stream with optional scrambler disabling. ■ Optional stream disabling. All streams operate byte wide at 77.76 MHz (622 Mbits/s) in all modes. EVEN/ODD PARITY (SOFT CTL) TOH TOH CLOCK SERIAL (COMMON TO DATA IN THE 2 CH) TOH CLOCK ENA (COMMON TO THE 2 CH) PAR ERR FLAG (SOFT REG) B1 ERROR B1 ERROR MASK INSERT CMD (SOFT REG) (SOFT CTL) PAR ERR FLAG (SOFT REG) TOH SER TO PAR CONVERTER + BUFFER LINE LPBK (SOFT CTL) INPUT BUS DATA(8) PARITY(1) TOH LPBK MUX SPE + TOH 77.76 MHz (TO ALL BLOCKS) SYSTEM FRAME TO RX SYSTEM CLOCK LINE LPBK (FROM RX) B1 BYTE PARITY GENERATOR B1 BUS PAR CHECK TX SYNC (COMMON TO THE 2 TX CHANNELS) TOH MODE TOH BYTES (INS/PASS) INS/PASS (SOFT CTL) SEL (SOFT CTL) TOH MUX A1/A2 A1/A2 MUX B1 MUX SONET SCRAMBLER PARALLEL TO SERIAL (MEGACELL FROM ASIC VENDOR) LVDS OUT#1 A1/A2 MUX CTL A1/A2 ERROR A1/A2 ERROR INSERT INSERTVALUE COUNT (SOFT REG) (SOFT REG) A1/A2 ERROR INSERTCMD (SOFT CTL) SCRAMBLER 77.76 MHz 622 MHz LVDS LPBK DISABLE (FROM PLL) (FROM PLL) (TO RX) (SOFT CTL) Figure 7. Transmitter Block 22 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Transmit Direction (Line to Backplane) (continued) Transport Overhead Serial Link The TOH serial links are used to insert TOH bytes into the transmit data. TOH_IN and TOH_CLK_EN get retimed by TOH_CLK in order to meet setup and hold specifications of the device. Insertion or passthrough of the TOH is under software control. TOH parity is calculated using the initial retimed data (TOH_IN_D). A1/A2 Frame Insert and Corruption When not corrupted, for each stream, all twelve A1 bytes of the STS-12 are set to 0xF6 and all twelve A2 bytes of the STS-12 are set to 0×28. Corruption is controlled per stream by the A1/A2 error insert register. When A1/A2 corruption is set for a particular stream, the A1/A2 value in the corrupted A1/A2 value registers are sent for the number of frames defined in the corrupted A1/A2 frame count register (see Table 6 on page 33 and Table 7 on page 36 for register details). Note: When the corrupted A1/A2 frame count register is set to zero, A1A2 corruption will continue until the A1/A2 error insert register is cleared, i.e., indefinitely. On a per-device basis, the A1 and A2 byte values are set, as well as the number of frames of corruption. Then, to insert the specified A1/A2 values, each channel has an enable register. When the enable register is set, the A1/A2 values are corrupted for the number specified in the number of frames to corrupt. To insert errors again, the perchannel fault insert register must be cleared, and set again. Only the last A1 and the first A2 are corrupted. B1 Calculation and Insertion The B1 calculation block computes a BIP-8 code, using even parity over all bits of the previous STS-n frame after scrambling and is inserted in the B1 byte of the current STS-n frame before scrambling. Per-bit B1 corruption is controlled by the force BIP-8 corruption register (per device register). For any bit set in this register, the corresponding bit in the calculated BIP-8 is inverted before insertion into the B1 byte position. Each stream has an independent fault insert register that enables the inversion of the B1 bytes. B1 bytes in all other STS-1s in the stream are passed through transparently. Stream Disable When disabled via the appropriate bit in the stream enable register, the prescrambled data for a stream is set to all ones, feeding the HSI. The HSI macro is powered down on a per-stream basis, as is the LVDS outputs. Scrambler The data stream is scrambled using a frame synchronous scrambler of sequence length 127, operating at the line rate. The scrambling function can be disabled by software. The generating polynomial for the scrambler is 1 + x6 + x7. The scrambler is reset to 111_1111 on the first byte of the SPE (byte following the Z0 byte in the twelfth STS-1). That byte and all subsequent bytes to be scrambled are exclusive ORed, with the output from the byte-wise scrambler. The scrambler runs continuously from that byte on throughout the remainder of the frame. A1, A2, J0, and Z0 bytes are not scrambled. Agere Systems Inc. 23 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Receiver Block EVEN/ODD PARITY (SOFT CTL) PROT SWITCH CH#1—2 PAR ERR PERF ENA MUX INSERT MONITORS (SOFT CTL) (SOFT CTL) (SOFT CTL) (SOFT REG) PROT SWITCH LINE PAR ERR PAR ERR FUNCTION HI-Z LPBK FLAG INSERT (SOFT CTL) (SOFT CTL) (TO TX) (SOFT REG) (SOFT CTL) LOF FLAG, TOH CLOCK TOH FRAME LOF COUNT, (COMMON TO (COMMON TO A1/A2 ERR COUNT LVDS LPBK THE 2 CH) THE 2 CH) (SOF REG) (SOFT CTL) TOH SERIAL TOH CLOCK B1 PAR ERR DATA OUT ENABLE COUNT, B1 16—622 MHz (COMMON TO PAR ERR FLAG CLOCKS LVDS LPBK THE 2 CH) (SOFT REG) (FROM PLL) (FROM TX) HI-Z (SOFT CTL) CH#1—2 MUX HI-Z 1 0 (SOFT CTL) (SOFT CTL) CH#2 OUT DATA TOH TOH PORT PAR TO SER CONTROL CONVERTER (COMMON TO B1 CTLS + BUFFER THE 2 CH) PROT SWITCH CTL PROT SWITCH FP BUS PARTIY GEN /CHECK CH#1 OUT BUS LINE FRAME CH#2 OUT DATA LOF AIS INS STS-12 POINTER MOVER PAR GEN FIFO ALIGNER RD WR FP FP SONET DESCRAMBLER FP SONET FRAME RECOVERY SYSTEM FRAME (FROM TX) FP SYSTEM CLOCK (77.76 MHz) SERIAL TO PARALLEL (MEGACELL FROM ASIC VENDOR) LPBK MUX RX CLK 77.76 MHz FIFO READ/WRITE CONTROL CTLS DATA(8) PARITY(1) SPE(1) C1J1(1) FP DATA PARTIY SPE C1J1 B1 PARITY ERROR COUNT LVDS #1 FP = FRAME PULSE FIFO SYNC (COMMON TO THE 2 CHANNELS) CTLS (TO/FROM OTHER CH) LINE LPBK (SOFT CTL) K1/K2 PASS /REGEN (SOFT CTL) FORCE AIS-L (SOFT CTL) FIFO RE-ALIGN (SOFT CTL) AIS-L CTLS ON LOF (TO OTHER (SOFT CTL) CH) CTLS (TO OTHER CH) FRAME OFFSET ALARM FLAG (SOFT REG) FIFO THRESHOLD ALARM FLAG (SOFT REG) FIFO MIN/MAX THRESHOLDS (SOFT REG) DESCRAMBLER DISABLE (SOFT CTL) Figure 8. Receiver Block Framer Subblock (Backplane to Line) The framer block takes byte-wide data from the HSI, and outputs a byte-aligned byte-wide stream and 8 kHz sync pulse (asserted one clock before the first A1 byte). The framer algorithm determines the out-of-frame/in-frame status of the incoming data and will cause interrupts on both an errored frame and an OOF state. Features ■ A1—A2 framing pattern detection. ■ Framing similar to SONET specification. ■ Generates timing and an 8 kHz frame pulse. ■ Detects OOF and generates an interrupt. ■ Detects errored frame and increments counter. 24 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Receiver Block (continued) Framer Subblock (Backplane to Line) (continued) Framer State Machine Figure 9 shows the state machine that controls the framer. Since the TTSV02622 is intended for use between ASICs via a backplane, there is only one errored frame state; thus, after two transitions are missed, the state machine goes into the OOF state and there is no SEF or LOF indication. OOF State. In this state, the A1 pattern is searched for on every clock cycle. A second stage of comparison is implemented to locate the A1/A2 transition. When the A1/A2 transition is found, the following occurs: ■ The state machine moves from the OOF state to the frame confirm state. ■ The A1offset for the byte start location is locked. ■ The row, column, and STS counters are set. Frame Confirm. In this state, the A1/A2 transition is only compared for at the appropriate location, i.e., beginning at the twelfth A1 location. This location is determined from the row, column, and STS counters which were set at the transition from OOF to frame confirm. If at this time the comparison fails, the state machine reverts to the OOF state. If the comparison passes, the next state will be In frame. In Frame. This state is similar to the frame confirm state except that if the comparison at the A1/A2 time is incorrect, the next state will be the errored frame state. If the comparison is correct, the next state will be in frame. Errored Frame. Once the errored frame state has been reached, if the next comparison is incorrect, the next state will be OOF. Otherwise, if correct, the next state will be in frame. This state will generate an error interrupt to the micro. Agere Systems Inc. 25 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Receiver Block (continued) Framer Subblock (Backplane to Line) (continued) EXPECT A1/A2 & FIND A1/A2 EXPECT A1/A2 & FIND A1/A2 EXPECT A1/A2 & !FIND A1/A2 IN FRAME EXPECT A1/A2 & FIND A1/A2 ERRORED FRAME FRAME CONFIRM EXPECT A1/A2 & !FIND A1/A2 - FIND A1/A2 TRANSITION - LOCK BARREL SHIFTER - SET ROW/COL/STS COUNTERS OOF EXPECT A1/A2 & !FIND A1/A2 RESET Notes: Row, column, and STS counters are only set/reset by state transition from OOF to frame confirm. Expect A1/A2 means that row/col/STS counter values indicate time for last (twelfth) A1 byte. Figure 9. Framer State Machine 26 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Receiver Block (continued) B1 Calculate and Descramble (Backplane to Line) Each Rx block receives byte-wide scrambled 77.76 MHz data and a frame sync from the framer. Since each HSI is independently clocked, the Rx block operates on individual streams. Timing signals required to locate overhead bytes to be extracted are generated internally based on the frame sync. The frame sync occurs one clock pulse before the first A1 byte of the stream. The Rx block produces byte-wide descrambled data and an output frame sync for the alignment FIFO block. The output frame sync occurs two clocks before the first A1 byte of the descrambled data stream to allow for metastable hardening by the write control subblock. On the received data, the following functionality is needed: ■ Descrambling of received data stream with optional descrambling disable. ■ B1 verification. Descrambling The streams are scrambled using a frame synchronous scrambler of sequence length 127, operating at the line rate. The descrambling function can be disabled by software. The generating polynomial for the scramble is 1 + x6 + x7. The scrambler is reset to 1111111 on the first byte of the SPE (byte following the Z0 byte in the twelfth STS-1). That byte and all subsequent bytes to be scrambled are exclusive ORed, with the output from the byte-wise scrambler. The scrambler runs continuously from that byte on throughout the remainder of the frame. A1, A2, J0, and Z0 bytes are not scrambled. B1 Verification The B1 calculation block computes a BIP-8 code, using even parity over all bits of the previous STS-12 frame before descrambling, and this value is checked against the B1 byte of the current frame after descrambling. A perstream B1 error counter is incremented for each bit that is in error. Alarm Indication Signal Line (AIS-L) Insertion If enabled via AIS_L_INSERT[x] bit in the AIS_L force register, AIS-L is inserted into the received frame by writing all ones for all bytes of the descrambled stream. AIS-L Insertion on Out of Frame If enabled via the appropriate bit in the AIS_L force on out of frame register, AIS-L is inserted into the received frame by writing all ones for all bytes of the descrambled stream when the framer indicates that an out of frame condition exists. Internal Parity Generation An even parity is generated on all data bytes and is routed in parallel with the data to be checked before the protection switch MUX at the parallel output. Agere Systems Inc. 27 TTSV02622 STS-24 Backplane Transceiver Data Sheet June 2003 Receiver Block (continued) FIFO Subblock (Backplane to Line) The FIFO subblock consists of a 24 by 10-bit FIFO per STS-12. This FIFO will be used to align up to ±154.3 ns of interlink skew and to transfer to the system clock. FIFO Sync Subblock (Backplane to Line) This FIFO sync block takes metastable hardened frame pulses from the write control blocks and produces sync signals that indicate when the read control blocks should begin reading from the first FIFO location. On top of the sync signals, this block produces an error indicator which indicates that the signals to be aligned are too far apart for alignment (i.e., greater than 18 clocks apart). Sync and error signals are sent to read control block for alignment. The read control block is synchronized only once on start-up, and any further synchronizing is software (S/W) controlled. The action of resynchronizing a read control block will always cause a data hit. A software register allows the read control block to be resynchronized. Recommended Procedure for Synchronization of Selected Streams ■ Force AIS-L in all streams to be synchronized. ■ Wait four frames. ■ Write a 1 to the FIFO alignment resynchronizing register, bit DB1 of register 0x06. ■ Wait four frames. ■ Release the AIS-L in all streams. Pointer Mover Subblock (Backplane to Line) The pointer mover simply maps incoming frames to the line framing. The K1/K2 bytes and H1—SS bits are also passed through to the pointer generator so that the line can receive them. The mover will handle both concatenations inside the STS-12, and to other STS-12s inside the TTSV02622. Pointer Interpreter State Machine The pointer interpreter is minimized as much as possible to keep the gate count low. In keeping with that goal, the pointer interpreter has only three states (NORM, AIS, and CONC). The interpreter’s highest priority is to maintain accurate dataflow (i.e., valid SPE only). This will ensure that any errors in the pointer value will be corrected by a standard pointer interpreter without any data hits. This means that error checking for increment, decrement, and NDF (i.e., 8 of 10) are maintained in order to ensure accurate dataflow. A single valid pointer (i.e., 0—782) that differs from the current pointer will be ignored. Two consecutive incoming valid pointers that differ from the current pointer will cause a reset of the J1 location to the latest pointer value (the generator will then produce an NDF). This block is designed to handle single bit errors without affecting dataflow or changing state, but it is not compliant with SONET standards. 28 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Receiver Block (continued) Pointer Mover Subblock (Backplane to Line) (continued) Rules for Concatenation. The pointer mover block can correctly process any length of concatenation (multiple of three) as long as it begins on an STS-3 boundary (i.e., STS-1 number 1, 4, 7, 10, etc.) and is contained within the smaller of STS-3, 12 or 24 (see Table 4). Table 4. Valid Starting Positions for a STS-MC STS-1 Number STS-3c SPE STS-6c SPE STS-9c SPE STS-12c SPE STS-15c SPE STS-18c to STS-24c SPEs 1 4 7 10 13 16 19 22 Y Y Y Y Y Y Y Y Y Y Y NO Y Y Y NO Y Y NO NO Y Y NO NO Y NO NO NO Y NO NO NO Y Y Y Y Y Y Y Y Y — — — — — — — Notes: Y = STS-Mc SPE can start in that STS-1. NO = STS-Mc SPE cannot start in that STS-1. — = Y or NO, depending on the particular value of M. Rules for Pointer Interpretation. ■ NDF ≤ N bits in H1 byte = (1001 + single bit error). ■ NRMNBTS (i.e., NDF not set) ≤ N bits in H1 byte = (0110 + single bit error). ■ CONC pointer ≤ (N bits in H1 byte = 1001 + single bit error) and offset = 11_1111_1111. ■ AIS pointer ≤ offset and N bits are all 1s (SS bits are ignored). ■ NORM pointer ≤ (offset 0—782) and (NDF or NRMNBITS). Agere Systems Inc. 29 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Receiver Block (continued) Pointer Mover Subblock (Backplane to Line) (continued) NORM State. This state will begin whenever two consecutive NORM pointers are received. If two consecutive NORM pointers are received, such that both differ from the current offset, then the current offset will be reset to the last received NORM pointer. When the pointer interpreter changes its offset, it causes the pointer generator to receive a J1 value in a new position. When the pointer generator gets an unexpected J1, it resets its offset value to the new location and declares an NDF. Note: The interpreter is only looking for two consecutive pointers that are different from the current value. These two consecutive NORM pointers do not have to have the same value. For example; if the current pointer is 10 and you receive a NORM pointer with offset of 15 and a second NORM pointer with offset of 25, then the interpreter will change the current pointer to be 25. CONC State. The receipt of two consecutive CONC pointers causes this state to be entered. Once in this state, offset values from the head of the concatenation chain are used to determine the location of the STS SPE for each STS in the chain. AIS State. Two consecutive AIS pointers cause this state to occur. Any two consecutive normal or concatenation pointers will end this state. This state will cause the data leaving the pointer generator to be overwritten with 0xFF. NORM M OR 2 IS xN M xC OR xA 2 xN ON C 2 2 CONC 2 x CONC AIS 2 x AIS Figure 10. Pointer Mover State Machine Pointer Generator The pointer generator simply maps the corresponding bytes into their appropriate location in the outgoing byte stream. The generator also creates offset pointers based on the location of the J1 byte as indicated by the pointer interpreter. The generator will signal NDFs when the interpreter signals that it is coming out of AIS state. The generator resets the pointer value and generates NDF every time a byte marked J1 is read from the elastic store that doesn’t match the previous offset. Increments and decrements signals from the pointer interpreter are latched once per frame on either the F1 or E2 byte times (depending on collisions), this ensures constant values during the H1 through H3 times. The choice of which byte time to do the latching on is made when the relative frame phases (i.e., received and system) is determined. This latch point will then be stable, unless the relative framing changes and the received H byte times collide with the system F1 or E2 times, in which case the latch point would be switched to the collision-free byte time. 30 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Receiver Block (continued) Pointer Mover Subblock (Backplane to Line) (continued) There is no restriction on how many or how often increments and decrements are processed. Any received increment or decrement is immediately passed to the generator for implementation regardless of when the last pointer adjustment was made. The responsibility for meeting the SONET criteria for max frequency of pointer adjustments is then left to the upstream pointer processor. When the interpreter signals an AIS state, the generator will immediately begin sending out 0xFF in place of data and H1, H2, H3. This will continue until the interpreter returns to NORM or CONC states and a J1 byte is received. Miscellaneous Functions K1/K2, A1/A2 Handling K1/K2 bytes can be optionally passed through the pointer mover under software control, or it can be set to zero with the other TOH bytes. A1/A2 bytes are regenerated and set to F6 and 28, respectively. SPE C1J1 Outputs In an attempt to minimize the complexity required from the pointer processor that may be hooked-up to the TTSV02622 parallel output port, two signals (per channel) must be provided to the external world; these are called SPE and C1J1. These two signals will allow a pointer processor to extract payload without interpreting the pointers. Table 5. SPE and C1J1 Functionality SPE C1J1 Description 0 0 1 1 0 1 0 1 TOH information excluding C1(J0) of STS-1 #1. Position of C1(J0) of STS-1 #1. SPE information excluding the 12 J1 bytes. Position of the twelve J1 bytes. The following rules must be observed for generating SPE and C1J1 signals: ■ ■ ■ ■ ■ On occurrence of AIS-P on any of the STS-1, there must be no corresponding J1 pulse. In case of concatenated payloads (up to STS-24c), only the head STS-1 of the group must have an associated J1 pulse. C1J1 signal must track any pointer movements. During a negative justification event, SPE must be set high during the H3 byte to indicate that payload data is available. During a positive justification event, SPE must be set low during the positive stuff opportunity byte to indicate that payload data is not available. Agere Systems Inc. 31 TTSV02622 STS-24 Backplane Transceiver Data Sheet June 2003 Registers Definition of Register Types The TTSV02622 design contains six structural register elements: SREG, CREG, PREG, IAREG, ISREG, and IEREG. There are no mixed registers in TTSV02622. This means that all bits of a particular register (particular address) are structurally the same and are as follows: ■ ■ ■ ■ ■ ■ Status register (SREG): — A status register is read only, and as the name implies is used to convey the status information of a particular element or function of the TTSV02622 chip. The reset value of an SREG is really the reset value of the particular element or function that is being read. In some cases, an SREG is really a fixed value; an example of which is the fixed id and revision registers. Control register (CREG): — A control register is read and writable memory element inside CORE_CONTROL. The value of a CREG will always be the value written to it. Events inside the TTSV02622 chip cannot affect a CREG value. The only exception is a soft reset, in which case the CREG will return to its reset value. The control register have reset values as defined in the reset value column of Table 6 on page 33. Pulse register (PREG): — Each element, or bit, of a pulse register is a control or event signal that is asserted and then deasserted when a value of 1 is written to it. This means that each bit is always of value 0 until it is written to, upon which it is pulsed to the value of 1 and then returned to a value of 0. A pulse register will always have a read value of 0. Interrupt alarm register (IAREG): — Each bit of an interrupt alarm register is a event latch. When a particular event is produced in the TTSV02622 chip, its occurrence is latched by its associated IAREG bit. To clear a particular IAREG bit, a value of 1 must be written to it. In the TTSV02622 chip, all IAREG reset values are 0. Interrupt status register (ISREG): — Each bit of an interrupt status register is physically the logical OR function. It is a consolidation of lower-level interrupt alarms and/or ISREG bits from other registers. A direct result of the fact that each bit of the ISREG is a logical OR function means that it will have a read value of 1 if any of the consolidation signals are of value 1, and will be of value 0 if and only if all consolidation signals are of value 0. In the TTSV02622 chip, all ISREG reset values are 0. Interrupt enable register (IEREG): — Each bit of a status register or alarm register has an associated enable bit. If this bit is set to value 1, then the event is allowed to propagate to the next higher level of consolidation. If this bit is set to zero, then the associated IAREG or ISREG bit can still be asserted but an alarm will not propagate to the next higher level. Obviously, an interrupt enable bit is an interrupt mask bit when it is set to value 0. 32 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Registers (continued) Register Map Table 6. Register Map ADDR* Reg. DB7 [6:0] Type DB6 DB5 DB4 DB3 DB2 DB1 DB0 Reset Comments Value (hex) 00 SREG FIXED ID MSB A0 01 SREG FIXED ID LSB 01 02 SREG FIXED REV 01 03 CREG SCRATCH PAD 00 04 CREG LOCKREG MSB 00 05 CREG LOCKREG LSB 00 06 PREG —† —† —† —† 08 CREG —† —† —† Rx TOH FRAME AND Rx TOH CLOCK ENABLE HI-Z CONTROL 09 CREG —† —† —† —† 0A CREG —† —† —† FIFO ALIGNER THRESHOLD VALUE (min) 02 0B CREG —† —† —† FIFO ALIGNER THRESHOLD VALUE (max) 15 0C CREG —† SCRAMBLER/ DESCREAMBLER CONTROL I/O PARALLEL BUS PARITY CONTROL 0D CREG A1 ERROR INSERT VALUE 0E CREG A2 ERROR INSERT VALUE 00 0F CREG TRANSMITTER B1 ERROR INSERT MASK 00 10 ISREG —† —† —† 11 IEREG —† —† —† 12 IAREG —† —† —† —† —† —† 13 IEREG —† —† —† —† —† —† —† —† FIFO ALIGNMENT COMMAND GLOBAL RESET COMMAND NA EXT PROT SW EN EXT PROT SW FUNC STS-12 SELECT LVDS LPBK CONTROL 00 —† PARALLEL PORT OUTPUT MUX SELECT FOR CH1 —† SERIAL PORT OUTPUT MUX SELECT FOR CH1 0F Generic register block. Device Register Block LINE LPBK CONTROL PER DEVICE INT NUMBER OF CONSECUTIVE A1/A2 ERRORS TO GENERATE [3:0] —† 60 Device register block (Rx). Device register block (Tx). 00 —† CH 2 INT CH 1 INT ENABLE/MASK REGISTER [4:0] WRITE TO LOCKED REGISTER ERROR FLAG 00 Top-level interrupts. 00 FRAME OFFSET ERROR FLAG ENABLE/MASK REGISTER 00 00 * ADDR values delimited by a comma indicate the address for each of two channels, from channel 1 or 2. For example, the register for Tx control signals has addresses of 20 and 38. This indicates that channel 1 Tx control signals are at address 20 and channel 2 Tx control signals are at address 38. † Reserved. Agere Systems Inc. 33 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Registers (continued) Register Map (continued) Table 6. Register Map (continued) ADDR* Reg. [6:0] Type DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Reset Comments Value (Hex) Channel Register Block 20, 38 CREG HI-Z CONTROL OF TOH DATA OUTPUT HI-Z CONTROL OF PARALLEL OUTPUT BUS CHANNEL ENABLE / DISABLE CONTROL PARALLEL OUTPUT BUS PARITY ERR INS CMD Rx K1/K2 SOURCE SELECT TOH SERIAL OUTPUT PORT PAR ERR INS CMD FORCE AIS-L CONTROL Rx BEHAVIOR IN LOF 01 Rx control signals. 21, 39 CREG Tx MODE OF OPERATION Tx E1/F1/E2 SOURCE SELECT Tx S1/M0 SOURCE SELECT Tx K1/K2 SOURCE SELECT Tx D12 SOURCE SELECT Tx D11 SOURCE SELECT Tx D10 SOURCE SELECT Tx D9 SOURCE SELECT 00 Tx control signals. 22, 3A CREG Tx D8 SOURCE SELECT Tx D7 SOURCE SELECT Tx D6 SOURCE SELECT Tx D5 SOURCE SELECT Tx D4 SOURCE SELECT Tx D3 SOURCE SELECT Tx D2 SOURCE SELECT Tx D1 SOURCE SELECT 00 23, 3B CREG —† —† —† —† —† —† B1 ERROR INSERT COMMAND A1/A2 ERROR INSERT COMMAND 00 24, 3C SREG —† —† —† —† CONCAT CONCAT CONCAT INDICATION INDICATION INDICATION 12 9 6 CONCAT INDICATION 3 NA 25, 3D SREG CONCAT INDICATION 11 CONCAT CONCAT CONCAT CONCAT CONCAT CONCAT INDICATION INDICATION INDICATION INDICATION INDICATION INDICATION 8 5 2 10 7 4 CONCAT INDICATION 1 NA 26, 3E ISREG —† PER STS-12 ALARM FLAG 00 —† —† —† —† ELASTIC STORE AIS-P FLAG OVERFLOW FLAG 27, 3F IEREG —† —† —† —† —† 28, 40 IAREG —† —† TOH SERIAL INPUT PORT PARITY ERROR FLAG INPUT PARALLEL BUS PARITY ERROR FLAG LVDS LINK B1 PARITY ERROR FLAG 29, 41 IEREG —† —† ENABLE/MASK REGISTER [2:0] LOF FLAG RECEIVER INTERNAL PATH PARITY ERROR FLAG ENABLE/MASK REGISTER [5:0] Per STS-1 change of state flag. Per-channel interrupt consolidation. 00 FIFO ALIGNER THRESHOLD ERROR FLAG 00 Per STS-12 interrupt flags. 00 * ADDR values delimited by a comma indicate the address for each of two channels, from channel 1 or 2. For example, the register for Tx control signals has addresses of 20 and 38. This indicates that channel 1 Tx control signals are at address 20 and channel 2 Tx control signals are at address 38. † Reserved. 34 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Registers (continued) Register Map (continued) Table 6. Register Map (continued) ADDR* [6:0] Reg. Type DB7 DB6 DB5 2A, 42 IAREG —† —† —† 2B, 43 IAREG 2C, 44 IEREG 2D, 45 IEREG 2E, 46 IAREG 2F, 47 IAREG 30, 48 IEREG 31, 49 IEREG DB4 DB3 DB2 DB1 DB0 Reset Comments Value (hex) Channel Register Block (continued) —† AIS AIS AIS AIS INTERRUPT INTERRUPT INTERRUPT INTERRUPT FLAGS FLAG FLAGS FLAGS 12 9 6 3 00 AIS AIS AIS AIS AIS AIS AIS AIS INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT FLAG FLAG FLAG FLAG FLAG FLAG FLAG FLAG 11 8 5 2 10 7 4 1 00 —† —† —† —† ENABLE/ ENABLE/ ENABLE/ ENABLE/ MASK AIS MASK AIS MASK AIS MASK AIS INTERRUPT INTERRUPT INTERRUPT INTERRUPT FLAGS FLAG FLAGS FLAGS 12 9 6 3 00 ENABLE/ ENABLE/ ENABLE/ ENABLE/ ENABLE/ ENABLE/ ENABLE/ ENABLE/ MASK AIS MASK AIS MASK AIS MASK AIS MASK AIS MASK AIS MASK AIS MASK AIS INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT INTERRUPT FLAG FLAG FLAG FLAG FLAG FLAG FLAG FLAG 11 8 5 2 10 7 4 1 00 —† —† —† —† ES ES ES ES OVERFLOW OVERFLOW OVERFLOW OVERFLOW FLAGS FLAG FLAGS FLAGS 12 9 6 3 00 ES ES ES ES ES ES ES ES OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW FLAG FLAG FLAG FLAG FLAG FLAG FLAG FLAG 11 8 5 2 10 7 4 1 00 —† —† —† —† ENABLE/ ENABLE/ ENABLE/ ENABLE/ MASK ES MASK ES MASK ES MASK ES OVERFLOW OVERFLOW OVERFLOW OVERFLOW FLAGS FLAG FLAGS FLAGS 12 9 6 3 00 ENABLE/ ENABLE/ ENABLE/ ENABLE/ ENABLE/ ENABLE/ ENABLE/ ENABLE/ MASK ES MASK ES MASK ES MASK ES MASK ES MASK ES MASK ES MASK ES OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW FLAG FLAG FLAG FLAG FLAG FLAG FLAG FLAG 11 8 5 2 10 7 4 1 00 32, 4A COUNTER OVERFLOW LVDS LINK B1 PARITY ERROR COUNTER 00 33, 4B COUNTER OVERFLOW LOF COUNTER 00 34, 4C COUNTER OVERFLOW A1/A2 FRAME ERROR COUNTER 00 Per STS-1 interrupt flags. Binning. * ADDR values delimited by a comma indicate the address for each of two channels, from channel 1 or 2. For example, the register for Tx control signals has addresses of 20 and 38. This indicates that channel 1 Tx control signals are at address 20 and channel 2 Tx control signals are at address 38. † Reserved. Agere Systems Inc. 35 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Register Descriptions Table 7. Register Description Address Bit (hex) Type Description Reset Value (hex) NA. NA. NA. The scratch pad has no function and is not used anywhere in the TTSV02622 chip. However, this register can be written to and read from. In order to write to registers in memory locations 06—7F, LOCKREG MSB and LOCKREG LSB must be respectively set to the values of A0 and 01. If the LOCKREG MSB and LOCKREG LSB values are not set to A0 and 01 respectively, then any values written to the registers in memory locations 06—7F will be ignored. After reset (both hard and soft), the TTSV02622 chip is in a write locked mode. The TTSV02622 chip needs to be unlocked before it can be written to. Also note that the scratch pad register (03) can always be written to since it is unaffected by write lock mode. See address 0x04 bits [7:0] description. The FIFO ALIGNMENT and GLOBAL RESET COMMANDS are both accessed via the pulse register in memory address 06. The FIFO ALIGNMENT command is used to frame align the outputs of the four receive STM stream FIFOs. The GLOBAL RESET COMMAND is a soft (software initiated) reset. Nevertheless, the GLOBAL RESET COMMAND will have the exact reset effect as a hard (RST_N pin) reset. See address 0x06 bit 0 description. A0 01 01 00 00 01 02 03 [7:0] [7:0] [7:0] [7:0] FIXED ID MSB FIXED ID LSB FIXED REV SCRATCH PAD SREG SREG SREG CREG 04 [7:0] LOCKREG MSB CREG 05 06 [7:0] 0 LOCKREG LSB GLOBAL RESET COMMAND CREG PREG 1 FIFO ALIGNMENT COMMAND PREG [7:2] 36 Name 00 00 NA Reserved. Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit (hex) 08 Name Type Description Device Register Blocks CREG 0 = No loopback. 1 = LVDS loopback, transmit to receive on. 1 CREG This control signal is untracked in the TTSV02622 chip. It is a scratch bit, and its value has no effect on the TTSV02622 chip. EXT Switching Control Master [3:2] EXT PROT SW EN CREG EXT PORT SW EN PROT SW (bit 3) FUNC EXT PROT SW FUNC 0 — ■ MUX is controlled by software (bit 2) (1 control bit per MUX). ■ Output buffers are controlled by software (1 control bit per channel). 1 0 ■ MUX on parallel output bus of CH 1 is controlled by PROT_SWITCH_A/B pin. 0 = CH 1. 1 = CH 2. ■ Output buffers are controlled by software (1 control bit per channel). 1 1 ■ MUX is controlled by software (1 control bit per MUX). ■ Output buffers on parallel output bus of CH 1 and CH 2 are controlled by PROT_SWITCH_A/B pin. 0 = Buffers active. 1 = HI-Z. CREG 0 = High impedance. 4 Rx TOH FRAME 1 = Enable receive TOH CLK and FP outputs. AND Rx TOH CLOCK ENABLE HI-Z CONTROL [7:5] Reserved. 0 Agere Systems Inc. LVDS LPBK CONTROL STS-12 SELECT Reset Value (hex) 00 00 00 00 37 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit (hex) 09 0 1 2 0A 3 [7:4] [4:0] Name SERIAL PORT OUTPUT MUX SELECT FOR CH 1 PARALLEL PORT OUTPUT MUX SELECT FOR CH 1 Type Description Reset Value (hex) Device Register Blocks (continued) CREG 0 = TOH output 1 is multiplexed to CH 2. 1 = TOH output 1 is multiplexed to CH 1. 0F Reserved. CREG 0 = Parallel output data bus 1 is multiplexed to CH 2. 1 = Parallel output data bus 1 is multiplexed to CH 1. Reserved. Reserved. FIFO ALIGNER CREG This is the minimum threshold value for the per-channel THRESHOLD VALUE receive direction alignment FIFOS. If and when the mini(min) mum threshold value is violated by a particular channel, then the interrupt event FIFO ALIGNER THRESHOLD ERROR will be generated for that channel and latched as a FIFO ALIGNER THRESHOLD ERROR FLAG in the respective per STS-12 interrupt alarm register. 0F 02 The allowable range for minimum threshold values is 1 to 23. 0B Note: The minimum FIFO aligner threshold values apply to both channels. [7:5] Reserved. [4:0] FIFO ALIGNER CREG This is the maximum threshold value for the per-channel receive direction alignment FIFOS. If and when the maxiTHRESHOLD VALUE mum threshold value is violated by a particular channel, (max) then the interrupt event FIFO ALIGNER THRESHOLD ERROR will be generated for that channel and latched as a FIFO ALIGNER THRESHOLD ERROR FLAG in the respective per STS-12 interrupt alarm register. 15 The allowable range for maximum threshold values is 0 to 22. [7:5] 38 Note: The minimum FIFO aligner threshold values apply to both channels. Reserved. Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit (hex) 0C [3:0] 4 5 6 0D 7 [7:0] 0E [7:0] 0F [7:0] Name NUMBER OF CONSECUTIVE A1/A2 ERRORS TO GENERATE [3:0] LINE LPBK CONTROL INPUT/OUTPUT PARALLEL BUS PARITY CONTROL SCRAMBLER/ DESCREAMBLER CONTROL A1 ERROR INSERT VALUE A2 ERROR INSERT VALUE TRANSMIT B1 ERROR INSERT MASK Agere Systems Inc. Type Description Device Register Blocks (continued) CREG These three (0C, 0D, and 0E) per-device control signals are used in conjunction with the per channel A1/A2 ERROR INSERT COMMAND control bits to force A1/A2 errors in the transmit direction. Reset Value (hex) 60 If a particular channel’s A1/A2 ERROR INSERT COMMAND control bit is set to the value 1, then the A1 and A2 error insert values will be inserted into that channels respective A1 and A2 bytes. The number of consecutive frames to be corrupted is determined by the NUMBER OF CONSECUTIVE A1 A2 ERRORS TO GENERATE [3:0] control bits. The error insertion is based on a rising edge detector. As such, the control must be set to value 0 before trying to initiate a second A1 A2 corruption. CREG 0 = No loopback. 1 = Rx to Tx loopback on line side. CREG 0 = Odd parity. 1 = Even parity. 0 1 1 CREG 0 = No Rx direction descramble/Tx direction scramble. 1 = In Rx direction, descramble channel after SONET frame recovery. In Tx direction, scramble data just before parallel-to-serial conversion. Reserved. CREG See address 0x0C bits [3:0] description. 00 CREG See address 0x0C bits [3:0] description. 00 CREG 0 = No error insertion. 1 = Invert corresponding bit in B1 byte. 00 39 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit (hex) 10 0 1 [3:2] 4 11 [7:5] [4:0] 12 [7:5] 0 13 40 Name Type Description Reset Value (hex) Device Register Blocks (continued) ISREG Consolidation interrupts. 0 = No interrupt. 1 = Interrupt. CH 2 INT ISREG Consolidation interrupts. 0 = No interrupt. 1 = Interrupt. Reserved. PER DEVICE INT ISREG Consolidation interrupts. 0 = No interrupt. 1 = Interrupt. Reserved. ENABLE/MASK IEREG REGISTER Reserved. FRAME OFFSET IAREG If in the receive direction the phase offset between any ERRROR FLAG two channels exceeds 17 bytes, then a frame offset error event will be issued. This condition is continuously monitored. CH 1 INT If the TTSV02622 memory map has not been unlocked (by writing a 001 to the lock registers), and any address other than the LOCKREG registers or SCRATCH PAD register is written to, then a WRITE TO LOCKED REGISTER event will be generated. 1 WRITE TO LOCKED IAREG See address 0x12 bit 0 description. REGISTER ERROR FLAG [7:2] Reserved. [1:0] ENABLE/MASK IEREG See address 0x12 bit 0 description. REGISTER [7:2] Reserved. 00 00 00 00 00 00 00 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit (hex) 20, 38 0 1 2 3 4 5 6 7 21, 39 0 1 2 3 4 5 6 7 Name Rx BEHAVIOR IN LOF FORCE AIS-L CONTROL TOH SERIAL OUTPUT PORT PAR ERR INS CMD Rx K1/K2 SOURCE SELECT PARALLEL OUTPUT BUS PARITY ERR INS CMD CHANNEL ENABLE/ DISABLE CONTROL HI-Z CONTROL OF PARALLEL OUTPUT BUS HI-Z CONTROL OF TOH DATA OUTPUT Tx D9 SOURCE SELECT Tx D10 SOURCE SELECT Tx D11 SOURCE SELECT Tx D12 SOURCE SELECT Tx K1/K2 SOURCE SELECT Tx S1/M0 SOURCE SELECT Tx E1/F2/E2 SOURCE SELECT Tx MODE OF OPERATION Agere Systems Inc. Type Description Channel Register Blocks CREG 0 = When Rx direction OOF occurs, do not insert AIS-L. 1 = When Rx direction OOF occurs, insert AIS-L. CREG 0 = Do not force AIS-L. 1 = Force AIS-L. CREG 0 = Do not insert a parity error. 1 = Insert parity error in parity bit of receive TOH serial output for as long as this bit is set. CREG 0 = Set receive direction K2/K2 bytes to 0. 1 = Pass receive direction K1/K2 though pointer mover. CREG 0 = Do not insert parity error. 1 = Insert parity error in the parity bit of receive direction parallel output bus for as long as this bit is set. CREG 0 = Powerdown channel and 3-state output buses. 1 = Functional mode. CREG 0 = 3-state output bus. 1 = Functional mode. CREG 0 = 3-state output lines. 1 = Functional mode. CREG 0 = Insert TOH from serial ports. 1 = Pass through that particular TOH byte. CREG 0 = Insert TOH from serial ports. 1 = Pass through that particular TOH byte. CREG 0 = Insert TOH from serial ports. 1 = Pass through that particular TOH byte. CREG 0 = Insert TOH from serial ports. 1 = Pass through that particular TOH byte. CREG 0 = Insert TOH from serial ports. 1 = Pass through that particular TOH byte. CREG 0 = Insert TOH from serial ports. 1 = Pass through that particular TOH byte. CREG 0 = Insert TOH from serial ports. 1 = Pass through that particular TOH byte. CREG 0 = Insert TOH from serial ports. 1 = Pass through all TOH. Reset Value (hex) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit (hex) 22, 3A 0 1 2 3 4 5 6 7 23, 3B 0 1 24, 3C [7:2] 0 Type Description Reset Value (hex) Channel Register Blocks (continued) Tx D1 SOURCE CREG 0 = Insert TOH from serial ports. SELECT 1 = Pass through that particular TOH byte. Tx D2 SOURCE CREG 0 = Insert TOH from serial ports. SELECT 1 = Pass through that particular TOH byte. Tx D3 SOURCE CREG 0 = Insert TOH from serial ports. SELECT 1 = Pass through that particular TOH byte. Tx D4 SOURCE CREG 0 = Insert TOH from serial ports. SELECT 1 = Pass through that particular TOH byte. Tx D5 SOURCE CREG 0 = Insert TOH from serial ports. SELECT 1 = Pass through that particular TOH byte. Tx D6 SOURCE CREG 0 = Insert TOH from serial ports. SELECT 1 = Pass through that particular TOH byte. Tx D7 SOURCE CREG 0 = Insert TOH from serial ports. SELECT 1 = Pass through that particular TOH byte. Tx D8 SOURCE CREG 0 = Insert TOH from serial ports. SELECT 1 = Pass through that particular TOH byte. A1/A2 ERROR CREG 0 = Do not insert error. INSERT COMMAND 1 = Insert error for number of frames in register 0x0C. B1 ERROR INSERT COMMAND The error insertion is based on a rising edge detector. As such, the control must be set to value 0 before trying to initiate a second A1 A2 corruption. CREG 0 = Do not insert error. 1 = Insert error for 1 frame in B1 bits defined by register 0x0F. CONCAT INDICATION 3 SREG 1 CONCAT INDICATION 6 SREG 2 CONCAT INDICATION 9 SREG 3 CONCAT INDICATION 12 SREG [7:4] 42 Name The error insertion is based on a rising edge detector. As such, the control must be set to value 0 before trying to initiate a second B1 corruption. Reserved. The value 1 in any bit location indicates that STS# is in CONCAT mode. A 0 indicates that the STS is not in CONCAT mode, or is the head of a concatenation group. The value 1 in any bit location indicates that STS# is in CONCAT mode. A 0 indicates that the STS is not in CONCAT mode, or is the head of a concatenation group. The value 1 in any bit location indicates that STS# is in CONCAT mode. A 0 indicates that the STS is not in CONCAT mode, or is the head of a concatenation group. The value 1 in any bit location indicates that STS# is in CONCAT mode. A 0 indicates that the STS is not in CONCAT mode, or is the head of a concatenation group. Reserved. 0 0 0 0 0 0 0 0 00 00 NA NA NA NA Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit (hex) 25, 3D 0 1 2 3 4 5 6 7 26, 3E 0 1 2 Name Type Description Channel Register Blocks (continued) SREG The value 1 in any bit location indicates that STS# is in CONCAT mode. A 0 indicates that the STS is not in CONCAT mode, or is the head of a concatenation group. CONCAT SREG The value 1 in any bit location indicates that STS# is in INDICATION 4 CONCAT mode. A 0 indicates that the STS is not in CONCAT mode, or is the head of a concatenation group. CONCAT SREG The value 1 in any bit location indicates that STS# is in INDICATION 7 CONCAT mode. A 0 indicates that the STS is not in CONCAT mode, or is the head of a concatenation group. CONCAT SREG The value 1 in any bit location indicates that STS# is in INDICATION 10 CONCAT mode. A 0 indicates that the STS is not in CONCAT mode, or is the head of a concatenation group. CONCAT SREG The value 1 in any bit location indicates that STS# is in INDICATION 2 CONCAT mode. A 0 indicates that the STS is not in CONCAT mode, or is the head of a concatenation group. CONCAT SREG The value 1 in any bit location indicates that STS# is in INDICATION 5 CONCAT mode. A 0 indicates that the STS is not in CONCAT mode, or is the head of a concatenation group. CONCAT SREG The value 1 in any bit location indicates that STS# is in INDICATION 8 CONCAT mode. A 0 indicates that the STS is not in CONCAT mode, or is the head of a concatenation group. CONCAT SREG The value 1 in any bit location indicates that STS# is in INDICATION 11 CONCAT mode. A 0 indicates that the STS is not in CONCAT mode, or is the head of a concatenation group. PER STS-12 ALARM ISREG These flag register bits PER STS-12 ALARM FLAG, FLAG AIS-P FLAG, and ELASTIC STORE OVERFLOW FLAG AIS-P FLAG ISREG are the per-channel interrupt status (consolidation) ELASTIC STORE ISREG register. CONCAT INDICATION 1 Reset Value (hex) NA NA NA NA NA NA NA NA 00 00 00 OVERFLOW FLAG 27, 3F [7:3] [2:0] [7:3] Agere Systems Inc. ENABLE/MASK REGISTER Reserved. IEREG These enable/mask register bits are the per-channel interrupt status (consolidation) register. Reserved. 0 43 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit (hex) 28, 40 0 1 2 3 4 5 29, 41 [7:6] [5:0] 2A, 42 [7:6] 0 1 2 3 [7:4] 44 Name Type Description Channel Register Blocks (continued) FIFO ALIGNER IAREG These are the PER STS-12 ALARM FLAGs. THRESHOLD ERROR FLAG RECEIVER INTER- IAREG These are the PER STS-12 ALARM FLAGs. NAL PATH PARITY ERROR FLAG LOF FLAG IAREG These are the PER STS-12 ALARM FLAGs. LVDS LINK B1 PAR- IAREG These are the PER STS-12 ALARM FLAGs. ITY ERROR FLAG INPUT PARALLEL IAREG These are the PER STS-12 ALARM FLAGs. BUS PARITY ERROR FLAG TOH SERIAL INPUT IAREG These are the PER STS-12 ALARM FLAGs. PORT PARITY ERROR FLAG Reserved. ENABLE/MASK IEREG These are the PER STS-12 ALARM FLAGs. REGISTER Reserved. AIS INTERRUPT IAREG These are the AIS-P ALARM FLAGs. FLAGS 3 AIS INTERRUPT IAREG These are the AIS-P ALARM FLAGs. FLAGS 6 AIS INTERRUPT IAREG These are the AIS-P ALARM FLAGs. FLAGS 9 AIS INTERRUPT IAREG These are the AIS-P ALARM FLAGs. FLAGS 12 Reserved. Reset Value (hex) 00 00 00 00 00 00 0 0 0 0 0 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit (hex) 2B, 43 2C, 44 2D, 45 Name Type Description Channel Register Blocks (continued) AIS INTERRUPT IAREG These are the AIS-P ALARM FLAGs. FLAGS 1 1 AIS INTERRUPT IAREG These are the AIS-P ALARM FLAGs. FLAGS 4 2 AIS INTERRUPT IAREG These are the AIS-P ALARM FLAGs. FLAGS 7 3 AIS INTERRUPT IAREG These are the AIS-P ALARM FLAGs. FLAGS 10 4 AIS INTERRUPT IAREG These are the AIS-P ALARM FLAGs. FLAGS 2 5 AIS INTERRUPT IAREG These are the AIS-P ALARM FLAGs. FLAGS 5 6 AIS INTERRUPT IAREG These are the AIS-P ALARM FLAGs. FLAGS 8 7 AIS INTERRUPT IAREG These are the AIS-P ALARM FLAGs. FLAGS 11 0 ENABLE/MASK AIS IEREG These are the AIS-P ALARM FLAGs. INTERRUPT FLAG 3 1 ENABLE/MASK AIS IEREG These are the AIS-P ALARM FLAGs. INTERRUPT FLAG 6 2 ENABLE/MASK AIS IEREG These are the AIS-P ALARM FLAGs. INTERRUPT FLAG 9 3 ENABLE/MASK AIS IEREG These are the AIS-P ALARM FLAGs. INTERRUPT FLAG 12 [7:4] Reserved. 0 ENABLE/MASK AIS IEREG These are the AIS-P ALARM FLAGs. INTERRUPT FLAG 1 1 ENABLE/MASK AIS IEREG These are the AIS-P ALARM FLAGs. INTERRUPT FLAG 4 2 ENABLE/MASK AIS IEREG These are the AIS-P ALARM FLAGs. INTERRUPT FLAG 7 3 ENABLE/MASK AIS IEREG These are the AIS-P ALARM FLAGs. INTERRUPT FLAG 10 4 ENABLE/MASK AIS IEREG These are the AIS-P ALARM FLAGs. INTERRUPT FLAG 2 5 ENABLE/MASK AIS IEREG These are the AIS-P ALARM FLAGs. INTERRUPT FLAG 5 6 ENABLE/MASK AIS IEREG These are the AIS-P ALARM FLAGs. INTERRUPT FLAG 8 7 ENABLE/MASK AIS IEREG These are the AIS-P ALARM FLAGs. INTERRUPT FLAG 11 0 Agere Systems Inc. Reset Value (hex) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 45 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit (hex) 2E, 46 2F, 47 30, 48 46 Name Type Description Reset Value (hex) Channel Register Blocks (continued) IAREG These are the ELASTIC STORE OVERFLOW alarm flags. 1 IAREG These are the ELASTIC STORE OVERFLOW alarm flags. 2 IAREG These are the ELASTIC STORE OVERFLOW alarm flags. 3 IAREG These are the ELASTIC STORE OVERFLOW alarm flags. [7:4] Reserved. 0 ES OVERFLOW IAREG These are the ELASTIC STORE OVERFLOW alarm FLAGS 1 flags. 1 ES OVERFLOW IAREG These are the ELASTIC STORE OVERFLOW alarm FLAGS 4 flags. 2 ES OVERFLOW IAREG These are the ELASTIC STORE OVERFLOW alarm FLAGS 7 flags. 3 ES OVERFLOW IAREG These are the ELASTIC STORE OVERFLOW alarm FLAGS 10 flags. 4 ES OVERFLOW IAREG These are the ELASTIC STORE OVERFLOW alarm FLAGS 2 flags. 5 ES OVERFLOW IAREG These are the ELASTIC STORE OVERFLOW alarm FLAGS 5 flags. 6 ES OVERFLOW IAREG These are the ELASTIC STORE OVERFLOW alarm FLAGS 8 flags. 7 ES OVERFLOW IAREG These are the ELASTIC STORE OVERFLOW alarm FLAGS 11 flags. 0 ENABLE/MASK ES IEREG These are the AIS-P ALARM FLAGs. OVERFLOW FLAG 3 1 ENABLE/MASK ES IEREG These are the AIS-P ALARM FLAGs. OVERFLOW FLAG 6 2 ENABLE/MASK ES IEREG These are the AIS-P ALARM FLAGs. OVERFLOW FLAG 9 3 ENABLE/MASK ES IEREG These are the AIS-P ALARM FLAGs. OVERFLOW FLAG 12 [7:4] Reserved. 0 ES OVERFLOW FLAGS 3 ES OVERFLOW FLAGS 6 ES OVERFLOW FLAGS 9 ES OVERFLOW FLAGS 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit (hex) 31, 49 32, 4A 33, 4B 34, 4C Name Type Description Channel Register Blocks (continued) ENABLE/MASK ES IEREG These are the AIS-P ALARM FLAGs. OVERFLOW FLAG 1 1 ENABLE/MASK ES IEREG These are the AIS-P ALARM FLAGs. OVERFLOW FLAG 4 2 ENABLE/MASK ES IEREG These are the AIS-P ALARM FLAGs. OVERFLOW FLAG 7 3 ENABLE/MASK ES IEREG These are the AIS-P ALARM FLAGs. OVERFLOW FLAG 10 4 ENABLE/MASK ES IEREG These are the AIS-P ALARM FLAGs. OVERFLOW FLAG 2 5 ENABLE/MASK ES IEREG These are the AIS-P ALARM FLAGs. OVERFLOW FLAG 5 6 ENABLE/MASK ES IEREG These are the AIS-P ALARM FLAGs. OVERFLOW FLAG 8 7 ENABLE/MASK ES IEREG These are the AIS-P ALARM FLAGs. OVERFLOW FLAG 11 COUN 7-bit count + overflow – reset on read. [6:0] LVDS LINK B1 PARITY ERROR TER COUNTER 7 OVERFLOW COUN — TER [6:0] LOF COUNTER COUN 7-bit count + overflow – reset on read. TER 7 OVERFLOW COUN — TER [6:0] A1/A2 FRAME COUN 7-bit count + overflow – reset on read. ERROR COUNTER TER 7 OVERFLOW COUN — TER 0 Agere Systems Inc. Reset Value (hex) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 8. Absolute Maximum Ratings Parameter Power Supply Voltage with Respect to Ground Input Voltages Power Dissipation Storage Temperature Range Symbol Min Max Unit VDD VIN PD Tstg — Vss – 0.3 — — 4.2 5.5 — — V V mW °C Handling Precautions Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114 (HBM) and JESD22-C101 (CDM) standards. Table 9. Handling Precautions Model Voltage Minimum HBM Threshold Minimum CDM on the corner pins only and the LU Minimum CDM on all other pins 2000 V 1000 V 500 V Recommended Operating Conditions The following tables list the voltages required for proper operation of the TTSV02622 device, along with their tolerances. Table 10. Recommended Operating Conditions Parameter Power Supply Voltage with Respect to Ground Input High Voltage (TTL input) Input Low Voltage (TTL input) Input Voltages Junction Temperature 48 Symbol Min Max Unit VDD VIH VIL VIN Tj 3.14 2.0 — Vss – 0.3 –40 3.47 5.5 0.8 5.5 125 V V V V °C Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Thermal Characteristics The TTSV02622 is a 5.86 mm x 6.49 mm die in the 272-pin PBGA (2-layer BGA). For thermal characteristics, the following values should be used: ■ ΘJc = 15.38 °C/W ΘJb = 25.09 °C/W ΘJa = 31.92 °C/W ■ ΨJt = 1.00 °C/W ■ ■ Table 11. Thermal Resistance—Junction to Ambient Air Speed in Linear Feet per Minute (LFPM) ΘJa (°C/W) JEDEC Standard Natural Convection 200 500 29.48 28.65 27.42 Power Consumption (Advance) Table 12. Power Consumption (Advance) Parameter 2 Channel Condition Max Unit At 3.3 V At 3.465 V 1.6 1.7 W W Electrical Characteristics Table 13. LVTTL Electrical Characteristics Parameter Output Voltage: Low High Symbol Test Conditions Min Max Unit VOL VOH — — — 2.4 0.4 — V V Propagation Delay Specifications 1. Delay in 77.78 MHz system clocks from the Tx line input to the LVDS backplane output is seven clocks (see Figure 15, Transmitter Transport Delay on page 56). 2. Propagation delay from a change on the PROT SW pin to a protection switch activity: ■ ■ NORM to HI-Z: — Five rising edges of SYS_CLK from assertion of the PROT_SW_A/C pins to the data changing to HI-Z. NORM to MUX switch: — Eight rising edges of SYS_CLK from assertion of the PROT_SW_A/C pins to the data changing from stream A to B. (See Figure 17 on page 58.) 3. Propagation delay from A1 STS-1 #1 arriving at LVDS input to RX_TOH_FP is 56 SYS_CLKs, and six TOH_CLKs. This will vary by ±14 SYS_CLKs, 12 each way for the FIFO alignment, and ±2 SYS_CLKs due to the variability in the clock recovery of the CDR macro. 4. Delay from CS_N going active (CPU write access to reset the chip) to reset being deactivated and CPU interface being ready to handle another access is nine SYS_CLKs. Agere Systems Inc. 49 TTSV02622 STS-24 Backplane Transceiver Data Sheet June 2003 LVDS I/O The LVDS buffers are compatible with IEEE ® 1596.3 and EIA ®/TIA-644. However, not all specs listed in the IEEE document pertained to just the buffer itself; rather they are system-level specifications. LVDS buffers in the TTSV02622 are compliant to all parts of the IEEE 1596.3 spec that pertain to silicon implementation. Unused inputs will not oscillate when they are open or short-circuited. Both P and N terminals of an input pad should not be held at voltages lower than 2.4 V. A 100 Ω resistor is included internally, so no board termination is necessary. Unused outputs do not need any termination, since they are terminated internally. This is valid for both powerdown mode and functional mode. The pin LVDS_EN is an enable that overrides any processor control over the powerdown of the LVDS input and output pads. This is for boundary scan use only, and should be pulled high during functional mode. For boundary scan, LVDS_EN = 0 and HIZ_N = 1. For board layout, LVDS traces should be run on controlled impedance layers, and should be specified as 50 Ω lineto-ground. The LVDS buffers support point-to-point connections. They are not intended for bussed implementations. 50 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver LVDS I/O (continued) LVDS DRIVER LVDS RECEIVER 100 Ω 50 Ω CENTER TAP 50 Ω EXTERNAL DEVICE PINS Figure 11. LVDS Driver and Receiver and Associated Internal Components DRIVER INTERCONNECT RECEIVER VOA A AA VIA VOB B BB VIB VGPD Figure 12. LVDS Driver and Receiver CA VOA A RLOAD VOB B V VOD = (VOA – VOB) CB Figure 13. LVDS Driver Agere Systems Inc. 51 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver LVDS I/O (continued) LVDS Receiver Buffer Capabilities A disabled or unpowered LVDS receiver can withstand a driving LVDS transmitter over the full range of driver operating range, for an unlimited period of time, without being damaged. Table 16 illustrates LVDS driver dc data, Table 17 the ac data, and Table 14 on page 52 and Table 15 on page 52 the LVDS receiver data. Table 14. LVDS Receiver dc Data* Parameter Symbol Conditions Min Typ Max Unit VI |VGPD| < 925 mV dc – 1 MHz 0 1.2 2.4 V Input Differential Threshold (Differential-Mode Voltage) VIDTH |VGPD| < 925 mV 800 MHz –100 — 100 mV Input Differential Hysteresis VHYST (+VIDTHH) – (–VIDTHL) — — —† mV RIN With Build-In Termination, Center-Tapped 80 100 120 Ω Input Voltage Range, VIA or VIB (Common-Mode Voltage) Receiver Differential Input Impedance * VDD = 3.1 V—3.5 V, 0 °C—125 °C, slow—fast process. † Buffer will not produce output transition when input is open-circuited. Table 15. LVDS Receiver ac Data* Parameter Rise Time (20%—80%) Fall Time (80%—20%) Symbol Conditions Min Max Unit tR tF CL = 1.5 pF CL = 1.5 pF 50 50 150 150 ps ps * VDD = 3.1 V—3.5 V, 0 °C—125 °C, slow—fast process. 52 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver LVDS I/O (continued) Table 16. LVDS Driver dc Data* Parameter Output Voltage High, VOA or VOB Output Voltage Low, VOA or VOB Output Differential Voltage Symbol Conditions Min VOH RLOAD = 100 Ω ± 1% — VOL |VOD| RLOAD = 100 Ω ± 1% RLOAD = 100 Ω ± 1% † 0.925 0.25 Typ Max Unit — 1.475† V — — V — † 0.45 † † V Output Offset Voltage VOS RLOAD = 100 Ω ± 1% 1.125 — 1.275 V Output Impedance, Signal Ended RO VCM = 1.0 V and 1.4 V 40 50 60 Ω ∆RO VCM = 1.0 V and 1.4 V — — 10 % Change in Differential Voltage Between Complementary States |∆VOD| RLOAD = 100 Ω ± 1% — — 25 mV Change in Output Offset Voltage Between Complementary States ∆VOS RLOAD = 100 Ω ± 1% — — 25 mV Output Current ISA, ISB Driver Shorted to GND — — 24 mA Output Current ISAB Drivers Shorted Together — — 12 mA |Ixa|, |Ixb| VDD = 0 V VPAD, VPADN = 0 V—3 V — — 30 µA RO Mismatch Between A and B Power-Off Output Leakage * VDD = 3.1 V—3.5 V, 0 °C—125 °C, slow—fast process. † External references selected (CNT = 0), REF10 = 1.0 V ± 3%, REF14 = 1.4 V ± 3%. Table 17. LVDS Driver ac Data* Parameter Symbol Conditions Min Max Unit VOD Fall Time, 80%—20% tF 100 200 ps VOD Rise Time, 20%—80% tR ZL = 100 Ω ± 1% CPAD = 3.0 pF, CPADN = 3.0 pF ZL = 100 Ω ± 1% CPAD = 3.0 pF, CPADN = 3.0 pF Any Differential Pair on Package at the 50% Point of the Transition 100 200 ps — 50 ps Differential Skew |tPHLA – tPHLB| or |TPHLB – TPLHA| tSKEW1 * VDD = 3.1 V—3.5 V, 0 °C—125 °C, slow—fast process. Table 18. LVDS Driver Reference Data Parameter Conditions Min Typ Max Unit REF10 Voltage Range — 0.95 1.0 1.05 V REF14 Voltage Range — 1.35 1.4 1.45 V Nominal Input Current— REF10 and REF14 Reference Inputs — — 10 — µA Agere Systems Inc. 53 TTSV02622 STS-24 Backplane Transceiver Data Sheet June 2003 Clock and Data Recovery (CDR) The following specifications are in reference to the clock and data recovery macro that is used for the backplane interface on the TTSV02622 chip. Input Data ■ ■ ■ ■ 622 Mbits/s scrambled data stream conforms to SONET STS-12 and SDH STM-4 data format using either a PN7 or PN9 sequence. The PN7 characteristic is 1+ x6 + x7 and The PN9 characteristic is 1+ x4 + x9. Longest stream of nontransitional 622 Mbits/s input data is 60 bits. This sequence should not occur more often than once per minute. Input signal phase change of no more than 100 ps over 200 ns time interval, which translates to a frequency change of 500 ppm. Eye opening greater than 0.4 UIp-p. Unit interval for 622 Mbits/s is 1.6075 ns. Jitter Tolerance Table 19. Jitter Tolerance Frequency UIp-p 250 kHz 25 kHz 2 kHz 0.6 6.0 60 Generated Output Jitter ■ 0.2 UIp-p from 250 kHz to 5 MHz as measured on a spectrum analyzer. PLL ■ Loop bandwidth of less than 6 MHz. ■ Jitter peaking of less than 2 dB. ■ Minimum powerup reset duration of 10 µs. ■ Maximum lock acquisition of less than 1 ms. ■ External 10 kΩ resistor to ground required. Input Reference Clock ■ Frequency deviation of no more than ± 20 ppm. ■ Phase change of no more than 100 ps in 200 ns. ■ Time interval that translates to a frequency change of 500 ppm. ■ Input reference clock of 77.76 MHz. 54 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Timing Characteristics All timing numbers are measured relative to 1.5 V. All outputs are driving 35 pF maximum, 5 pF minimum, except DB pins which drive 100 pF. TP TL SYS_CLK TH SYS_FP FIRST A1 OF STS-1 #1 INPUT BUS TSU THD Figure 14. Input Parallel Port Timing Table 20. Input Parallel Port Timing Requirements Symbol TP TL TH TSU THD Parameter Clock Period Clock Low Time Clock High Time Data Setup Time Data Hold Time Agere Systems Inc. Min Typ Max Unit — 5.1 5.1 3 0 12.86 — — — — — 7.7 7.7 — — ns ns ns ns ns 55 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Timing Characteristics (continued) TPROP SYS_CLK SYS_FP PARALLEL DATA INPUT BUS A1 OF STS-1 #1 LVDS DATA OUT MSB OF FIRST A1 OF STS-1 #1 Figure 15. Transmitter Transport Delay Table 21. Transmitter Transport Delay Timing Requirements Symbol TPROP Parameter Number of Clocks of Delay from Parallel Bus Input to LVDS Output Typ Unit 7 SYS_CLK Notes: LVDS data transmitted MSB first. Min/max variation due to clock phase selected in clock recovery block. 56 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Timing Characteristics (continued) TP TL SYS_CLK TH LINE_FP TSU THD OUTPUT BUS FIRST A1 OF STS-1 #1 PARITY, SPE, C1J1 PINS TCO Figure 16. Output Parallel Port Timing Table 22. Output Parallel Port Timing Requirements Symbol TP TL TH TSU THD TCO Parameter Clock Period Clock Low Time Clock High Time Data Setup Time Data Hold Time Clock to Output Time of Data, Parity, SPE, and C1J1 Pins Min Typ Max Unit — 5.1 5.1 3 0 1.3 12.86 6.43 6.43 — — — — 7.7 7.7 — — 7 ns ns ns ns ns ns Note: Min TCO number is calculated based on 5 pF load. Max TCO is calculated based on 35 pF load. Agere Systems Inc. 57 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Timing Characteristics (continued) THD TSU CH A CH A TTR SYS_CLK PROT_SW_A OUTPUT BUS* A CH A CH A CH B THIZ TCH SYS_CLK OUTPUT BUS A&B CH A & B CH A & B CH A & B CH A & B Figure 17. Protection Switch Timing Table 23. Protection Switch Timing Requirements Symbol TTR THIZ TCH TSU THD Parameter Transport Delay from Latching of PROT_SW_A to Actual Data Switch Transport Delay from Latching of PROT_SW_A to Actual Data HI-Z Propagation Delay from SYS_CLK to HI_Z of Output Bus Setup Time Required from Change in PROT_SW_A to Rising SYS_CLK Hold Time Required from Rising SYS_CLK to Change in PROT_SW_A Min Typ Max Unit — 8 — — 5 — — 3 — — 25 — Leading edge SYS_CLKs Leading edge SYS_CLKs ns ns 0 — — ns Notes: Output bus refers to 8 bits data, 1 bit parity, 1 bit SPE, and 1 bit C1J1. Channel A refers to whether the PROT_SW_A pins that are activated. For example, if the PROT_SW_A pin is activated, the timing diagram for output bus A refers to output bus A. Min/max variation on TRT and THIZ due to clock phase selected in clock recovery block. 58 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Timing Characteristics (continued) SYS_CLK SYS_FP ROW #1 INPUT PARALLEL BUS 36 bytes TOH ROW #9 1044 bytes SPE 1044 bytes SPE GUARD BAND (4 TOH CLK) 36 bytes TOH GUARD BAND (4 TOH CLK) TP THI TLO TOH_CLK TS TH TX TOH_ CLK_ENA TOH SERIAL INPUT MSBIT(7) OF B1 BYTE STS-1 #1 BIT 6 OF B1 BYTE STS-1 #1 Figure 18. Input Serial Port Timing Table 24. Input Serial Port Timing Requirements Symbol TP THI TLO TS TH Parameter Clock Period Clock High Time Clock Low Time Data Setup Time Data Hold Time Agere Systems Inc. Min Typ Max Unit 12.86 5.1 5.1 3 0 — — — — — 40 24 24 — — ns ns ns ns ns 59 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Timing Characteristics (continued) ROW #1 INPUT LVDS SERIAL 622 Mbits/s DATA 36 bytes TOH ROW #9 1044 bytes SPE 1044 bytes SPE 36 bytes TOH TTRANS_SYS TTRANS_TOH TOH_CLK RX TOH FP TCO RX TOH CLK ENA TOH SERIAL OUTPUT MSBIT(7) OF A1 BYTE STS-1 #1 BIT 6 OF A1 BYTE STS-1 #1 BIT 0 OF A1 BYTE STS-1 #1 Figure 19. Output Serial Port Timing Table 25. Output Serial Port Timing Requirements Symbol TCO TTRANS_SYS TTRANS_TOH Parameter Data Clock to Out Delay from First A1 LVDS Serial Input to Transfer to TOH_CLK Delay from Transfer to TOH_CLK to RX_TOH_FP Min Typ Max Unit 2 44 — 56 8 68 ns SYS_CLKs — 6 — TOH_CLKs Note: The total delay from A1 STS-1 #1 arriving at LVDS input to RX_TOH_FP is 56 SYS_CLKs, and 6 TOH_CLKs. This will vary by ±14 SYS_CLKs, 12 each way for the FIFO alignment, and ± 2 SYS_CLKs due to the variability in the clock recovery of the CDR macro. 60 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Timing Characteristics (continued) CPU Interface Timing TACCESS_MIN TPULSE CS_N TRD_WR_N, ADDR_MAX, DB_HOLD RD_WR_N ADDR[6:0] DATA VALID DB[7:0] INTERNAL REGISTER (SYS_CLK DOMAIN) OLD VALUE NEW VALUE TADDR_MAX TDAT_MAX, TRD_WR_MAX TINT_MAX TWRITE_MAX INT_N Figure 20. Write Transaction Table 26. Write Transaction Timing Requirements Symbol Parameter Min Max Unit TPULSE Minimum Pulse Width for CS_N Maximum Time from Negative Edge of CS_N to ADDR Valid Maximum Time from Negative Edge of CS_N to Data Valid Maximum Time from Negative Edge of CS_N to Negative Edge of RD_WR_N Maximum Time from Negative Edge of CS_N to Contents of Internal Register Latching DB[7:0] Minimum Time Between a Write Cycle (falling edge of CS_N) and Any other Transaction (read or write, at falling edge of CS_N) Maximum Time from Register FF to Pad Minimum Hold Time that RD_WR_N, ADDR, and DB Must Be Held Valid from the Negative Edge of CS_N 5 — — — — 18 25 26 ns ns ns ns — 60 ns 60 — ns — 57 20 — ns ns TADDR_MAX TDAT_MAX TRD_WR_MAX TWRITE_MAX TACCESS_MIN TINT_MAX TRD_WR_N, ADDR_MAX, DB_HOLD Agere Systems Inc. 61 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Timing Characteristics (continued) CPU Interface Timing (continued) TACCESS_MIN TPULSE CS_N TDH RD_WR_N ADDR[6:0] THIZ_MAX DB[7:0] DATA VALID TADDR_MAX TRD_WR_MAX TDATA_MAX Figure 21. Read Transaction Table 27. Read Transaction Timing Requirements Symbol Parameter Min Max Unit TPULSE TADDR_MAX TRD_WR_MAX TDATA_MAX THIZ_MAX TDH TACCESS_MIN Minimum Pulse Width for CS_N Maximum Time from Negative Edge of CS_N to Addr Valid Maximum Time from Negative Edge of CS_N to RD_WR_N Rising Maximum Time from Negative Edge of CS_N to Data Valid on DB Port Maximum Time from Rising Edge of CS_N to DB Port Going HI-Z Data Hold Time After CS_N Is Deasserted Minimum Time Between a Read Cycle (falling edge of CS_N) and Any Other Transaction (read or write, at falling edge of CS_N) 5 — — — — 0 60 — 5 5 56 12 — — ns ns ns ns ns ns ns 62 Agere Systems Inc. Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Outline Diagram 272-Pin PBGA Dimensions are in millimeters. 27.00 ± 0.20 +0.70 24.00 –0.00 A1 BALL IDENTIFIER ZONE 24.00 +0.70 –0.00 27.00 ± 0.20 MOLD COMPOUND PWB 1.17 ± 0.05 0.36 ± 0.04 2.13 ± 0.19 SEATING PLANE 0.20 SOLDER BALL 0.60 ± 0.10 19 SPACES @ 1.27 = 24.13 CENTER ARRAY FOR THERMAL ENHANCEMENT (OPTIONAL) A1 BALL CORNER Agere Systems Inc. Y W V U T R P N M L K J H G F E D C B A 0.75 ± 0.15 19 SPACES @ 1.27 = 24.13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 63 Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Ordering Information Device Code Package Temperature TTSV02622V2-DB 272-pin PBGA –40 °C to +125 °C Comcode (Ordering Number) 700034617 For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: [email protected] N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere Logo are trademarks of Agere Systems Inc. Copyright © 2003 Agere Systems Inc. All Rights Reserved June 2003 DS02-340SONT