ASAHI KASEI
[AK2504A]
AK2504A
DS3/STS-1/E3 Transceiver
GENERAL DESCRIPTION
FEATURE
The AK2504A is a DSP based line transceiver. It
provides the analog transmit/receive line interface
functions for DS3(44.736MHz) /STS-1(51.84MHz)
or E3(34.368MHz) interface.
-
“Robust” DSP based line transceiver
-
Provides Complete Analog Line Transmitter
and Receiver function for DS3, STS-1 and E3
Applications
Transmitter includes on-chip pulse shaper, B3ZS/
HDB3 Encoder. Pulse level adjustment function is
very useful to put a pulse into pulse mask for any
customer’s system.
Receiver includes root-f equalizer, automatic-gain
control, clock and data recovery, B3ZS/HDB3
Decoder, Loss-Of-Signal and Loss-Of-Lock alarm
function.
-
Transmit Pulse Level Adjustment
-
Provides Line Equalization, and Clock and
Data Recovery Functions
-
Compliance with Bellcore GR-499-CORE and
GR-253-CORE, ANSI T1.102, T1.404,
-
Compliance with ITU-T G.703 and G.823
-
Local/Remote Loopback functions
-
B3ZS/HDB3 Encoder/Decoder
-
Low voltage supply : +3.3V
Local and Remote Loop-back function is included
for system level trouble shooting.
The device operates at a single +3.3 Volt supply
and is transparent to the framing format.
PACKAGE
-
64 pin LQFP
APPLICATIONS
-
Interfacing network transmission equipment
such as SONET multiplexor and M13 to a
DSX-3 cross connect.
-
Interfacing
equipment.
-
MS0143-E-01
-1-
E3
network
transmission
Interfacing customer premises equipment to a
line.
2004/01
ASAHI KASEI
[AK2504A]
BLOCK DIAGRAM
RESET
E3
61
TPDATA
TNDATA
TCLK
LBO
43
TAOS
60
PLA
35
56
39
24
25
23
B3ZS/HDB3
PULSE
OUTPUT
ENCODER
SHAPER
DRIVER
37
TTIP
TRING
LOOP
BACK
NRZ
3
CLOCK
7
TCKPOL
RCKPOL
41
51
20
45
21
B3ZS/HDB3
DATA
GAIN and LINE
22
RECOVERY
RNDATA
/LCV
DECODER
EQUALIZATION
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
46
9
27
RPDATA
26
19
58
40
11
MS0143-E-01
RLOL
EXCLK
RECOVERY
6
RCLK
14
MUX
TEST
LOS
CIRCUIT
LOGIC
12
13
VSSS VDDD
VSSD
8
10
RLOOP LLOOP
42
LOSTHR
-2-
62
RLOS
30
28
44
55
EQDIS
RTIP
RRING
36
VDDT
29
VSST
38
VSST
59
VDDA
52
53
4
5
54
57
VDDV
VSSV
VDDP
VSSP
VDDB
VSSB
TCAP1 TCAP2 IREF
2004/01
ASAHI KASEI
[AK2504A]
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
NC
TEST1
RTIP
RRING
E3
LOSTHR
RCKPOL
TEST7
TTIP
VSST
TRING
VDDT
TAOS
NC
NC
PIN LOCATION
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NC
NC
TCAP1
VSST
TCAP2
TEST3
TEST4/eTX
TNDATA
TPDATA
TCLK
RNDATA/LCV
RPDATA
RCLK
TEST5
NC
NC
NC
NC
NRZ
VDDP
VSSP
TCKPOL
EXCLK
RLOOP
TEST2
LLOOP
VSSS
VDDD
VSSD
RLOL
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
NC
EQDIS
VDDV
VSSV
VDDB
IREF
PLA
VSSB
TEST6
VDDA
LBO
RESET
RLOS
NC
NC
NC: No Connection. Leave these pins open.
MS0143-E-01
-3-
2004/01
ASAHI KASEI
[AK2504A]
PIN CONDITION
No.
Pin Name
I/O
Pin Type
CMOS
3
NRZ
I
4
VDDP
-
5
VSSP
-
6
TCKPOL
I
CMOS
7
EXCLK
I
CMOS
8
RLOOP
I
CMOS
9
TEST2
I
CMOS
10
LLOOP
I
CMOS
11
VSSS
-
12
VDDD
-
13
VSSD
-
14
RLOL
O
CMOS
19
TEST5
I
CMOS
20
RCLK
O
21
23
RPDATA
RNDATA
/LCV
TCLK
24
Maximum
AC load
Minimum
DC load
Status on
Reset
Remarks
15pF
“H”
CMOS
15pF
“H”
O
CMOS
15pF
“L”
O
CMOS
15pF
“L”
I
CMOS
TPDATA
I
CMOS
25
TNDATA
I
CMOS
26
TEST4
O
CMOS
27
TEST3
I
CMOS
28
TCAP2
O
Analog
Note 1
29
VSST
-
30
TCAP1
O
Analog
Note 1
22
Note:
*) NC pin number : No. 1, 2, 15, 16, 17, 18, 31, 32 NC: No Connection. Leave these pins open.
1)External capacitor (0.1 uF) is connected to VSS.
MS0143-E-01
-4-
2004/01
ASAHI KASEI
No.
Pin Name
35
[AK2504A]
I/O
Pin Type
TAOS
I
CMOS
36
VDDT
-
37
TRING
O
38
VSST
-
39
TTIP
40
Maximum
AC load
Minimum
DC load
Status on
Reset
Remarks
Analog
Hi-Z
O
Analog
Hi-Z
TEST7
O
CMOS
41
RCKPOL
I
CMOS
42
LOSTHR
I
Analog
43
E3
I
CMOS
44
RRING
I
Analog
45
RTIP
I
Analog
46
TEST1
I
CMOS
51
EQDIS
I
CMOS
52
VDDV
-
53
VSSV
-
54
VDDB
-
55
IREF
O
Analog
Note 2
56
PLA
O
Analog
Note 3
57
VSSB
-
58
TEST6
I
59
VDDA
-
60
LBO
I
CMOS
61
RESET
I
CMOS
62
RLOS
O
CMOS
CMOS
Note 4
15pF
“H”
Note
*)NC pin number : No. 33, 34, 47, 48, 49, 50, 63, 64 NC: No Connection. Leave these pins open.
2)External resister 4.7 kΩ±1% should be connected between IREF and VSS.
3)External resister should be connected between PLA and VSS.
Normally 1.33kΩ is connected for DS3/STS-1 or 1.27kΩ for E3.
4)Pulled up to VDD with internal register. (typical 50k Ω)
MS0143-E-01
-5-
2004/01
ASAHI KASEI
[AK2504A]
PIN DESCRIPTION
Receive
No. Pin Name
42
LOSTHR
I
14
RLOL
O
45
RTIP
I
44
RRING
62
RLOS
O
7
EXCLK
I
20
RCLK
O
22
RNDATA
/LCV
O
21
RPDATA
O
41
RCKPOL
I
51
EQDIS
I
Function
Loss of Signal Threshold Control (See Table 15)
The voltage forced on this pin controls the input loss-of-signal threshold.
Two settings are provided by forcing VSS or VDD.
Receive PLL Loss-of-Lock
Active High alarm. If the recovered clock frequency is larger than
approximately 0.5% of EXCLK, RLOL alarm goes High.
Receive Tip Input
Receive input for differential AMI signal. Requires a 1:1 transformer.
Receive Ring Input
Receive input for differential AMI signal. Requires a 1:1 transformer.
Receive Loss-of-Signal.
This pin is set high on loss of the incoming signal at RIN.
External Reference Clock.
A valid DS3/STS-1/E3 clock must be provided at this input. The EXCLK
frequency determines the operating frequency of the device.
Recovered Clock.
Receive Negative Data/Line Code Violation Indicator
This pin’s function depends on the input level.
NRZ = Low : Receive Negative Data output
NRZ = High : Bipolar Violation Output
1 bit period of High level signal is output if a bipolar violation not
corresponding to the appropriate coding rule or a code error is detected in the
incoming data stream. The violation pulse corresponding to the appropriate
coding rule is removed from the incoming data.
Receive Positive Data
This pin’s function depends on the input level.
NRZ = low : Receive Positive Data output
NRZ = high : NRZ data output
RCLK Polarity select.
RCKPOL=L : Received data is output on the rising edge of RCLK.
RCKPOL=H : Received data is output on the falling edge of RCLK.
Equalizer Disable. When EQDIS=H, Equalizer is disable.
59
VDDA
-
Power Supply for ADC.
+3.3 volts.
52
VDDV
-
Power Supply for VGA.
+3.3 volts.
53
VSSV
-
Ground for VGA.
4
VDDP
-
Power Supply for PLL.
5
VSSP
-
Ground for PLL.
54
VDDB
-
Power Supply for Bandgap Reference.
57
VSSB
-
Ground for Bandgap Reference.
MS0143-E-01
I/O
0 volts.
+3.3 volts
0 volts.
-6-
+3.3 volts.
0 volts.
2004/01
ASAHI KASEI
Transmit
No. Pin Name
[AK2504A]
I/O
24
TPDATA
I
25
TNDATA
I
23
TCLK
I
6
TCKPOL
I
39
TTIP
O
37
TRING
O
56
PLA
I
3
NRZ
I
Function
Transmit Positive Data/NRZ data
This pin’s function depends on the input level.
NRZ = Low : Positive AMI data output
NRZ = High : NRZ data
Transmit Negative Data
This pin’s function depends on the input level.
NRZ = Low : Negative AMI data output
NRZ = High : Should be tied to VSS
Transmit Clock
TPDATA and TNDATA are sampled on the rising or falling edge of TCLK.
Sampling edge must be assigned by TCKPOL pin.
TCLK Polarity select.
TCKPOL=Low : Transmit data is sampled on the rising edge of TCLK.
TCKPOL=High : Transmit data is sampled on the falling edge of TCLK.
Transmit Tip / Ring Output
AMI signal output. Requires a 1:1CT transformer. Hi-Z when RESET = Low.
Pulse Level Adjustment
Transmit pulse level can be adjusted by the external resister.
Normally 1.33kΩ is connected for DS3/STS-1 or 1.27kΩ for E3.
If the signal power level is larger than a requirement, you can tweak
it by increasing the value of this resister.
NRZ mode Enable
Active High input enables NRZ data interface with TPDATA and RPDATA.
NRZ
0
1
TPDATA TNDATA
Positive Negative
NRZ
(VSS)
RPDATA RNDATA
Positive Negative
NRZ
LCV
In NRZ mode, TNDATA should be tied to VSS and RNDATA indicates LCV.
Line Built Out
If LBO is set to High, Line Built Out function is enable.
60
LBO
I
LBO input
Low
High
Cable length
225 – 450ft
0 – 225ft
30
TCAP1
O
28
TCAP2
O
35
TAOS
I
36
29,
38
VDDT
-
This pin is active only with E3 pin set to High(DS3/STS-1 mode).
Reference Voltage Output for the TX driver.
An external capacitor (0.1µF±20%) should be connected to VSSA.
Reference Voltage Output for the TX driver.
An external capacitor (0.1µF±20%) should be connected to VSSA.
Transmit All Ones Select
Active High input. A continuous AMI all 1’s pattern to be transmitted from
TTIP and TRING. Transmit rate is defined by TCLK.
Power Supply for Transmitter. +3.3 volts.
VSST
-
Ground for Transmitter.
MS0143-E-01
-7-
0 volts
2004/01
ASAHI KASEI
Others
No. Pin Name
[AK2504A]
43
E3
-
55
IREF
O
8
RLOOP
I
10
LLOOP
I
61
RESET
I
46
TEST1
I
9
TEST2
I
Function
DS3/STS-1 or E3 select pin
High : DS3/STS-1
Low : E3
Current Reference Output
External resistance (4.7 kΩ±1%) should be connected to VSSA.
Remote Loop Back
Active High input. RPDATA and RNDATA are transmitted from TTIP and
TRING using RCLK. Input High on both RLOOP and LLOOP are inhibited.
Local Loop Back
Active High input. TPDATA,TNDATA and TCLK are looped back to RPDATA,
RNDATA and RCLK. Input High on both RLOOP and LLOOP are inhibited.
Active low RESET.
Pulled up to VDD with internal resister.
Test Mode.
Should be connected to VSS.
TEST1=High : The part goes into Test mode.
TEST1=Low : The part goes into the Normal operation mode.
Should be connected to VSS.
27
TEST3
I
Should be connected to VSS.
26
TEST4
O
Output “Low” when TEST1=Low (Normal operation mode)
19
TEST5
I
Should be connected to VSS.
58
TEST6
I
Should be connected to VSS.
40
TEST7
O
Should be open.
12
VDDD
-
Power Supply for Digital.
13
VSSD
-
Ground for Digital.
11
VSSS
-
Ground for Substrate.
MS0143-E-01
I/O
+3.3 volts.
0 volts
0 volts
-8-
2004/01
ASAHI KASEI
[AK2504A]
FUNCTIONAL DESCRIPTION
The AK2504A provides the basic transmit and receive functions of a high-speed line card.
Signal Requirements
DS3/STS1
Pulse characteristics are specified at the DSX-3.
Table 1. DS3 Interface Specification
Parameter
Specification
Line Rate
44.736Mbps±20ppm
Line Code
B3ZS
Test Load
75Ω±5%
Standards
GR-499-CORE , ANSI T1.102 , T1.404
Table 2. STS-1 Interface Specification
Parameter
Specification
Line Rate
51.840Mbps±20ppm
Line Code
B3ZS
Test Load
75Ω±5%
Standards
GR-253-CORE , ANSI T1.102
MS0143-E-01
-9-
2004/01
[AK2504A]
1.2
1.2
1.0
1
0.8
0.8
Normilized Amplitude
Normalized Amplitude
ASAHI KASEI
0.6
0.4
0.2
0.6
0.4
0.2
0.0
0
-0.2
-1.0
-0.5
0.0
0.5
1.0
-0.2
-1.00
1.5
-0.50
Time[UI]
0.00
0.50
1.00
1.50
Time[UI]
Fig. 1 DSX-3 Pulse Mask
Fig. 2 STS-1 Pulse Mask
Table 3. DS3 Pulse Mask and Equations (ANSI T1.102, T1.404, GR-499-CORE)
Lower Curve
Upper Curve
Time
Equation
Time
Equation
-0.85 ≤ T ≤ -0.36
-0.03
-0.85 ≤ T ≤ -0.68
0.03
-0.36 ≤ T ≤ 0.36
0.5{1+sin[(π/2)(1+T/0.18)]}-0.03
-0.68 ≤ T ≤ 0.36
0.5{1+sin[(π/2)(1+T/0.34)]}+0.03
0.36 ≤ T ≤ 1.4
-0.03
0.36 ≤ T ≤ 1.4
0.08+0.407e-1.84(T-0.36)
Table 4 STS-1 Pulse Mask and Equations (GR-253-CORE, T1.102)
Lower Curve
Upper Curve
Time
Equation
Time
Equation
-0.85 ≤ T ≤ -0.36
-0.03
-0.85 ≤ T ≤ -0.68
0.03
-0.36 ≤ T ≤ 0.36
0.5{1+sin[(π/2)(1+T/0.18)]}-0.03
-0.68 ≤ T ≤ 0.26
0.5{1+sin[(π/2)(1+T/0.34)]}+0.03
0.36 ≤ T ≤ 1.4
-0.03
0.26 ≤ T ≤ 1.4
0.1+0.61e-2.4(T-0.26)
MS0143-E-01
- 10 -
2004/01
ASAHI KASEI
[AK2504A]
E3
Pulse characteristics are specified at the output ports
Table 5. E3 Pulse Specification (G.703)
Pulse shape (nominally rectangular)
All marks of a valid signal must conform with the
mask (see Fig.3), irrespective of the sign
Pair(s) in each direction
One coaxial pair
Test load impedance
75 Ωs resistive
Nominal peak voltage of a mark (pulse)
1.0 V
Peak voltage of a space (no pulse)
0 V ± 0.1 V
Nominal pulse width
14.55 ns
Ratio of the amplitudes of positive and negative
pulses at the center of a pulse interval
0.95 to 1.05
Ratio of the widths of positive and negative
pulses at the nominal half amplitude
0.95 to 1.05
17 ns
(14.55 + 2.45)
0.1
1.0
0.2
8.65 ns
(14.55 – 5.90)
0.2
0.1
V
Nominal pulse
14.55 ns
0.5
12.1 ns
(14.55 – 2.45)
0.1
0.1
(14.55 + 9.95)
0.2
0.1
0.1
24.5 ns
0
29.1 ns
(14.55 + 14.55)
T1818860-92
FIGURE 17/G.703
Pulse mask at the 34 368-kbit/s interface
Fig. 3 E3 Pulse Mask
MS0143-E-01
- 11 -
2004/01
ASAHI KASEI
[AK2504A]
Logic Data Interface
AK2504A can handle Positive/Negative data and NRZ data.
Positive/Negative data Interface
If NRZ pin = Low, the transmitter accepts Positive/Negative transmit data on TPDATA/TNDATA and the receiver
outputs Positive/Negative received data on RPDATA/RNDATA. In this mode, B3ZS/HDB3 Encoder/Decoder is
disable. Transmit and Received data is output transparently.
NRZ data Interface
If NRZ pin = High, the transmitter accepts NRZ transmit data on TPDATA (TNDATA should be tied to VSS).
The receiver outputs NRZ received data on RPDATA. In this mode, B3ZS/HDB3 Encoder/Decoder is enable.
LCV alarm will be indicated on RNDATA whenever a bipolar violation is detected in the incoming data stream.
Low
High
NRZ
NRZ
Disable
TPOS
TPDATA
TNEG
TNDATA
RPOS
RPDATA
RNEG
RNDATA
Enable
TNRZ
B3ZS
HDB3
Encoder
Decoder
TPDATA
TNDATA
RNRZ
RPDATA
BPV
RNDATA
Positive/Negative AMI
B3ZS
HDB3
Encoder
Decoder
NRZ
Fig. 4 Logic Data Interface
Line Code Violation
If a bipolar violation not corresponding to the appropriate coding rule or a code error is detected in the incoming
data stream, LCV is set high for one bit period. The violation pulse corresponding to the appropriate coding rule is
removed from the incoming data.
Bipolar Violation
B3ZS, HDB3 :
B, V
(+1,+1) or (-1,–1)
→
RPDATA --LCV
---
1, 1
0, 1
HDB3:
B, 0, V
(+1, 0,+1) or (-1, 0,–1)
→
RPDATA
LCV
1, 0, 1
0, 0, 1
-----
Coding Violation (With an even number of Bs since the last V)
B3ZS :
0, V
( 0,+1) or ( 0,–1)
→
RPDATA --LCV
---
0, 1
0, 1
HDB3:
0, 0, V
( 0, 0,+1) or ( 0, 0,–1)
→
RPDATA --LCV
---
0, 0, 1
0, 0, 1
MS0143-E-01
- 12 -
2004/01
ASAHI KASEI
[AK2504A]
Excessive Zeros
B3ZS :
0, 0, 0
→
RPDATA --LCV
---
0, 0, 0
0, 0, 1
HDB3:
0, 0, 0, 0
→
RPDATA --LCV
---
0, 0, 0, 0
0, 0, 0, 1
Receive data
0
includes B3ZS
encode error
1
0
0
V 1
1
1
0
V 1
V 0
0
1
1
0
V 0
0
0
1
AMI
Bipolar
violation
0
RPDATA
0
0
0
0
Code
violation
Excessive
zeros
0
LCV
Fig. 5 RPDATA and LCV outputs in NRZ mode (B3ZS)
Receive data
0
includes HDB3
encode error
1
0
0
0
V 1
1
1
0
0
V 1
V 0
0
1
1
0
0
V 0
0
0
0
1
AMI
Bipolar
violation
RPDATA
0
0
0
0
0
0
0
Code
violation
Excessive
zeros
0
LCV
Fig. 6 RPDATA and LCV outputs in NRZ mode (HDB3)
MS0143-E-01
- 13 -
2004/01
ASAHI KASEI
[AK2504A]
Pulse Shaper
Pulse Shaper generates a waveform meeting the pulse mask such as described in Table 3,4,5.
The input data of Pulse Shaper is the sampled data of TPDATA and/or TNDATA pins on the rising or falling edge
of TCLK. Polarity of TCLK is selected by TCKPOL pin.
Line Built Out
When LBO = High, the transmit pulse is output through LBO circuit which makes transmit pulse filtered with the
frequency response equivalent to the 225ft cable.
Table 6 Transmit Pulse Amplitude (DS3/STS-1)
LBO
Cable Length
DS3, STS-1
Low
225 – 450 ft
1150mVpk(typ)
High
0 – 225ft
800mVpk(typ)
Note; LBO pin is active only with E3 pin set to High(DS3/STS-1 mode).
Transmit All Ones Select
If TAOS pin is high, continuos AMI 1s are transmitted from TTIP/TRING. While this All 1s pattern is transmitted,
the input data on TPDATA/TNDATA are ignored. In Local Loopback mode (LLOOP pin is high), TAOS request
is accepted and the input data on TPDATA/TNDATA are loopback to RPDATA/RNDATA. In Remote Loopback
mode (RLOOP pin is high), TAOS request is accepted and the recoverd data is output to RPDATA/RNDATA.
Line Short Protect
If Line is short, there is no large current on the transmit output driver because that the driver is a current source
drive type.
MS0143-E-01
- 14 -
2004/01
ASAHI KASEI
[AK2504A]
Equalization
DS3/STS1
The incoming data may have the loss of cable and/or flat. Cable type and length from the cross-connect are
specified as shown in Table 8. Equalizer compensates appropriately for a nominal DSX-3/STS-1 pulse as
attenuated by 450 feet of 728A cable.
Table 8 DS3/STS-1 Cable Specification
Parameter
Specification
Cable Type
Type 728A coaxial cable (or equivalent)
Cable Length
0 – 450 feet (from DSX-3 point)
Remarks
Fig.7–(1)(2)
E3
The incoming data may have the cable loss as shown in Table 9. Equalizer compensates appropriately for a
nominal E3 pulse as attenuated by the cable.
Table 9 E3 Cable Specification
Parameter
Cable Loss
Specification
Remarks
0 – 12dB
Fig.7–(1)(2)
Equalizer Bypass
If the incoming signal is attenuated by flat loss only (zero cable loss), the internal equalizer should be bypassed
with EQDIS=1. The level of the incoming signal should satisfy the RIN input range (50mVpk - 1000mVpk for
DS3/STS-1, 90mVpk - 1200mVpk for E3).
Table 10 Equalizer Bypass Control
EQDIS
0
1
Equalizer
Enable
Bypass
Flat Loss
0 - 6dB
Cable
(1)Cable loss + Flat loss
DS3 : DSX-3
STS-1 : DSX-3
E3
: Transmitter Port
DS3 :0 – 450 feet
STS-1:0 – 450 feet
E3
:0 – 12 dB
AK2504
EQDIS
0
Equalizer enable
Flat Loss
(2) Flat loss only
Monitoring
circuit
Transmitter
AK2504
EQDIS
1
Equalizer bypass
Fig. 7 AK2504A Application
MS0143-E-01
- 15 -
2004/01
ASAHI KASEI
[AK2504A]
Clock Acquisition
If a valid input signal is assumed to be already present at the analog input, the maximum time between the
application of device power and error-free operation is typically 20 ms.
Table 11 PLL Lock Acquisition Time
(TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND** = 0V)
Power up
Input data restore
Conditions
Power : Off -> On
Input data : Valid
Power : On
Input data : Loss -> Valid
min
typ
Max
20
1.0
Units
ms
5.0
ms
**) GND=VSSP= VSSV= VSSB=VSST=VSSS=VSSD=0V
Output Jitter
Typical output jitter characteristics is shown in the table of ANALOG SPECIFICATIONS .
Jitter Transfer
Jitter transfer characteristics is shown in the table of ANALOG SPECIFICATIONS.
Jitter Tolerance
Typical jitter tolerance characteristics is shown in the table of ANALOG SPECIFICATIONS.
DS3/STS-1
Compliance with GR-499-CORE, GR-253-CORE, G.752, G.824
E3
Compliance with ITU-T G.823.
MS0143-E-01
- 16 -
2004/01
ASAHI KASEI
[AK2504A]
Loopback
AK2504A has two loopback modes, which are Remote Loopback mode and Local Loopback mode.
Each function of those is shown in Table 12 and Fig. 8.
Table 12 Loopback Function
Mode
RLOOP
LLOOP
Remote
1
0
Local
0
1
1
1
RPDATA
RNDATA
TPDATA
TNDATA
TCLK
TTIP
TRING
RPDATA
RNDATA
RCLK
Function
Transmit rate is determined by RCLK.
TPDATA/TNDATA are ignored.
Transmit rate is determined by TCLK.
TPDATA/TNDATA are ignored.
Not permitted that both RLOOP and LLOOP are high.
LOOP BACK
MUX
Remote
LoopBack
TPDATA
TNDATA
B3ZS/HDB3
PULSE SHAPER
ENCODER
OUTPUT DRIVER
B3ZS/HDB3
CLOCK&DATA
ENCODER
RECOVERY
TTIP
TRING
TCLK
RLOOP=1
LLOOP=0
RPDATA
RNDATA/BPV
RCLK
RTIP
RRING
RLOOP LLOOP
LOOP BACK
MUX
Local
LoopBack
TPDATA
TNDATA
B3ZS/HDB3
PULSE SHAPER
ENCODER
OUTPUT DRIVER
B3ZS/HDB3
CLOCK&DATA
ENCODER
RECOVERY
TTIP
TRING
TCLK
RLOOP=0
LLOOP=1
RPDATA
RNDATA/BPV
RCLK
RTIP
RRING
RLOOP LLOOP
Fig. 8 Loopback Path
MS0143-E-01
- 17 -
2004/01
ASAHI KASEI
[AK2504A]
TX and RX Output status related to NRZ, TAOS, RLOOP, LLOOP input
Table 13 TX and RX Output status
E3B
X
0
1
X
0
1
X
0
1
X
0
1
X
X
0
1
NRZ TAOS RLOO LLOO
TTIP/TRING
P
P
0
1
1
0 AMI ones
1
1
1
0 AMI ones
1
1
1
0 AMI ones
0
0
1
0 Recovered data
1
0
1
0 Recovered data
1
0
1
0 Recovered data
0
1
0
1 AMI ones
1
1
0
1 AMI ones
1
1
0
1 AMI ones
0
0
0
1 TPDATA/TNDATA
1
0
0
1 TPDATA/TNDATA(HDB3)
1
0
0
1 TPDATA/TNDATA(B3ZS)
X
1
0
0 AMI ones
0
0
0
0 TPDATA/TNDATA
1
0
0
0 TPDATA/TNDATA(HDB3)
1
0
0
0 TPDATA/TNDATA(B3ZS)
RPDATA/RNDATA
Recovered data
Recovered data(UNHDB3)
Recovered data(UNB3ZS)
Recovered data
Recovered data(UNHDB3)
Recovered data(UNB3ZS)
TPDATA/TNDATA
TPDATA/TNDATA(UNHDB3)
TPDATA/TNDATA(UNB3ZS)
TPDATA/TNDATA
TPDATA/TNDATA(UNHDB3)
TPDATA/TNDATA(UNB3ZS)
Recovered data
Recovered data
Recovered data(UNHDB3)
Recovered data(UNB3ZS)
Loss-of-Lock Detection
If the recovered clock frequency is larger than approximately 0.5% of EXCLK, RLOL alarm goes High.
External Reference Clock
An external reference clock EXCLK is used to set the frequency of the PLL. The frequency of EXCLK should
be within the ideal clock±100ppm.
Reset
AK2504A goes into RESET status if RESET input is low.
Output pins status is as follows during the low input on RESET .
RLOS
:
RLOL
:
RPDATA :
RNDATA :
RCLK
:
High
High
Low
Low
High
Test Mode
The AK2504A goes into Test Mode when TEST1 pin is High.
MS0143-E-01
- 18 -
2004/01
ASAHI KASEI
[AK2504A]
Loss of Signal
DS3/STS-1
AK2504A detects the loss of signal by analog and digital methods. Loss of Signal function in DS3/STS-1 mode is
as follows.
Analog Loss of Signal(ALOS)
Analog loss detector operates as follows.
- Analog loss detector monitors the peak level of the incoming signal.
- If the peak level falls below Alarm set threshold as shown in Table 14, output pins status is shown in the
diagram below.
Table 14 Analog Loss-of-Signal thresholds (DS3/STS-1/E3)
LOSTHR
Clear Alarm Level
Set Alarm Level
Voltage
Min. Upper
Threshold
Max. Upper
Threshold
Min. Lower
Threshold
Max. Lower
Threshold
Units
VSS
80
160
70
150
mVpk
VDD
50
110
40
100
mVpk
Notes:
- Set Alarm Level is 0.5dB lower than Clear Alarm Level.
Digital Loss of Signal(DLOS)
Digital loss detector operates as follows.
- A digital loss detector monitors consecutive 0s and 1s density in recovered data.
- RLOS is set high if 175±5 consecutive 0s is detected.
- RPDATA,RNDATA are set low if ALOS is detected.
- RLOS is set low if 33% 1s density (58 1s in 175 consecutive bits) and no consecutive 100 0s are detected.
MS0143-E-01
- 19 -
2004/01
ASAHI KASEI
[AK2504A]
Normal Operation
RCLK
: Recovered from RIN data
RPDATA : Recovered data
RNDATA : Recovered data
RLOS
: Low
175 +/- 5 bits of consecutive
0s in the incoming data
DLOS
RCLK
175bits of the incoming data
includes the following data.
1) 58bits of 1s (33% 1s density)
2) No 100bits of consecutive 0s
: Recovered from RIN data
RPDATA : Recovered data
RNDATA : Recovered data
RLOS
Peak level of
the incoming
data
: High
Set Alarm
Threshold
<
Level
Peak level of
the incoming
data
Clear Alarm
Threshold
>
Level
ALOS
RCLK
: Recovered from EXCLK
RPDATA : Low
RNDATA : Low
RLOS
: High
Fig. 9 Loss of Signal state diagram (DS3/STS-1)
MS0143-E-01
- 20 -
2004/01
ASAHI KASEI
[AK2504A]
Loss of Signal
E3
AK2504A detects the loss of signal by analog and digital methods. Loss of Signal function in E3 mode is as
follows.
-
-
-
Analog loss detector monitors the peak level of the incoming signal.
If the peak level falls below Set Alarm Threshold Level as shown in Table 15, DLOS circuit starts counting
the number of the incoming data bits as described in the following section “DLOS”.
If DLOS circuit detects consecutive 128±5 bits of the incoming data lower than Set Alarm Threshold Level,
AK2504A alarms Loss of Signal by setting RLOS high. Other output pins status is as shown in the diagram
below.
RLOS is set low if 32±5 bits of the incoming data higher than Clear Alarm Threshold Level are detected.
Normal Operation
RCLK
: Recovered from RIN input
RPDATA : Recovered data
RNDATA : Recovered data
RLOS
Peak level of
the incoming
data
: Low
Peak level of
the incoming
data
Set Alarm
Threshold
<
Level
for 128 +/- 5 consecutive bits
of the incoming data
Set Alarm
Threshold
>
Level
for 32 +/- 5 bits
of the incoming data
LOS
RCLK
: Recovered from EXCLK
RPDATA : Low
RNDATA : Low
RLOS
: High
Fig. 10 Loss of Signal state diagram (E3)
MS0143-E-01
- 21 -
2004/01
ASAHI KASEI
[AK2504A]
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Min
Max
Units
DC Supply (referenced to GND) (Note 1)
V+
-0.3
4.6
V
Input Voltage, Any Pin
Vin
GND-0.3
(V+)+0.3
V
Input Current, Any Pin (Note 2)
Iin
-
10
MA
Ambient Operating Temperature
TA
-40
85
°C
Storage Temperature
Tstg
-65
150
°C
Power Dissipation
PD
-
1
W
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Note;
1.GND=VSSV=VSSP=VSSB=VSST=VSSD=VSSS=0V
2.Transient currents of up to 100 mA will not cause SCR latch up.
RECOMMENDED OPERATING CONDITIONS
Parameter
Min
Typ
Max
Units
V+
3.0
3.3
3.6
V
TA
-40
25
85
°C
PN20
-
200
220
mA
PN20
-
210
230
mA
PN20
-
160
180
mA
DS3
44.736
- 100ppm
44.736
44.736
+ 100ppm
MHz
STS-1
51.84
- 100ppm
51.84
51.84
+ 100ppm
MHz
E3
34.368
- 100ppm
34.368
34.368
+ 100ppm
MHz
DC Supply
(referenced to GND)
Ambient Operating
Temperature
Supply Current:
DS3
STS-1
E3
EXCLK
Frequency
MS0143-E-01
Symbol
IS
Condition
- 22 -
2004/01
ASAHI KASEI
[AK2504A]
ANALOG SPECIFICATIONS
RECEIVER
(TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND = 0V)
Parameter
Condition
Jitter Transfer
3dB Bandwidth
with repetitive 100 pattern (Note 3)
Peaking
Jitter Tolerance
(Note 4)
Signal Noise Immunity
Min
Typ
Max
Units
-
205
-
kHz
-
0.05
0.1
dB
5kHz
20
Uipp
10kHz
15
Uipp
60kHz
2
Uipp
300kHz
0.6
Uipp
1MHz
0.4
Uipp
(Note 5)
-
8
12
dB
All one's pattern
-
1.4
-
nsp-p
Repetitive 1000 pattern
-
1.8
-
nsp-p
45
-
55
%
DS3/STS1
50
-
1000
mVpk
E3
90
-
1200
mVpk
DLOS detection
DS3/STS1
170
175
180
bits
Loss Detection
E3
123
128
133
bits
8
bits
Output Jitter
(Note 3)
Output Clock Duty Cycle
(Note 3)
Receiver Input Range
RIN to RPDATA Delay Time
Note; 3. Measured with repetitive input at nominal DSX-3 level(DS3/STS-1), nominal G.703 level(E3)
with (V+)=3.3V, TA=25°C
4. Typical performance is shown in Fig 11.
5. Measured with sinusoidal noise, peak amplitude of noise is 11dB down from peak amplitude of signal. The
noise frequency is 22MHz(DS3), 25MHz(STS-1), 17MHz(E3).
100
3 .2 k , 1 4 U Ip p
G .7 5 2
G R - 4 9 9 C a te g o r y II
Jitter Amplitude [UIpp]
10
G R - 4 9 9 C a te g o r y I
1
3 0 0 k , 0 .3 U Ip p
0 .1
0 .0 5 U Ip p
0 .0 1
0 .0 1
0 .1
1
10
100
1000
10000
J itte r F r e q u e n c y [ k H z ]
Fig. 11 Jitter Tolerance
MS0143-E-01
- 23 -
2004/01
ASAHI KASEI
TRANSMITTER
[AK2504A]
ANALOG SPECIFICATIONS
(TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND = 0V)
Parameter
Condition
Transmitter amplitude
DS3/STS1
(Note 6)
Min
Typ
Max
Units
LBO=1
700
800
900
mVpk
LBO=0
1050
1150
1250
mVpk
920
1000
1080
mVpk
E3
Note; 6. Measured at the line side of the transformer.
DIGITAL CHARACTERISTICS
(TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND = 0V)
Parameter
Symbol
Min
Typ
Max
Units
High-Level Input Voltage
VIH
(V+) x 0.7
-
(V+)
V
Low-Level Input Voltage
VIL
GND
-
0.5
V
High-Level Output Voltage IOUT=-40µA
VOH
(V+) x 0.8
-
(V+)
V
Low-Level Output Voltage
VOL
GND
-
0.4
V
±10
µA
Input Leakage Current
IOUT=1.6mA (Note 7)
IOUT=0.4mA (Note 8)
(Note 9)
Note; 7. RCLK, RPDATA, RNDATA
8. RLOS, RLOL, TEST4, TEST7
9. Except for RESET
MS0143-E-01
- 24 -
2004/01
ASAHI KASEI
[AK2504A]
RECEIVER SWITCHING SPECIFICATIONS
(TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND = 0V; Input: Logic 0 = 0V, Logic 1 = V+ )
Parameter
Symbol
Min
Typ
Max
Units
RCLK Pulse Width
DS3
Tpwh
(Note 10, 11) Tpwl
10.1
10.1
11.177
11.177
12.2
12.2
ns
ns
RCLK Pulse Width
STS-1
Tpwh
(Note 12, 11) Tpwl
8.7
8.7
9.645
9.645
10.6
10.6
ns
ns
RCLK Pulse Width
E3
Tpwh
(Note 13, 11) Tpwl
13.1
13.1
14.548
14.548
16.0
16.0
ns
ns
45
-
55
%
EXCLK Duty Cycle (EXCLK Min Rise/Fall time : 5ns)
Rise Time, RCLK
(Note 11)
tr
-
-
3.5
ns
Fall Time, RCLK
(Note 11)
tf
-
-
3.5
ns
0
-
3.5
ns
Delay Time: RCLK high to RPDATA/RNDATA (Note 14) Tdcrd
TRANSMITTER SWITCHING SPECIFICATIONS
(TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND = 0V; Input: Logic 0 = 0V, Logic 1 = V+ )
Parameter
Symbol
TCLK Duty Cycle (TCLK Min Rise/Fall time : 5ns)
Min
Typ
Max
Units
30
-
70
%
Rise Time, TCLK
(Note 11)
tr
-
-
3.5
ns
Fall Time, TCLK
(Note 11)
tf
-
-
3.5
ns
Setup Time, TPDATA/TNDATA to TCLK Falling
Tstdc
4
-
-
ns
Hold Time, TPDATA/TNDATA to TCLK Falling
Thtdc
5
-
-
ns
Note;
10.
11.
12.
13.
14.
MS0143-E-01
Assumes PLL is locked to 44.736 MHz signal.
The sum of the pulse widths must always meet the frequency specifications.
Assumes PLL is locked to 51.84 MHz signal
Assumes PLL is locked to 34.368MHz signal.
Load cap = 15pF.
- 25 -
2004/01
ASAHI KASEI
[AK2504A]
tr
tf
90%
90%
10%
RCLK
10%
Fig. 12 Signal Rise and Fall Characteristics
t pwh
t pwl
t dcrd
RCLK
RPDATA
RNDATA
Fig. 13 Recovered Clock and Data Switching Characteristics
t pwh1
VDD/2
EXCLK
t pw
Fig. 14 EXCLK Duty Cycle Requirements
TCLK
t sdc
t hdc
TPDATA
TNDATA
Fig. 15 Transmitter Switching Characteristics
MS0143-E-01
- 26 -
2004/01
ASAHI KASEI
[AK2504A]
Application Circuit Example
Note :
Recommended Diode :
Leave the following NC pins open.
Pin 1,2,15,16,17,18,31,32,33,34,47,48,49,50,63,64.
Any diode with V(forward) = 0.58V to 0.89V
for I(forward)=10mA in all temperature range
can be used. e.g. 1SS184, 1SS181
3.3V
FRAMER
CONTROL
LOGIC
23
TCLK
24
TPDATA
25
TNDATA
20
RCLK
CLOCK
SOURCE
TRING
AK2504A
RPDATA
22
RNDATA
6
TCKPOL
41
3
RCKPOL
TAOS
14
RLOL
VSST
RTIP
RRING
39 Ω
38
0.1 uF
37.4 Ω 1:1
45
37.4 Ω
0.01 uF
RLOS
LOSTHR
60
LBO
51
EQDIS
RESET
RLOOP
VDDV
52
VSSV
53
VDDP
4
VSSP
5
VDDB
54
VSSB
57
VDDT
36
10
LLOOP
43
E3
46
TEST1
9
TEST2
27
TEST3
VDDD
12
TEST4, TEST7
VSSD
13
VSSS
11
TEST5
TEST6
7
EXCLK
TCAP1
30
0.1uF
3.3V
59
0.01 uF
42
58
COAX
44
VDDA
62
19
150 nH
37
NRZ
35
26,40
1CT : 1
39 39 Ω
75 Ω
21
61
8
Open
TTIP
0.01 uF
0.01 uF
0.01 uF
0.01 uF
VSST
29
0.01 uF
Recommended Transformer :
TCAP2
28
0.1uF
PLA IREF
56
RPLA
55
Maker
Product No.
Ratio
TDK
WBTRID2.5-J004C002
1CT:1
TDK
WBTRID2.5-0340N
1:1
4.7 kΩ±1%
RPLA: 1.33kΩ ±1% for DS3/STS-1, 1.27kΩ ±1% for E3
NOTE) If the power of transmit signal is larger than the requirement,
the power can be reduced by increasing the value of RPLA.
MS0143-E-01
- 27 -
2004/01
ASAHI KASEI
[AK2504A]
Marking
- 64pin LQFP
(1) Pin #1 indication
(2) Date Code: 7digits XXXXYZZ
(3)Marketing Code: AK2504A
(4)AKM Logo
AKM
AK2504A
XXXXYZZ
MS0143-E-01
- 28 -
2004/01
ASAHI KASEI
[AK2504A]
Outline Dimensions
12.0±0.3
10.0
33
49
32
64
17
10.0
12.0±0.3
48
16
1
0.10
0°-10°
1.40
0.21±0.05
M
MS0143-E-01
0.10
0.45±0.2
- 29 -
0.10±0.10
0.17±0.05
1.0
1.70MAX
0.5
2004/01
ASAHI KASEI
[AK2504A]
IMPORTANT NOTICE
These products and their specifications are subject to change without notice.
Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd.
(AKM) sales office or authorized distributor concerning their current status.
AKM assumes no liability for infringement of any patent, intellectual property, or other
right in the application or use of any information contained herein.
Any export of these products, or devices or systems containing them, may require an
export license or other official approval under the law and regulations of the country of
export pertaining to customs and tariffs, currency exchange, or strategic materials.
AKM products are neither intended nor authorized for use as critical components in any
safety, life support, or other hazard related device or system, and AKM assumes no
responsibility relating to any such use, except with the express written consent of the
Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or
other fields, in which its failure to function or perform may reasonably be expected to
result in loss of life or in significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or
effectiveness of the device or system containing it, and which must therefore meet very
high standards of performance and reliability.
It is the responsibility of the buyer or distributor of an AKM product who distributes,
disposes of, or otherwise places the product with a third party to notify that party in advance
of the above content and conditions, and the buyer or distributor agrees to assume any and
all responsibility and liability for and hold AKM harmless from any and all claims arising
from the use of said product in the absence of such notification.
MS0143-E-01
- 30 -
2004/01