ASAHI KASEI [AK4631] AK4631 16-Bit ∆Σ Mono CODEC with ALC & MIC/SPK-AMP GENERAL DESCRIPTION The AK4631 is a 16-bit mono CODEC with Microphone-Amplifier and Speaker-Amplifier. Input circuits include a Microphone-Amplifier and an ALC (Automatic Level Control) circuit. Output circuits include a Speaker-Amplifier and Mono Line Output. The AK4631 suits a moving picture of Digital Still Camera and etc. This speaker-Amplifier supports a Piezo Speaker. The AK4631 is housed in a space-saving 28-pin QFN package. FEATURE 1. 16-Bit Delta-Sigma Mono CODEC 2. Recording Function • 1ch Mono Input • 1st MIC Amplifier: 0dB, 20dB, 26dB or 32dB • 2nd Amplifier with ALC: -8dB ∼ +27.5dB, 0.5dB Step • ADC Performance: S/(N+D): 80dB, DR, S/N: 85dB 3. Playback Function • Digital Volume: +12dB ∼ -115dB, 0.5dB Step, Mute • Mono Line Output Performance: S/(N+D): 85dB, S/N: 93dB • Mono Speaker-Amp - Speaker-Amp Performance: S/(N+D): 50dB, S/N: 90dB (240mW@ 8Ω) - BTL Output - ALC (Automatic Level Control) Circuit - Output Power: 250mW @ 8Ω, SVDD=3.3V 3.0Vrms@SVDD=5V • Beep Input 4. Power Management 5. Flexible PLL Mode: • Frequencies: 11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin) 1fs (FCK pin) 16fs, 32fs or 64fs (BICK pin) 6. EXT Mode: • Frequencies: 256fs, 512fs or 1024fs (MCKI pin) 7. Sampling Rate: • PLL Slave Mode (FCK pin) : 7.35kHz ~ 26kHz • PLL Slave Mode (BICK pin) : 7.35kHz ~ 48kHz • PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz • PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz • EXT Slave Mode: 7.35kHz ~ 48kHz (256fs), 7.35kHz ~ 26kHz (512fs), 7.35kHz ~ 13kHz (1024fs) 8. Output Master Clock Frequency: 256fs 9. Serial µP Interface: 3-wire 10. Master / Slave Mode MS0317-E-01 2004/11 -1- ASAHI KASEI [AK4631] 11. Audio Interface Format: MSB First, 2’s compliment • ADC: DSP Mode, 16bit MSB justified, I2S • DAC: DSP Mode, 16bit MSB justified, 16bit LSB justified, I2S 12. Ta = -10 ∼ 70°C 13. Power Supply • CODEC: 2.6 ∼ 3.6V (typ. 3.3V) • Speaker-Amp: 2.6 ∼ 5.25V (typ. 3.3V/5.0V) 14. Power Supply Current: 16mA (All Power ON) 15. Package: 28pin QFN 16. Pin and Register Compatible with AK4536/AK4630 Block Diagram AVSS AVDD MICOUT MPI AIN PMMIC MIC Power Supply PMADC ALC1 (IPGA) MIC MIC-AMP 0dB or 20dB or 26dB or 32dB ADC HPF PDN Audio ALC1A PMAO FCK Interface PMDAC BICK DACA DAC AOUT BEEPA DACM SVDD DVOL SDTO ALC1M SDTI SVSS DSP and uP PMSPK SPP SPKAMP MIX ALC2 CSN Control Register SPN CCLK CDTI PMBP PMPLL MCKO PLL MCKI VCOM BEEP MIN MOUT VCOC DVSS DVDD Figure 1. AK4631 Block Diagram MS0317-E-01 2004/11 -2- ASAHI KASEI [AK4631] Ordering Guide AK4631VN AKD4631 −10 ∼ +70°C 28pin QFN (0.5mm pitch) Evaluation board for AK4631 MPI MIC MICOUT AIN BEEP AOUT MOUT 28 27 26 25 24 23 22 Pin Layout VCOM 1 21 MIN AVSS 2 20 SVSS AVDD 3 19 SVDD VCOC 4 18 SPN PDN 5 17 SPP CSN 6 16 MCKO CCLK 7 15 MCKI 8 9 10 11 12 13 14 CDTI SDTI SDTO FCK BICK DVDD DVSS Top View MS0317-E-01 2004/11 -3- ASAHI KASEI [AK4631] Compare AK4536/AK4630 with AK4631 In the case of using the AK4536 or the AK4630, it will be possible to change to the AK4631 from the AK4536 or the AK4630 without modifying the software and the design circuit except the items shown by shading in the following compatibility. 1. Function Function Dynamic Speaker AVDD, DVDD, SVDD SPK-Amp Output Volage at ALC2 OFF and AVDD=DVDD=SVDD=3.3V SPK-Amp Output Volage At ALC2 ON and AVDD=DVDD=SVDD=3.3V Piezo Speaker AVDD, DVDD SVDD SPK-Amp Output Voltage Others X’tal Oscillator MCKI pin AC Coupling Input Master Clock Output Reference Value at ALC2 Recovery Operation Sampling Rate MIC Amp Gain Soft Transition Time of Output Digital Volume Master Clock for PLL Mute Function of AOUT Output of AOUT pin in power down mode BEEP Æ SPP/SPN Gain (External Input Resistance = 20kΩ) R and C of VCOC pin at PLL reference clock = FCK pin. Audio I/F Format at PLL Master Mode Audio I/F Format at PLL Slave Mode FCK Pulse width “H” at PLL Master Mode The size of the black part at four corners in package diagram The minimum height of package The thickness of package except lead frame AK4536VN AK4630VN AK4631VN 2.4V ∼ 3.6V 2 mode 150mW@8Ω 250mW@8Ω 2.4V ∼ 3.6V 2 mode 150mW@8Ω 250mW@8Ω 2 mode 150mW@8Ω 250mW@8Ω 2 mode 150mW@8Ω 250mW@8Ω Not Available Not Available 2.6V ∼ 3.6V 2.6V ∼ 5.25V 4 mode Yes No No Fixed : +18dB No No Yes Fixed : +18dB No No Yes Variable : +19.5dB∼-14.0dB 7.35kHz ∼ 26kHz 0dB/+20dB 1061/fs 7.35kHz ∼ 26kHz 0dB/+20dB 1061/fs 7.35kHz ∼ 48kHz 0dB/+20dB/+26dB/+32dB 1061/fs or 256/fs 11.2896MHz, 12MHz, 12.288MHz 11.2896MHz, 12MHz, 12.288MHz No Hi-Z No Hi-Z 11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz Yes AVSS +6dB at SPKG bit = “0” +6dB at SPKG bit = “0” +7.84 dB at SPKG1-0 bits = “00” 10kΩ + 470nF 10kΩ + 470nF 6.8kΩ + 220nF Only DSP Mode All Modes All Modes Only DSP Mode All Modes All Modes 1/tBCK 50% duty 50% duty 0.55 ± 0.20 mm 0.55 ± 0.20 mm 0.70 mm 0.70 mm No Spec No Spec 0.2 +0.10 -0.20 mm 0.80 mm 0.78 +0.17 -0.28 MS0317-E-01 2.6V ∼ 3.6V 4 mode 150mW@8Ω 250mW@8Ω +4.2dB from 250mW mode +6.2dB from 250mW mode 2 mode 150mW@8Ω 240mW@8Ω 2004/11 -4- ASAHI KASEI [AK4631] Function AK4536VN AK4630VN AK4631VN Mono Line Output Characteristics D-Range (typ) 95dB 95dB 93dB S/N(typ) 95dB 95dB 93dB Speaker-Amp Characteristics Output Voltage (at -0.5dBFS) SPKG1-0 bits = “00” (typ) 2.92Vpp 2.92Vpp 3.09Vpp SPKG1-0 bits = “01” (typ) 3.78Vpp 3.78Vpp 3.92Vpp S/(N+D) (at 240mW) 50dB SPKG1-0 bits =“01” (typ) S/(N+D) (at 250mW) 50dB 50dB 20dB SPKG1-0 bits =“01” (typ) ADC Digital Filter (HPF) Characteristics: fs=8kHz Frequency Response -3.0dB 1.25Hz 1.25 Hz 0.62 Hz (typ) -0.5dB 3.56 Hz 3.56 Hz 1.81 Hz -0.1dB 8.14 Hz 8.14 Hz 3.99 Hz Note 1. The black part of the AK4631 is wider than that of the AK4536. Check if this black parts are open without contacting trace line and GND. 2. Pin Layout Pin No. # 15 # 16 AK4536VN MCKI / XTI XTO AK4630VN MCKI MCKO AK4631VN MCKI MCKO MS0317-E-01 2004/11 -5- ASAHI KASEI [AK4631] 3. Register (1) Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Input PGA Control Digital Volume Control ALC2 Mode Control D7 0 0 SPPS 0 PLL3 0 DVTM 0 0 0 DVOL7 0 Bold D6 D5 D4 D3 D2 PMVCM PMBP PMSPK PMAO PMDAC 0 0 0 M/S MCKPD BEEPS ALC2S DACA DACM MPWR SPKG0 BEEPA AOPSN MGAIN1 SPKG1 PLL2 PLL1 PLL0 BCKO1 BCKO0 0 MSBS BCKP FS2 FS3 ROTM ZTM1 ZTM0 WTM1 WTM0 ALC2 ALC1 ZELM LMAT1 LMAT0 REF6 REF5 REF4 REF3 REF2 IPGA6 IPGA5 IPGA4 IPGA3 IPGA2 DVOL6 DVOL5 DVOL4 DVOL3 DVOL2 0 RFS5 RFS4 RFS3 RFS2 Register bits changed from the AK4536 or the AK4630. Register bits added from the AK4536 and the AK4630. D1 PMMIC MCKO MICAD ALC1M DIF1 FS1 LTM1 RATT REF1 IPGA1 DVOL1 RFS1 D0 PMADC PMPLL MGAIN0 ALC1A DIF0 FS0 LTM0 LMTH REF0 IPGA0 DVOL0 RFS0 (2) MCKO bit (Addr = 01H, D1 bit) Register Addr = 01H, D1 AK4536 PMXTL bit AK4630/AK4631 MCKO bit 0: “L” output (Default) 1: 256fs output (3) FS1-0 bits (Addr = 05H, D1-0 bits) When PLL reference clock input is FCK or BICK pin, the setting of FS3-0 bits are changed as shown in the following table. Sampling Frequency Range Mode FS3 bit FS2 bit FS1 bit FS0 bit AK4536/AK4630 AK4631 0 Don’t care 0 0 0 7.35kHz ≤ fs ≤ 10kHz 7.35kHz ≤ fs ≤ 8kHz 0 Don’t care 1 1 0 10kHz < fs ≤ 14kHz 8kHz < fs ≤ 12kHz 0 Don’t care 0 2 1 14kHz < fs ≤ 20kHz 12kHz < fs ≤ 16kHz 0 Don’t care 1 3 1 20kHz < fs ≤ 26kHz 16kHz < fs ≤ 24kHz 1 Don’t care 0 N/A 6 1 24kHz < fs ≤ 32kHz 1 Don’t care 1 N/A 7 1 32kHz < fs ≤ 48kHz Others Others N/A N/A When the sampling rate is 8kHz, 11.025kHz, 16kHz, 22.05kHz and 24kHz, the FS3-0 bits setting of the AK4631 is same as that of the AK4536 and the AK4630. MS0317-E-01 2004/11 -6- ASAHI KASEI [AK4631] PIN/FUNCTION No. Pin Name I/O 1 VCOM O 2 3 AVSS AVDD - 4 VCOC O 5 PDN I 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CSN CCLK CDTI SDTI SDTO FCK BICK DVDD DVSS MCKI MCKO SPP SPN SVDD SVSS MIN MOUT AOUT BEEP AIN MICOUT MIC MPI I I I I O I/O I/O I O O O I O O I I O I O Function Common Voltage Output Pin, 0.45 x AVDD Bias voltage of ADC inputs and DAC outputs. Analog Ground Pin Analog Power Supply Pin Output Pin for Loop Filter of PLL Circuit This pin should be connected to AVSS with one resistor and capacitor in series. Power-Down Mode Pin “H”: Power up, “L”: Power down reset and initialize the control register. Chip Select Pin Control Data Clock Pin Control Data Input Pin Audio Serial Data Input Pin Audio Serial Data Output Pin Frame Clock Pin Audio Serial Data Clock Pin Digital Power Supply Pin Digital Ground Pin External Master Clock Input Pin (Internal Pull Down 25kΩ@PDN pin =“L”) Master Clock Output Pin Speaker Amp Positive Output Pin Speaker Amp Negative Output Pin Speaker Amp Power Supply Pin Speaker Amp Ground Pin ALC2 Input Pin Mono Analog Output Pin Mono Line Output Pin Beep Signal Input Pin IPGA (ALC1) Input Pin Microphone Analog Output Pin Microphone Input Pin (Mono Input) MIC Power Supply Pin for Microphone Note: All input pins except analog input pins (MIC, AIN, MIN and BEEP pins) should not be left floating. Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Pin Name Analog Input MIC, AIN, BEEP, MIN Analog Output MICOUT, MPI, AOUT, MOUT, SPP, SPN MCKI, SDTI, FCK(when M/S bit = “0”), BICK(when M/S bit = “0”) MCKO, SDTO, FCK(when M/S bit = “1”), BICK(when M/S bit = “1”) Digital Input Digital Output MS0317-E-01 Setting These pins should be open and each path should be switched off. These pins should be open. These pins should be connected to DVSS. These pins should be open. 2004/11 -7- ASAHI KASEI [AK4631] ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS, SVSS=0V; Note 2) Parameter Power Supplies: Analog Digital Speaker-Amp |AVSS – DVSS| (Note 3) |AVSS – SVSS| (Note 3) Input Current, Any Pin Except Supplies Analog Input Voltage Digital Input Voltage Ambient Temperature (powered applied) Storage Temperature Maximum Power Dissipation (Note 4) Symbol AVDD DVDD SVDD ∆GND1 ∆GND2 IIN VINA VIND Ta Tstg Pd min −0.3 −0.3 −0.3 −0.3 −0.3 −10 −65 - max 6.0 6.0 6.0 0.3 0.3 ±10 AVDD+0.3 DVDD+0.3 70 150 520 Units V V V V V mA V V °C °C mW Note 2. All voltages with respect to ground. Note 3. AVSS, DVSS and SVSS must be connected to the same analog ground plane. Note 4. In case that PCB wiring density is 100%. This power is the AK4631 internal dissipation that does not include power of externally connected speaker. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS, SVSS=0V; Note 2) Parameter Symbol min typ Power Supplies Analog AVDD 2.6 3.3 (Note 5) Digital DVDD 2.6 3.3 Speaker-Amp (Note 6) SVDD 2.6 3.3 / 5.0 Difference AVDD-DVDD -0.3 0 max 3.6 3.6 5.25 0.3 Units V V V V Note 2. All voltages with respect to ground Note 5. The power up sequence between AVDD, DVDD and SVDD is not critical. When the power supplies are partially powered OFF, the AK4631 must be reset by bringing PDN pin “L” after these power supplies are powered ON again. Note 6. SVDD = 2.6 ∼ 3.6V when 8Ω dynamic speaker is connected to the AK4631. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0317-E-01 2004/11 -8- ASAHI KASEI [AK4631] ANALOG CHRACTERISTICS (Ta=25°C; AVDD, DVDD, SVDD=3.3V; AVSS=DVSS=SVSS=0V; fs=8kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 3.4kHz; EXT Slave Mode; unless otherwise specified) min typ max Units Parameter MIC Amplifier Input Resistance 20 30 40 kΩ Gain (MGAIN1-0 bits = “00”) 0 dB (MGAIN1-0 bits = “01”) 20 dB (MGAIN1-0 bits = “10”) 26 dB (MGAIN1-0 bits = “11”) 32 dB MIC Power Supply: MPI pin Output Voltage (Note 7) 2.22 2.47 2.72 V Load Resistance 2 kΩ Load Capacitance 30 pF Input PGA Characteristics: Input Resistance (Note 8) 5 10 15 kΩ Step Size 0.05 0.5 0.9 dB Gain Control Range +27.5 dB −8 ADC Analog Input Characteristics: MIC Æ IPGA Æ ADC, MIC Gain=20dB, IPGA=0dB, ALC1=OFF Resolution 16 Bits Input Voltage (MIC Gain=20dB, Note 9) 0.168 0.198 0.228 Vpp 68 80 dB S/(N+D) (−1dBFS) (Note 10) 75 85 dB D-Range (−60dBFS) S/N 75 85 dB DAC Characteristics: Resolution 16 Bits Mono Line Output Characteristics: AOUT pin, DAC → AOUT, RL=10kΩ 1.78 1.98 2.18 Vpp Output Voltage (Note 11) 73 85 dB S/(N+D) (0dBFS) (Note 10) 83 93 dB D-Range (-60dBFS) 83 93 dB S/N 10 Load Resistance kΩ 30 pF Load Capacitance Speaker-Amp Characteristics: SPP/SPN pins, MIN Æ SPP/SPN, ALC2=OFF, RL=8Ω, BTL, SVDD=3.3V Output Voltage SPKG1-0 bits = “00” (-0.5dBFS) 2.47 3.09 3.71 Vpp (Note 12) SPKG1-0 bits = “01” (-0.5dBFS) 3.10 4.00 4.80 Vpp SPKG1-0 bits =“00” (at 150mW) 40 60 dB S/(N+D) SPKG1-0 bits =“01” (at 240mW) 20 50 dB SPKG1-0 bits =“01” (at 250mW) 20 dB 80 90 dB S/N (Note 14) Load Resistance 8 Ω 30 pF Load Capacitance Speaker-Amp Characteristics: MIN Æ SPP/SPN pins, ALC2=OFF, CL=3µF, Rserial=10Ω x 2, BTL, SVDD=5.0V Output Voltage SPKG1-0 bits = “10” (0dBFS) 6.72 Vpp (Note 12) SPKG1-0 bits = “11” (0dBFS) 6.80 8.50 10.20 Vpp S/(N+D) (Note 12) SPKG1-0 bits = “10” (0dBFS) 60 dB (Note 13) SPKG1-0 bits = “11” (0dBFS) 20 50 dB 80 80 90 S/N (Note 13) (Note 14) Load Impedance (Note 15) 50 Ω 3 Load Capacitance µF MS0317-E-01 2004/11 -9- ASAHI KASEI [AK4631] min typ Parameter BEEP Input: BEEP pin, External Input Resistance= 20kΩ Maximum Input Voltage (Note 16) 1.98 Output Voltage (Input Voltage=0.6Vpp) 0.74 1.48 BEEP Æ SPP/SPN (SPKG1-0 bits = “00”) 0.3 0.6 BEEP Æ AOUT Mono Input: MIN pin 2.18 Maximum Input Voltage (Note 17) 12 24 Input Resistance (Note 18) Mono Output: MOUT pin, DAC→ MOUT 1.78 1.98 Output Voltage (Note 19) Load Resistance 10 Load Capacitance Power Supplies Power Up (PDN pin = “H”) All Circuit Power-up: (Note 20) AVDD+DVDD fs=8kHz 9 fs=48kHz 11.5 SVDD: Speaker-Amp Normal Operation (SPPS bit = “1”, No Output) SVDD=3.3V 7 SVDD=5.0V 9 Power Down (PDN pin = “L”) 10 AVDD+DVDD+SVDD max Units - Vpp 2.22 0.9 Vpp Vpp 36 Vpp kΩ 2.18 30 Vpp kΩ pF 17.5 mA mA 27 mA mA 200 µA Note 7. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ) Note 8. When IPGA Gain is changed, this typical value changes between 8kΩ and 11kΩ. Note 9. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ) Note 10. When a PLL reference clock is FCK pin in PLL Slave Mode, S/(N+D) is 77dB (typ). Note 11. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ) Note 12. The full scale of Input signal of MIN pin is 1.98Vpp. Note 13. In case of measuring between SPP pin and SPN pin directly. Note 14. There are no relations with the setup of SPKG1-0 bits, and it is the same value. Note 15. Load impedance is total impedance of series resistance and piezo speaker impedance at 1kHz in Figure 34. Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 10Ω or more series resistors should be connected at both SPP and SPN pins, respectively. Note 16. The maximum input voltage of the BEEP is proportional to AVDD voltage and external input resistance(Rin). Vout = 0.6 x AVDD x Rin/20kΩ(max). Note 17. Maximum Input Voltage is proportional to AVDD voltage. Vin = 0.66 x AVDD (max) Note 18. When ALC2 Gain is changed, this typical value changes between 22kΩ and 26kΩ. Note 19. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ) Note 20. PLL Master Mode (MCKI = 12.288MHz) and PMMIC = PMADC = PMDAC = PMSPK = PMVCM = PMPLL = MCKO = PMAO = PMBP = M/S = “1”. And output current from MPI pin is 0mA. When the AK4631 is EXT mode (PMPLL = MCKO = M/S = “0”), “AVDD+DVDD” is typically 7mA@fs=8kHz, 9.5mA@fs=48kHz). MS0317-E-01 2004/11 - 10 - ASAHI KASEI [AK4631] FILTER CHRACTERISTICS (Ta = 25°C; AVDD, DVDD = 2.6 ∼ 3.6V; SVDD =2.6 ∼ 5.25V; fs=8kHz) Parameter Symbol min ADC Digital Filter (Decimation LPF): ±0.16dB PB 0 Passband (Note 21) −0.66dB −1.1dB −6.9dB Stopband (Note 21) SB 4.7 Passband Ripple PR Stopband Attenuation SA 73 Group Delay (Note 22) GD Group Delay Distortion ∆GD ADC Digital Filter (HPF): Frequency Response (Note 21) −3.0dB FR −0.5dB −0.1dB DAC Digital Filter: Passband (Note 21) ±0.1dB PB 0 −0.7dB −6.0dB Stopband (Note 21) SB 4.6 Passband Ripple PR Stopband Attenuation SA 59 Group Delay (Note 22) GD DAC Digital Filter + Analog Filter: Frequency Response: 0 ∼ 3.4kHz FR typ max Units 3.5 3.6 4.0 3.0 - kHz kHz kHz kHz kHz dB dB 1/fs µs ±0.1 17.1 0 0.62 1.81 3.99 - Hz Hz Hz 3.6 4.0 3.6 - kHz kHz 16.8 kHz dB dB 1/fs ±1.0 dB ±0.01 Note 21. The passband and stopband frequencies are proportional to fs (system sampling rate). For example, ADC is PB=0.45*fs (@-1.1dB). A reference of frequency response is 1kHz. Note 22. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 16-bit data of a channel from the input register to the output register of the ADC. This time includes the group delay of the HPF. For the DAC, this time is from setting the 16-bit data of a channel from the input register to the output of analog signal. DC CHRACTERISTICS (Ta = 25°C; AVDD, DVDD = 2.6 ∼ 3.6V; SVDD =2.6 ∼ 5.25V) Parameter Symbol min High-Level Input Voltage VIH 70%DVDD Low-Level Input Voltage VIL High-Level Output Voltage (Iout=−80µA) VOH DVDD−0.4 Low-Level Output Voltage (Iout= 80µA) VOL Input Leakage Current Iin - MS0317-E-01 typ - max 30%DVDD 0.4 ±10 Units V V V V µA 2004/11 - 11 - ASAHI KASEI [AK4631] SWITING CHARACTERISTICS (Ta = 25°C; AVDD, DVDD = 2.6 ∼ 3.6V; SVDD =2.6 ∼ 5.25V; CL=20pF) Parameter Symbol min typ PLL Master Mode (PLL Reference Clock = MCKI pin) (Figure 2) MCKI Input: Frequency fCLK 11.2896 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK MCKO Output: Frequency fMCK 256 x fFCK Duty Cycle except fs=29.4kHz, 32kHz dMCK 40 50 fs=29.4kHz, 32kHz (Note 23) dMCK 33 FCK Output: Frequency fFCK 8 Duty Cycle dFCK 50 BICK: Period (BCKO1-0 = “00”) tBCK 1/16fFCK (BCKO1-0 = “01”) tBCK 1/32fFCK (BCKO1-0 = “10”) tBCK 1/64fFCK Duty Cycle dBCK 50 Audio Interface Timing DSP Mode: (Figure 3, Figure 4) 0.5 x tBCK 0.5 x tBCK -40 tDBF FCK “↑” to BICK “↑” (Note 24) 0.5 x tBCK 0.5 x tBCK -40 tDBF FCK “↑” to BICK “↓” (Note 25) -70 tBSD BICK “↑” to SDTO (BCKP = “0”) -70 tBSD BICK “↓” to SDTO (BCKP = “1”) 50 tSDH SDTI Hold Time 50 tSDS SDTI Setup Time Except DSP Mode: (Figure 5) -40 tBFCK BICK “↓” to FCK Edge -70 tFSD FCK to SDTO (MSB) (Except I2S mode) -70 tBSD BICK “↓” to SDTO 50 tSDH SDTI Hold Time 50 tSDS SDTI Setup Time MS0317-E-01 max Units 27.0 MHz ns ns 60 48 kHz % % kHz % ns ns ns % 0.5 x tBCK + 40 0.5 x tBCK +40 70 70 ns ns ns ns ns ns 40 70 ns ns 70 ns ns ns 2004/11 - 12 - ASAHI KASEI [AK4631] Parameter Symbol min PLL Slave Mode (PLL Reference Clock: FCK pin) (Figure 6, Figure 7) FCK: Frequency DSP Mode: Pulse Width High Except DSP Mode: Duty Cycle BICK: Period Pulse Width Low Pulse Width High fFCK tFCKH duty tBCK tBCKL tBCKH 7.35 tBCK-60 45 1/64fFCK 240 240 typ max Units 8 26 1/fFCK-tBFCK 55 1/16fFCK kHz ns % ns ns ns 8 48 1/fFCK-tBFCK 55 kHz ns % ns ns ns ns ns 27.0 MHz ns ns PLL Slave Mode (PLL Reference Clock: BICK pin) (Figure 6, Figure 7) FCK: Frequency DSP Mode: Pulse width High Except DSP Mode: Duty Cycle BICK: Period (PLL3-0 = “0001”) (PLL3-0 = “0010”) (PLL3-0 = “0011”) Pulse Width Low Pulse Width High fFCK tFCKH duty tBCK tBCK tBCK tBCKL tBCKH 7.35 tBCK-60 45 1/16fFCK 1/32fFCK 1/64fFCK 0.4 x tBCK 0.4 x tBCK PLL Slave Mode (PLL Reference Clock: MCKI pin) (Figure 8) MCKI Input: Frequency Pulse Width Low Pulse Width High MCKO Output: Frequency Duty Cycle except fs=29.4kHz, 32kHz fs=29.4kHz, 32kHz (Note 23) FCK: Frequency DSP Mode: Pulse width High Except DSP Mode: Duty Cycle BICK: Period Pulse Width Low Pulse Width High Audio Interface Timing DSP Mode: (Figure 9,Figure 10) FCK “↑” to BICK “↑” (Note 24) FCK “↑” to BICK “↓” (Note 25) BICK “↑” to FCK “↑” (Note 24) BICK “↓” to FCK “↑” (Note 25) BICK “↑” to SDTO (BCKP = “0”) BICK “↓” to SDTO (BCKP = “1”) SDTI Hold Time SDTI Setup Time Except DSP Mode: (Figure 12) FCK Edge to BICK “↑” (Note 26) BICK “↑” to FCK Edge (Note 26) FCK to SDTO (MSB) (Except I2S mode) BICK “↓” to SDTO SDTI Hold Time SDTI Setup Time fCLK fCLKL fCLKH fMCK dMCK dMCK fFCK tFCKH duty tBCK tBCKL tBCKH 11.2896 0.4/fCLK 0.4/fCLK 40 8 tBCK-60 45 1/64fFCK 0.4 x tBCK 0.4 x tBCK tFCKB tFCKB tBFCK tBFCK tBSD tBSD tSDH tSDS 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK tFCKB tBFCK tFSD tBSD tSDH tSDS 50 50 MS0317-E-01 256 x fFCK 50 33 60 48 1/fFCK-tBFCK 55 1/16fFCK 80 80 50 50 80 80 50 50 kHz % % kHz ns % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2004/11 - 13 - ASAHI KASEI [AK4631] Parameter EXT Slave Mode (Figure 11) Symbol min typ Max Units MCKI Frequency: 256fs 512fs 1024fs Pulse Width Low Pulse Width High FCK Frequency (MCKI = 256fs) (MCKI = 512fs) (MCKI = 1024fs) Duty Cycle BICK Period BICK Pulse Width Low Pulse Width High fCLK fCLK fCLK tCLKL tCLKH fFCK fFCK fFCK duty tBCK tBCKL tBCKH 1.8816 3.7632 7.5264 0.4/fCLK 0.4/fCLK 7.35 7.35 7.35 45 312.5 130 130 2.048 4.096 8.192 12.288 13.312 13.312 MHz MHz MHz ns ns 8 8 8 48 26 13 55 Audio Interface Timing (Figure 12) FCK Edge to BICK “↑” (Note 26) BICK “↑” to FCK Edge (Note 26) FCK to SDTO (MSB) (Except I2S mode) BICK “↓” to SDTO SDTI Hold Time SDTI Setup Time tFCKB tBFCK tFSD tBSD tSDH tSDS 50 50 kHz kHz % ns ns ns 80 80 ns ns ns ns ns ns max Units 50 50 Note 23. Duty Cycle = (the width of “L” ) / (the period of clock) × 100 Note 24. MSBS, BCKP bits = “00” or “11” Note 25. MSBS, BCKP bits = “01” or “10” Note 26. BICK rising edge must not occur at the same time as FCK edge. Parameter Control Interface Timing: CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” Reset Timing PDN Pulse Width PMADC “↑” to SDTO valid (Note 27) (Note 28) Symbol min typ tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 40 40 150 150 50 ns ns ns ns ns ns ns ns tPD tPDV 150 ns 1/fs 1059 Note 27. The AK4631 can be reset by the PDN pin = “L” Note 28. This is the count of FCK “↑” from the PMADC = “1”. MS0317-E-01 2004/11 - 14 - ASAHI KASEI [AK4631] Timing Diagram 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fFCK 50%DVDD FCK dFCK dFCK 1/fMCK 50%DVDD MCKO tMCKOH tMCKOL dMCK = tMCKOL x fMCK x 100 Figure 2. Clock Timing (PLL Master mode) FCK 50%DVDD tBCK tDBF dBCK BICK (BCKP = "0") 50%DVDD BICK (BCKP = "1") 50%DVDD tBSD SDTO MSB tSDS 50%DVDD tSDH VIH SDTI MSB VIL Figure 3. Audio Interface Timing (PLL Master mode & DSP mode: MSBS = “0”) MS0317-E-01 2004/11 - 15 - ASAHI KASEI [AK4631] FCK 50%DVDD tBCK tDBF dBCK BICK (BCKP = "1") 50%DVDD BICK (BCKP = "0") 50%DVDD tBSD SDTO 50%DVDD MSB tSDS SDTI tSDH VIH MSB VIL Figure 4. Audio Interface Timing (PLL Master mode & DSP mode: MSBS = “1”) 50%DVDD FCK tBFCK dBCK BICK 50%DVDD tFSD tBSD SDTO 50%DVDD tSDS tSDH VIH SDTI VIL Figure 5. Audio Interface Timing (PLL Master mode & Except DSP mode) MS0317-E-01 2004/11 - 16 - ASAHI KASEI [AK4631] 1/fFCK VIH FCK VIL tFCKH tBFCK tBCK VIH BICK (BCKP = "0") VIL tBCKH tBCKL VIH BICK (BCKP = "1") VIL Figure 6. Clock Timing (PLL Slave mode; PLL Reference clock = FCK or BICK pin & DSP mode; MSBS = 0) 1/fFCK VIH FCK VIL tFCKH tBFCK tBCK VIH BICK (BCKP = "1") VIL tBCKH tBCKL VIH BICK (BCKP = "0") VIL Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = FCK or BICK pin & DSP mode; MSBS = 1) MS0317-E-01 2004/11 - 17 - ASAHI KASEI [AK4631] 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fFCK VIH FCK VIL tFCKH tFCKL tBCK VIH BICK VIL tBCKH tBCKL 1/fMCK 50%DVDD MCKO tMCKOH tMCKOL dMCK = tMCKOL x fMCK x 100 Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode) MS0317-E-01 2004/11 - 18 - ASAHI KASEI [AK4631] tFCKH VIH FCK VIL tFCKB VIH BICK VIL (BCKP = "0") VIH BICK (BCKP = "1") VIL tBSD SDTO 50%DVDD MSB tSDS tSDH VIH SDTI MSB VIL Figure 9. Audio Interface Timing (PLL Slave mode & DSP mode; MSBS = 0) tFCKH VIH FCK VIL tFCKB VIH BICK VIL (BCKP = "1") VIH BICK (BCKP = "0") VIL tBSD SDTO MSB tSDS 50%DVDD tSDH VIH SDTI MSB VIL Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = 1) MS0317-E-01 2004/11 - 19 - ASAHI KASEI [AK4631] 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fFCK VIH FCK VIL tFCKH tFCKL tBCK VIH BICK VIL tBCKH tBCKL Figure 11. Clock Timing (EXT Slave mode) VIH FCK VIL tBFCK tFCKB VIH BICK VIL tBSD tFSD SDTO MSB tSDS 50%DVDD tSDH VIH SDTI VIL Figure 12. Audio Interface Timing (PLL, EXT Slave mode & Except DSP mode) MS0317-E-01 2004/11 - 20 - ASAHI KASEI [AK4631] VIH CSN VIL tCCKL tCSS tCCKH VIH CCLK VIL tCCK tCDH tCDS VIH CDTI C1 C0 R/W VIL Figure 13. WRITE Command Input Timing tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI D2 D1 D0 VIL Figure 14. WRITE Data Input Timing VIH CSN VIL tPDV SDTO 50%DVDD Figure 15. Power Down & Reset Timing 1 tPD PDN VIL Figure 16. Power Down & Reset Timing 2 MS0317-E-01 2004/11 - 21 - ASAHI KASEI [AK4631] OPERATION OVERVIEW System Clock There are the following four clock modes to interface with external devices. (See Table 1 and Table 2) Mode PMPLL bit M/S bit PLL3-0 bit PLL Master Mode 1 1 See Table 4 PLL Slave Mode 1 1 0 See Table 4 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 1 0 See Table 4 (PLL Reference Clock: FCK or BICK pin) EXT Slave Mode 0 0 X Invalid state (Note 29) 0 1 X Table 1. Clock Mode Setting (X: Don’t care) MCKPD bit 0 Figure Figure 18 0 Figure 19 1 Figure 20 0 X Figure 21 - Note 29. If this mode is selected, the invalid clocks are output from MCKO, FCK and BICK pins. Mode PLL Master Mode PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 (PLL Reference Clock: FCK or BICK pin) EXT Slave Mode MCKO bit MCKO pin MCKI pin BICK pin FCK pin 0 “L” Output Master Clock Input for PLL (Note 30) 16fs/32fs/64fs Output 1fs Output 1 256fs Output 0 “L” Output 256fs Output Master Clock Input for PLL (Note 30) 16fs/32fs/64fs Input 1fs Input 1 0 “L” Output GND 16fs/32fs/64fs Input 1fs Input 256fs/ 512fs/ ≥ 32fs 0 “L” Output 1024fs Input Input Note 30. 11.2896MHz/12MHz/12.288MHz/13.5MHz/24MHz/27MHz Table 2. Clock pins state in Clock Mode 1fs Input [Pull-down resistor of MCKI pin] When the master clock is input, MCKPD bit should be “0”. When the MCKI pin is floating, the pin should be pulled-down by internal 25kΩ resistor at MCKPD bit = “1”(Default). MCKI MCKPD bit ="0" 25kΩ AK4631 Figure 17. Pull-down resistor of MCKI pin MS0317-E-01 2004/11 - 22 - ASAHI KASEI [AK4631] Master Mode/Slave Mode The M/S bit selects either master or slave modes. M/S bit = “1” selects master mode and “0” selects slave mode. When the AK4631 is power-down mode (PDN pin = “L”) and exits reset state, the AK4631 is slave mode. After exiting reset state, the AK4631 goes master mode by changing M/S bit = “1”. When the AK4631 is used by master mode, FCK and BICK pins are a floating state until M/S bit becomes “1”. FCK and BICK pins of the AK4631 should be pulled-down or pulled-up by about 100kΩ resistor externally to avoid the floating state. M/S bit Mode 0 Slave Mode Default 1 Master Mode Table 3. Select Master/Salve Mode PLL Mode When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK4631 is supplied to a stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes. 1) Setting of PLL Mode PLL R and C of Input Reference VCOC pin Frequency Clock Input C[F] R[Ω] Pin 0 FCK pin 1fs 6.8k 220n 1 BICK pin 16fs 10k 4.7n 0 BICK pin 32fs 10k 4.7n 1 BICK pin 64fs 10k 4.7n 0 MCKI pin 11.2896MHz 10k 4.7n 1 MCKI pin 12.288MHz 10k 4.7n 0 MCKI pin 12MHz 10k 4.7n 1 MCKI pin 24MHz 10k 4.7n 0 MCKI pin 13.5MHz 10k 10n 1 MCKI pin 27MHz 10k 10n N/A Table 4. Setting of PLL Mode (*fs: Sampling Frequency) Mode PLL3 bit PLL2 bit PLL1 bit 0 1 2 3 4 5 6 7 12 13 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 Others Others PLL0 bit PLL Lock Time (max) 160ms 2ms 2ms 2ms 40ms 40ms 40ms 40ms 40ms 40ms Default 2) Setting of sampling frequency in PLL Mode. When PLL2 bit is “1” (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS2-0 bits as defined in Table 5. Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency 0 0 0 0 0 8kHz Default 1 0 0 0 1 12kHz 2 0 0 1 0 16kHz 3 0 0 1 1 24kHz 4 0 1 0 0 7.35kHz 5 0 1 0 1 11.025kHz 6 0 1 1 0 14.7kHz 7 0 1 1 1 22.05kHz 10 1 0 1 0 32kHz 11 1 0 1 1 48kHz 14 1 1 1 0 29.4kHz 15 1 1 1 1 44.1kHz Others Others N/A Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” MS0317-E-01 2004/11 - 23 - ASAHI KASEI [AK4631] When PLL2 bit is “0” (PLL reference clock input is FCK or BICK pin), the sampling frequency is selected by FS3, FS1-0 bits. (See Table 6) Mode 0 1 2 3 6 7 Others FS3 bit 0 0 0 0 1 1 FS2 bit FS1 bit FS0 bit Sampling Frequency Range Don’t care 0 0 Default 7.35kHz ≤ fs ≤ 8kHz Don’t care 1 0 8kHz < fs ≤ 12kHz Don’t care 0 1 12kHz < fs ≤ 16kHz Don’t care 1 1 16kHz < fs ≤ 24kHz Don’t care 0 1 24kHz < fs ≤ 32kHz Don’t care 1 1 32kHz < fs ≤ 48kHz Others N/A Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” PLL Unlock State 1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) In this mode, irregular frequency clocks are output from FCK, BICK and MCKO pins after PMPLL bit = “0” Æ “1” or sampling frequency is changed. After that PLL is unlocked, BICK and FCK pins output “L” for a moment, and invalid frequency clock is output from MCKO pin at MCKO bit = “1”. If MCKO bit is “0”, MCKO pin is output to “L”. (See Table 7) After the PLL is locked, a first period of FCK and BICK may be invalid clock, but these clocks return to normal state after a period of 1/fs. MCKO pin BICK pin FCK pin MCKO bit = “0” MCKO bit = “1” After that PMPLL bit “0” Æ “1” “L” Output Invalid Invalid Invalid PLL Unlock “L” Output Invalid “L” Output “L” Output PLL Lock “L” Output 256fs Output See Table 9 1fs Output Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) PLL State 2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) In this mode, an invalid clock is output from MCKO pin after PMPLL bit = “0” Æ “1” or sampling frequency is changed. After that, 256fs is output from MCKO pin when PLL is locked. ADC and DAC output invalid data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACA and DACM bits in Addr=02H. MCKO pin MCKO bit = “0” MCKO bit = “1” After that PMPLL bit “0” Æ “1” “L” Output Invalid PLL Unlock “L” Output Invalid PLL Lock “L” Output 256fs Output Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) PLL State MS0317-E-01 2004/11 - 24 - ASAHI KASEI [AK4631] PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) When an external clock (11.2896MHz, 12MHz , 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to MCKI pin, the MCKO, BICK and FCK clocks are generated by an internal PLL circuit. The MCKO output frequency is fixed to 256fs, the output is enabled by MCKO bit. The BICK is selected among 16fs, 32fs or 64fs, by BCKO1-0 bits. (See Table 9) When BICK output frequency is 16fs, the audio interface format supports only Mode 0 (DSP Mode). 11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz DSP or µP AK4631 MCKI MCKO BICK FCK 256fs 16fs, 32fs, 64fs 1fs MCLK BCLK FCK SDTO SDTI SDTI SDTO Figure 18. PLL Master Mode Mode 0 1 2 3 BICK Output Frequency 0 0 16fs 0 1 32fs 1 0 64fs 1 1 N/A Table 9. BICK Output Frequency at Master Mode BCKO1 BCKO0 MS0317-E-01 Default 2004/11 - 25 - ASAHI KASEI [AK4631] PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to MCKI, BICK or FCK pin. The required clock to the AK4631 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits. When BICK input frequency is 16fs, the audio interface format supports only Mode 0 (DSP Mode). a) PLL reference clock: BICK or FCK pin In the case of using BICK as PLL reference clock, the sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits. In the case of using FCK, the sampling frequency corresponds to 7.35kHz to 26kHz. (SeeTable 6) AK4631 DSP or µP MCKO MCKI BICK FCK 16fs, 32fs, 64fs 1fs BCLK FCK SDTO SDTI SDTI SDTO Figure 19. PLL Slave Mode 1 (PLL Reference Clock: FCK or BICK pin) b) PLL reference clock: MCKI pin BICK and FCK inputs should be synchronized with MCKO output. The phase between MCKO and FCK dose not matter. Sampling frequency can be selected by FS3-0 bits. (See Table 5) 11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz AK4631 DSP or µP MCKI MCKO BICK FCK 256fs 16fs, 32fs, 64fs 1fs MCLK BCLK FCK SDTO SDTI SDTI SDTO Figure 20. PLL Slave Mode 2 (PLL Reference Clock: MCKI pin) The external clocks (MCKI, BICK and FCK) should always be present whenever the ADC or DAC is in operation (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4631 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADC bit =PMDAC bit = “0”). MS0317-E-01 2004/11 - 26 - ASAHI KASEI [AK4631] EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0”, the AK4631 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 512fs or 1024fs), FCK (fs) and BICK (32fs∼). The master clock (MCKI) should be synchronized with FCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS3-0 bits. (See Table 10) Mode 0 1 2 3 FS3-2 bits FS1 bit FS0 bit MCKI Input Sampling Frequency Frequency Range Don’t care 0 256fs 0 7.35kHz ≤ fs ≤ 48kHz Don’t care 1 1024fs 0 7.35kHz < fs ≤ 13kHz Don’t care 0 256fs 1 7.35kHz < fs ≤ 48kHz Don’t care 1 512fs 1 7.35kHz < fs ≤ 26kHz Table 10. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) Default External Slave Mode does not support Mode 0 (DSP Mode) of Audio Interface Format. The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. When the out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output through AOUT amp at fs=8kHz is shown in Table 11. S/N (fs=8kHz, 20kHzLPF + A-weight) 256fs 83dB 512fs 93dB 1024fs 93dB Table 11. Relationship between MCKI and S/N of AOUT MCKI The external clocks (MCKI, BICK and FCK) should always be present whenever the ADC or DAC is in operation (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4631 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADC bit = PMDAC bit = “0”). AK4631 DSP or µP MCKO 256fs, 512fs or 1024fs MCKI BICK FCK MCLK 32fs, 64fs 1fs BCLK FCK SDTO SDTI SDTI SDTO Figure 21. EXT Slave Mode MS0317-E-01 2004/11 - 27 - ASAHI KASEI [AK4631] Audio Interface Format Four types of data formats are available and are selected by setting the DIF1-0 bits. (See Table 12) In all modes, the serial data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. FCK and BICK are output from AK4631 in master mode, but must be input to AK4631 in slave mode. In Mode 1-3, the SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the rising edge. Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 0 1 0 1 SDTO (ADC) SDTI (DAC) BICK DSP Mode DSP Mode ≥ 16fs MSB justified MSB justified ≥ 32fs MSB justified MSB justified ≥ 32fs I2S compatible I2S compatible ≥ 32fs Table 12. Audio Interface Format Figure See Table 13 Figure 26 Figure 27 Figure 28 Default In Mode0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits. When BCKP bit is “0”, SDTO data is output by rising edge of BICK, SDTI data is latched by falling edge of BICK. When BCKP bit is “1”, SDTO data is output by falling edge of BICK, SDTI data is latched by rising edge of BICK. MSB data position of SDTO and SDTI can be shifted by MSBS bit. The shifted period is a half of BICK. MSBS bit BCKP bit Audio Interface Format 0 0 Figure 22 0 1 Figure 23 1 0 Figure 24 1 1 Figure 25 Table 13. Audio Interface Format in Mode 0 Default If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1” at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit data. System Reset Upon power-up, reset the AK4631 by bringing the PDN pin = “L”. This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle that starts when the PMADC bit is changed from “0” to “1”. The initialization cycle time is 1059/fs, or 133ms@fs=8kHz. During the initialization cycle, the ADC digital data outputs of both channels are forced to a 2's compliment, “0”. The ADC output reflects the analog input signal after the initialization cycle is complete. The DAC does not require an initialization cycle. MS0317-E-01 2004/11 - 28 - ASAHI KASEI [AK4631] FCK 15 0 1 8 2 8 9 10 11 12 13 14 15 0 1 8 2 8 9 10 11 12 13 14 15 0 BICK(16fs) SDTO(o) 0 15 14 SDTI(i) 0 15 14 15 0 1 8 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 2 14 15 16 17 18 29 30 31 0 1 8 7 6 5 4 3 2 1 0 15 7 6 5 4 3 2 1 0 15 8 2 8 9 10 11 12 13 30 31 0 15 0 BICK(32fs) SDTO(o) 15 14 SDTI(i) 15 14 8 2 1 0 2 1 0 Don’t Care 15 14 8 2 1 0 15 14 8 2 1 0 Don’t Care 1/fs 1/fs 15:MSB, 0:LSB Figure 22. Mode 0 Timing (BCKP = “0”, MSBS = “0”) FCK 15 0 1 8 2 8 9 10 11 12 13 14 15 0 1 8 2 8 9 10 11 12 13 14 BICK(16fs) SDTO(o) 0 15 14 SDTI(i) 0 15 14 15 0 1 8 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 2 14 15 16 17 18 29 30 31 0 1 8 7 6 5 4 3 2 1 0 15 7 6 5 4 3 2 1 0 15 8 2 8 9 10 11 12 13 30 31 0 BICK(32fs) SDTO(o) 15 14 SDTI(i) 15 14 8 2 1 0 2 1 0 Don’t Care 15 14 8 2 1 0 15 14 8 2 1 0 Don’t Care 1/fs 1/fs 15:MSB, 0:LSB Figure 23. Mode 0 Timing (BCKP = “1”, MSBS = “0”) MS0317-E-01 2004/11 - 29 - ASAHI KASEI [AK4631] FCK 15 0 1 8 2 8 9 10 11 12 13 14 15 0 1 8 2 8 9 10 11 12 13 14 15 0 BICK(16fs) SDTO(o) 0 15 14 SDTI(i) 0 15 14 15 0 1 8 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 2 14 15 16 17 18 29 30 31 0 1 8 7 6 5 4 3 2 1 0 15 7 6 5 4 3 2 1 0 15 8 2 8 9 10 11 12 13 30 31 0 15 0 BICK(32fs) SDTO(o) 15 14 SDTI(i) 15 14 8 2 1 0 2 1 0 Don’t Care 15 14 8 2 1 0 15 14 8 2 1 0 Don’t Care 1/fs 1/fs 15:MSB, 0:LSB Figure 24. Mode 0 Timing (BCKP = “0”, MSBS = “1”) FCK 15 0 1 8 2 8 9 10 11 12 13 14 15 0 1 8 2 8 9 10 11 12 13 14 BICK(16fs) SDTO(o) 0 15 14 SDTI(i) 0 15 14 15 0 1 8 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 2 14 15 16 17 18 29 30 31 0 1 8 7 6 5 4 3 2 1 0 15 7 6 5 4 3 2 1 0 15 8 2 8 9 10 11 12 13 30 31 0 BICK(32fs) SDTO(o) 15 14 SDTI(i) 15 14 8 2 1 0 2 1 0 Don’t Care 15 14 8 2 1 0 15 14 8 2 1 0 Don’t Care 1/fs 1/fs 15:MSB, 0:LSB Figure 25. Mode 0 Timing (BCKP = “1”, MSBS = “1”) MS0317-E-01 2004/11 - 30 - ASAHI KASEI [AK4631] FCK 0 1 2 8 3 9 10 11 12 13 14 15 0 1 2 3 8 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 15 14 13 SDTI(i) 15 14 13 0 1 2 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 3 14 15 16 17 18 31 15 15 Don’t Care 0 1 2 3 14 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) 15 14 13 SDTI(i) Don’t Care 15:MSB, 0:LSB 2 1 0 15 15 14 1 Don’t Care 0 Data 1/fs Figure 26. Mode 1 Timing FCK 0 1 2 8 9 10 11 12 13 14 15 0 1 2 8 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 15 14 8 7 6 5 4 3 2 1 0 SDTI(I) 15 14 8 7 6 5 4 3 2 1 0 0 1 2 3 14 15 16 17 18 31 15 15 Don’t Care 0 1 2 3 14 14 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) 15 14 13 13 2 1 0 SDTI(i) 15 14 13 13 2 1 0 15 Don’t Care Don’t Care 15 15:MSB, 0:LSB Data 1/fs Figure 27. Mode 2 Timing MS0317-E-01 2004/11 - 31 - ASAHI KASEI [AK4631] FCK 0 1 2 3 4 9 10 11 12 13 14 15 0 1 2 3 1 2 3 4 9 10 11 12 13 14 15 16 17 18 14 15 0 1 31 0 1 BICK(32fs) SDTO(o) 15 14 13 SDTI(i) 15 14 13 0 1 2 4 3 7 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 14 15 16 17 18 31 0 4 BICK(64fs) SDTO(o) 15 14 13 2 1 0 SDTI(i) 15 14 13 2 1 0 15:MSB, 0:LSB Don’t Care Don’t Care Data 1/fs Figure 28. Mode 3 Timing Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.25Hz (@fs=8kHz) and scales with sampling rate (fs). MIC Gain Amplifier The AK4631 has a Gain Amplifier for Microphone input. This gain is 0dB, +20dB, +26dB or +32dB, selected by the MGAIN1-0 bit. The typical input impedance is 30kΩ. MGAIN1 bit 0 0 1 1 MGAIN0 bit Input Gain 0 0dB 1 +20dB 0 +26dB 1 +32dB Table 14. Input Gain Default MIC Power The MPI pin supplies power for the Microphone. This output voltage is typically 0.75 x AVDD and the load resistance is minimum 2kΩ. No capacitor must not be connected directly to MPI pin. (See Figure 29) MIC Power MPI pin ≥ 2k Ω Microphone MIC pin MIC-Amp Figure 29. MIC Block Circuit MS0317-E-01 2004/11 - 32 - ASAHI KASEI [AK4631] Manual Mode The AK4631 becomes a manual mode at ALC1 bit = “0”. This mode is used in the case shown below. 1. After exiting reset state, set up the registers for the ALC1 operation (ZTM1-0, LMTH and etc) 2. When the registers for the ALC1 operation (Limiter period, Recovery period and etc) are changed. For example; When the change of the sampling frequency. 3. When IPGA is used as a manual volume. When IPGA6-0 bits are written at manual mode, the counter for zero cross time out is reset and restart. The IPGA6-0 bits value are reflected to IPGA at zero cross or zero cross time out. The time of zero cross time out is set by ZTM1-0 bits. When writing to IPGA6-0 bits continually, the control register should be written by an interval of more than zero crossing timeout. MIC-ALC Operation The ALC (Automatic Level Control) of MIC input is done by ALC1 block when ALC1 bit is “1”. [1] ALC1 Limiter Operation When the ALC1 limiter is enabled, and IPGA output exceeds the ALC1 limiter detection level (LMTH), the IPGA value is attenuated by the amount defined in the ALC1 limiter ATT step (LMAT1-0 bits) automatically. When the ZELM bit = “1”, the timeout period is set by the LTM1-0 bits. The operation for attenuation is done continuously until the input signal level becomes LMTH or less. If the ALC1 bit does not change into “0” after completing the attenuation, the attenuation operation repeats while the input signal level equals or exceeds LMTH. When the ZELM bit = “0”, the timeout period is set by the ZTM1-0 bits. This enables the zero-crossing attenuation function so that the IPGA value is attenuated at the zero-detect points of the waveform. [2] ALC1 Recovery Operation The ALC1 recovery refers to the amount of time that the AK4631 will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits to define the wait period used after completing an ALC1 limiter operation. If the input signal does not exceed the “ALC1 Recovery Waiting Counter Reset Level”, the ALC1 recovery operation starts. The IPGA value increases automatically during this operation up to the reference level (REF6-0 bits). The ALC1 recovery operation is done at a period set by the WTM1-0 bits. Zero crossing is detected during WTM1-0 period, the ALC1 recovery operation waits WTM1-0 period and the next recovery operation starts. During the ALC1 recovery operation, when input signal level exceeds the ALC1 limiter detection level (LMTH), the ALC1 recovery operation changes immediately into an ALC1 limiter operation. In the case of “(Recovery waiting counter reset level) ≤ IPGA Output Level < Limiter detection level” during the ALC1 recovery operation, the wait timer for the ALC1 recovery operation is reset. Therefore, in the case of “(Recovery waiting counter reset level) > IPGA Output Level”, the wait timer for the ALC1 recovery operation starts. The ALC1 operation corresponds to the impulse noise. When the impulse noise is input, the ALC1 recovery operation becomes faster than a normal recovery operation. MS0317-E-01 2004/11 - 33 - ASAHI KASEI [AK4631] [3] Example of ALC1 Operation Table 15 shows the example of the ALC1 setting. In case of this example, ALC1 operation starts from 0dB. fs=8kHz Operation -4dBFS Don’t use Enable 16ms Register Name Comment LMTH LTM1-0 ZELM ZTM1-0 Limiter detection Level Limiter operation period at ZELM = 1 Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM1-0 bits should be the same data 00 16ms as ZTM1-0 bits Maximum gain at recovery operation 47H +27.5dB IPGA gain at the start of ALC1 operation 10H 0dB Limiter ATT Step 00 1 step Recovery GAIN Step 0 1 step ALC1 Enable bit 1 Enable Table 15. Examples of the ALC1 Setting WTM1-0 REF6-0 IPGA6-0 LMAT1-0 RATT ALC1 Data 1 00 0 00 fs=16kHz Data Operation 1 -4dBFS 00 Don’t use 0 Enable 01 16ms 01 16ms 47H 10H 00 0 1 +27.5dB 0dB 1 step 1 step Enable The following registers should not be changed during the ALC1 operation. These bits should be changed, after the ALC1 operation is finished by ALC1 bit = “0” or PMMIC bit = “0”. • LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits When setting IPGA gain at the start of ALC1 operation, IPGA6-0 bits should be set while PMMIC bit is “1” and ALC1 bit is “0”. When PMMIC bit = “1”, IPGA6-0 bits value aren’t reflected to IPGA. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set automatically by ALC1 operation. Example: Limiter = Zero crossing Enable Recovery Cycle = 16ms @ fs= 8kHz Limiter and Recovery Step = 1 Maximum Gain = +27.5dB Limiter Detection Level = -4dBFS Manual Mode ALC2 bit = “1” (default) WR (ZTM1-0, WTM1-0, LTM1-0) (1) Addr=06H, Data=00H WR (REF6-0) (2) Addr=08H, Data=47H WR (IPGA6-0) * The value of IPGA should be (3) Addr=09H, Data=10H the same or smaller than REF’s WR (ALC1= “1”, LMAT1-0, RATT, LMTH, ZELM) (4) Addr=07H, Data=61H ALC1 Operation Note : WR : Write Figure 30. Registers set-up sequence at the ALC1 operation MS0317-E-01 2004/11 - 34 - ASAHI KASEI [AK4631] Digital Output Volume The AK4631 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVOL7-0 bits. The volume is included in front of a DAC block, a input data of DAC is changed from +12 to –115dB with MUTE. This volume has a soft transition function. It takes 1061/fs or 256/fs from 00H to FFH. DVOL7-0 Gain 00H +12.0dB 01H +11.5dB 02H +11.0dB • • 18H 0dB Default • • FDH −114.5dB FEH −115.0dB FFH MUTE (−∞) Table 16. Digital Output Volume Code Table DVTM bit 0 1 The transition time from 00H to FFH of DVOL7-0 bits Transition Time fs=8kHz fs=22.05kHz 1061/fs 133msec 48msec 256/fs 32msec 12msec Table 17.Setting of transition time BEEP Input When the PMBP bit is set to “1”, the beep input is powered-up. And when the BEEPS bit is set to “1”, the input signal from the BEEP pin is output to Speaker-Amp. When the BEEPA bit is set to “1”, the input signal from the BEEP pin is output to the mono line output amplifier. The external resister Ri adjusts the signal level of BEEP input. The gains are shown in Table 18, when Ri = 20kΩ. These gain are in inverse proportion to Ri. Rf Ri - BEEP + Figure 31. Block Diagram of BEEP pin SPKG1-0 bits 00 01 10 11 BEEP Æ SPP/SPN Gain BEEP Æ AOUT Gain +7.89dB 0dB +9.93dB 0dB +14.11dB 0dB +16.15dB 0dB Table 18. Beep input gain at Ri = 20kΩ MS0317-E-01 2004/11 - 35 - ASAHI KASEI [AK4631] MONO LINE OUTPUT (AOUT pin) A signal of DAC is output from AOUT pin. When the DACA bit is “0”, this output is OFF. The load resistance is 10kΩ(min). When PMAO bit is “0” and AOPSN bit is “0”, the mono line output enters power-down and is pulled down by 100Ω(typ). If PMAO bit is controlled at AOPSN bit = “1”, POP noise will be reduced at power-up and down. Then, this line should be pulled down by 20kΩ of resister after C-coupling shown in Figure 32. This rising and falling time is max 300 ms at C=1.0µF . When PMAO bit is “1” and AOPSN bit is “0”, the mono line output enters power-up state. 1µF AOUT 220Ω 20kΩ Figure 32. AOUT external circuit in case of using POP Reduction function. AOUT Control Sequence in case of using POP Reduction Circuit (2 ) (5 ) P M A O b it (1 ) (3 ) (4 ) (6 ) A O P S N b it A O U T p in N o r m a l O u tp u t ≥ 300 m s ≥ 300 m s Figure 33. Mono Line Output Control Sequence in case of using POP Reduction function.. (1) Set AOPSN bit = “1”. Mono line output enters the power-save mode. (2) Set PMAO bit = “1”. Mono line output exits the power-down mode. AOUT pin rises up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1µF. (3) Set AOPSN bit = “0” after AOUT pin rises up. Mono line output exits the power-save mode. Mono line output is enabled. (4) Set AOPSN bit = “1”. Mono line output enters power-save mode. (5) Set PMAO bit = “1”. Mono line output enters power-down mode. AOUT pin falls down to AVSS. Fall time is 200ms (max 300ms) at C=1µF. (6) Set AOPSN bit = “0” after AOUT pin falls down. Mono line output exits the power-save mode. MS0317-E-01 2004/11 - 36 - ASAHI KASEI [AK4631] Speaker Output The power supply voltage for Speaker-Amp SVDD can be set to from 2.6V to 5.25V. However, SVDD should be set to from 2.6V to 3.6V, when the load resistance is less than 50Ω(ex. a dynamic speaker). The output signal from DAC is input to the Speaker-amp via the ALC2 circuit. This Speaker-amp is a mono output controlled by BTL and a gain of the Speaker-Amp is set by SPKG1-0 bit. In the case of ALC2 OFF, the output voltage depends on AVDD and SPKG1-0 bits. In the case of ALC2 ON, the output voltage depends on SVDD and SPKG1-0 bits. The output level of ALC2 is proportional to SVDD. SPKG1-0 bits Gain 00 0dB 01 +2.04dB 10 +6.22dB 11 +8.26dB (Note) These Gain from the level at SPKG1-0bits= “00”. Table 19. Gain of Speaker-Amp at ALC2 OFF Output Voltage from Speaker-Amp Output Voltage from SPKG1-0 bits AVDD SVDD at ALC2 OFF and DAC Input=-0.5dBFS Speaker-Amp at ALC ON 00 3.3V 3.3V 3.09Vpp, 150mW@8Ω 3.09Vpp, 150mW@8Ω 01 3.3V 3.3V 3.92Vpp, 240mW@8Ω 3.92Vpp, 240mW@8Ω 10 3.3V 3.3V 6.34Vpp (Note) Not Available 11 3.3V 3.3V 8.02Vpp (Note) Not Available 00 3.3V 5.0V 3.09Vpp Not Available 01 3.3V 5.0V 3.92Vpp Not Available 10 3.3V 5.0V 6.34Vpp 6.34Vpp 11 3.3V 5.0V 8.02Vpp 8.02Vpp (Note) This output voltage is assumed that the signal isn’t clipped. In actual, the signal will be clipped when DAC outputs 0dBFS signal. In order to avoid this clipping, Speaker-Amp output voltage should be attenuated to less than 3.92Vpp by the digital volume. Table 20 Speaker-Amp Output Voltage [Caution for using Piezo Speaker] When a piezo speaker (load capacitance > 30pF) is used, resistances more than 10Ω should be inserted between SPP/SPN pins and speaker in series, respectively, as shown in Figure 34. Zener diodes should be inserted between speaker and GND as shown in Figure 34, in order to protect SPK-Amp of AK4631 from the power that the piezo speaker outputs when the speaker is pressured. Zener diodes of the following Zener voltage should be used. 92% of SVDD ≤ Zener voltage of Zener diodo(ZD of Figure 34) ≤ SVDD+0.3V Ex) In case of SVDD = 5.0V : 4.6V ≤ ZD ≤ 5.3V For example, Zener diode which Zener voltage is 5.1V(Min :4.97V, Max 5.24V) can be used. MS0317-E-01 2004/11 - 37 - ASAHI KASEI [AK4631] ZD SPK-Amp SPP ≥10Ω SPN ≥10Ω ZD Figure 34. Circuit of Speaker Output(Load Capacitance > 30pF) <Control Sequence of Speaker Amp> Speaker blocks (MOUT, ALC2 and Speaker-amp) can be powered-up/down by controlling the PMSPK bit. When the PMSPK bit is “0”, the MOUT, SPP and SPN pins are placed in a Hi-Z state. When the PMSPK bit is “1” and SPPS bit is “0”, the Speaker-amp enters power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin goes to SVDD/2 voltage. And then the Speaker output gradually changes to the SVDD/2 voltage and this mode can reduce pop noise at power-up. When the AK4631 is powered-down, pop noise can be also reduced by first entering power-save-mode. PMSPK bit SPPS bit SPP pin SPN pin Hi-Z Hi-Z Hi-Z SVDD/2 SVDD/2 >t1(Note) Hi-Z >0 Figure 35. Power-up/Power-down Timing for Speaker-Amp (Note) “t1” depends on the time constant of input resistance of MIN and capacitor between MOUT pin and MIN pin. If Speaker-Amp output is enabled before MIN-Amp (ALC2) becomes stable, pop noise may occur. Ex) C of MOUT pin – MIN pin = 0.1 µF, Input resistance of MIN pin = 36kΩ(Max) : t1 = 5τ = 18ms C of MOUT pin – MIN pin and the Input resistance(Rin) of MIN pin compose of HPF which cut off frequency(fc) are the followings. fc = 66Hz@Rin=24kΩ(typ), 133Hz@Rin=12kΩ(min), 44Hz@Rin=36kΩ(max) MS0317-E-01 2004/11 - 38 - ASAHI KASEI [AK4631] SPK-ALC Operation The ALC (Automatic Level Control) operation of speaker output is done by ALC2 block when ALC2 bit is “1”. Input resistance of the ALC2 is 24kΩ (typ) and centered around VCOM voltage. The ALC2 level diagram is shown in Figure 36 ~Figure 39. The limiter detection level is proportional to SVDD voltage. The output level is limited by the ALC2 circuit when the input signal exceeds –7.1dBV (@SPKG1 bit = “0”, SVDD=3.3V or @SPKG1 bit = “1”, SVDD = 5V). When a continuous signal of –7.1dBV or greater is input to the ALC2 circuit, the change period of the ALC2 limiter operation is 250µs (=2/fs@fs=8kHz) and the attenuation level is 0.5dB/step. The ALC2 recovery operation uses zero crossings and gains of 1dB/step. The ALC2 recovery operation is done until the input level of the Speaker-amp goes to –9.1dBV (@SPKG1 bit = “0”, SVDD=3.3V or @SPKG1 bit = “1”, SVDD = 5V). Maximum gain of the ALC2 recovery operation is set by RFS5-0 bits. When the input signal is between –9.1dBV and –7.1dBV, the ALC2 limiter or recovery operations are not done. When the PMSPK bit changes from “0” to “1”, the initilization cycle (512/fs = 64ms @fs=8kHz at ROTM bit = “0”) starts. The ALC2 is disabled (The ALC2 gain is fixed to “-3.5dB”.) during the initilization cycle and the ALC2 starts from “–2dB” after completing the initilization cycle. The ROTM bit and RFS5-0 bits set during the PMSPK bit = “0”. When the ALC2 is disable, a gain of the ALC2 block is fixed to -3.5dB. Therefore, a gain of internal speaker block is shown in Table 22. Parameter −5.2dBV −7.2dBV 2/fs = 250µs 512/fs=64ms fs=16kHz 2/fs = 125µs 512/fs=32ms No Yes (Timeout = Period Time) Zero-crossing Detection ATT/GAIN ALC2 Recovery operation fs=8kHz Operation Start Level Period ALC2 Limiter operation 0.5dB step 1dB step Table 21. Limiter /Recovery of ALC2 (ROTM bit = “0”) SPKG1-0 bits Gain 00 +4.4dB 01 +6.4dB 10 +10.6dB 11 +12.7dB Table 22. Gain of Speaker-Amp at ALC2 OFF(Full-differential Output) MS0317-E-01 2004/11 - 39 - ASAHI KASEI [AK4631] 0.8dBV -3.1dBV +7.9dB FS-4.0dB = -7.1dBV -3.1dBV FS -4.0dB 0dBV -1.2dBV +7.9dB +1.9dB -8dB -10dBV -11.1dBV -15.1dBV FS-6.0dB = -9.1dBV -15.1dBV +6.0dB +14.0dB -8dB Single-ended -5.2dBV +2.0dB FS-12dB Full-differential -20dBV -23.1dBV -30dBV DVOL DAC ALC2 SPK-AMP (AVDD=3.3V, SVDD=3.3V, DVOL=−8.0dB/0dB, SPKG1-0 bit = “00”,) * FS = Full Scale Figure 36. Speaker-Amp Output Level Diagram 10dBV Full-differential 2.8dBV FS-4dB = -7.1dBV 0.8dBV 0dBV -3.1dBV -3.1dBV +9.9dB FS +9.9dB -3.2dBV Single-ended +3.9dB -4.0dB -8dB +2.0dB -10dBV -11.1dBV FS-12dB FS-6.0dB = -9.1dBV -15.1dBV +6.0dB -15.1dBV +14.0dB -8dB -20dBV -23.1dBV -30dBV DVOL DAC ALC2 SPK-AMP (AVDD=3.3V, SVDD=3.3V, DVOL=−8.0dB/0dB, SPKG1-0 bit = “01”,) * FS = Full Scale Figure 37. Speaker-Amp Output Level Diagram MS0317-E-01 2004/11 - 40 - ASAHI KASEI [AK4631] 10dBV 7.0dBV +14.1dB +14.1dB Full-differential 5.0dBV Single-ended 1.0dBV 0dBV -3.1dBV -3.1dBV FS FS-4dB = -7.1dBV +8.1dB -4.0dB -8dB +2.0dB -10dBV -11.1dBV FS-12dB FS-6.0dB = -9.1dBV -15.1dBV +6.0dB -15.1dBV +14.0dB -8dB -20dBV -23.1dBV -30dBV DVOL DAC ALC2 SPK-AMP (AVDD=3.3V, SVDD=5.0V, DVOL=−8.0dB/0dB, SPKG1-0 bit = “10”,) * FS = Full Scale Figure 38. Speaker-Amp Output Level Diagram 10dBV 9.1dBV +16.2dB Full-differential 7.1dBV Single-ended 3.1dBV +16.2dB 0dBV -3.1dBV -3.1dBV FS FS-4dB = -7.1dBV +10.2dB -4.0dB -8dB +2.0dB -10dBV -11.1dBV FS-12dB FS-6.0dB = -9.1dBV -15.1dBV +6.0dB -15.1dBV +14.0dB -8dB -20dBV -23.1dBV -30dBV DVOL DAC ALC2 SPK-AMP (AVDD=3.3V, SVDD=5.0V, DVOL=−8.0dB/0dB, SPKG1-0 bit = “11”,) * FS = Full Scale Figure 39. Speaker-Amp Output Level Diagram MS0317-E-01 2004/11 - 41 - ASAHI KASEI [AK4631] Serial Control Interface Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface consists of a 2-bit Chip address (Fixed to “10”), Read/Write (Fixed to “1”), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. The clock speed of CCLK is 5MHz (max). The value of internal registers is initialized at PDN pin = “L”. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A2 A0 D7 D6 D5 D4 D3 D2 D1 D0 “1” “0” “1” C1-C0: R/W: A4-A0: D7-D0: Chip Address (C1 = “1”, C0 = “0”); Fixed to “10” READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1” Register Address Control data Figure 40. Serial Control I/F Timing MS0317-E-01 2004/11 - 42 - ASAHI KASEI [AK4631] Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Input PGA Control Digital Volume Control ALC2 Mode Control D7 0 0 SPPS 0 PLL3 0 DVTM 0 0 0 DVOL7 0 D6 PMVCM 0 BEEPS AOPSN PLL2 0 ROTM ALC2 REF6 IPGA6 DVOL6 0 D5 PMBP 0 ALC2S MGAIN1 PLL1 FS3 ZTM1 ALC1 REF5 IPGA5 DVOL5 RFS5 D4 PMSPK 0 DACA SPKG1 PLL0 MSBS ZTM0 ZELM REF4 IPGA4 DVOL4 RFS4 D3 PMAO M/S DACM SPKG0 BCKO1 BCKP WTM1 LMAT1 REF3 IPGA3 DVOL3 RFS3 D2 PMDAC MCKPD MPWR BEEPA BCKO0 FS2 WTM0 LMAT0 REF2 IPGA2 DVOL2 RFS2 D1 PMMIC MCKO MICAD ALC1M DIF1 FS1 LTM1 RATT REF1 IPGA1 DVOL1 RFS1 D0 PMADC PMPLL MGAIN0 ALC1A DIF0 FS0 LTM0 LMTH REF0 IPGA0 DVOL0 RFS0 The PDN pin = “L” resets the registers to their default values. Note: Unused bits must contain a “0” value. Note: Only write to address 00H to 0BH. MS0317-E-01 2004/11 - 43 - ASAHI KASEI [AK4631] Register Definitions Addr 00H Register Name Power Management 1 Default D7 0 0 D6 PMVCM 0 D5 PMBP 0 D4 PMSPK 0 D3 PMAO 0 D2 PMDAC 0 D1 PMMIC 0 D0 PMADC 0 PMADC: ADC Block Power Control 0: Power down (Default) 1: Power up When the PMADC bit changes from “0” to “1”, the initialization cycle (1059/fs=133ms@8kHz) starts. After initializing, digital data of the ADC is output. PMMIC: MIC In Block (MIC-Amp and ALC1) Power Control 0: Power down (Default) 1: Power up PMDAC: DAC Block Power Control 0: Power down (Default) 1: Power up PMAO: Mono Line Out Power Control 0: Power down (Default) 1: Power up PMSPK: Speaker Block Power Control 0: Power down (Default) 1: Power up PMBP: BEEP In Power Control 0: Power down (Default) 1: Power up Even if PMBP bit is “0”, the path is still connected between BEEP and AOUT/SPK-Amp. BEEPS and BEEPA bits should be set to “0” to disconnect these paths. PMVCM: VCOM Block Power Control 0: Power down (Default) 1: Power up Each block can be powered-down respectively by writing “0” in each bit. When the PDN pin is “L”, all blocks are powered-down. When PMPLL and MCKO bits and all bits in 00H address are “0”, all blocks are powered-down. Though the IPGA resisters are initialized, the other registers remain unchanged. (refer to the IPGA6-0 bits description) When any of the blocks are powered-up, the PMVCM bit must be set to “1”. When PMPLL and MCKO bits and all bits in 00H address are “0”, PMVCM bit can write to “0”. When BEEP signal is output from Speaker-Amp (Signal path: BEEP pin Æ SPP/SPN pins) or Mono Lineout-Amp (Signal path: BEEP pin Æ AOUT pin) only, the clocks may not be present. When ADC, DAC, ALC1 or ALC2 is in operation, the clocks must always be present. MS0317-E-01 2004/11 - 44 - ASAHI KASEI Addr 01H Register Name Power Management 2 Default [AK4631] D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 M/S 0 D2 MCKPD 1 D1 MCKO 0 D0 PMPLL 0 PMPLL: PLL Block Power Control Select 0: PLL is Power down and External is selected. (Default) 1: PLL is Power up and PLL Mode is selected. MCKO: Master Clock Output Enable 0: “L” Output (Default) 1: 256fs Output MCKPD: MCKI pin pull down control 0: Master Clock input enable 1: Pull down by 25kΩ (typ.) (Default) M/S: Select Master / Slave Mode 0: Slave Mode (Default) 1: Master Mode MS0317-E-01 2004/11 - 45 - ASAHI KASEI Addr 02H Register Name Signal Select 1 Default [AK4631] D7 SPPS 0 D6 BEEPS 0 D5 ALC2S 0 D4 DACA 0 D3 DACM 0 D2 MPWR 0 D1 MICAD 0 D0 MGAIN0 1 MGAIN1-0 : 1st MIC-amp Gain control(See Table 23) MGAIN 1 bit is located at D6 bit of 03H MGAIN1 bit 0 0 1 1 MGAIN0 bit Input Gain 0 0dB 1 +20dB 0 +26dB 1 +32dB Table 23. Input Gain Default MICAD: Switch Control from MIC In to ADC. 0: OFF (Default) 1: ON When MICAD bit is “1”, the ALC1 output signal is input to ADC. MPWR: Power Supply Control for Microphone 0: OFF (Default) 1: ON When PMMIC bit is “1”, MPWR bit is enabled. DACM: Switch Control from DAC to mono amp. 0: OFF (Default) 1: ON When PMSPK bit is “1”, DACM bit is enabled. When PMSPK bit is “0”, MOUT pin is Hi-Z state. DACA: Switch Control from DAC to mono line amp 0: OFF (Default) 1: ON When PMAO bit is “1”, DACA bit is enabled. When PMAO bit is “0”, the AOUT pin is AVSS. ALC2S: ALC2 output to Speaker-Amp Enable 0: OFF (Default) 1: ON When ALC2S bit is “1”, the ALC2 output signal is input to Speaker-Amp. BEEPS: BEEP pin to Speaker-Amp Enable 0: OFF (Default) 1: ON When BEEPS bit is “1”, the beep signal is input to Speaker-Amp. SPPS: Speaker-amp Power-Save-Mode 0: Power Save Mode (Default) 1: Normal Operation When SPPS bit is “1”, the Speaker-amp is in power-save-mode and the SPP pin becomes Hi-z and SPN pin is set to SVDD/2 voltage. When the PMSPK bit = “1”, this bit is valid. After the PDN pin changes from “L” to “H”, the PMSPK bit is “0”, which powers down Speaker-amp. MS0317-E-01 2004/11 - 46 - ASAHI KASEI Addr 03H Register Name Signal Select 2 Default [AK4631] D7 0 0 D6 0 0 D5 MGAIN1 0 D4 SPKG1 0 D3 SPKG0 0 D2 BEEPA 0 D1 ALC1M 0 D0 ALC1A 0 ALC1A: Switch Control from ALC1 output signal to mono line output amp. 0: OFF (Default) 1: ON When PMAO bit is “1”, ALC1A bit is enabled. When PMAO bit is “0”, the AOUT pin is AVSS. ALC1M: Switch Control from ALC1 output signal to mono amp. 0: OFF (Default) 1: ON When PMSPK bit is “1”, ALC1M is enabled. When PMSPK bit is “0”, the MOUT pin goes Hi-Z state. BEEPA: Switch Control from beep signal to mono line output amp. 0: OFF (Default) 1: ON When PMAO bit is “1”, BEEPA is enabled. When PMAO bit is “0”, the AOUT pin is AVSS. SPKG1-0: Select Speaker-Amp Output Gain (See Table 24) SPKG1-0 bits Gain 00 0dB 01 +2.2dB 10 +4.4dB 11 +8.7dB Table 24. Gain of Speaker-Amp MGAIN1: Mic-Amplifier Gain Control(See Table 23) ALC1M IPGA ALC2S DACM MIX ALC2 SPK DAC BEEPS BEEP ALC1A DACA AOUT BEEPA Figure 41. Speaker and Mono Lineout-Amps switch control MS0317-E-01 2004/11 - 47 - ASAHI KASEI [AK4631] AOPSN: Mono Line Output Power-Save Mode 0: Normal Operation 1: Power-Save Mode (Default) Power-save mode is enable at AOPSN bit = “1”. POP noise at power-up/down can be reduced by changing at AOPSN bit = “1”. (See Figure 33) Addr 04H Register Name Mode Control 1 Default D7 PLL3 0 D6 PLL2 0 D5 PLL1 0 D4 PLL0 0 D3 BCKO1 0 D2 BCKO0 0 D1 DIF1 1 D0 DIF0 0 DIF1-0: Audio Interface Format (See Table 25) Mode 0 1 2 3 DIF1 bit 0 0 1 1 DIF0 bit 0 1 0 1 SDTO (ADC) SDTI (DAC) DSP Mode DSP Mode MSB justified LSB justified MSB justified MSB justified I2S compatible I2S compatible Table 25. Audio Interface Format BICK ≥ 16fs ≥ 32fs ≥ 32fs ≥ 32fs Figure See Table 31 Figure 26 Figure 27 Figure 28 Default BCKO1-0: Select BICK output frequency at Master Mode (See Table 26) Mode 0 1 2 3 BICK Output Frequency 0 0 16fs 0 1 32fs 1 0 64fs 1 1 N/A Table 26. BICK Output Frequency at Master Mode BCKO1 bit BCKO0 bit Default PLL3-0: Select input frequency at PLL mode (See Table 27) Mode 0 1 2 3 4 5 6 7 12 13 Others PLL3 bit 0 0 0 0 0 0 0 0 1 1 PLL2 bit 0 0 0 0 1 1 1 1 1 1 PLL1 bit 0 0 1 1 0 0 1 1 0 0 PLL0 bit 0 1 0 1 0 1 0 1 0 1 PLL Reference Input Clock Input Pin Frequency FCK pin 1fs BICK pin 16fs BICK pin 32fs BICK pin 64fs MCKI pin 11.2896MHz MCKI pin 12.288MHz MCKI pin 12MHz MCKI pin 24MHz MCKI pin 13.5MHz MCKI pin 27MHz Others N/A Table 27. Setting of PLL Mode (*fs: Sampling Frequency) MS0317-E-01 Default 2004/11 - 48 - ASAHI KASEI Addr 05H [AK4631] Register Name Mode Control 2 Default D7 0 0 D6 0 0 D5 FS3 0 D4 MSBS 0 D3 BCKP 0 D2 FS2 0 D1 FS1 0 D0 FS0 0 FS3-0: Setting of Sampling Frequency (See Table 28 and Table 29) and MCKI Frequency (See Table 30) These bits are selected to sampling frequency at PLL mode and MCKI frequency at EXT mode. Mode 0 1 2 3 4 5 6 7 10 11 14 15 Others Mode 0 1 2 3 6 7 Others Mode 0 1 2 3 FS3 bit 0 0 0 0 0 0 0 0 1 1 1 1 FS2 bit 0 0 0 0 1 1 1 1 0 0 1 1 FS1 bit 0 0 1 1 0 0 1 1 1 1 1 1 FS0 bit 0 1 0 1 0 1 0 1 0 1 0 1 Sampling Frequency 8kHz Default 12kHz 16kHz 24kHz 7.35kHz 11.025kHz 14.7kHz 22.05kHz 32kHz 48kHz 29.4kHz 44.1kHz Others N/A Table 28. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” FS3 bit 0 0 0 0 1 1 FS2 bit FS1 bit FS0 bit Sampling Frequency Range Don’t care 0 0 Default 7.35kHz ≤ fs ≤ 8kHz Don’t care 1 0 8kHz < fs ≤ 12kHz Don’t care 0 1 12kHz < fs ≤ 16kHz Don’t care 1 1 16kHz < fs ≤ 24kHz Don’t care 0 1 24kHz < fs ≤ 32kHz Don’t care 1 1 32kHz < fs ≤ 48kHz Others N/A Table 29. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” FS3-2 bits FS1 bit FS0 bit MCKI Input Sampling Frequency Frequency Range Don’t care 0 256fs 0 7.35kHz ≤ fs ≤ 48kHz Don’t care 1 1024fs 0 7.35kHz < fs ≤ 13kHz Don’t care 0 256fs 1 7.35kHz < fs ≤ 48kHz Don’t care 1 512fs 1 7.35kHz < fs ≤ 26kHz Table 30. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) Default BCKP, MSBS: “00” (Default) (See Table 31) MSBS bit BCKP bit Audio Interface Format 0 0 Figure 22 0 1 Figure 23 1 0 Figure 24 1 1 Figure 25 Table 31. Audio Interface Format in Mode 0 MS0317-E-01 Default 2004/11 - 49 - ASAHI KASEI Addr 06H [AK4631] Register Name Timer Select Default D7 DVTM 0 D6 ROTM 0 D5 ZTM1 0 D4 ZTM0 0 D3 WTM1 0 D2 WTM0 0 D1 LTM1 0 D0 LTM0 0 LTM1-0: ALC1 limiter operation period at zero crossing disable (ZELM bit = “1”) (see Table 32) The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is done by the period specified by the LTM1-0 bits. Default is “00” (0.5/fs). ALC1 Limiter Operation Period 8kHz 16kHz 0 0 0.5/fs Default 63µs 31µs 0 1 1/fs 125µs 63µs 1 0 2/fs 250µs 125µs 1 1 4/fs 500µs 250µs Table 32. ALC1 Limiter Operation Period at zero crossing disable (ZELM bit=“1”) LTM1 bit LTM0 bit WTM1-0: ALC1 Recovery Waiting Period (see Table 33) A period of recovery operation when any limiter operation does not occur during the ALC1 operation. Default is “00” (128/fs). ALC1 Recovery Operation Waiting Period 8kHz 16kHz 0 128/fs 16ms 8ms 1 256/fs 32ms 16ms 0 512/fs 64ms 32ms 1 1024/fs 128ms 64ms Table 33. ALC1 Recovery Operation Waiting Period WTM1 bit 0 0 1 1 WTM0 bit Default ZTM1-0: ALC1 Zero crossing timeout Period (see Table 34) When the IPGA perform zero crossing or timeout, the IPGA value is changed by the µP WRITE operation, ALC1 recovery operation or ALC1 limiter operation (ZELM bit = “0”). Default is “00” (128/fs). ZTM1 bit 0 0 1 1 Zero Crossing Timeout Period 8kHz 16kHz 0 128/fs 16ms 8ms 1 256/fs 32ms 16ms 0 512/fs 64ms 32ms 1 1024/fs 128ms 64ms Table 34. Zero Crossing Timeout Period ZTM0 bit Default ROTM: Period time for ALC2 Recovery operation, ALC2 Zero Crossing Timeout and ALC2 initializing cycle. 0: 512/fs (Default) 1: 1024/fs The ROTM bit is set during the PMSPK bit = “0”. DVTM : Digital Volume Soft Transition Time Control 0: 1061/fs (Default) 1: 256/fs This is the time to FFH from 00H of DVOL7-0 bits. MS0317-E-01 2004/11 - 50 - ASAHI KASEI Addr 07H [AK4631] Register Name ALC Mode Control 1 Default D7 0 0 D6 ALC2 1 D5 ALC1 0 D4 ZELM 0 D3 LMAT1 0 D2 LMAT0 0 D1 RATT 0 D0 LMTH 0 LMTH: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (see Table 35 ) The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about ±2dB. Default is “0”. LMTH bit 0 1 ALC1 Limiter Detection Level ALC1 Recovery Waiting Counter Reset Level ADC Input ≥ −6.0dBFS −6.0dBFS > ADC Input ≥ −8.0dBFS ADC Input ≥ −4.0dBFS −4.0dBFS > ADC Input ≥ −6.0dBFS Table 35. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level Default RATT: ALC1 Recovery GAIN Step (see Table 36) During the ALC1 recovery operation, the number of steps changed from the current IPGA value is set. For example, when the current IPGA value is 30H and RATT bit = “1” is set, the IPGA changes to 32H by the ALC1 recovery operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value exceeds the reference level (REF6-0 bits), the IPGA value does not increase. RATT bit GAIN STEP 0 1 Default 1 2 Table 36. ALC1 Recovery Gain Step Setting LMAT1-0: ALC1 Limiter ATT Step (see Table 37) During the ALC1 limiter operation, when IPGA output signal exceeds the ALC1 limiter detection level set by LMTH, the number of steps attenuated from the current IPGA value is set. For example, when the current IPGA value is 47H and the LMAT1-0 bits = “11”, the IPGA transition to 43H when the ALC1 limiter operation starts, resulting in the input signal level being attenuated by 2dB (=0.5dB x 4). When the attenuation value exceeds IPGA = “00” (−8dB), it clips to “00”. LMAT1 bit LMAT0 bit ATT STEP 0 0 1 0 1 2 1 0 3 1 1 4 Table 37. ALC1 Limiter ATT Step Setting Default ZELM: Enable zero crossing detection at ALC1 Limiter operation 0: Enable (Default) 1: Disable When the ZELM bit = “0”, the IPGA of each L/R channel perform a zero crossing or timeout independently and the IPGA value is changed by the ALC1 operation. The zero crossing timeout is the same as the ALC1 recovery operation. When the ZELM bit = “1”, the IPGA value is changed immediately. MS0317-E-01 2004/11 - 51 - ASAHI KASEI [AK4631] ALC1: ALC1 Enable 0: ALC1 Disable (Default) 1: ALC1 Enable When ALC1 bit is “1”, the ALC1 operation is enabled. ALC2: ALC2 Enable 0: ALC2 Disable 1: ALC2 Enable (Default) After completing the initializing cycle (512/fs = 64ms @fs=8kHz at ROTM bit = “0”), the ALC2 operation is enabled. When the PMSPK bit changes from “0” to “1” or PDN pin changes from “L” to “H”, the initilization cycle starts. Addr 08H Register Name ALC Mode Control 2 Default D7 0 0 D6 REF6 0 D5 REF5 1 D4 REF4 1 D3 REF3 0 D2 REF2 1 D1 REF1 1 D0 REF0 0 REF6-0: Reference value at ALC1 Recovery Operation (see Table 38) During the ALC1 recovery operation, if the IPGA value exceeds the setting reference value by gain operation, then the IPGA does not become larger than the reference value. For example, when REF7-0 = “30H”, RATT = 2step, IPGA = 2FH, even if the input signal does not exceed the “ALC1 Recovery Waiting Counter Reset Level”, the IPGA does not change to 2FH + 2step = 31H, and keeps 30H. Default is “36H”. DATA (HEX) GAIN (dB) STEP 47 +27.5 46 +27.0 45 +26.5 : : 36 +19.0 Default : : 10 +0.0 : : 0.5dB 06 −5.0 05 −5.5 04 −6.0 03 −6.5 02 −7.0 01 −7.5 00 −8.0 Table 38. Setting Reference Value at ALC1 Recovery Operation MS0317-E-01 2004/11 - 52 - ASAHI KASEI Addr 09H Register Name Input PGA Control Default [AK4631] D7 0 0 D6 IPGA6 0 D5 IPGA5 0 D4 IPGA4 1 D3 IPGA3 0 D2 IPGA2 0 D1 IPGA1 0 D0 IPGA0 0 IPGA6-0: Input Analog PGA (see Table 39) Default: “10H” (0dB) When IPGA gain is changed, IPGA6-0 bits should be written while PMMIC bit is “1” and ALC1 bit is “0”. IPGA6-0 bits should be set at 2/fs(250µs@fs=8kHz) after PMMIC bit is set to “1”. IPGA gain is reset when PMMIC bit is “0”, and then IPGA operation starts from the default value when PMMIC bit is changed to “1”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set automatically by ALC1 operation. In a manual mode, IPGA can be set to any values in Table 39.The ZTM1-0 bits set zero crossing timeout period when IPGA value is changed. When the control register is written from the µP, the zero crossing counter is reset and its counter starts. When the signal zero crossing or zero crossing timeout, the written value from the µP becomes valid. DATA (HEX) GAIN (dB) STEP 47 +27.5 46 +27.0 45 +26.5 : : 36 +19.0 : : 10 +0.0 : : 0.5dB 06 −5.0 05 −5.5 04 −6.0 03 −6.5 02 −7.0 01 −7.5 00 −8.0 Table 39. Input Gain Setting Addr 0AH Register Name Digital Volume Control Default D7 DVOL7 0 D6 DVOL6 0 D5 DVOL5 0 D4 DVOL4 1 Default D3 DVOL3 1 D2 DVOL2 0 D1 DVOL1 0 D0 DVOL0 0 DVOL7-0: Output Digital Volume (see Table 40) The AK4631 has a digital output volume (256 levels, 0.5dB step, Mute). The gain can be set by the DVOL7-0 bits. The volume is included in front of a DAC block, a input data of DAC is changed from +12 to –115dB with MUTE. This volume has a soft transition function. It takes 1061/fs (=133ms @ fs = 8kHz) or 256/fs (=32ms @ fs = 8kHz) from 00H to FFH. Soft Transition Time is set by DVTM bit. DVOL7-0 Gain 00H +12.0dB 01H +11.5dB 02H +11.0dB • • 18H 0dB Default • • FDH −114.5dB FEH −115.0dB FFH MUTE (−∞) Table 40. Digital Volume Code Table MS0317-E-01 2004/11 - 53 - ASAHI KASEI Addr 0BH [AK4631] Register Name ALC2 Mode Control Default D7 0 0 D6 0 0 D5 RFS5 1 D4 RFS4 1 D3 RFS3 1 D2 RFS2 1 D1 RFS1 0 D0 RFS0 0 RFS6-0: Reference value at ALC2 Recovery Operation (see Table 41) REFS5-0 bits Volume[dB] Step 3F +19.5 3E +19.0 3D +18.5 3C +18.0 Default : : 0.5dB 19 +0.5 18 +0.0 17 -0.5 : : 03 -10.5 02 -11.0 01 -11.5 00 -12.0 Table 41. Setting Reference Value at ALC2 Recovery Operation MS0317-E-01 2004/11 - 54 - ASAHI KASEI [AK4631] SYSTEM DESIGN Figure 42 shows the system connection diagram. An evaluation board [AKD4631] is available which demonstrates the optimum layout, power supply arrangements and measurement results. 20k C MOUT 22 AOUT 23 AIN 25 BEEP 24 MIN 21 3 AVDD SVDD 19 4 VCOC SPN 18 Top View 7 CCLK MCKI 15 10µ + R2 Analog Supply 2.6∼5.25V Speaker R1 ZD2 14 DVSS MCKO 16 13 DVDD 6 CSN 12 BICK SPP 17 11 FCK 5 PDN 8 CDTI Rp SVSS 20 10 SDTO Cp 2.6∼3.6V 0.1µ 1µ 0.1µ 0.1µ + 220 R 2 AVSS 9 SDTI 10µ Analog Supply 1 VCOM 0.1µ 0.22µ MICOUT 26 MPI 28 + 2.2µ MIC 27 1µ 2.2k ZD1 Dynamic SPK : R1,R2 : Short ZD1,ZD2 : Open Peizo SPK : R1,R2 : 10Ω ZD1,ZD2 : Required 0.1µ 10 + 10µ DSP or µP Figure 42. Typical Connection Diagram Notes: - AVSS, DVSS and SVSS of the AK4631 should be distributed separately from the ground of external controllers. - All digital input pins except pull-down pin should not be left floating. - Value of R and C of BEEP pin should depend on system. - When the AK4631 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed. - When the AK4631 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 42. - Input resistance of AIN pin and Capacitance between MICOUT pin and AIN pin compose of HPF. When the capacitance is 0.22µF, the cut off frequency is typ.72Hz(typ)(min. 48Hz, max. 145Hz). Mode PLL3 bit PLL2 bit PLL1 bit PLL0 bit 0 1 2 3 4 5 6 7 12 13 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 Others Others PLL Reference Clock Input Pin Input Frequency Rp and Cp of VCOC pin Rp[Ω] Cp[F] 6.8k 220n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 10n 10k 10n FCK pin 1fs BICK pin 16fs BICK pin 32fs BICK pin 64fs MCKI pin 11.2896MHz MCKI pin 12.288MHz MCKI pin 12MHz MCKI pin 24MHz MCKI pin 13.5MHz MCKI pin 27MHz N/A Table 42. Setting of PLL Mode (*fs: Sampling Frequency) MS0317-E-01 PLL Lock Time (max) 160ms 2ms 2ms 2ms 40ms 40ms 40ms 40ms 40ms 40ms Default 2004/11 - 55 - ASAHI KASEI [AK4631] 1. Grounding and Power Supply Decoupling The AK4631 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and SVDD are usually supplied from the system’s analog supply. If AVDD, DVDD and SVDD are supplied separately, the correct power up sequence should be observed. AVSS, DVSS and SVSS of the AK4631 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4631 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference VCOM is a signal ground of this chip. A 2.2µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4631. 3. Analog Inputs The Mic and Beep inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp for the Mic input and 0.6 x AVDD Vpp for the Beep input, centered around the internal common voltage (approx. 0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2πRC). The AK4631 can accept input voltages from AVSS to AVDD. 4. Analog Outputs The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). Mono output from the MOUT pin and Mono Line Output from the AOUT pin are centered at 0.45 x AVDD (typ). The Speaker-Amp output is centered at SVDD/2. MS0317-E-01 2004/11 - 56 - ASAHI KASEI [AK4631] CONTROL SEQUENCE Clock Set up When ADC, DAC, ALC1, ALC2 and IPGA are used, the clocks must be supplied. 1. In case of PLL Master Mode. Power Supply Example: (1) Audio I/F Format: DSP Mode, BCKP = MSBS = “0” BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO : Enable Sampling Frequency:8kHz PDN pin (2) (3) PMVCM bit (Addr:00H, D6) (4) MCKPD bit (1) Power Supply & PDN pin = “L” Æ “H” (Addr:01H, D2) (5) MCKO bit (Addr:01H, D1) (2)Addr:01H, Data:0CH Addr:04H, Data:48H Addr:05H, Data:00H PMPLL bit (Addr:01H, D0) (6) MCKI pin Input (3)Addr:00H, Data:40H M/S bit (Addr:01H, D3) 40msec(max) (7) BICK pin FCK pin (4)Addr:01H, Data:0BH Output (8) 1msec (max) MCKO, BICK and FCK output 40msec(max) (10) MCKO pin (9) Output Figure 43. Clock Set Up Sequence (1) <Example> (1) After Power Up, PDN pin = “L” Æ “H” “L” time (1) of 150ns or more is needed to reset the AK4631. (2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits should be set during this period. (3) Power UpVCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered-up before the other block operates. (4) Release the pull-down resistor of the MCKI pin: MCKPD bit = “1” → “0” (5) In case of using MCKO output: MCKO bit = “1” In case of not using MCKO output: MCKO bit = “0” (6) PLL lock time is 40ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source. (7) The AK4631 starts to output the FCK and BICK clocks after the PLL becomes stable. The normal operation of the block which a clock is necessary for becomes possible. (8) The invalid frequencies are output from FCK and BICK pins during this period. (9) The invalid frequency is output from MCKO pin during this period. (10) The normal clock is output from MCKO pin after the PLL is locked. MS0317-E-01 2004/11 - 57 - ASAHI KASEI [AK4631] 2. When the external clocks (FCK or BICK pin) are used in PLL Slave Mode. Example: Power Supply Audio I/F Format : DSP Mode, BCKP = MSBS = “0” PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz (1) PDN pin (2) (3) 4fs (1)ofPower Supply & PDN pin = “L” Æ “H” PMVCM bit (Addr:00H, D6) MCKPD bit (2) Addr:04H, Data:30H Addr:05H, Data:00H (4) "H" (Addr:01H, D2) PMPLL bit (Addr:01H, D0) (3) Addr:00H, Data:40H FCK pin BICK pin Input (5) (4) Addr:01H, Data:05H Internal Clock (6) BICK and FCK input Figure 44. Clock Set Up Sequence (2) <Example> (1) After Power Up: PDN pin “L” Æ “H” “L” time (1) of 150ns or more is needed to reset the AK4631. (2) DIF1-0, FS3-0, PLL3-0, MSBS and BCKP bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered up before the other block operates. (4) Pull down of the MCKI pin: MCKPD bit = “1” (5) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (FCK or BICK pin) is supplied. PLL lock time is 160ms(max) when FCK is a PLL reference clock. And PLL lock time is 2ms(max) when BICK is a PLL reference clock. (6) Normal operation stats after the PLL is locked. MS0317-E-01 2004/11 - 58 - ASAHI KASEI [AK4631] 3. When the external clock (MCKI pin) is used in PLL Slave Mode. Example: Audio I/F Format: DSP Mode, BCKP = MSBS = “0” BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO : Enable Sampling Frequency:8kHz Power Supply (1) PDN pin (2) (3) PMVCM bit (1) Power Supply & PDN pin = “L” Æ “H” (Addr:00H, D6) (4) MCKPD bit (Addr:01H, D2) (2)Addr:01H, Data:04H Addr:04H, Data:48H Addr:05H, Data:00H (5) MCKO bit (Addr:01H, D1) PMPLL bit (Addr:01H, D0) (3)Addr:00H, Data:40H (6) MCKI pin Input (4)Addr:01H, Data:03H 40msec(max) (7) MCKO pin Output (8) MCKO output start (9) BICK pin FCK pin Input BICK and FCK input start Figure 45. Clock Set Up Sequence (3) <Example> (1) After Power Up: PDN pin “L” Æ “H” “L” time (1) of 150ns or more is needed to reset the AK4631. (2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered up before the other block operates. (4) Release the pull-down resistor of the MCKI pin: MCKPD bit = “1” → “0” (5) Enable MCKO output: MCKO bit = “1” (6) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied. PLL lock time is 40ms(max). (7) The normal clock is output from MCKO after PLL is locked. (8) The invalid frequency is output from MCKO during this period. (9) BICK and FCK clocks should be synchronized with MCKO clock. MS0317-E-01 2004/11 - 59 - ASAHI KASEI [AK4631] 4. EXT Slave Mode Example Audio I/F Format:MSB justified (ADC and DAC) Input MCKI frequency: 1024fs Sampling Frequency:8kHz MCKO: Disable Power Supply (1) (1) Power Supply & PDN pin = “L” Æ “H” PDN pin (2) (3) PMVCM bit (Addr:00H, D6) (2) Addr:04H, Data:02H Addr:05H, Data:01H MCKPD bit (Addr:01H, D2) (4) (3) Addr:00H, Data:40H PMPLL bit (Addr:01H, D0) "L" (5) MCKI pin Input (4) Addr:01H, Data:00H (5) FCK pin BICK pin Input MCKI, BICK and FCK input Figure 46. Clock Set Up Sequence (4) <Example> (1) After Power Up: PDN pin “L” Æ “H” “L” time (1) of 150ns or more is needed to reset the AK4631. (2) DIF1-0 and FS1-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered up before the other block operates. (4) Release the pull-down resistor of the MCKI pin: MCKPD bit = “1” Æ “0” Power down PLL: PMPLL bit = “0” (5) Normal operation starts after the MCKI, FCK and BICK are supplied. MS0317-E-01 2004/11 - 60 - ASAHI KASEI [AK4631] MIC Input Recording Example: FS3-0 bits (Addr:05H, D5,D2-0) XXXX MIC Control (Addr:02H, D2-0) ALC1 Control 1 (Addr:06H) ALC1 Control 2 (Addr:08H) ALC1 Control 3 (Addr:07H) PLL Master Mode Audio I/F Format:DSP Mode, BCKP=MSBS=“0” Sampling Frequency:8kHz Pre MIC AMP:+20dB MIC Power On ALC1 setting:Refer to Figrure 29 ALC2 bit=“1”(default) XXX (1) 001 X1X (1) Addr:05H, Data:00H 00H (2) Addr:02H, Data:07H 47H (3) Addr:06H, Data:00H 61H or 21H (4) Addr:08H, Data:47H (2) XXH (3) XXH (4) XXH (5) ALC1 State ALC1 Disable ALC1 Enable ALC1 Disable (5) Addr:07H, Data:61H PMADC bit (6) Addr:00H, Data:43H (Addr:00H, D0) (6) PMMIC bit 1059 / fs (Addr:00H, D1) ADC Internal State (7) Power Down Recording Initialize Normal State Power Down (7) Addr:00H, Data:40H Figure 47. MIC Input Recording Sequence <Example> This sequence is an example of ALC1 setting at s=8kHz. If the parameter of the ALC1 is changed, please refer to “Figure 30. Registers set-up sequence at the ALC1 operation” At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bit). When the AK4631 is PLL mode, MIC and ADC should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up MIC input (Addr: 02H) (3) Set up Timer Select for ALC1 (Addr: 06H) (4) Set up REF value for ALC1 (Addr: 08H) (5) Set up LMTH, RATT, LMAT1-0 and ALC1 bits (Addr: 07H) (6) Power Up MIC and ADC: PMMIC bit = PMADC bit = “0” → “1” The initialization cycle time of ADC is 1059/fs=133ms@fs=8kHz. After the ALC1 bit is set to “1” and MIC block is powered-up, the ALC1 operation starts from IPGA default value (0dB). (7) Power Down MIC and ADC: PMMIC bit = PMADC bit = “1” → “0” When the registers for the ALC1 operation are not changed, ALC1 bit may be keeping “1”. The ALC1 operation is disabled because the MIC block is powered-down. If the registers for the ALC1 operation are also changed when the sampling frequency is changed, it should be done after the AK4631 goes to the manual mode (ALC1 bit = “0”) or MIC block is powered-down (PMMIC bit = “0”). IPGA gain is reset when PMMIC bit is “0”, and then IPGA operation starts from the default value when PMMIC bit is changed to “1”. MS0317-E-01 2004/11 - 61 - ASAHI KASEI [AK4631] Speaker-amp Output Example: FS2-0 bits (Addr:05H, D5, D2-0) XXXX PLL, Master Mode Audio I/F Format :DSP Mode, BCKP=MSBS= “0” Sampling Frequency: 8kHz Digital Volume: -8dB ALC2 : Enable XXXX (1) (8) DACM bit (1) Addr:05H, Data:00H (Addr:02H, D3) (2) ALC2S bit (2) Addr:02H, Data:28H (Addr:02H, D5) ALC2 bit (Addr:07H, D6) DVOL7-0 bits (Addr:0AH, D7-0) 0 (3) Addr:07H, Data:40H X (3) 0001100 (4) Addr:0AH, Data:28H XXXXXXX (4) (9) PMDAC bit (5) Addr:00H, Data:54H (Addr:00H, D2) (5) PMSPK bit (6) Addr:02H, Data:A8H (Addr:00H, D4) (6) SPPS bit Playback (Addr:02H, D7) (7) SPP pin SPN pin Hi-Z Hi-Z Normal Output SVDD/2 Normal Output Hi-Z SVDD/2 (7) Addr:02H, Data:28H Hi-Z (8) Addr:00H, Data:40H Figure 48. Speaker-Amp Output Sequence <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4631 is PLL mode, DAC and Speaker-Amp should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up the path of “DAC Æ SPK-Amp” DACM = ALC2S bit: “0” Æ “1” (3) Set up the ALC2 Enable/Disable (4) Set up the digital volume (Addr: 0AH) After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft transition. (5) Power Up of DAC and Speaker-Amp: PMDAC bit = PMSPK bit = “0” → “1” When ALC2 bit = “1”, the ALC2 is disabled (ALC2 gain is fiexed to “–2dB”) during the initilization cycle (512/fs = 64ms @ fs=8kHz, ROTM bit = “0”) and the ALC2 starts from “–2dB” after completing the initilization cycle. (6) Exit the power-save-mode of Speaker-Amp: SPPS bit = “0” → “1” “(6)” time depends on the time constant of input impedance of MIN pin and capacitor between MIN pin and MOUT pin. If Speaker-Amp output is enabled before MIN-Amp (ALC2) becomes stable, pop noise may occur. e.g. Input Impedance of MIN pin =36kΩ (max), C=0.1µF: Recommended wait time is more than 5τ = 18ms. (7) Enter the power-save-mode of Speaker-Amp: SPPS bit = “1” → “0” (8) Disable the path of “DAC Æ SPK-Amp” DACM = ALC2S bit: “1” Æ “0” (9) Power Down DAC and Speaker-Amp: PMDAC bit = PMSPK bit = “1” → “0” MS0317-E-01 2004/11 - 62 - ASAHI KASEI [AK4631] BEEP signal output from Speaker-Amp Clocks can be stopped. CLOCK ALC2 bit (Addr:07H, D6) 0 or 1 Example: (1) Addr:07H, Data:00H 0 (1) (2) Addr:00H, Data:70H PMBP bit (Addr:00H, D2) (2) (6) PMSPK bit (3) Addr:02H, Data:60H (Addr:00H, D4) ALC2S bit (Addr:02H, D5) 0 or 1 (4) Addr:02H, Data:E0H 0 (3) (7) BEEPS bit (Addr:02H, D6) BEEP Signal Output (4) SPPS bit (Addr:02H, D7) (5) Addr:02H, Data:60H (5) SPP pin Hi-Z Normal Output Hi-Z (6) Addr:00H, Data:40H SPN pin Hi-Z SVDD/2 Normal Output SVDD/2 Hi-Z (7) Addr:02H, Data:00H Figure 49. “BEPP-Amp Æ Speaker-Amp” Output Sequence <Example> The clocks can be stopped when only BEEP-Amp and Speaker-Amp are operating. However ALC2 must be disabled. (1) ALC2 Disable: ALC2 bit = “0” (2) Power Up BEEP-Amp and Speaker-Amp: PMBP bit = PMSPK bit = “0” → “1” (3) Disable the path of “ALC2 Æ SPK-Amp”: ALC2S bit = “0” Enable the path of “BEEP Æ SPK-Amp”: BEEPS bit = “0” → “1” (4) Exit the power-save-mode of Speaker-Amp: SPPS bit = “0” → “1” “(4)” time depends on the time constant of external resistor and capacitor connected to BEEP pin. If Speaker-Amp output is enabled before input of BEEP-Amp becomes stable, pop noise may occur. e.g. R=20k, C=0.1µF: Recommended wait time is more than 5τ = 10ms. (5) Enter the power-save-mode of Speaker-Amp: SPPS bit = “1” → “0” (6) Power Down BEEP-Amp and Speaker-Amp: PMBP bit = PMSPK bit = “1” → “0” (7) Disable the path of “BEEP Æ SPK-Amp”: BEEPS bit = “1” → “0” MS0317-E-01 2004/11 - 63 - ASAHI KASEI [AK4631] MONO LINEOUT 1. In case of using an external mute circuit.(Compatible with AK4536/AK4630) Example: PLL, Master Mode Audio I/F Format :DSP Mode, BCKP=MSBS= “0” Sampling Frequency: 8kHz Digital Volume: -8dB FS3-0 bits (Addr:05H, D5,D2-0) XXXX XXXX (1) Addr:05H, Data:00H (1) (6) DACA bit (2) (2) Addr:02H, Data:10H (Addr:02H, D4) (3) DVOL7-0 bits (Addr:0AH, D7-0) 00011000 (3) Addr:0AH, Data:28H XXXXXXX PMDAC bit (4) Addr:00H, Data:4CH (Addr:00H, D2) (5) (4) PMAO bit Playback (Addr:00H, D3) AOUT pin Hi-Z Normal Output Hi-Z (5) Addr:00H, Data:40H (6) Addr:02H, Data:00H Figure 50. Mono Lineout Sequence <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4631 is PLL mode, DAC and Mono Line Amp should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up the path of “DAC Æ Mono Line Amp” DACA bit: “0” Æ “1” (3) Set up the digital volume (Addr: 0AH) After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft transition. (4) Power Up of DAC and Mono Line Amp: PMDAC bit = PMAO bit = “0” → “1” When DAC and Mono Line Amp are powered-up, the pop noise occurs from AOUT pin. Therefore AOUT pin should be muted by external circuit. (5) Power Down of DAC and Mono Line Amp: PMDAC bit = PMAO bit = “1” Æ “0” When DAC and Mono Line Amp are powered-down, the pop noise occurs from AOUT pin. Therefore AOUT pin should be muted by external circuit. (6) Disable the path of “DAC Æ Mono Line Amp” DACA bit: “1” Æ “0” MS0317-E-01 2004/11 - 64 - ASAHI KASEI [AK4631] 2. In case of using POP reduction circuit of AK4631. Example: PLL, Master Mode Audio I/F Format :DSP Mode, BCKP=MSBS= “0” Sampling Frequency: 8kHz Digital Volume: -8dB MGAIN1=SPKG1=SPKG0=BEEPA=ALC1M =ALC1A= “0” (1) Addr:05H, Data:00H (2) Addr:02H, Data:10H FS2-0 bits (Addr:05H, D5,D2-0) XXXX XXXX (3) Addr:0AH, Data:28H (1) (9) DACA bit (4) Addr:03H, Data:40H (2) (Addr:02H, D4) (3) DVOL7-0 bits (Addr:0AH, D7-0) (5) Addr:00H, Data:4CH 00011000 XXXXXXX (6) Addr:03H, Data:00H PSAON bit (Addr:03H, D6) (7) (6) (4) (10) Playback PMDAC bit (Addr:00H, D2) (7) Addr:03H, Data:40H (5) (8) PMAO bit (Addr:00H, D3) (8) Addr:00H, Data:40H >300 ms >300 ms AOUT pin Normal Output (9) Addr:02H, Data:00H (10) Addr:03H, Data:00H Figure 51. Mono Lineout Sequence <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4631 is PLL mode, DAC and Mono Line Amp should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up the path of “DAC Æ Mono Line Amp” : DACA bit: “0” Æ “1” (3) Set up the digital volume (Addr: 0AH) After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft transition. (4) Enter power-save mode of Mono Line Amp: AOPSN bit = “0” → “1” (5) Power Up of DAC and Mono Line Amp: PMDAC bit = PMAO bit = “0” → “1” AOUT pin rises up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1µF. (6) Exit power-save mode of Mono Line Amp after AOUT pin rises up. : AOPSN bit = “1” → “0” Mono Line Amp goes to normal operation. (7) Enter power-save mode of Mono Line Amp: AOPSN bit = “0” → “1” (8) Power Down of DAC and Mono Line Amp: PMDAC bit = PMAO bit = “1” Æ “0” AOUT pin falls down to AVSS. Fall time is 200ms (max 300ms) at C=1µF. (9) Disable the path of “DAC Æ Mono Line Amp” : DACA bit: “1” Æ “0” (10) Exit power-save mode of Mono Line Amp after AOUT pin falls down. : AOPSN bit = “1” → “0” MS0317-E-01 2004/11 - 65 - ASAHI KASEI [AK4631] Stop of Clock Master clock can be stopped when ADC, DAC, ALC1, ALC2 and IPGA don’t operate. 1. In case of PLL Master Mode Example: (1) Audio I/F Format: DSP Mode, BCKP = MSBS = “0” BICK frequency at Master Mode : 64fs Input Master Clock Select at PLL Mode : 11.2896MHz Sampling Frequency:8kHz PMPLL bit (Addr:01H,D0) (2) MCKO bit "H" or "L" (1) (2) (3) Addr:01H, Data:0CH (Addr:01H,D1) (3) MCKPD bit Stop an external MCKI (Addr:01H,D2) (4) External MCKI Input Figure 52. Clock Stopping Sequence (1) <Example> (1) Power down PLL: PMPLL bit = “1” → “0” (2) Stop MCKO clock: MCKO bit = “1” → “0” (3) Pull down the MCKI pin: MCKPD bit = “0” → “1” When the external master clock becomes Hi-Z, MCKI pin should be pulled down. (4) Stop an external master clock. 2. When an external clocks (FCK or BICK pins) are used in PLL Slave Mode. Example Audio I/F Format : DSP Mode, BCKP = MSBS = “0” PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz (1) PMPLL bit (Addr:01H,D0) (2) External BICK Input (1) Addr:01H, Data:04H (2) External FCK Input (2) Stop the external clocks Figure 53. Clock Stopping Sequence (2) <Example> (1) Power down PLL: PMPLL bit = “1” → “0” (2) Stop the external BICK and FCK clocks MS0317-E-01 2004/11 - 66 - ASAHI KASEI [AK4631] 3. When an external clock (MCKI pin) is used in PLL Slave Mode. (1) PMPLL bit (Addr:01H,D0) (1) Example MCKO bit Audio I/F Format : DSP Mode, BCKP = MSBS = “0” PLL Reference clock: MCKI BICK frequency: 64fs Sampling Frequency: 8kHz (Addr:01H,D1) (1) MCKPD bit (Addr:01H,D2) (1) Addr:01H, Data:04H (2) External MCKI Input (2) Stop the external clocks Figure 54. Clock Stopping Sequence (3) <Example> (1) Power down PLL: PMPLL bit = “1” → “0” Stop MCKO output: MCKO bit = “1” → “0” Pull down the MCKI pin: MCKPD bit = “0” → “1” When the external master clock becomes Hi-Z, MCKI pin should be pulled down. (2) Stop the external master clock. 4. EXT Slave Mode Example Audio I/F Format :MSB justified(ADC and DAC) Input MCKI frequency:1024fs Sampling Frequency:8kHz (1) MCKPD bit (Addr:01H,D2) (2) External MCKI Input External BICK Input External FCK Input (1) Addr:01H, Data:04H (2) (2) Stop the external clocks (2) Figure 55. Clock Stopping Sequence (4) <Example> (1) Pull down the MCKI pin: MCKPD bit = “0” → “1” When the external master clock becomes Hi-Z, MCKI pin should be pulled down. (2) Stop the external MCKI, BICK and FCK clocks. Power down If the clocks are supplied, power down VCOM (PMVCM bit: “1” → “0”) after all blocks except for VCOM are powered-down and a master clock stops. The AK4631 is also powered-down by PDN pin = “L”. When PDN pin = “L”, the registers are initialized. MS0317-E-01 2004/11 - 67 - ASAHI KASEI [AK4631] PACKAGE • 28pin QFN (Unit: mm) 0. 55 ± 2 0. C 4- 0 5.2 ± 0.20 25 6 0. 0. ± 5.0 ± 0.10 0. 5.0 ± 0.10 5.2 ± 0.20 10 28 1 0.60 ± 0.10 0.80 +0.20 0.05 -0.02 M 0.02 +0.03 0.21 ± 0.05 0.50 0.05 -0.10 0.22 ± 0.05 Note) The part of black at four corners on reverse side must not be soldered and must be open. Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate (Pb free) MS0317-E-01 2004/11 - 68 - ASAHI KASEI [AK4631] MARKING 4631 XXXXX 1 XXXX : Date code identifier (5 digits) Revision History Date (YY/MM/DD) 04/06/15 04/11/19 Revision 00 01 Reason First Edition Addition of explanation Page Contents 4-6 Some explanation of “Compare with AK4536 and AK4630 are added Recommended Operating Conditions : Note 6 is added for Speaker-Amp. “Note 6. SVDD = 2.6 ∼ 3.6V when 8Ω dynamic speaker is connected to the AK4631.” 8 IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0317-E-01 2004/11 - 69 -