AKM AK5386

ASAHI KASEI
[AK5386]
AK5386
Single-ended 24-Bit 192kHz ∆Σ ADC
GENERAL DESCRIPTION
The AK5386 is a stereo A/D Converter with wide sampling rate of 8kHz ∼ 216kHz and is suitable for
consumer to professional audio system. The AK5386 achieves high accuracy and low cost by using
Enhanced dual bit ∆Σ techniques. The AK5386 requires no external components because the analog
inputs are single-ended. The audio interface has two formats (MSB justified, I2S) and can correspond to
various systems like DVD Recorder, AV Receiver, PC Sound card and Music Instrument recording.
FEATURES
† Single-ended Input
† Digital HPF for DC-Offset cancel
† S/(N+D): 96dB
† DR:
110dB
† S/N:
110dB
† Linear Phase Digital Anti-Alias Filtering
Passband: 0 ∼ 21.768kHz (@ fs=48kHz)
Passband Ripple: ±0.005dB
Stopband Attenuation: 80dB
† Master Clock: 512fs/768fs
(Normal Speed)
256fs/384fs (Double Speed)
128fs/192fs (Quad Speed)
† Sampling Frequency:
Normal Speed: 8kHz ∼ 54kHz
(512fs)
8kHz ∼ 48kHz
(768fs)
Double Speed: 54kHz ∼ 108kHz (256fs)
48kHz ∼ 96kHz
(384fs)
∼
Quad Speed: 108kHz 216kHz (128fs)
96kHz ∼ 192kHz
(192fs)
† Master / Slave Mode
2
† Audio Interface: 24bit MSB justified / I S selectable
† Input level: CMOS
† Power Supply:
Analog: 4.5 ∼ 5.5V
Digital: 2.7 ∼ 3.6V (Normal Speed)
3.0 ∼ 3.6V (Double Speed, Quad Speed)
† Ta = −40 ∼ 85°C
† Small 16pin TSSOP Package
† AK5357/58/59/81 Pin-compatible
MS0579-E-00
2006/12
-1-
ASAHI KASEI
[AK5386]
VA AGND
MCLK
VD DGND
Clock Divider
AINL
AINR
VCOM
∆Σ
Modulator
Decimation
Filter
∆Σ
Modulator
Decimation
Filter
SCLK
Serial I/O
Interface
Voltage Reference
CKS2 CKS1
LRCK
CKS0
PDN
SDTO
DIF
Block Diagram
„ Compatibility with AK5357, AK5358, AK5359, AK5381 and AK5386
fs
S/(N+D)
DR
MCLK @ 48kHz
VIH @ TTL Level
Mode
VA(Analog Supply)
AK5357
4kHz to 96kHz
88dB
102dB
AK5358
8kHz to 96kHz
92dB
102dB
AK5381
4kHz to 96kHz
96dB
106dB
AK5359
8kHz to 216kHz
94dB
102dB
256/512/384/768fs
256/512/384/768fs
256/512/384/768fs
256/512/384/768fs
AK5386
8kHz to 216kHz
96dB
110dB
512/768fs
2.2V
2.2V
2.4V
Not Available
Not Available
2.7 to 5.5V
4.5 to 5.5V
4.5 to 5.5V
VD (Digital Supply)
2.7 to 5.5V
2.7 to 5.5V
Available
ET: −20∼+85°C
VT: −40∼+85°C
Not Available
ET: −20∼+85°C
4.5 to 5.5V
2.7 to 5.5V
3.0 to [email protected]
fs=96kHz
Available
ET: −20∼+85°C
VT: −40∼+85°C
XT: −40∼+85°C
4.5 to 5.5V
2.7 to 3.6V
3.0 to 3.6V @
fs=96k, 192kHz
Available
VT: −40∼+85°C
HPF Disable
Operating
Temperature
MS0579-E-00
2.7 to 5.5V
Available
ET: −20∼+85°C
VT: −40∼+85°C
2006/12
-2-
ASAHI KASEI
[AK5386]
„ Ordering Guide
16pin TSSOP (0.65mm pitch)
−40 ∼ +85°C
Evaluation Board for AK5386
AK5386VT
AKD5386
„ Pin Layout
AINR
1
16
CKS0
AINL
2
15
CKS2
CKS1
3
14
DIF
VCOM
4
13
PDN
AGND
5
12
SCLK
VA
6
11
MCLK
VD
7
10
LRCK
DGND
8
9
SDTO
Top View
PIN / FUNCTION
No. Pin Name
1
2
3
AINR
AINL
CKS1
I/O
Function
I
I
I
Rch Analog Input Pin
Lch Analog Input Pin
Mode Select 1 Pin
Common Voltage Output Pin, VA/2
4 VCOM
O
Bias voltage of ADC input.
5 AGND
Analog Ground Pin
6 VA
Analog Power Supply Pin, 5V
7 VD
Digital Power Supply Pin, 3.3V
8 DGND
Digital Ground Pin
Audio Serial Data Output Pin
9 SDTO
O
“L” Output at Power-down mode.
Output Channel Clock Pin
10 LRCK
I/O
“L” Output in Master Mode at Power-down mode.
11 MCLK
I
Master Clock Input Pin
Audio Serial Data Clock Pin
12 SCLK
I/O
“L” Output in Master Mode at Power-down mode.
Power Down & Reset Mode Pin
13 PDN
I
“H”: Power up, “L”: Power down & Reset
The AK5386 must be reset once upon power-up.
Audio Interface Format Pin
14 DIF
I
“H”: 24bit I2S Compatible, “L”: 24bit MSB justified
15 CKS2
I
Mode Select 2 Pin
16 CKS0
I
Mode Select 0 Pin
Note: Do not allow all digital input pins except for analog input pins (AINL and AINR pins) to float.
MS0579-E-00
2006/12
-3-
ASAHI KASEI
[AK5386]
„ Handling of Unused Pin
The unused input pins should be processed appropriately as below.
Classification
Analog
Pin Name
AINL
AINR
Setting
This pin should be open.
This pin should be open.
ABSOLUTE MAXIMUM RATINGS
(AGND, DGND=0V; Note 1)
Parameter
Symbol
min
Power Supplies:
Analog
VA
−0.3
(Note 2)
Digital
VD
−0.3
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage (AINL, AINR, CKS1 pins)
VINA
−0.3
Digital Input Voltage (Note 3)
VIND
−0.3
Ambient Temperature (powered applied)
Ta
-40
Storage Temperature
Tstg
−65
Note 1. All voltages with respect to ground.
Note 2. AGND and DGND must be connected to the same analog ground plane.
Note 3. DIF, PDN, SCLK, MCLK, LRCK, CKS0 and CKS2 pins
max
6.0
6.0
±10
VA+0.3
VD+0.3
85
150
Units
V
V
mA
V
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND=0V; Note 1)
Parameter
Symbol
Power Supplies
Analog
VA
(Note 4) Digital: Normal Speed
VD
Double/Quad Speed
VD
Note 4. The power up sequence between VA and VD is not critical.
min
4.5
2.7
3.0
typ
5.0
3.3
3.3
max
5.5
3.6
3.6
Units
V
V
V
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0579-E-00
2006/12
-4-
ASAHI KASEI
[AK5386]
ANALOG CHARACTERISTICS
(Ta=25°C; VA=5.0V, VD=3.3V; AGND=DGND=0V; fs=48kHz, 96kHz, 192kHz; SCLK=64fs; Signal
Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=48kHz, 40Hz ∼ 40kHz at fs=96kHz,
40Hz ∼ 40kHz at fs=192kHz; unless otherwise specified)
Parameter
min
typ
max
Units
ADC Analog Input Characteristics:
Resolution
24
Bits
Input Voltage
(Note 5)
2.7
3.0
3.3
Vpp
S/(N+D)
fs=48kHz
86
96
dB
−1dBFS
BW=20kHz
47
dB
−60dBFS
fs=96kHz
86
92
dB
−1dBFS
BW=40kHz
42
dB
−60dBFS
fs=192kHz
90
dB
−1dBFS
BW=40kHz
42
dB
−60dBFS
DR
(−60dBFS with A-weighted)
102
110
dB
S/N
(A-weighted)
102
110
dB
Input Resistance
4
6
kΩ
Interchannel Isolation
95
115
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Gain Drift
100
ppm/°C
Power Supply Rejection
(Note 6)
50
dB
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
VA
20
30
VD
(fs=48kHz)
7
11
VD
(fs=96kHz)
10
15
VD
(fs=192kHz)
10
15
Power down mode (PDN pin = “L”)
(Note 7)
VA+VD
10
100
Note 5. This value is the full scale (0dB) of the input voltage. Input voltage is proportional to VA voltage.
Vin = 0.6 x VA (Vpp).
Note 6. PSR is applied to VA and VD with 1kHz, 50mVpp.
Note 7. All digital input pins are held VD or DGND.
MS0579-E-00
mA
mA
mA
mA
µA
2006/12
-5-
ASAHI KASEI
[AK5386]
FILTER CHARACTERISTICS (fs=48kHz)
(Ta=−40 ∼ 85°C; VA=4.5 ∼ 5.5V; VD=2.7 ∼ 3.6V)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 8) ±0.02dB
PB
0
221.
−0.1dB
22.3
−0.2dB
23.5
−3.0dB
Stopband
SB
26.5
Passband Ripple
PR
Stopband Attenuation
SA
80
Group Delay Distortion
0
∆GD
Group Delay
(Note 9)
GD
29.4
ADC Digital Filter (HPF):
Frequency Response (Note 8) −3dB
FR
1.0
6.5
−0.1dB
FILTER CHARACTERISTICS (fs=96kHz)
(Ta=−40 ∼ 85°C; VA=4.5 ∼ 5.5V; VD=3.0 ∼ 3.6V)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 8) ±0.02dB
PB
0
44.3
−0.1dB
44.6
−0.2dB
47.0
−3.0dB
Stopband
SB
53.0
Passband Ripple
PR
Stopband Attenuation
SA
80
Group Delay Distortion
0
∆GD
Group Delay
(Note 9)
GD
29.4
ADC Digital Filter (HPF):
Frequency Response (Note 8) −3dB
FR
2.0
13.0
−0.1dB
MS0579-E-00
max
Units
21.768
±0.005
-
kHz
kHz
kHz
kHz
kHz
dB
dB
µs
1/fs
-
Hz
Hz
max
Units
43.536
±0.005
-
kHz
kHz
kHz
kHz
kHz
dB
dB
µs
1/fs
-
Hz
Hz
2006/12
-6-
ASAHI KASEI
[AK5386]
FILTER CHARACTERISTICS (fs=192kHz)
(Ta=−40 ∼ 85°C; VA=4.5 ∼ 5.5V; VD=3.0 ∼ 3.6V)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
Passband
(Note 8) ±0.1dB
PB
0
43.8
kHz
52.9
kHz
−0.2dB
90.1
kHz
−3.0dB
Stopband
SB
112
kHz
Passband Ripple
PR
dB
±0.005
Stopband Attenuation
SA
72
dB
Group Delay Distortion
0
∆GD
µs
Group Delay
(Note 9)
GD
16.5
1/fs
ADC Digital Filter (HPF):
Frequency Response (Note 8) −3dB
FR
4.0
Hz
26.0
Hz
−0.1dB
Note 8. The passband and stopband frequencies scale with fs. For example, PB (±0.02dB) at fs=48kHz is 0.4535 × fs. The
reference frequency of these response is 1kHz.
Note 9. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting
of 24bit data both channels to the ADC output register for ADC.
DC CHARACTERISTICS
(Ta=−40 ∼ 85°C; VA=4.5 ∼ 5.5V; VD=2.7 ∼ 3.6V at Normal Speed, VD=3.0 ∼ 3.6V at Double/Quad Speed)
Parameter
Symbol
min
typ
max
High-Level Input Voltage
VIH
70%VD
Low-Level Input Voltage
VIL
30%VD
High-Level Output Voltage
(Iout=−1mA)
VOH
VD−0.5
Low-Level Output Voltage
(Iout=1mA)
VOL
0.5
Input Leakage Current
Iin
±10
MS0579-E-00
Units
V
V
V
V
µA
2006/12
-7-
ASAHI KASEI
[AK5386]
SWITCHING CHARACTERISTICS (Normal Speed)
(Ta=−40 ∼ 85°C; VA=4. 5 ∼ 5.5V; VD=2.7 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
Frequency: 512fs
fCLK
4.096
768fs
fCLK
6.144
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
LRCK
Frequency: 512fs
768fs
Duty Cycle
max
Units
27.648
36.864
-
MHz
MHz
ns
ns
fs
fs
8
8
45
-
50
54
48
55
-
kHz
kHz
%
%
Slave mode
Master mode
Audio Interface Timing
Slave mode
SCLK Period
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SCLK “↑”
(Note 10)
SCLK “↑” to LRCK Edge
(Note 10)
LRCK to SDTO (MSB) (Except I2S mode)
SCLK “↓” to SDTO
Master mode
SCLK Frequency
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
tSCK
tSCKL
tSCKH
tLRSH
tSHLR
tLRS
tSSD
1/128fs
60
60
20
20
-
-
40
40
ns
ns
ns
ns
ns
ns
ns
fSCK
dSCK
tMSLR
tSSD
−20
−20
64fs
50
-
40
40
Hz
%
ns
ns
Reset Timing
PDN Pulse Width
(Note 11)
PDN “↑” to SDTO valid at Slave Mode (Note 12)
PDN “↑” to SDTO valid at Master Mode (Note 12)
tPD
tPDV
tPDV
150
-
4132
4129
-
ns
1/fs
1/fs
MS0579-E-00
2006/12
-8-
ASAHI KASEI
[AK5386]
SWITCHING CHARACTERISTICS (Double / Quad Speed)
(Ta=−40 ∼ 85°C; VA=4. 5 ∼ 5.5V; VD=3.0 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
Frequency: 128fs, 256fs
fCLK
13.824
192fs, 384fs
fCLK
18.432
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
-
max
Units
27.648
36.864
-
MHz
MHz
ns
ns
LRCK
Frequency:
Duty Cycle
Double Speed:256fs
fs
54
-
108
kHz
384fs
-
96
kHz
fs
48
Quad Speed: 128fs
fs
108
-
216
kHz
192fs
fs
96
45
-
50
192
55
-
kHz
%
%
tSCK
tSCK
tSCKL
tSCKH
tLRSH
tSHLR
tLRS
tSSD
1/128fs
1/64fs
33
33
20
20
-
-
20
20
ns
ns
ns
ns
ns
ns
ns
ns
fSCK
dSCK
tMSLR
tSSD
−20
−20
64fs
50
-
20
20
Hz
%
ns
ns
4132
4129
-
ns
1/fs
1/fs
Slave mode
Master mode
Audio Interface Timing
Slave mode
SCLK Period: Double Speed
Quad Speed
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SCLK “↑”
(Note 10)
SCLK “↑” to LRCK Edge
(Note 10)
LRCK to SDTO (MSB) (Except I2S mode)
SCLK “↓” to SDTO
Master mode
SCLK Frequency
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
Reset Timing
tPD
PDN Pulse Width
(Note 11)
150
tPDV
PDN “↑” to SDTO valid at Slave Mode (Note 12)
tPDV
PDN “↑” to SDTO valid at Master Mode (Note 12)
Note 10. SCLK rising edge must not occur at the same time as LRCK edge.
Note 11. The AK5386 can be reset by bringing the PDN pin = “L”
Note 12. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
MS0579-E-00
2006/12
-9-
ASAHI KASEI
[AK5386]
„ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tSCK
VIH
SCLK
VIL
tSCKH
tSCKL
Clock Timing
VIH
LRCK
VIL
tSHLR
tLRSH
VIH
SCLK
VIL
tSSD
tLRS
SDTO
50%VD
Audio Interface Timing (Slave mode)
MS0579-E-00
2006/12
- 10 -
ASAHI KASEI
[AK5386]
LRCK
50%VD
tMSLR
dSCK
SCLK
50%VD
tSSD
SDTO
50%VD
Audio Interface Timing (Master mode)
VIH
PDN
VIL
tPD
tPDV
SDTO
50%VD
Power Down & Reset Timing
MS0579-E-00
2006/12
- 11 -
ASAHI KASEI
[AK5386]
OPERATION OVERVIEW
„ System Clock
MCLK, SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized with
MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system
clock frequency. MCLK frequency, SCLK frequency, HPF (ON or OFF) and master/slave are selected by CKS2-0 pins as
shown in Table 3. When MCLK is 192fs, 384fs or 768fs, the sampling frequency does not support variable pitch.
All external clocks (MCLK, SCLK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided,
the AK5386 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK5386 in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be
provided unless PDN pin = “L”.
fs
32kHz
44.1kHz
48kHz
96kHz
192kHz
128fs
N/A
N/A
N/A
N/A
24.576MHz
MCLK
192fs
256fs
384fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.576MHz
36.864MHz
36.864MHz
N/A
N/A
Table 1. System Clock Example
Mode
Sampling Frequency
8kHz ≤ fs ≤ 54kHz
Normal Speed
8kHz ≤ fs ≤ 48kHz
54kHz < fs ≤ 108kHz
Double Speed
48kHz < fs ≤ 96kHz
108kHz < fs ≤ 216kHz
Quad Speed
96kHz < fs ≤ 192kHz
Table 2. Sampling Frequency Range
CKS2 pin
CKS1 pin
CKS0 pin
L
L
L
L
L
H
L
L
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
H
HPF
Master/Slave
512fs
16.384MHz
22.5792MHz
24.576MHz
N/A
N/A
768fs
24.576MHz
33.8688MHz
36.864MHz
N/A
N/A
MCLK
512fs
768fs
256fs
384fs
128fs
192fs
MCLK
128/192fs (Quad Speed)
ON
Slave
256/384fs (Double Speed)
512/768fs (Normal Speed)
128/192fs (Quad Speed)
OFF
Slave
256/384fs (Double Speed)
512/768fs (Normal Speed)
ON
Master
256fs (Double Speed)
ON
Master
512fs (Normal Speed)
ON
Master
128fs (Quad Speed)
ON
Master
192fs (Quad Speed)
ON
Master
384fs (Double Speed)
ON
Master
768fs (Normal Speed)
Table 3. Mode Select
SCLK
≥ 48fs or 32fs
(Note 13)
≥ 48fs or 32fs
(Note 13)
64fs
64fs
64fs
64fs
64fs
64fs
Note 13. SDTO outputs 16bit data at SCLK=32fs.
MS0579-E-00
2006/12
- 12 -
ASAHI KASEI
[AK5386]
„ Audio Interface Format
Two kinds of data formats can be chosen with the DIF pin (Table 4). In both modes, the serial data is in MSB first, 2’s
complement format. The SDTO is clocked out on the falling edge of SCLK. The audio interface supports both master and
slave modes. In master mode, SCLK and LRCK are output with the SCLK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode
0
1
DIF pin
L
H
SDTO
LRCK
SCLK
24bit, MSB justified
H/L
≥ 48fs or 32fs
24bit, I2S Compatible
L/H
≥ 48fs or 32fs
Table 4. Audio Interface Format
Figure
Figure 1
Figure 2
LRCK
0 1 2
31 0 1 2
20 21 22 23 24
20 21 22 23 24
31 0 1
SCLK(64fs)
SDTO(o)
23 22
4 3 2 1 0
23 22
4 3 2 1 0
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0 1 2 3
21 22 23 24 25
0 1 2
21 22 23 24 25
0 1
SCLK(64fs)
SDTO(o)
23 22
4 3 2 1 0
23 22
4 3 2 1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1 Timing
„ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz (@fs=48kHz)
and scales with sampling rate (fs).
HPF is controlled by CKS2-0 pins (Table 3). If HPF setting (ON/OFF) is changed at operating, click noise occurs by
changing DC offset. It is recommended that HPF setting is changed at PDN pin = “L”.
MS0579-E-00
2006/12
- 13 -
ASAHI KASEI
[AK5386]
„ Power down
The AK5386 is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same
time. This reset should always be done after power-up. In the power-down mode, the VCOM are AGND level. An analog
initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available after
4129 cycles of LRCK clock in master mode or 4132 cycles of LRCK clock in slave mode. During initialization, the ADC
digital data outputs of both channels are forced to a 2’s complement “0”. The ADC outputs settle in the data
corresponding to the input signals after the end of initialization (Settling approximately takes the group delay time).
(1)
PDN
Internal
State
Normal Operation
Power-down
Initialize
Normal Operation
GD (2)
GD
A/D In
(Analog)
A/D Out
(Digital)
Clock In
MCLK,LRCK,SCLK
(3)
“0”data
Idle Noise
“0”data
Idle Noise
(4)
Notes:
(1) 4132/fs in slave mode and 4129/fs in master mode.
(2) Digital output corresponding to analog input has the group delay (GD).
(3) A/D outputs “0” data at the power-down state.
(4) When the external clocks (MCLK, SCLK and LRCK) are stopped, the AK5386 should be in the power-down state.
Figure 3. Power-down/up sequence example
„ System Reset
The AK5386 should be reset once by bringing PDN pin “L” after power-up. In slave mode, the internal timing starts
clocking by the rising edge (falling edge at mode 1) of LRCK after exiting from reset and power down state by MCLK.
The AK5386 is power down state until LRCK is input. In master mode, the internal timing starts when MCLK is input.
MS0579-E-00
2006/12
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ASAHI KASEI
[AK5386]
SYSTEM DESIGN
Figure 4 shows the system connection diagram. An evaluation board is available which demonstrates application circuits,
the optimum layout, power supply arrangements and measurement results.
Rch In
1 AINR
CKS0 16
Lch In
2 AINL
CKS2 15
2.2u
3 CKS1
DIF 14
4 VCOM
PDN 13
5 AGND
Analog 5V
+
10u
Digital 3.3V
+
10u
0.1u
0.1u
AK5386
Mode
Control
Reset
SCLK 12
6 VA
MCLK 11
7 VD
LRCK 10
8 DGND
SDTO 9
Audio
Controller
Analog Ground
System Ground
Notes:
- AGND and DGND of the AK5386 should be distributed separately from the ground of external digital devices
(MPU, DSP etc.).
- All digital input pins should not be left floating.
- The CKS1 pin should be connected to VA or AGND.
Figure 4. Typical Connection Diagram
Digital Ground
Analog Ground
System
Controller
1
AINR
CKS0 16
2
AINL
CKS2 15
3
CKS1
DIF 14
4
VCOM
PDN 13
5
AGND
SCLK 12
6
VA
MCLK 11
7
VD
LRCK 10
8
DGND
SDTO 9
AK5386
Figure 5. Ground Layout
Note: AGND and DGND must be connected to the same analog ground plane.
MS0579-E-00
2006/12
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ASAHI KASEI
[AK5386]
1. Grounding and Power Supply Decoupling
The AK5386 requires careful attention to power supply and grounding arrangements. To minimize coupling from digital
noise, decoupling capacitors should be connected to VA and VD respectively. VA is supplied from the analog supply in
the system, and VD is supplied from the digital supply in the system. The power up sequence is not critical between VA
and VD. AGND and DGND of the AK5386 must be connected to one analog ground plane. System analog
ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit
board. Decoupling capacitors should be as near to the AK5386 as possible, with the small value ceramic capacitor being
the nearest.
2. Voltage Reference
The voltage input to VA sets the analog input range. VCOM are 50%VA and normally connected to AGND with a 0.1µF
ceramic capacitor. A capacitor 2.2µF attached to VCOM pin eliminates the effects of high frequency noise. No load
current may be drawn from these pins. All signals, especially clocks, should be kept away from the VA and VCOM pins
in order to avoid unwanted coupling into the AK5386.
3. Analog Inputs
The ADC inputs are single-ended and internally biased to the common voltage (50%VA) with 6kΩ (typ, @fs=48kHz,
96kHz, 192kHz) resistance. The input signal range scales with the supply voltage and nominally 0.6xVA Vpp (typ). The
ADC output data format is 2’s complement. The internal HPF removes the DC offset.
The AK5386 samples the analog inputs at 128fs (@ fs=48kHz), 64fs (@ fs=96kHz) or 32fs(@ fs=192kHz). The digital
filter rejects noise above the stop band except for multiples of 64fs or 32fs. The AK5386 includes an anti-aliasing filter
(RC filter) to attenuate a noise around 128fs, 64fs or 32fs.
MS0579-E-00
2006/12
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ASAHI KASEI
[AK5386]
PACKAGE
16pin TSSOP (Unit: mm)
5.0
16
1.10max
9
4.4
6.4±0.2
A
1
0.22±0.1
8
0.17±0.05
0.65
0.1±0.1
0.5±0.2
Detail A
Seating Plane
0.10
0∼10°
„ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0579-E-00
2006/12
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ASAHI KASEI
[AK5386]
MARKING
AKM
5386VT
XXYYY
1) Pin #1 indication
2) Date Code: XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
3) Marketing Code: 5386VT
Revision History
Date (YY/MM/DD)
06/12/13
Revision
00
Reason
First Edition
Page
Contents
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Bef ore considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or dev ices or systems containing them, may require an export
license or other off icial approval under the law and regulations of the country of export pertaining
to customs and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representativ e Director of AKM. As
used here:
a. A hazard related dev ice or system is one designed or intended for life support or maintenance
of saf ety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to f unction or perform may reasonably be expected to result in loss of life or in
significant injury or damage to person or property.
b. A critical component is one whose failure to function or perform may reasonably be expected
to result, whether directly or indirectly, in the loss of the saf ety or effectiveness of the device
or system containing it, and which must therefore meet very high standards of performance
and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the abov e content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless f rom any and all claims arising from the use of said product in the
absence of such notification.
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2006/12
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