AKM AKD4104

[AK4104]
AK4104
192kHz 24-Bit 3.3V DIT
GENERAL DESCRIPTION
The AK4104 is a digital audio interface transmitter (DIT) which supports data rate up to 192kHz sample rate
operation. The AK4104 encodes and transmits audio data according to the AES3, IEC60958, S/PDIF & EIAJ
CP1201 interface standards. The AK4104 accepts audio and digital data, which is then encoded. The audio
serial port supports four formats.
FEATURES
† Sampling Rate up to 192kHz
† Support AES3, IEC60958, S/PDIF & EIAJ CP1201 Consumer Formats
† Generates Parity Bits
† 1-channel Transmission Output
† 42-bit Channel Status Buffer
† Supports Multiple Clock Frequencies: 128/192/256/384/512/768/1024/1536fs
† Supports Left/Right justified and I2S Audio Formats
† Easy to use 4 wire/3 wire Serial Host Interface
† CMOS Input Level
† Power Supply: 2.7 to 3.6V
† Small Package: 16pin TSSOP
† Temperature Range of -20 to 85 °C
MS0642-E-00
2007/07
-1-
[AK4104]
MCLK
CSN
CCLK
CDTI
µP
Interface
VDD
Prescaler
VSS
CDTO
SDTI1
LRCK
BICK
Audio
Data
Interface
Biphase
Encoder
TX
PDN
Figure 1. AK4104 Block Diagram (Mode= “0”)
MCLK
CSN
CCLK
CDTI
µP
Interface
VDD
Prescaler
VSS
SDTI2
SDTI1
LRCK
Audio
Data
Interface
Biphase
Encoder
TX
BICK
PDN
Figure 2. AK4104 Block Diagram (Mode= “1”)
MS0642-E-00
2007/07
-2-
[AK4104]
■ Ordering Guide
−20 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4104
AK4104ET
AKD4104
■ Pin Layout
MCLK
1
16
TX
BICK
2
15
CDTO/ SDTI2
SDTI1
3
14
VDD
LRCK
4
13
VSS
PDN
5
12
TEST4
CSN
6
11
TEST3
CCLK
7
10
TEST2
CDTI
8
9
TEST1
AK4104
Top
View
MS0642-E-00
2007/07
-3-
[AK4104]
PIN/FUNCTION
No.
1
2
3
4
Pin Name
MCLK
BICK
SDTI1
LRCK
I/O
I
I
I
I
5
PDN
I
6
7
8
CSN
CCLK
CDTI
I
I
I
9
TEST1
I
10
TEST2
O
11
TEST3
O
12
TEST4
O
13
14
VSS
VDD
CDTO
SDTI2
O
I
TX
O
15
16
Function
Master Clock Input Pin
Audio Serial Data Clock Pin
Audio Serial Data Input 1 Pin
Input Channel Clock Pin
Power Down and Reset Pin
“L”: Power down and Reset, “H”: Power up
Chip Select Pin
Control Data Clock Pin
Control Data Input Pin
TEST Pin
This pin should be connected to VDD.
TEST Pin
This pin should be OPEN.
TEST Pin
This pin should be OPEN.
TEST Pin
This pin should be OPEN.
Ground Pin
Power Supply Pin, 2.7 ∼ 3.6V
Control Data Output Pin, The output is “Hi-Z” when PDN pin = “L”.
Audio Serial Data Input 2 Pin
Transmit Channel Output Pin, The output is “L” when PDN pin = “L” or RSTN bit
=“0” or PW bit = “0” or MCLK stops.
Note: All digital input pins should not be left floating.
MS0642-E-00
2007/07
-4-
[AK4104]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter
Power Supply
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Temperature (Powered applied)
Storage Temperature
(Note 2)
Symbol
VDD
IIN
VIND
Ta
Tstg
min
−0.3
−0.3
−20
−65
max
4.6
±10
VDD+0.3
85
150
Units
V
mA
V
°C
°C
Note 1. All voltages with respect to ground.
Note 2. MCLK, BICK, SDTI1, LRCK, PDN, CSN, CCLK, CDTI, SDTI2
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Power Supply
Symbol
VDD
min
2.7
typ
3.3
max
3.6
Units
V
Note 1. All voltages with respect to ground.
WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
DC CHARACTERISTICS
(Ta=25°C; VDD=2.7 ∼ 3.6V)
Parameter
Symbol
min
Power Supply Current
(Note 3)
Normal Operation (PDN pin = “H”, fs=44.1kHz) (Note 3)
Full power-down mode (PDN pin = “L”)
(Note 4)
High-Level Input Voltage
VIH
70%VDD
Low-Level Input Voltage
VIL
VOH1
VDD-0.4
High-Level Output Voltage (Iout=-80μA)
VOL1
Low-Level Output Voltage (Iout=80µA)
Input Leakage Current
Iin
-
typ
max
Units
0.9
10
-
1.8
50
30%VDD
0.4
± 10
mA
μA
V
V
V
V
µA
Note 3. TX pin: open . Power supply current ([email protected]) is 1.0mA(typ)@fs=48kHz, 1.4mA(typ)@fs=96kHz and
2.6mA(typ)@fs=192kHz. IDD is 10µA(typ) if PDN= “L” and all other input pins are held to VSS(@3.3V).
(TX pin: 20pF, Power supply current ([email protected]) is 3.3mA(typ)@fs=192kHz.)
Note 4. All digital input pins are fixed to VDD or VSS.
TX CHARACTERISTICS
(Ta=25°C; VDD=2.7 ∼ 3.6V)
Parameter
High-Level Output Voltage ( Iout=-400μA)
Low-Level Output Voltage ( Iout=400μA)
Load Capacitance
Symbol
VOH2
VOL2
CL
MS0642-E-00
min
VDD-0.4
-
typ
-
max
0.4
50
Units
V
V
pF
2007/07
-5-
[AK4104]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=2.7 ∼ 3.6V, CL=20pF)
Parameter
Symbol
min
Master Clock Frequency
Frequency
fCLK
2.048
Duty Cycle
dCLK
40
LRCK Frequency
Frequency
fs
8
Duty Cycle
dCLK
45
Audio Interface Timing
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
30
Pulse Width High
tBCKH
30
BICK “↑” to LRCK Edge
(Note 5)
tBLR
20
LRCK Edge to BICK “↑”
(Note 5)
tLRB
20
SDTI Hold Time
tSDH
20
SDTI Setup Time
tSDS
20
Control Interface Timing
CCLK Period
200
tCCK
CCLK Pulse Width Low
80
tCCKL
Pulse Width High
80
tCCKH
CDTI Setup Time
40
tCDS
CDTI Hold Time
40
tCDH
CSN “H” Time
150
tCSW
150
CSN “↓” to CCLK “↑”
tCSS
50
tCSH
CCLK “↑” to CSN “↑”
tDCD
CDTO Delay
tCCZ
CSN “↑” to CDTO Hi-Z
Power-Down & Reset Timing
PDN Pulse Width
(Note 6)
tPD
150
typ
max
Units
36.864
60
MHz
%
192
55
kHz
%
ns
ns
ns
ns
ns
ns
ns
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 5. BICK rising edge must not occur at the same time as LRCK edge.
Note 6. The AK4104 can be reset by bringing PDN pin = “L”.
MS0642-E-00
2007/07
-6-
[AK4104]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 3. Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDTI
VIL
Figure 4. Serial Interface Timing
MS0642-E-00
2007/07
-7-
[AK4104]
VIH
CSN
VIL
tCSS
tCCK
tCCKL tCCKH
VIH
CCLK
VIL
tCDH
tCDS
CDTI
C1
C0
A4
R/W
VIH
VIL
Hi-Z
CDTO
Figure 5. WRITE/READ Command Input Timing in 3-wire/4-wire serial mode
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
VIH
D0
VIL
Hi-Z
CDTO
Figure 6. WRITE Data Input Timing in 3-wire/4-wire serial mode
VIH
CSN
VIL
VIH
CCLK
VIL
CDTI
A1
VIH
A0
VIL
tDCD
CDTO
Hi-Z
D7
D6
D5
50%VDD
Figure 7. READ Data Output Timing 1 in 4-wire serial mode
MS0642-E-00
2007/07
-8-
[AK4104]
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
VIL
tCCZ
CDTO
D3
D2
D1
D0
Hi-Z
50%VDD
Figure 8. READ Data Output Timing 2 in 4-wire serial mode
tPD
PDN
VIL
Figure 9. Power-Down & Reset Timing
MS0642-E-00
2007/07
-9-
[AK4104]
OPERATION OVERVIEW
■ Reset and Initialization
The AK4104 should be reset once by bringing PDN = “L” upon power-up. It takes 8 bit clock cycles for the AK4104 to
initialize after PDN pin goes “H”.
■ MCLK and LRCK Relationship
For correct synchronization, MCLK and LRCK should be derived from the same clock signal either directly (as through a
frequency divider) or indirectly (for example, as through a DSP). The phase relationship between MCLK and LRCK
should be kept after power-up. The MCLK frequencies shown in Table 1 are supported. The internal clock frequency is
set depending on the external MCLK frequency automatically.
MCLK
128fs
192fs
256fs
384fs
512fs
768fs
1024fs
1536fs
Fs
16k-192kHz
16k-192kHz
8k-128kHz
8k-96kHz
8k-48kHz
8k-48kHz
8k-32kHz
8k-24kHz
Table 1. MCLK Frequency
MS0642-E-00
2007/07
- 10 -
[AK4104]
■ Audio Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF1-0 bits as shown in Table 2 can select four
serial data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of
BICK. Mode 3 can be used for 16bit I2S Compatible format by zeroing the unused LSBs at BICK ≥ 48fs or BICK = 32fs.
Mode
0
1
2
3
DIF1
0
0
1
1
DIF0
SDTI Format
0
16bit, LSB justified
1
24bit, LSB justified
0
24bit, MSB justified
1
16/24bit, I2S Compatible
Table 2. Audio Interface Format
BICK
≥ 32fs
≥ 48fs
≥ 48fs
≥ 48fs or 32fs
Figure
Figure 10
Figure 11
Figure 12
Figure 13
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
0 1 2 3
17 18 19 20
31 0 1 2 3
7 6 5 4 3 2 1 0 15
17 18 19 20
31 0 1
BICK(64fs)
SDTI(i)
Don't Care
15 14 13 12
1 0
Don't Care
15 14 13 12
2 1 0
SDTI-15:MSB, 0:LSB
Lch Data
Rch Data
Figure 10. Mode 0 Timing
LRCK
0 1 2
8 9
24
31 0 1 2
8 9
24
31 0 1
BICK(64fs)
SDTI(i)
Don't Care
23
8
1 0
Don't Care
23
8
1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 11. Mode 1 Timing
LRCK
0 1 2
20 21 22 23 24
31 0 1 2
20 21 22 23 24
31 0 1
BICK(64fs)
SDTI(i)
23 22
4 3 2 1 0 Don't Care 23 22
4 3 2 1 0
Don't Care 23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 12. Mode 2 Timing
MS0642-E-00
2007/07
- 11 -
[AK4104]
LRCK
0 1 2 3
21 22 23 24 25
0 1 2
21 22 23 24 25
0 1
BICK(64fs)
SDTI(i)
23 22
4 3 2 1 0 Don't Care 23 22
4 3 2 1 0
Don't Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 13. Mode 3 Timing
■ DIT input select
The AK4104 can select 4-wire μP I/F mode (MODE bit = “0”) or 3-wire μP I/F mode (MODE bit = “1”). In 3-wire μP I/F
mode, the AK4104 can select the input data of DIT from SDTI1 or SDTI2 data.
MODE
0
1
1
1
1
SEL1
x
0
0
1
1
SEL0
x
0
1
0
1
μP I/F
4-wire
3-wire
3-wire
3-wire
Reserved
DIT input
SDTI1
SDTI1
SDTI2
SDTI2:DIT Bypass
(x: Don’t care)
Table 3. DIT Input
MS0642-E-00
2007/07
- 12 -
[AK4104]
■ Data Transmission Format
The Data transmitted on the TX outputs is formatted in blocks as shown in Figure 14. Each block consists of 192 frames.
A frame of data contains two sub-frames. A sub-frame consists of 32 bits of information. Each received data bit is coded
using a bi-phase mark encoding as a two binary state symbol. The preambles violate bi-phase encoding so they may be
differentiated from data. In bi-phase encoding, the first state of input symbol is always the inverse of the last state of the
previous data symbol. For a logic 0, the second state of the symbol is the same as the first state. For a logic 1, the second
state is opposite of the first. Figure 15 illustrates a sample stream of 8 data bits encoded in 16 symbol states.
M Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1 W Channel 2
Sub-frame
Frame 191
Sub-frame
Frame 0
Frame 1
Figure 14. Block format
0
1
1
0
0
0
1
0
Figure 15. A biphase-encoded bit stream
The sub-frame is defined in Figure 16 below. Bits 0-3 of the sub-frame represent a preamble for synchronization. There
are three preambles. The block preamble, B, is contained in the first sub-frame of Frame 0. The channel 1 preamble, M, is
contained in the first sub-frame of all other frames. The channel 2 preamble, W, is contained in all of the second
sub-frames.
Table 4 below defines the symbol encoding for each of the preambles. Bits 4-27 of the sub-frame contain the 24 bit audio
sample in 2’s complement format with bit 27 as the most significant bit. For 16 bit mode, Bits 4-11 are all 0. Bit 28 is the
validity flag. It is “H” if the audio sample is unreliable. Bit 29 is a user data bit. Frame 0 contains the first bit of a 192 bit
user data word. Frame 191 contains the last bit of the user data word. Bit 30 is a channel status bit. Again frame 0 contains
the first bit of the 192 bit word with the last bit in frame 191. Bit 31 is an even parity bit for bits 4-31 of the sub-frame.
0
3 4
L
Sync
S
B
27 28 29 30 31
M
S V U C P
B
Audio sam ple
Figure 16. Sub-frame format
The block of data contains consecutive frames transmitted at a state-bit rate of 64 times the sample frequency, fs. For
stereophonic audio, the left or A channel data is in channel 1 while the right or B data is in channel 2. For monophonic
audio, channel 1 contains the audio data.
Preamble
B
M
W
Preceding state = 0
11101000
11100010
11100100
Preceding state = 1
00010111
00011101
00011011
Table 4. Sub-frame preamble encoding
Channel Status bit
In the consumer mode (bit0 = “0”), bits20-23(audio channel) must be controlled by the CT20 bit. When the CT20 bit is
“1”, the AK4104 corresponds to “stereo mode”, bits20-23 are set to “1000”(left channel) in sub-frame 1, and is set to
“0100”(right channel) in sub-frame 2. When the CT20 bit is “0”, bits20-23 is set to “0000” in both sub-frame 1 and
sub-frame 2.
MS0642-E-00
2007/07
- 13 -
[AK4104]
■ μP Control Interface
The AK4104 can select 4-wire μP I/F mode (MODE bit = “0”) or 3-wire μP I/F mode (MODE bit = “1”).
1.4-wire Serial mode (MODE bit = “0”, default)
The internal registers may be either written or read by the 4-wire μP interface pins: CSN, CCLK, CDTI and CDTO. The
data on this interface consists of Chip address (2bits, C1/0; fixed to “11”), Read/Write (1bit), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is clocked
out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low
transition of CSN. CSN should be set to “H” once after the 16th CCLK. For read operations, the CDTO output goes high
impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN pin = “L” resets the
registers to their default values.
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13
14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
WRITE
Hi-Z
CDTO
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
READ
CDTO
C1-C0:
R/W:
A4-A0:
D7-D0:
Hi-Z
D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
Chip Address: (Fixed to “11”)
READ/WRITE (0:READ, 1:WRITE)
Register Address
Control Data
Figure 17. 4-wire μP I/F Timing
*When the AK4104 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
MS0642-E-00
2007/07
- 14 -
[AK4104]
2.3-wire μP I/F mode (MODE bit = “1”)
Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists
of Chip Address (2bits, C1/0; fixed to “11”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first,
5bits) and Control Data (MSB first, 8bits). The AK4104 latches the data on the rising edge of CCLK, so data should
clocked in on the falling edge. The writing of data becomes valid by 16th CCLK after a high to low transition of CSN.
CSN should be set to “H” once after the 16th CCLK. The clock speed of CCLK is 5MHz (max).
PDN pin = “L” resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers
are not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “11”)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 18. 3-wire μP I/F Timing
*The AK4104 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4104 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
MS0642-E-00
2007/07
- 15 -
[AK4104]
■ Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
Control 1
1
0
0
0
DIF1
DIF0
PW
RSTN
01H
02H
Reserved
Control 2
0
0
1
0
0
0
1
0
1
0
0
MODE
1
SEL1
1
SEL0
03H
TX
1
0
0
0
0
0
V
TXE
04H
05H
06H
07H
08H
09H
Channel Status Byte0
Channel Status Byte1
Channel Status Byte2
Channel Status Byte3
Channel Status Byte4
Channel Status Byte5
CS7
CS15
CS23
CS31
CS39
0
CS6
CS14
CS22
CS30
CS38
0
CS5
CS13
CS21
CS29
CS37
0
CS4
CS12
CS20
CS28
CS36
0
CS3
CS11
CS19
CS27
CS35
0
CS2
CS10
CS18
CS26
CS34
0
CS1
CS9
CS17
CS25
CS33
CS41
CS0
CS8
CS16
CS24
CS32
CS40
Notes:
For addresses from 0AH to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default
values. All data can be written to the register even if PW or RSTN bit is “0”.
The “0” register should be written “0”, the “1” register should be written “1” data.
■ Register Definitions
Addr
00H
Register Name
Control 1
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
DIF1
DIF0
PW
RSTN
1
1
1
1
R/W
Default
R/W
1
0
0
0
RSTN: Internal timing reset control
0: Reset. All registers are not initialized.
1: Normal Operation
PW: Power down control
0: Power down. All registers are not initialized.
1: Normal Operation
DIF1-0: Audio data interface formats (Table 2)
Initial: “11”, Mode 3
MS0642-E-00
2007/07
- 16 -
[AK4104]
Register Name
02H
Control 3
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
MODE
SEL1
SEL0
0
0
0
0
R/W
Default
R/W
0
0
0
0
MODE: Mode Control
0: 4 wire mode
1: 3 wire mode
SEL1-0: DIT input
00: SDTI1 input
01: SDTI2 input
10: SDTI2 input (DIT Bypass)
11: Reserved
(NOTE) SEL1-0 bits can not use in 4 wire mode (MODE=“0”).
Register Name
03H
TX
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
V
TXE
0
0
0
1
R/W
Default
R/W
1
0
0
0
V: Validity Flag
0: Valid
1: Invalid
TXE: TX output
0: “L”
1: normal operation
Register Name
04H
D7
D6
D5
D4
D3
D2
D1
D0
CS7
CS6
CS5
CS4
CS3
CS2
CS1
CS0
0
0
0
0
0
1
0
0
CS15
CS14
CS13
CS12
CS11
CS10
CS9
CS8
0
0
0
0
0
0
0
0
CS23
CS22
CS21
CS20
CS19
CS18
CS17
CS16
0
0
0
0
0
0
0
0
Channel Status Byte3
CS31
CS30
CS29
CS28
CS27
CS26
CS25
CS24
Default
Channel Status Byte4
Default
Channel Status Byte5
0
CS39
0
0
0
CS38
0
0
0
CS37
0
0
0
CS36
0
0
0
CS35
0
0
0
CS34
0
0
0
CS33
0
CS41
0
CS32
0
CS40
0
0
0
0
0
0
0
0
Channel Status Byte0
Default
05H
Channel Status Byte1
Default
06H
Channel Status Byte2
Default
07H
08H
09H
Default
CS7-0: Transmitter Channel Status Byte 0
Default: “00000100”
CS39-8: Transmitter Channel Status Byte 4-1
Default: “00000000”
CS41-CS40: Transmitter Channel Status Byte 5
Default: “00000000”, D7-D2 bits should be written “1”.
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[AK4104]
SYSTEM DESIGN
Figure 19 and Figure 20 shows the system connection diagram. The evaluation board AKD4104 demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
Master Clock
1
MCLK
64fs
2
BICK
CDTO
15
24bit Audio Data
3
SDTI
VDD
14
fs
Reset & Power down
Micro
Controller
TX
Optic transmitting
module
16
0.1u
4
LRCK
VSS
13
5
PDN
TEST4
12
6
CSN
TEST3
11
7
CCLK
TEST2
10
8
CDTI
TEST1
9
AK4104
+
10u
Analog Supply
2.7 to 3.6V
Figure 19. Typical Connection Diagram (Mode= “0”, 4 wire mode )
24bit Audio Data2
Master Clock
1
MCLK
64fs
2
3
24bit Audio Data1
fs
Reset & Power down
Micro
Controller
TX
16
BICK
SDTI2
15
SDTI
VDD
14
Optic transmitting
module
0.1u
4
LRCK
5
VSS
13
PDN
TEST4
12
6
CSN
TEST3
11
7
CCLK
TEST2
10
8
CDTI
TEST1
9
AK4104
+
10u
Analog Supply
2.7 to 3.6V
Figure 20. Typical Connection Diagram (Mode= “1”, 3 wire mode )
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[AK4104]
PACKAGE
16pin TSSOP (Unit: mm)
*5.0±0.1
9
A
8
1
0.13 M
6.4±0.2
*4.4±0.1
16
1.05±0.05
0.22±0.1
0.65
0.17±0.05
Detail A
0.5±0.2
0.1±0.1
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
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[AK4104]
MARKING
AKM
4104ET
XXYYY
1)
2)
3)
4)
Pin #1 indication
Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
Marketing Code : 4104ET
Asahi Kasei Logo
REVISION HISTORY
Date (YY/MM/DD)
07/07/09
Revision
00
Reason
First Edition
Page
Contents
MPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
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