ASAHI KASEI [AKD4126-A] AKD4126-A AK4126 Evaluation Board Rev.2 GENERAL DESCRIPTION The AKD4126-A is an evaluation board for the AK4126, the digital sample rate converter. The AKD4126-A has the digital audio interface and can achieve the interface with digital audio system via opt-connector. Ordering guide AKD4126-A --- AK4126 Evaluation Board FUNCTION • DIR/DIT with optical input/output • 10pin Header for AKM AD/DA evaluation board 5V Opt In GND AK4114 AK4114 Opt Out Regulator COAX 10pin Header COAX AK4126 DSP Data 10pin Header DSP Data Figure 1. AKD4126-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM083203> 2007/01 -1- ASAHI KASEI [AKD4126-A] Operation sequence [1] Set up lines of power supply [VDD] (Red) = +5[V] (Power supply for regulator REG1 and REG2. REG1 and REG2 supplies 3.3V to the AKD4126-A.) [GND] (Black) = 0[V] [2] Set up jumper pins of power supply (1). Set up AVDD1 and DVDD1 (Set up AVDD and DVDD of the AK4126) Power supply source of AVDD1 and DVDD1 is selected by JP23. (a) From VDD terminal (b) From REG1 JP23 VDD-AK4126 VDD JP23 VDD-AK4126 REG1 VDD (VDD) REG1 (REG1) (2). Set up VDD1 and VDD2 (Set up AVDD, DVDD and TVDD of the AK4114, VDD of logic IC and others) Power supply source of VDD1 and VDD2 is selected by JP24. (a) From VDD terminal (b) From REG2 JP24 VDD-LOGIC VDD JP24 VDD-LOGIC REG2 VDD (VDD) REG2 (REG2) [3] Evaluation modes (1). Input PORT (1)-1. DIR functions of the AK4114 (U2) are used. (Default) (1)-2. External equipments are connected via 10-pin connector (PORT2). (2). Output PORT (2)-1. DIT functions of the AK4114 (U3) are used. (Default) (2)-2. External equipments are connected via 10-pin connector (PORT4). [4] Set up jumper pins and DIP-switches of evaluation modes. (Refer to the following.) [5] Power on. Power down reset of the AK4126 (U1), the AK4114 (U2) and the AK4114 (U3) should be done once after power on. Method of power down reset of them is that after once put them on power-down bringing toggle switches SW6 and SW8 to “L”, release them from power-down bringing toggle switches SW6 and SW8 to “H”. <KM083203> 2007/01 -2- ASAHI KASEI [AKD4126-A] Set up jumper pins and DIP-switches of evaluation modes (1). Set up jumper pins and DIP-switches of input PORT (1)-1. DIR functions of the AK4114 (U2) are used. (Default) (1)-1-1. Set up RX Select input connector of RX by JP7 (RX). (a) RX is input from PORT1 (OPT) (b) RX is input from J1 (COAX) JP7 RX JP7 RX OPT COAX (O P T ) OPT COAX (C O A X ) (1)-1-2. Set up IBICK, ILRCK and SDTI Clocks (IBICK and ILRCK) and data (SDTI) of the AK4126 (U1) are supplied from the AK4114 (U2). As 10-pin connector: PORT2 (INPUT) is not used, please don’t connect anything. JP8 X T I-R X (O p e n ) JP9 X T E -R X (S h o rt) JP13 IM C L K JP10 IB IC K 1 JP 12 IL R C K J P 11 SDTI (O p e n ) (S h o rt) (S h o rt) (S h o rt) <KM083203> 2007/01 -3- ASAHI KASEI [AKD4126-A] (1)-1-3. Set up SDTI1, SDTI2 and SDTI3 Select input data to SDTI1, SDTI2 and SDTI3 of the AK4126 (U1). When these jumper pins are set to SDTI side, SDTO of the AK4114 (U2) is input to SDTI1, SDTI2 and SDTI3. When these jumper pins are set to GND side, “0” data is input to SDTI1, SDTI2 and SDTI3. (a) “0” data is input to SDTI1 (b) SDTO of the AK4114 (U2) is input to SDTI1 JP1 S D T I1 GND JP1 S D T I1 SDTI GND SDTI (G N D ) (S D T I) (a) “0” data is input to SDTI2 (b) SDTO of the AK4114 (U2) is input to SDTI2 JP3 S D T I2 JP3 S D T I2 GND SDTI GND (G N D ) SDTI (S D T I) (a) “0” data is input to SDTI3 (b) SDTO of the AK4114 (U2) is input to SDTI3 JP5 S D T I3 JP5 S D T I3 GND SDTI GND SDTI (G N D ) (S D T I) (1)-1-4. Set up PLL Mode and Input Audio Interface Format of the AK4126 (U1) Set up PLL Mode and Input Audio Interface Format of the AK4126 (U1) by SW1. About setting of default, please refer to Table1. About setting except default, please refer to Table2 and Table3. (1)-1-5. Set up Output Audio Interface Format, Clock Mode and Master Clock Frequency of the AK4114 (U2) Set up Output Audio Interface Format, Clock Mode and Master Clock Frequency of theAK4114 (U2) by SW4. About setting of default, please refer to Table4. About setting except default, please refer to Table5, Table6, and Table7. <KM083203> 2007/01 -4- ASAHI KASEI (1)-2. [AKD4126-A] External equipments are connected via 10-pin connector (PORT2). (1)-2-1. Set up RX As Optical connector: PORT1 (OPT) and BNC connector: J1 (COAX) are not used, please don’t connect anything. (1)-2-2. Set up IBICK, ILRCK and SDTI Clocks (IBICK and ILRCK) and data (SDTI) of AK4126 (U1) are supplied from external equipments via 10-pin connector: PORT2 (INPUT). JP 13 IM C L K JP 10 IB IC K 1 JP 12 IL R C K JP 11 SDTI JP 14 IB IC K 2 (O pen) (O pen) (O p e n ) (O p e n ) IN V THR (T H R ) (1)-2-3. Set up SDTI1, SDTI2 and SDTI3 Select input data to SDTI1, SDTI2 and SDTI3 of the AK4126 (U1). When these jumper pins are set to SDTI side, output data of external equipment is input to SDTI1, SDTI2 and SDTI3 via 10-pin connector: PORT2 (INPUT). When these jumper pins are set to GND side, “0” data is input to SDTI1, SDTI2 and SDTI3. (a) “0” data is input to SDTI1 (b) Output data of external equipment is input to SDTI1 JP1 S D T I1 GND JP1 S D T I1 SDTI GND SDTI (G N D ) (S D T I) (a) “0” data is input to SDTI2 (b) Output data of external equipment is input to SDTI2 JP3 S D T I2 JP3 S D T I2 GND SDTI GND (G N D ) SDTI (S D T I) (a) “0” data is input to SDTI3 (b) Output data of external equipment is input to SDTI3 JP5 S D T I3 JP5 S D T I3 GND SDTI GND SDTI (G N D ) (S D T I) (1)-2-4. Set up PLL Mode and Input Audio Interface Format of the AK4126 (U1) Set up PLL Mode and Input Audio Interface Format of the AK4126 (U1) by SW1. About setting of default, please refer to Table1. About setting except default, please refer to Table2 and Table3. <KM083203> 2007/01 -5- ASAHI KASEI [AKD4126-A] (2). Set up jumper pins and DIP-switches of output PORT (2)-1. DIT functions of AK4114 (U3) are used. (Default) (2)-1-1. Set up TX Select output connector of TX by JP15 (TX). (a) TX is output from J3 (COAX) (b) TX is output from PORT3 (OPT) JP15 TX COAX JP15 TX O PT COAX (C O A X ) OPT (O P T ) (2)-1-2. Set up XTI Clock source of XTI of the AK4114 (U3) is selected by JP16 (XTI-TX) and JP17 (XTE-TX). When X’tal: X2 is selected, and OBICK frequency and OLRCK frequency are changed, the value of X’tal: X2 should be changed. (a) XTI is supplied from X’tal: X2 (b) XTI is supplied from J4 (XTI-TX) JP16 X T I-T X JP 17 X T E -T X JP16 X T I-T X JP17 X T E -T X (O p e n ) (S h o rt) (S h o rt) (O p e n ) (2)-1-3. Set up OBICK, OLRCK and SDTO Clocks (OBICK and OLRCK) of the AK4126 (U1) are supplied from the AK4114 (U3), and data (SDTO) of the AK4126 (U1) is output to the AK4114 (U3). As 10-pin connector: PORT4 (OUTPUT) is not used, please don’t connect anything. JP21 O M C LK JP19 O B IC K 1 JP20 O LR C K JP18 SDTO (O p e n ) (S h o rt) (S h o rt) (S h o rt) <KM083203> 2007/01 -6- ASAHI KASEI [AKD4126-A] (2)-1-4. Set up SDTO1, SDTO2 and SDTO3 A data selected among SDTO1, SDTO2 and SDTO3 of the AK4126 (U1), is input to DAUX of the AK4114 (U3). SDTO1, SDTO2 and SDTO3 cannot be selected at same time. (a) SDTO1 is input to DAUX of the AK4114 (U3). JP2 SDTO1 SDTO SDTO1 (S D T O ) JP4 SDTO2 SDTO SDTO2 (O p e n ) JP6 SDTO 3 SDTO SDTO3 (O p e n ) (b) SDTO2 is input to DAUX of the AK4114 (U3). JP2 SDTO1 SDTO SDTO1 (O p e n ) JP4 SDTO2 SDTO SDTO2 (S D T O ) JP6 SDTO 3 SDTO SDTO3 (O p e n ) (c) SDTO3 is input to DAUX of the AK4114 (U3). JP2 SDTO1 SDTO SDTO1 (O p e n ) JP4 SDTO2 SDTO SDTO2 (O p e n ) JP6 SDTO 3 SDTO SDTO3 (S D T O ) (2)-1-5. Set up Output Audio Interface Format 2 and Output Audio Interface Format 1 of the AK4126 (U1) Set up Output Audio Interface Format 2 and Output Audio Interface Format 1 of the AK4126 (U1) by SW2. About setting of default, please refer to Table8. About setting except default, please refer to Table9, Table11. (2)-1-6. Set up Input Audio Interface Format, Clock Mode and Master Clock Frequency of the AK4114 (U3) Set up Input Audio Interface Format, Clock Mode and Master Clock Frequency of the AK4114 (U3) by SW5. About setting of default, please refer to Table12. About setting except default, please refer to Table13, Table14, and Table15. <KM083203> 2007/01 -7- ASAHI KASEI [AKD4126-A] (2)-2. External equipments are connected via 10-pin connector (PORT4). (2)-2-1. Set up TX As Optical connector: PORT3 (OPT) and BNC connector: J3 (COAX) are not used, please don’t connect anything. (2)-2-2. Set up OBICK, OLRCK and SDTO Clocks (OBICK and OLRCK) of the AK4126 (U1) are supplied from external equipment via 10-pin connector: PORT4 (OUTPUT), and output data (SDTO) of the AK4126 (U1) is output to external equipment via 10-pin connector: PORT4 (OUTPUT). JP21 O M C LK JP19 O B IC K 1 JP20 O LR C K JP18 SDTO (O p e n ) (O p e n ) (O p e n ) (O p e n ) JP22 O B IC K 2 THR IN V (T H R ) (2)-2-3. Set up SDTO1, SDTO2 and SDTO3 A data selected among SDTO1, SDTO2 and SDTO3 of the AK4126 (U1), is input to external equipment via 10-pin connector: PORT4 (OUTPUT). SDTO1, SDTO2 and SDTO3 cannot be selected at same time. (a) SDTO1 is input to external equipment JP2 SDTO1 SDTO SDTO1 (S D T O ) JP4 SDTO2 SDTO SDTO2 (O p e n ) JP6 SDTO3 SDTO SDTO3 (O p e n ) (b) SDTO2 is input to external equipment JP2 SDTO1 SDTO SDTO1 (O p e n ) JP4 SDTO2 SDTO SDTO2 (S D T O ) JP6 SDTO3 SDTO SDTO3 (O p e n ) (c) SDTO3 is input to external equipment JP2 SDTO1 SDTO SDTO1 (O p e n ) JP4 SDTO2 SDTO SDTO2 (O p e n ) JP6 SDTO3 SDTO SDTO3 (S D T O ) (2)-2-4. Set up Output Audio Interface Format 2 and Output Audio Interface Format 1 of the AK4126 (U1) Set up Output Audio Interface Format 2 and Output Audio Interface Format 1 of the AK4126 (U1) by SW2. About setting of default, please refer to Table8. About setting except default, please refer to Table9 and Table11. <KM083203> 2007/01 -8- ASAHI KASEI [AKD4126-A] (3). Set up other modes (3)-1. Set up TEST Pin, Soft Mute Cycle Mode, De-emphasis Filter Mode and Channel Mode of the AK4126 (U1) Set up TEST Pin, Soft Mute Cycle Mode, De-emphasis Filter Mode and Channel Mode of the AK4126 (U1) by SW3. About setting of default, please refer to Table16. About setting except default, please refer to Table17, Table18, and Table19. • Set up SW3 ON is “H”, and OFF is “L”. Setting of default is as follows. (Please refer to Table 16.) SW3 No. 1 2 3 4 5 6 7 TI2 TI1 TI0 SMT1 SMT0 DEM1 DEM0 8 PM Mode 0 1 2 3 Name ON (“H”) OFF (“L”) AK4126 TEST Pin Fixed to “L”. AK4126 Soft Mute Cycle Mode Setting (On Manual Mode) Please refer to Table 17. AK4126 De-emphasis Filter Mode Setting Please refer to Table 18. AK4126 Channel Mode Setting Please refer to Table 19. Table 16. SW3 Setting Soft Mute Cycle SMT1 SMT0 Period pin pin fso=48kHz fso=96kHz fso=192kHz L L 1024/fso 21.3ms 10.7ms 5.3ms L H 2048/fso 42.7ms 21.3ms 10.7ms H L 4096/fso 85.3ms 42.7ms 21.3ms H H 8192/fso 170.7ms 85.3ms 42.7ms Table 17. AK4126 Soft Mute Cycle Mode Setting (On Manual Mode) Default L L L L L L H L (Default) Mode DEM1 DEM0 De-emphasis pin pin Filter 0 L L 44.1kHz 1 L H OFF (Default) 2 H L 48kHz 3 H H 32kHz Table 18. AK4126 De-emphasis Filter Mode Setting Mode PM Channel pin Mode 0 L 6-channel (Default) 1 H 4-channel Table 19. AK4126 Channel Mode Setting <KM083203> 2007/01 -9- ASAHI KASEI [AKD4126-A] Set up DIP-switches (1). Set up input mode (1)-1. Set up the AK4126 (U1) • Set up SW1 ON is “H”, and OFF is “L”. Setting of default (Slave Mode, 24bit MSB justified, IBICK lock mode (64fsi), IBICK=Input, ILRCK=Input) is as follows. (Please refer to Table 1.) SW1 No. 1 2 3 4 5 6 Name ON (“H”) PLL2 PLL1 PLL0 IDIF2 IDIF1 IDIF0 OFF (“L”) Default AK4126 PLL Mode Setting Please refer to Table 2. AK4126 Input Audio Interface Format Setting Please refer to Table 3. H L H L H L Table 1. SW1 Setting 0 1 PLL2 pin L L PLL1 pin L L PLL0 pin L H 2 L H L 3 L H H 4 H L L 5 6 H H L H H L 7 H H H Mode ILRCK Freq 8k ~ 96kHz 8k ~ 192kHz 16k ~ 192kHz (Note 1) IBICK Freq SMUTE Depending on IDIF2-0 Manual (Note 4) Semi-Auto (Note 5) Reserved 32fsi (Note 3) 64fsi 8k ~ 192kHz (Note 2) 128fsi 64fsi Manual (Note 4) (Default) Semi-Auto (Note 5) Table2. AK4126 PLL Mode Setting (Input PORT) (Note 1) PLL lock range is changed by values of R and C connected by FILT pin. For more further details, please refer to datasheet: “PLL Loop Filter”. (Note 2) IBICK should be always and continuously supplied, except when clocks are changed. (Note 3) IBICK = 32fsi is applied to only two audio data formats of 16bit LSB justified and 16bit I2S Compatible. (Note 4) Please refer to datasheet: “Soft Mute Operation”: “Manual mode”. (Note 5) Please refer to datasheet: “Soft Mute Operation ”: “Semi-Auto mode”. Mode IDIF2 IDIF1 IDIF0 SDTI Format IBICK pin pin pin Freq 0 L L L 16bit, LSB justified ≥ 32fsi 1 L L H 20bit, LSB justified ≥ 40fsi 2 L H L 24/20bit, MSB justified ≥ 48fsi 3 L H H 24/16bit, I2S Compatible ≥ 48fsi or 32fsi 4 H L L 24bit, LSB justified ≥ 48fsi 5 H L H Reserved 6 H H L Reserved 7 H H H Reserved Table 3. AK4126 Input Audio Interface Format Setting (Input PORT) <KM083203> (Default) 2007/01 - 10 - ASAHI KASEI [AKD4126-A] (1)-2. Set up the AK4114 (U2) • Set up SW4 ON is “H”, and OFF is “L”. Setting of default (Master mode, 24bit Left justified) is as follows. (Please refer to Table 4.) SW4 No. 1 2 3 4 5 6 7 Mode 0 1 2 3 4 5 6 7 Mode 0 1 2 3 Name DIF2 DIF1 DIF0 CM1 CM0 OCKS1 OCKS0 DIF2 pin L L L L H H H H ON (“H”) OFF (“L”) AK4114 Output Audio Interface Format Setting Please refer to Table 5. AK4114 Clock Mode Setting Fixed to “L”. AK4114 Master Clock Frequency Setting Please refer to Table 7. Table 4. SW4 Setting Default H L L L L H L LRCK BICK DIF1 DIF0 SDTO Format pin pin I/O L L 16bit, Right justified H/L O 64fs L H 18bit, Right justified H/L O 64fs H L 20bit, Right justified H/L O 64fs H H 24bit, Right justified H/L O 64fs L L 24bit, Left justified H/L O 64fs L H 24bit, I2S Compatible L/H O 64fs H L 24bit, Left justified H/L I 64-128fs H H 24bit, I2S Compatible L/H I 64-128fs Table 5. AK4114 Output Audio Interface Format Setting OCKS1 OCKS0 MCKO1 MCKO2 X’tal fs (max) pin pin L L 256fs 256fs 256fs 96 kHz L H 256fs 128fs 256fs 96 kHz H L 512fs 256fs 512fs 48 kHz H H 128fs 64fs 128fs 192 kHz Table 7. AK4114 Master Clock Frequency Setting <KM083203> I/O O O O O O O I I (Default) (Default) 2007/01 - 11 - ASAHI KASEI [AKD4126-A] (2). Set up output mode (2)-1. Set up the AK4126 (U1) • Set up SW2 ON is “H”, and OFF is “L”. Setting of default (Slave Mode, 24bit MSB justified, OLRCK=Input, OBICK=Input, fso=8K~192KHz) is as follows. (Please refer to Table 8.) SW2 No. 1 2 3 4 5 6 7 8 Name DITHER OBIT1 OBIT0 TEST1 TEST2 TEST3 ODIF1 ODIF0 ON (“H”) OFF (“L”) Dither ON Dither OFF AK4126 Output Audio Interface Format 2 Setting Please refer to Table 9. AK4126 TEST Pin. Fixed to “H”. AK4126 TEST Pin. Fixed to “L”. AK4126 Output Audio Interface Format 1 Setting Please refer to Table 11. Table 8. SW2 Setting Default L H H H L L H L OBICK Frequency MSB justified, LSB justified I2S Compatible 0 L L 16bit ≥ 32fso 1 L H 18bit ≥ 36fso 64fso 2 H L 20bit ≥ 40fso (Default) 3 H H 24bit ≥ 48fso Table 9. AK4126 Output Audio Interface Format 2 Setting (Output PORT) Mode OBIT1 OBIT0 pin pin SDTO ODIF1 ODIF0 SDTO Format pin pin 0 L L LSB justified 1 L H (Reserved) 2 H L MSB justified (Default) 3 H H I2S Compatible Table 11. AK4126 Output Audio Interface Format 1 Setting (Output PORT) Mode <KM083203> 2007/01 - 12 - ASAHI KASEI [AKD4126-A] (2)-2. Set up the AK4114 (U3) • Set up SW5 ON is “H”, and OFF is “L”. Setting of default (Master mode, 24bit Left justified) is as follows. (Please refer to Table 12.) SW5 No. 1 2 3 4 5 6 7 Mode 0 1 2 3 4 5 6 7 Mode 0 1 2 3 Name DIF2 DIF1 DIF0 CM1 CM0 OCKS1 OCKS0 ON (“H”) OFF (“L”) Default H L L L H L L AK4114 Input Audio Interface Format Setting Please refer to Table 13. AK4114 Clock Mode Setting Fixed to “L”. AK4114 Clock Mode Setting Fixed to “H”. AK4114 Master Clock Frequency Setting Please refer to Table 15. Table 12. SW5 Setting LRCK BICK DIF2 DIF1 DIF0 DAUX Format pin pin pin I/O L L L 24bit, Left justified H/L O 64fs L L H 24bit, Left justified H/L O 64fs L H L 24bit, Left justified H/L O 64fs L H H 24bit, Left justified H/L O 64fs H L L 24bit, Left justified H/L O 64fs H L H 24bit, I2S Compatible L/H O 64fs H H L 24bit, Left justified H/L I 64-128fs H H H 24bit, I2S Compatible L/H I 64-128fs Table 13. AK4114 Input Audio Interface Format Setting OCKS1 OCKS0 MCKO1 MCKO2 X’tal pin pin L L 256fs 256fs 256fs L H 256fs 128fs 256fs H L 512fs 256fs 512fs H H 128fs 64fs 128fs Table 15. AK4114 Master Clock Frequency Setting <KM083203> I/O O O O O O O I I (Default) fs (max) 96 kHz 96 kHz 48 kHz 192 kHz (Default) 2007/01 - 13 - ASAHI KASEI [AKD4126-A] Toggle Switch Operation Upper side is “H” and lower side is “L”. [SW6] (PDN-AK4126): Power down switch of the AK4126 (U1). The AK4126 (U1) should be reset once by bringing to “L” upon power-up. Keep “H” during normal operation. [SW7] (SMUTE-AK4126): Soft mute switch of the AK4126 (U1). Output of the AK4126 (U1) is soft-muted by bringing to “H”. [SW8] (PDN-AK4114-RX/TX): Power down switch of the AK4114 (U2) and the AK4114 (U3). The AK4114 (U2) and the AK4114 (U3) should be reset once by bringing to “L” upon power-up. Keep “H” during normal operation. LED Indication [LED1] (UNLOCK): Output of UNLOCK pin of the AK4126 (U1). Turns on when PLL of the AK4126 (U1) is unlocked. [LED2] (INT0): Output of INT0 pin of the AK4114 (U2). Turns on when the AK4114 (U2) is unlocked. <KM083203> 2007/01 - 14 - ASAHI KASEI [AKD4126-A] MEASUREMENT RESULTS [Measurement condition] • Measurement unit • Power Supply • Band width • Temperature : Audio Precision, System Two Cascade : AVDD=DVDD=3.3V : 20Hz ∼ FSO/2 : Room [Measurement Result] SRC Characteristics THD+N (Input = 1kHz, 0dBFS) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 48kHz/192kHz FSO/FSI = 192kHz/48kHz Worst Case (FSO/FSI = 32kHz/176.4kHz) Dynamic Range (Input = 1kHz, −60dBFS) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 48kHz/192kHz FSO/FSI = 192kHz/48kHz FSO/FSI = 48kHz/32kHz Dynamic Range (Input = 1kHz, −60dBFS, A-weighted) FSO/FSI = 44.1kHz/48kHz SDTO1 Lch SDTO1 SDTO2 Rch Lch SDTO2 SDTO3 SDTO3 Rch Lch Rch Unit 130.2 124.9 136.2 124.9 96.1 130.2 124.9 136.2 124.9 96.1 130.2 124.9 136.2 124.9 96.1 130.2 124.9 136.2 124.9 96.1 130.2 124.9 136.2 124.9 96.1 130.2 124.9 136.2 124.9 96.1 dB dB dB dB dB 136.2 136.4 136.2 135.6 137.3 136.2 136.4 136.2 135.6 137.3 136.2 136.4 136.2 135.6 137.3 136.2 136.4 136.2 135.6 137.3 136.2 136.4 136.2 135.6 137.3 136.2 136.4 136.2 135.6 137.3 dB dB dB dB dB 139.6 139.6 139.6 139.6 139.6 139.6 dB <KM083203> 2007/01 - 15 - ASAHI KASEI [AKD4126-A] [Plot] AK4126 FFT Plot (fsi=48KHz, fso=44.1KHz) AVDD=DVDD=3.3V, Input=0dBFS, fin=1KHz +0 -10 -20 -30 -40 -50 -60 -70 -80 d B F S -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Fig 6. FFT Plot (Input = 0dBFS) AK4126 FFT Plot (fsi=48KHz, fso=44.1KHz) AVDD=DVDD=3.3V, Input=-60dBFS, fin=1KHz +0 -10 -20 -30 -40 -50 -60 -70 -80 d B F S -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 20 50 100 200 500 1k 2k 5k Hz Fig 7. FFT Plot (Input = -60dBFS) <KM083203> 2007/01 - 16 - ASAHI KASEI [AKD4126-A] AK4126 THD+N vs Input Level (fsi=48KHz, fso=44.1KHz) AVDD=DVDD=3.3V, fin=1KHz -120 -122 -124 -126 -128 -130 -132 d B F S -134 -136 -138 -140 -142 -144 -146 -148 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Fig 1. THD+N vs. Input Level AK4126 THD+N vs Input Frequency (fsi=48KHz, fso=44.1KHz) AVDD=DVDD=3.3V, Input Level=0dBFS -80 -85 -90 -95 -100 -105 -110 d B F S -115 -120 -125 -130 -135 -140 -145 -150 20 50 100 200 500 1k 2k 5k 10k 20k Hz Fig 2. THD+N vs. Input Frequency (Input = 0dBFS) <KM083203> 2007/01 - 17 - ASAHI KASEI [AKD4126-A] AK4126 THD+N vs Input Frequency (fsi=48KHz, fso=44.1KHz) AVDD=DVDD=3.3V, Input Level=-60dBFS -100 -105 -110 -115 -120 -125 -130 d B F S -135 -140 -145 -150 -155 -160 -165 -170 -175 -180 20 50 100 200 500 1k 2k 5k 10k 20k Hz Fig 3. THD+N vs. Input Frequency (Input = -60dBFS) AK4126 Linearity (fsi=48KHz, fso=44.1KHz) AVDD=DVDD=3.3V, fin=1KHz +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Fig 4. Linearity <KM083203> 2007/01 - 18 - ASAHI KASEI +1 [AKD4126-A] AK4126 Frequency Response (fsi=48KHz, fso=44.1KHz) AVDD=DVDD=3.3V, Input Level=0dBFS +0.5 -0 -0.5 -1 -1.5 -2 d B F S -2.5 -3 -3.5 -4 -4.5 -5 -5.5 -6 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k Hz Fig 5. Frequency Response +1 AK4126 Frequency Response (Blue: fsi=48KHz, Red: fsi=96KHz, Green: fsi=192KHz), fso=48KHz AVDD=DVDD=3.3V, Input Level=0dBFS +0.5 -0 -0.5 -1 -1.5 fsi=192kHz -2 fsi=96kHz -2.5 d B F S -3 fsi=48kHz -3.5 -4 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k Hz Fig 8. Frequency Response <KM083203> 2007/01 - 19 - ASAHI KASEI [AKD4126-A] AK4126 Frequency Response (Yellow: fsi=44.1KHz, Blue: fsi=48KHz, Red: fsi=96KHz, Green: fsi=192KHz), fso=44.1KHz AVDD=DVDD=3.3V, Input Level=0dBFS +1 +0.5 fsi=44.1kHz -0 -0.5 -1 -1.5 fsi=192kHz -2 -2.5 d B F S fsi=96kHz -3 fsi=48kHz -3.5 -4 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k Hz Fig 9. Frequency Response <KM083203> 2007/01 - 20 - ASAHI KASEI [AKD4126-A] Revision History Date (YY/MM/DD) 07/01/09 Manual Revision KM083203 Board Reason Revision First Edition 2 Contents IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <KM083203> 2007/01 - 21 - A B C D AVDD1 12 11 10 9 8 7 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 INPUT-AK4126 ODIF0 ODIF1 TEST3 TEST2 TEST1 OBIT0 OBIT1 DITHER 8 7 6 5 4 3 2 1 A OUTPUT-AK4126 C1 10u RP2 M9-1-473 + RP1 M7-1-473 SW2 DSS108 9 10 11 12 13 14 15 16 VDD1 VDD1 64 1 2 3 4 5 6 DVDD1 CN1 64pin_4 SW1 DSS106 PLL2 PLL1 PLL0 IDIF2 IDIF1 IDIF0 A E 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 C2 0.1u C3 C4 1 1 IMCLK 2 R2 51 2 ILRCK 3 R4 51 3 IBICK 4 R6 51 4 49 NC 50 52 47K TST7 DVSS 53 54 PLL2 PLL1 PLL0 55 56 57 TST9 59 58 TST10 AVDD NC 60 61 FILT 62 AVSS TST11 63 64 NC CN3 0.1u 51 C6 1n U1 DVDD1 10u R1 470 TST8 C5 DVDD 47K + 0.22u 64pin_3 NC NC TEST0 TEST4 ILRCK OLRCK IBICK OBICK 48 48 47 R3 51 47 OMCLK 46 R5 51 46 OLRCK R7 51 45 OBICK B B 45 DVDD1 5 5 C7 + 10u 7 7 SDTI1 HIF3G-50P-2.54DSA (3x1)J JP1 P1 SDTI GND SDTI2 HIF3G-50P-2.54DSA (3x1)J JP3 P3 SDTI SDTI3 SDTI 9 9 10 R12 51 10 DVSS 44 TST0 TST6 SDTI1 SDTO1 AK4126 SDTI2 SDTO2 SDTI3 SDTO3 IDIF0 ODIF0 IDIF1 ODIF1 IDIF2 TEST3 TST1 TEST2 +C8 10u 43 43 42 41 42 R9 JP2 51 41 SDTO1 JP4 40 R11 51 40 SDTO2 39 R13 51 39 SDTO3 JP6 HIF3G-50P-2.54DSA (2x1) SDTO SDTO HIF3G-50P-2.54DSA (2x1) SDTO HIF3G-50P-2.54DSA (2x1) SDTO C GND 11 12 12 2 DVSS 44 38 38 37 37 VDD1 14 LED1 SML-210LT 1 8 51 11 VDD1 51 R10 GND HIF3G-50P-2.54DSA (3x1)J JP5 P5 C R8 DVDD C10 0.1u 6 8 DVDD C9 0.1u 6 SDTI DVDD1 R14 1k U4A 2 1 7 UNLOCK 13 13 36 36 74AC14 14 14 15 15 TST2 TEST1 35 35 34 34 VDD1 TST5 OBIT1 33 CN2 32 31 OBIT0 30 DEM1 PM 29 28 SMT1 DEM0 27 26 SMT0 25 DITHER PDN 24 R45 100 R46 100 D 32 31 30 29 28 27 26 25 24 22 10u 21 + 20 19 18 17 23 SMUTE DVSS 21 22 DVDD TST4 UNLOCK 19 17 20 0.1u C13 VDD1 33 C12 23 7 DVDD1 1 3 4 C11 0.1u SW7 ATE1D-2M3 SMUTE-AK4126 3 74HC14 2 D 2 74HC14 TST3 U6B 1 H 14 U6A L 64pin_1 VDD1 NC 7 R15 10k VDD1 14 2 1 D1 HSU119 NC 18 16 16 1 H 3 L U6D 9 74HC14 8 SW3 DSS108 VDD1 C14 0.1u 2 SW6 ATE1D-2M3 74HC14 VDD1 6 7 5 14 R16 10k VDD1 U6C 7 1 D2 HSU119 14 2 CN4 64pin_2 PDN-AK4126 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 PM DEM0 DEM1 SMT0 SMT1 TI0 TI1 TI2 RP3 M9-1-473 MODE-AK4126 E 1 2 3 4 5 6 7 8 9 E Title 47K Size A2 Date: A B C D AKD4126-A Document Number Rev AK4126 Thursday, August 03, 2006 E Sheet 2 1 of 4 A B C D E VDD1 L1 47u PORT1 TORX141 VCC A RX(OPT) GND OUT C15 0.1u 3 A 2 1 R17 470 OPT RX(COAX) COAX J1 BNC-R-PC C16 JP7HIF3G-50P-2.54DSA (3x1) RX 0.1u VDD1 + R18 75 C17 10u C18 0.1u 14 13 12 11 10 9 8 R19 18k 1 37 INT0 3 36 74AC14 2 3 NC OCKS0 DIF0 OCKS1 VDD1 14 INT1 38 AVDD 40 39 R AVSS VCOM 41 42 RX0 44 45 43 NC RX2 RX1 U4B IPS0 4 R20 1k LED2 SML-210LT 2 1 VDD1 B INT0 7 INPUT-AK4114 46 47 NC 48 RX3 U2 8 7 6 5 4 3 2 1 B C19 0.47u VDD1 TEST1 RP4 M8-1-473 1 2 3 4 5 6 7 + DIF2 DIF1 DIF0 CM1 CM0 OCKS1 OCKS0 SW4 DSS107 35 34 47K 4 5 TEST2 CM1 DIF1 CM0 33 32 VDD1 13 1 3 12 11 30 10 IPS1 XTO 29 7 74HC14 C22 0.1u C20 10p VDD1 9 P/SN DAUX XTL0 MCKO2 XTL1 BICK 14 JP8 HIF3G-50P-2.54DSA (2x1) 6 VDD1 J2 BNC-R-PC XTI-RX U4C 5 XTI-RX C21 10p 74AC14 R47 51 JP9 HIF3G-50P-2.54DSA (2x1) XTE-RX 28 PDN-4114-TX 2 SW8 ATE1D-2M3 C PDN-AK4114-RX/TX VDD1 JP10 HIF3G-50P-2.54DSA (2x1) IBICK1 25 JP11 HIF3G-50P-2.54DSA (2x1) SDTI LRCK 26 24 MCKO1 23 DVSS DVDD 27 JP12 HIF3G-50P-2.54DSA (2x1) ILRCK JP13 HIF3G-50P-2.54DSA (2x1) IMCLK + 22 C24 0.1u C26 10u + C25 10u 21 VOUT UOUT 20 19 COUT 18 BOUT 17 16 13 C23 0.1u TX1 SDTO TX0 VIN TVDD 12 DVSS 11 15 10 14 C 74HC14 7 H XTI X1 HC-49/U 24.576MHz 8 L DIF2 31 7 U6E PDN 1 7 VDD1 AK4114 NC 2 U6F 14 1 D3 HSU119 R21 10k VDD1 14 2 6 VDD1 D D R22 51 IBICK THR JP14 HIF3G-50P-2.54DSA (3x1) R23 VDD1 IBICK2 51 U4D 14 IMCLK ILRCK 74AC14 8 INV 7 9 SDTI R26 220k R27 220k R28 220k R24 51 R25 51 IMCLK IBICK ILRCK SDTI PORT2 A1-10PA-2.54DSA 1 3 5 7 9 2 4 6 8 10 INPUT R29 220k E E Title Size A2 Date: A B C D AKD4126-A Document Number Rev INPUT RX AK4114 Thursday, August 03, 2006 E Sheet 2 2 of 4 A B C D E PORT3 TOTX141 TX(OPT) IN VCC GND 3 2 1 VDD2 C27 0.1u OPT COAX TX JP15 HIF3G-50P-2.54DSA (3x1) A A R30 240 C28 VDD2 + J3 T1 BNC-R-PC DA-02F TX(COAX) 0.1u C29 10u R31 150 C30 0.1u 1:1 RP5 M8-1-473 1 2 OUTPUT-AK4114 3 4 37 INT1 AVDD 40 39 R AVSS VCOM 41 42 43 NC RX0 44 RX1 45 47 48 46 RX2 TEST1 VDD2 8 7 6 5 4 3 2 1 B NC 14 13 12 11 10 9 8 RX3 1 2 3 4 5 6 7 U3 38 C31 0.47u + DIF2 DIF1 DIF0 CM1 CM0 OCKS1 OCKS0 SW5 DSS107 IPS0 INT0 NC OCKS0 DIF0 OCKS1 TEST2 CM1 DIF1 CM0 36 35 34 33 B 47K PDN DIF2 XTI 31 30 JP16 HIF3G-50P-2.54DSA (2x1) C32 10p XTO 29 2 IPS1 C33 10p JP18 VDD2 9 P/SN DAUX VDD2 U5A 74AC14 2 1 XTI-TX X2 HC-49/U 11.2896MHz 8 14 7 AK4114 NC 7 6 32 1 5 HIF3G-50P-2.54DSA (2x1) J4 BNC-R-PC XTI-TX R48 51 JP17 HIF3G-50P-2.54DSA (2x1) XTE-TX 28 SDTO PDN-4114-TX 10 XTL0 MCKO2 27 JP19 HIF3G-50P-2.54DSA (2x1) 11 XTL1 BICK 26 OBICK1 VDD2 25 C LRCK 24 MCKO1 23 DVSS DVDD + 22 C35 0.1u C37 10u + C36 10u 21 VOUT 20 COUT UOUT 19 18 BOUT 17 TX1 16 15 TVDD 13 C34 0.1u TX0 SDTO DVSS VIN 14 12 C JP20 HIF3G-50P-2.54DSA (2x1) OLRCK JP21 HIF3G-50P-2.54DSA (2x1) OMCLK VDD2 D D OMCLK OBICK U5B 14 THR JP22 HIF3G-50P-2.54DSA (3x1) VDD2 74AC14 OLRCK 4 INV 51 R33 51 OBICK2 7 3 R32 SDTO R36 220k R37 220k R38 220k R34 51 R35 51 PORT4 A1-10PA-2.54DSA OMCLK OBICK OLRCK SDTO 1 3 5 7 9 2 4 6 8 10 OUTPUT R39 220k E E Title Size A2 Date: A B C D AKD4126-A Document Number Rev OUTPUT TX AK4114 Thursday, August 03, 2006 E Sheet 3 of 2 4 A B C D E VDD A A VDD B + C38 47u IN OUT C39 0.1u JP23 HIF3G-50P-2.54DSA (3x1) R40 VDD-AK4126 (short) AVDD1 (for AVDD of AK4126) R41 (short) DVDD1 (for DVDD of AK4126) REG1 2 1 3 GND REG1 LT1117-3.3 + C46 47u C40 0.1u B C C VDD 11 7 74AC14 U5F 8 C48 0.1u for 74AC14 TX (short) VDD2 (for AVDD, DVDD, TVDD of AK4114 (TX)) (for VCC of TOTX141 (TX Opt)) (for VDD of 74AC14(TX)) (for SW5,RP5) VDD2 12 E Title AKD4126-A Size Document Number A4 B C Rev 2 POWER SUPPLY Date: A D 10 13 74AC14 R43 14 14 6 9 74AC14 7 74AC14 12 C45 0.1u for 74AC14 RX U5E 14 7 U5D 13 E 5 74AC14 14 U4F 10 7 14 U5C C44 0.1u for 74HC14 7 + C47 47u C43 0.1u VDD1 11 74AC14 VDD1 (for AVDD, DVDD, TVDD of AK4114 (RX)) (for VCC of TORX141 (RX Opt)) (for VDD of 74AC14(RX)) (for VDD of 74HC14) (for SW1,SW2,SW3,SW4,SW6,SW7,SW8,RP1,RP2,RP3,RP4,LED1,LED2) REG2 2 D U4E (short) 14 OUT JP24 HIF3G-50P-2.54DSA (3x1) R42 VDD-LOGIC 7 + C42 0.1u C41 47u IN 1 3 GND REG2 LT1117-3.3 Thursday, August 03, 2006 D Sheet 4 E of 4