AKM AKD4126

ASAHI KASEI
[AK4126]
AK4126
6ch 192kHz / 24-Bit Asynchronous SRC
GENERAL DESCRIPTION
AK4126 is a 6ch digital sample rate converter (SRC). The input sample rate ranges from 8kHz to 192kHz.
The output sample rate is from 8kHz to 192kHz. By using the AK4126, the system can take very simple
configuration because the AK4126 has an internal PLL and does not need any master clock Then the
AK4126 is suitable for the application interfacing to different sample rates like multi-channel high-end Car
Audio, DVD recorder, etc.
FEATURES
1. SRC
• 6 channels input/output
• Asynchronous Sample Rate Converter
• Input Sample Rate Range (fsi): 8kHz ∼ 192kHz
• Output Sample Rate Range (fso): 8kHz ∼ 192kHz
• Input to Output Sample Rate Ratio: 1/6 to 6
• THD+N: −130dB
• Dynamic Range: 140dB (A-weighted)
• I/F format: MSB justified, LSB justified and I2S compatible
• PLL for Internal Operation Clock
• Digital De-emphasis Filter (32kHz, 44.1kHz and 48kHz)
• Soft Mute Function
2. Power Supply
• AVDD, DVDD: 3.0 ∼ 3.6V (typ. 3.3V)
3. Ta = −40 ∼ 85°C
4. Package: 64LQFP
MS0544-E-00
2006/09
-1-
ASAHI KASEI
[AK4126]
IDIF2 IDIF1 IDIF0 DEM1DEM0
DVDD DVSS ODIF1 ODIF0
OBIT1
OBIT0
IBICK
ILRCK
SDTI1
SDTI2
Serial
Audio
I/F
DEM
SRC
Serial
Audio
I/F
OLRCK
OBICK
SDTO1
SDTO2
SDTI3
SDTO3
AVDD
AVSS
PDN
SMUTE
PLL2
PLL1
PLL0
DITHER
PLL
PM
SMT1
SMT0
UNLOCK
Figure 1. AK4126 Block Diagram
„ Compatibility with AK4125
Parameter
Channel
Maximum Sampling Frequency
Maximum BICK Frequency
Bypass Mode
Master Mode
De-emphasis
Variable Soft Mute Cycle
Group Delay
Package
AK4126
6ch
192kHz
64fs
No
No
Yes
Yes
typ. 57/fs
64LQFP(12mm x 12mm)
MS0544-E-00
AK4125
2ch
216kHz
128fs
Yes
Yes
No
No
typ. 56/fs
30VSOP (9.7mm x 7.6mm)
2006/09
-2-
ASAHI KASEI
[AK4126]
„ Application Block Circuit Example
1. Most Î Amp Unit
MOST
AK4126
IBCLK
ASIC
OBCLK
BCLK
BICK
ILRCK
LRCK
OLRCK
LRCK
SRC
3
SDTO1-3
SDTI1-3
3
SDTI
SDTO
fs = 192kHz
fs = 96kHz
fs = 176.4kHz
fs = 88.2kHz
fs = 96kHz
SRC
fs = 48kHz
fs = 88.2kHz
fs = 44.1kHz
fs = 48kHz
fs = 44.1kHz
2. DVD (5.1ch) Î MOST or ASIC
ASIC (Endec)
AK4126
IBCLK
MOST or ASIC
OBCLK
BCLK
BICK
ILRCK
LRCK
OLRCK
3
SDTO1-3
SDTI1-3
3
SDTI
SDTO
fs = 96kHz
fs = 192kHz
fs = 96kHz
LRCK
SRC
fs = 88.2kHz
SRC
fs = 48kHz
fs = 48kHz
fs = 44.1kHz
MS0544-E-00
2006/09
-3-
ASAHI KASEI
[AK4126]
„ Ordering Guide
−40 ∼ +85°C
64LQFP (0.5mm pitch)
Evaluation Board for AK4126
AK4126VQ
AKD4126
TST10
TST9
PLL0
PLL1
PLL2
DVSS
DVDD
TST8
TST7
NC
56
55
54
53
52
51
50
49
59
57
NC
60
58
FILT
AVDD
61
TST11
AVSS
62
NC
63
64
„ Pin Layout
NC
1
48
NC
TEST0
2
47
TEST4
ILRCK
3
46
OLRCK
IBICK
4
45
OBICK
DVDD
5
44
DVDD
DVSS
6
43
DVSS
TST0
7
42
TST6
SDTI1
8
41
SDTO1
Top View
SDTI2
9
40
SDTO2
SDTI3
10
39
SDTO3
IDIF0
11
38
ODIF0
IDIF1
12
37
ODIF1
IDIF2
13
36
TEST3
TST1
14
35
TEST2
TST2
15
34
TEST1
33
NC
23
24
25
26
27
28
29
30
31
32
DITHER
PDN
SMT0
SMT1
DEM0
DEM1
PM
OBIT0
OBIT1
TST5
21
20
DVDD
22
19
SMUTE
18
UNLOCK
DVSS
17
TST4
16
TST3
NC
MS0544-E-00
2006/09
-4-
ASAHI KASEI
[AK4126]
PIN / FUNCTION
No.
1, 16,
33,48,
49,59,
64
Pin Name
I/O
NC
-
2
TEST0
I
3
4
5
6
ILRCK
IBICK
DVDD
DVSS
I
I
-
7
TST0
I
8
9
10
11
12
13
SDTI1
SDTI2
SDTI3
IDIF0
IDIF1
IDIF2
I
I
I
I
I
I
14
TST1
I
15
TST2
I
17
TST3
I
18
TST4
I
19
20
21
UNLOCK
DVDD
DVSS
O
-
22
SMUTE
I
23
DITHER
I
24
PDN
I
25
26
27
28
29
30
31
SMT0
SMT1
DEM0
DEM1
PM
OBIT0
OBIT1
I
I
I
I
I
I
I
Function
No Connect Pin.
No internal bonding. This pin must be connected to DVSS.
TEST Pin
This pin must be connected to DVSS.
Input Channel Clock Pin
Audio Serial Data Clock Pin
Digital Power Supply Pin, 3.0 ∼ 3.6V
Digital Ground Pin
TEST Pin
This pin must be connected to DVSS.
Audio Serial Data Input #1 Pin
Audio Serial Data Input #2 Pin
Audio Serial Data Input #3 Pin
Audio Interface Format #0 Pin for Input PORT
Audio Interface Format #1 Pin for Input PORT
Audio Interface Format #2 Pin for Input PORT
TEST Pin
This pin must be connected to DVSS.
TEST Pin
This pin must be connected to DVSS.
TEST Pin
This pin must be connected to DVSS.
TEST Pin
This pin must be connected to DVSS.
Unlock Status Pin
Digital Power Supply Pin, 3.0 ∼ 3.6V
Digital Ground Pin
Soft Mute Pin
“H” : Soft Mute, “L” : Normal Operation
Dither Enable Pin
“H” : Dither ON, “L” : Dither OFF
Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initializes the control register.
The AK4126 should be reset once by bringing PDN pin = “L” upon power-up.
Soft Mute Timer Select #0 Pin
Soft Mute Timer Select #1 Pin
De-emphasis Control #0 Pin
De-emphasis Control #1 Pin
4ch/6ch Mode Select Pin
Bit Length Select #0 Pin for Output Data
Bit Length Select #1 Pin for Output Data
Note: All input pins should not be left floating.
MS0544-E-00
2006/09
-5-
ASAHI KASEI
[AK4126]
PIN / FUNCTION
No.
Pin Name
I/O
32
TST5
I
34
TEST1
I
35
TEST2
I
36
TEST3
I
37
38
39
40
41
ODIF1
ODIF0
SDTO3
SDTO2
SDTO1
I
I
O
O
O
42
TST6
I
43
44
45
46
DVSS
DVDD
OBICK
OLRCK
I
I
47
TEST4
I
50
TST7
I
51
TST8
I
52
53
54
55
56
DVDD
DVSS
PLL2
PLL1
PLL0
I
I
I
57
TST9
I
58
TST10
I
60
61
62
AVDD
FILT
AVSS
O
-
63
TST11
O
Function
TEST Pin
This pin must be connected to DVSS.
TEST Pin
This pin must be connected to DVDD.
TEST Pin
This pin must be connected to DVSS.
TEST Pin
This pin must be connected to DVSS.
Audio Interface Format #1 Pin for Output PORT
Audio Interface Format #0 Pin for Output PORT
Audio Serial Data Output #3 Pin for Output PORT
Audio Serial Data Output #2 Pin for Output PORT
Audio Serial Data Output #1 Pin for Output PORT
TEST Pin
This pin must be connected to DVSS.
Digital Ground Pin
Digital Power Supply Pin, 3.0 ∼ 3.6V
Audio Serial Data Clock Pin for Output PORT
Output Channel Clock Pin for Output PORT
TEST Pin
This pin must be connected to DVSS.
TEST Pin
This pin must be connected to DVSS.
TEST Pin
This pin must be connected to DVSS.
Digital Power Supply Pin, 3.0 ∼ 3.6V
Digital Ground Pin
PLL Mode Select #2 Pin
PLL Mode Select #1 Pin
PLL Mode Select #0 Pin
TEST Pin
This pin must be connected to DVSS.
TEST Pin
This pin must be connected to DVSS.
Analog Power Supply Pin, 3.0 ∼ 3.6V
PLL Loop Filter Pin
Analog Ground Pin
TEST Pin
This pin must be open.
Note: All input pins should not be left floating.
MS0544-E-00
2006/09
-6-
ASAHI KASEI
[AK4126]
„ Handling of Unused pins
The unused digital I/O pins should be processed appropriately as below.
Classification
Digital
Pin Name
SMUTE, DITHER, PM,
TEST0, TEST2 ∼4, NC,
TST0 ∼10, SDTI1,
SDTI2, SDTI3
TEST1
UNLOCK, SDTO1,
SDTO2, SDTO3, TST11
Setting
These pins must be connected to DVSS.
This pin must be connected to DVDD.
These pins must be open.
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 1)
Parameter
Power Supplies:
Analog
(Note 2)
Digital
Input Current, Any Pin Except Supplies
Digital Input Voltage
(Note 3)
Ambient Temperature (Power applied) (Note 4)
Storage Temperature
Symbol
min
max
Units
AVDD
DVDD
IIN
VIND
Ta
Tstg
−0.3
−0.3
−0.3
−40
−65
4.6
4.6
±10
DVDD+0.3
85
150
V
V
mA
V
°C
°C
Note 1. All voltages with respect to ground.
Note 2. AVSS and DVSS must be connected to the same ground.
Note 3. IDIF2-0, DEM1-0, ODIF1-0, OBIT1-0, OLRCK, OBICK, PDN, SMUTE, PM, SMT1-0, TEST4-0, TST10-0,
PLL2-0, SDTI3-1, ILRCK and IBICK pins
Note 4. In case that wiring density is 100%.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 1)
Parameter
Symbol
min
typ
Power Supplies:
Analog
AVDD
3.0
3.3
(Note 5)
Digital
DVDD
3.0
3.3
Difference
AVDD - DVDD
-0.3
0
max
3.6
3.6
+0.3
Units
V
V
V
Note 1. All voltages with respect to ground.
Note 5. The power up sequence between AVDD and DVDD is not critical.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0544-E-00
2006/09
-7-
ASAHI KASEI
[AK4126]
SRC CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=3.3V; AVSS=DVSS=0V; Signal Frequency = 1kHz; data = 24bit;
Measurement bandwidth = 20Hz ~ FSO/2; unless otherwise specified.)
Parameter
Symbol
min
typ
SRC Characteristics:
Resolution
Input Sample Rate
FSI
8
Output Sample Rate
FSO
8
THD+N
(Input = 1kHz, 0dBFS, Note 6)
FSO/FSI = 44.1kHz/48kHz
−130
FSO/FSI = 48kHz/44.1kHz
−124
FSO/FSI = 48kHz/192kHz
−133
FSO/FSI = 192kHz/48kHz
−124
Worst Case (FSO/FSI = 32kHz/176.4kHz)
Dynamic Range (Input = 1kHz, −60dBFS, Note 6)
FSO/FSI = 44.1kHz/48kHz
136
FSO/FSI = 48kHz/44.1kHz
136
FSO/FSI = 48kHz/192kHz
136
FSO/FSI = 192kHz/48kHz
136
Worst Case (FSO/FSI = 48kHz/32kHz)
132
Dynamic Range (Input = 1kHz, −60dBFS, A-weighted, Note 6)
FSO/FSI = 44.1kHz/48kHz
140
Ratio between Input and Output Sample Rate
FSO/FSI
1/6
max
Units
24
192
192
Bits
kHz
kHz
−91
dB
dB
dB
dB
dB
-
dB
dB
dB
dB
dB
6
dB
-
Note 6. Measured by Audio Precision System Two Cascade.
MS0544-E-00
2006/09
-8-
ASAHI KASEI
[AK4126]
FILTER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V)
Parameter
Symbol
min
Digital Filter
Passband −0.01dB
0.985 ≤ FSO/FSI ≤ 6.000
PB
0
0.905 ≤ FSO/FSI < 0.985
PB
0
0.714 ≤ FSO/FSI < 0.905
PB
0
0.656 ≤ FSO/FSI < 0.714
PB
0
0.536 ≤ FSO/FSI < 0.656
PB
0
0.492 ≤ FSO/FSI < 0.536
PB
0
0.452 ≤ FSO/FSI < 0.492
PB
0
0.357 ≤ FSO/FSI < 0.452
PB
0
0.324 ≤ FSO/FSI < 0.357
PB
0
0.246 ≤ FSO/FSI < 0.324
PB
0
0.226 ≤ FSO/FSI < 0.246
PB
0
0.1667 ≤ FSO/FSI < 0.226
PB
0
Stopband
0.985 ≤ FSO/FSI ≤ 6.000
SB
0.5417FSI
0.905 ≤ FSO/FSI < 0.985
SB
0.5021FSI
0.714 ≤ FSO/FSI < 0.905
SB
0.3965FSI
0.656 ≤ FSO/FSI < 0.714
SB
0.3643FSI
0.536 ≤ FSO/FSI < 0.656
SB
0.2974FSI
0.492 ≤ FSO/FSI < 0.536
SB
0.2813FSI
0.452 ≤ FSO/FSI < 0.492
SB
0.2604FSI
0.357 ≤ FSO/FSI < 0.452
SB
0.2116FSI
0.324 ≤ FSO/FSI < 0.357
SB
0.1969FSI
0.246 ≤ FSO/FSI < 0.324
SB
0.1573FSI
0.226 ≤ FSO/FSI < 0.246
SB
0.1471FSI
0.1667 ≤ FSO/FSI < 0.226
SB
0.1020FSI
Passband Ripple
PR
Stopband
0.985 ≤ FSO/FSI ≤ 6.000
SA
121.2
Attenuation
0.905 ≤ FSO/FSI < 0.985
SA
121.4
0.714 ≤ FSO/FSI < 0.905
SA
115.3
0.656 ≤ FSO/FSI < 0.714
SA
116.9
0.536 ≤ FSO/FSI < 0.656
SA
114.6
0.492 ≤ FSO/FSI < 0.536
SA
100.2
0.452 ≤ FSO/FSI < 0.492
SA
103.3
0.357 ≤ FSO/FSI < 0.452
SA
102.0
0.324 ≤ FSO/FSI < 0.357
SA
103.6
0.246 ≤ FSO/FSI < 0.324
SA
104.0
0.226 ≤ FSO/FSI < 0.246
SA
103.3
0.1667 ≤ FSO/FSI < 0.226
SA
73.2
Group Delay
(Note 7)
GD
-
typ
max
Units
0.4583FSI
0.4167FSI
0.3195FSI
0.2852FSI
0.2182FSI
0.2177FSI
0.1948FSI
0.1458FSI
0.1302FSI
0.0917FSI
0.0826FSI
0.0583FSI
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
1/fs
±0.01
57
-
Note 7. This value is the time from the rising edge of LRCK after data is input to rising edge of LRCK after data is output,
when LRCK for Output data corresponds with LRCK for Input.
MS0544-E-00
2006/09
-9-
ASAHI KASEI
[AK4126]
DC CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
High-Level Output Voltage
(Iout=−400µA)
VOH
DVDD−0.4
Low-Level Output Voltage
(Iout=400µA)
VOL
Input Leakage Current
Iin
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
FSI=FSO=48kHz: AVDD=DVDD=3.3V
FSI=FSO=192kHz: AVDD=DVDD=3.3V
AVDD=DVDD=3.6V
Power down (PDN pin = “L”)
(Note 8)
AVDD+DVDD
typ
-
max
30%DVDD
0.4
±10
Units
V
V
V
V
µA
48
192
250
mA
mA
mA
10
100
µA
Note 8. All digital input pins are held DVSS.
This value is measured after the internal SRAM is initialized by inputting “0” data to SDTI1, SDTI2, and SDTI3
during (ILRCK x 100) cycles.
MS0544-E-00
2006/09
- 10 -
ASAHI KASEI
[AK4126]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
LRCK for Input data (ILRCK)
Frequency
fs
8
Duty Cycle
Duty
48
LRCK for Output data (OLRCK)
Frequency
fs
8
Duty Cycle
Duty
48
Audio Interface Timing
Input PORT
IBICK Period
IBICK Pulse Width Low
Pulse Width High
ILRCK Edge to IBICK “↑”
(Note 9)
IBICK “↑” to ILRCK Edge
(Note 9)
SDTI Hold Time from IBICK “↑”
SDTI Setup Time to IBICK “↑”
Output PORT
OBICK Period
OBICK Pulse Width Low
Pulse Width High
OLRCK Edge to OBICK “↑”
(Note 9)
OBICK “↑” to OLRCK Edge
(Note 9)
OLRCK to SDTO (MSB) (Except I2S mode)
OBICK “↓” to SDTO
Reset Timing
PDN Pulse Width
(Note 10)
typ
max
Units
50
192
52
kHz
%
50
192
52
kHz
%
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
1/64fs
27
27
15
15
15
15
ns
ns
ns
ns
ns
ns
ns
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/64fs
27
27
20
20
ns
ns
ns
ns
ns
ns
ns
tPD
150
20
20
ns
Note 9. BICK rising edge must not occur at the same time as LRCK edge.
Note 10. The AK4126 can be reset by bringing the PDN pin = “L”.
MS0544-E-00
2006/09
- 11 -
ASAHI KASEI
[AK4126]
„ Timing Diagram
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSD
tLRS
SDTO
50%DVDD
tSDH
tSDS
VIH
SDTI
VIL
Audio Interface Timing
Note: BICK shows IBICK and OBICK. LRCK shows ILRCK and OLRCK. SDTI shows SDTI1, SDTI2 and SDTI2.
SDTO shows SDTO1, SDTO2 and SDTO3.
tPD
PDN
VIL
Power Down & Reset Timing
MS0544-E-00
2006/09
- 12 -
ASAHI KASEI
[AK4126]
OPERATION OVERVIEW
„ System Clock & Audio Interface Format for Input PORT
The input port works in slave mode. The clocks supply ILRCK and IBICK externally. An internal system clock is created
by the internal PLL using ILRCK (Mode 0 ∼ 2 of Table 2) or IBICK (Mode 4, 5, 7of Table 2). The PLL2-0 pins and
IDIF2-0 pins select the PLL mode. The PLL2-0 pins and IDIF2-0 pins should be controlled when PDN pin = “L”.
The IDIF2-0 pins select the audio interface format for the input port. The audio data is MSB first, 2’s complement format.
The SDTI is latched on the rising edge of IBICK. Select the audio interface format when PDN pin = “L”. The audio
interface format of SDTI1, SDTI2 and SDTI3 becomes the same setting. The maximum input frequency of IBICK is 64fsi.
Mode
0
1
2
3
4
5
6
7
IDIF2
L
L
L
L
H
H
H
H
IDIF1
L
L
H
H
L
L
H
H
IDIF0
L
H
L
H
L
H
L
H
SDTI Format
IBICK Frequency
16bit, LSB justified
≥ 32fsi
20bit, LSB justified
≥ 40fsi
24/20bit, MSB justified
≥ 48fsi
24/16bit, I2S Compatible
≥ 48fsi or 32fsi
24bit, LSB justified
≥ 48fsi
Reserved
Reserved
Reserved
Table 1. Input Audio Interface Format (Input PORT)
SMUTE
(Note 14)
Mode
PLL2
PLL1
PLL0
ILRCK Freq
IBICK Freq
0
L
L
L
1
L
L
H
2
L
H
L
8k ∼ 96kHz
8k ∼ 192kHz
16k ∼ 192kHz
(Note 11)
Depending on
IDIF2-0
(Note 12)
3
4
5
6
L
H
H
H
H
L
L
H
H
L
H
L
8k ∼ 192kHz
(Note 12)
Reserved
32fsi (Note 13)
64fsi
Reserved
Manual
7
H
H
H
8k ∼ 192kHz
(Note 12)
64fsi
Semi-Auto
Manual
Semi-Auto
Note 11. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter”.
Note 12. The IBCIK must be continuous except when the clocks are changed.
Note 13. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible.
Note 14. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode.
Table 2. PLL Setting (Input PORT)
MS0544-E-00
2006/09
- 13 -
ASAHI KASEI
[AK4126]
ILRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
IBICK(32fs)
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
0 1 2 3
17 18 19 20
31 0 1 2 3
7 6 5 4 3 2 1 0 15
17 18 19 20
31 0 1
IBICK(64fs)
SDTI(i)
Don't Care
15 14 13 12
1 0
Don't Care
15 14 13 12
2 1 0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 0 Timing
ILRCK
0 1 2
12 13
24
31 0 1 2
12 13
24
31 0 1
IBICK(64fs)
SDTI(i)
19
Don't Care
8
1 0
Don't Care
19
8
1 0
19:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 1 Timing
ILRCK
0 1 2
20 21 22 23 24
31 0 1 2
20 21 22 23 24
31 0 1
IBICK(64fs)
SDTI(i)
23 22
4 3 2 1 0
Don't Care 23 22
4 3 2 1 0
Don't Care 23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 2 Timing (24bit MSB)
ILRCK
0 1 2 3
21 22 23 24 25
0 1 2
21 22 23 24 25
0 1
IBICK(64fs)
SDTI(i)
23 22
4 3 2 1 0 Don't Care 23 22
4 3 2 1 0
Don't Care
23:MSB, 0:LSB
Lch Data
Rch Data
2
Figure 5. Mode 3 Timing (24bit I S)
MS0544-E-00
2006/09
- 14 -
ASAHI KASEI
[AK4126]
ILRCK
0 1 2
8 9
24
31 0 1 2
8 9
24
31 0 1
IBICK(64fs)
Don't Care
SDTI(i)
23
8
1 0
Don't Care
23
8
1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 6. Mode 4 Timing
Note: SDTI shows SDTI1, SDTI2 and SDTI3.
„ System Clock & Audio Interface Format for Output PORT
The output port works in slave mode. The clocks supply OLRCK and OBICK externally. The ODIF1-0 pins and OBIT1-0
pins select the audio interface format for the output port. The audio data is MSB first, 2’s complement format. The SDTO
is clocked out on the falling edge of OBICK. Select the audio interface format when PDN pin = “L”. The audio interface
format of SDTO1, SDTO2 and SDTO3 becomes the same setting. The maximum input frequency of OBICK is 64fso.
Mode
0
1
2
3
ODIF1
L
L
H
H
ODIF0
L
H
L
H
SDTO Format
LSB justified
(Reserved)
MSB justified
I2S Compatible
Table 3. Output Audio Interface Format 1 (Output PORT)
Mode
OBIT1
OBIT0
SDTO
0
1
2
3
L
L
H
H
L
H
L
H
16bit
18bit
20bit
24bit
OBICK Frequency
MSB justified, I2S LSB justified
≥ 32fso
≥ 36fso
64fso
≥ 40fso
≥ 48fso
Table 4. Output Audio Interface Format 2 (Output PORT)
OLRCK
0 1
8 9 10 11 12 13 14 15 16 17
20 21 22 23
29 30 31 0 1
8 9 10 11 12 13 14 15 16 17
20 21 22 23
29 30 31 0 1 2
OBICK(64fs)
15 14
11 10 9 8
2 1 0
15 14
11 10 9 8
2 1 0
17 16 15 14
11 10 9 8
2 1 0
17 16 15 14
11 10 9 8
2 1 0
19 18 17 16 15 14
11 10 9 8
2 1 0
19 18 17 16 15 14
11 10 9 8
2 1 0
11 10 9 8
2 1 0
23 22 21 20 19 18 17 16 15 14
11 10 9 8
2 1 0
SDTO(O)
15:MSB, 0:LSB
SDTO(O)
17:MSB, 0:LSB
SDTO(O)
19:MSB, 0:LSB
SDTO(O)
23 22 21 20 19 18 17 16 15 14
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 7. LSB Timing
MS0544-E-00
2006/09
- 15 -
ASAHI KASEI
[AK4126]
OLRCK
0 1 2 3 4
13 14 15 16 17 18 19 20 21 22 23 24
31 0 1 2 3 4
13 14 15 16 17 18 19 20 21 22 23 24
31 0 1 2
OBICK(64fs)
SDTO(O)
15 14 13 12
2 1 0
15 14 13 12
2 1 0
15 14
17 16 15 14
4 3 2 1 0
17 16
19 18 17 16
6 5 4 3 2 1 0
19 18
23 22 21 20
10 9 8 7 6 5 4 3 2 1 0
23 22
15:MSB, 0:LSB
SDTO(O)
17 16 15 14
4 3 2 1 0
17:MSB, 0:LSB
SDTO(O)
19 18 17 16
6 5 4 3 2 1 0
19:MSB, 0:LSB
SDTO(O)
23 22 21 20
10 9 8 7 6 5 4 3 2 1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 8. MSB Timing
OLRCK
0 1 2 3 4
14 15 16 17 18 19 20 21 22 23 24
0 1 2 3 4
14 15 16 17 18 19 20 21 22 23 24
31 0 1 2
OBICK(64fs)
SDTO(O)
15 14 13 12
2 1 0
15 14 13 12
2 1 0
15
17 16 15 14
4 3 2 1 0
17
19 18 17 16
6 5 4 3 2 1 0
19
23 22 21 20
10 9 8 7 6 5 4 3 2 1 0
23
15:MSB, 0:LSB
SDTO(O)
17 16 15 14
4 3 2 1 0
17:MSB, 0:LSB
SDTO(O)
19 18 17 16
6 5 4 3 2 1 0
19:MSB, 0:LSB
SDTO(O)
23 22 21 20
10 9 8 7 6 5 4 3 2 1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 9. I2S Compatible Timing
Note: SDTO shows SDTO1, SDTO2 and SDTO3.
„ 4-channel Mode
The AK4126 has 4-channel mode to reduce power supply current when using four channels in six channels. When PM pin
is set to “H”, four channels (SDTI1Æ SDTO1 and SDTI2 Æ SDTO2) in six channels work, and other 2 channels (SDTI3
Æ SDTO3) are powered-down (SDTO3 outputs “L”.).
PM pin
Mode
L
6-channel mode
H
4-channel mode
Table 5. Channel Mode Setting
MS0544-E-00
2006/09
- 16 -
ASAHI KASEI
[AK4126]
„ Soft Mute Operation
1. Manual mode
The soft mute operation is performed in the digital domain of the SRC output. The soft mute can be controlled by SMUTE
pin. When SMUTE pin goes “H”, all the SRC output data are attenuated by −∞ during 1024 OLRCK cycles (@ SMT1 pin
= “L” and SMT0 pin = “L”). When the SMUTE pin goes “L” the mute is cancelled and the output attenuation gradually
changes to 0dB during 1024 OLRCK cycles (@ SMT1 pin = “L” and SMT0 pin = “L”). If the soft mute is cancelled before
mute state after starting of the operation, the attenuation is discontinued and returned to 0dB by the same cycles. The soft
mute is effective for changing the signal source. Soft mute cycle is selected by SMT1-0 pins. SMT1-0 pins must not be
changed during soft mute transition.
SMT1pin
L
L
H
H
SMT0 pin
L
H
L
H
Period
fso=48kHz
fso=96kHz
1024/fso
21.3ms
10.7ms
2048/fso
42.7ms
21.3ms
4096/fso
85.3ms
42.7ms
8192/fso
170.7ms
85.3ms
Table 6. Soft Mute Cycle Setting
fso=192kHz
5.3ms
10.7ms
21.3ms
42.7ms
SM U T E
0dB
(1)
(1)
(2)
Attenuation
-∞
SD T O
Note: SDTO shows SDTO1, SDTO2 and SDTO3.
(1) The soft mute cycle is selected by SMT1-0 pins. (See Table 6) The output data is attenuated by −∞ during the soft mute
cycle.
(2) If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is discontinued and
returned to 0dB by the same number of clock cycles.
Figure 10. Soft Mute Function (Manual Mode)
MS0544-E-00
2006/09
- 17 -
ASAHI KASEI
[AK4126]
2. Semi-Auto mode
The soft mute is cancelled automatically by the setting of PLL2-0 pins (refer to Table 2), after the AK4126 detects the
rising edge (PDN pin = “L” → “H”) and the mute is continued during [email protected]=44.1kHz. After PDN pin =
“L” → “H” and when SMUTE pin is “H”, the mute is not cancelled.
PD N pin
“L”
D on’t care
SM U T E pin
“L”
(1)
0dB
Attenuation
4410/fso
-∞
SD T O
Note: SDTO shows SDTO1, SDTO2 and SDTO3.
(1) The output data is attenuated by −∞ during the soft mute cycle (See Table 6)
Figure 11. Soft Mute Function (Semi-Auto Mode)
„ Dither
The AK4126 includes the dither circuit. The dither circuit adds the dither to the LSB of all the output data set with the
OBIT1-0 pins by DITHER pin = “H”.
„ De-emphasis Filter
The AK4126 includes a digital de-emphasis filter (tc = 50/15µs) via an IIR filter. This filter corresponds to three
frequencies (32kHz, 44.1kHz and 48kHz). This setting is done via DEM1-0 pins (See Table 7), and it is applied to all input
data.
DEM1pin
DEM0 pin
Mode
L
L
44.1kHz
L
H
OFF
H
L
48kHz
H
H
32kHz
Table 7. De-emphasis Filter Setting
MS0544-E-00
2006/09
- 18 -
ASAHI KASEI
[AK4126]
„ System Reset
Bringing the PDN pin = “L” sets the AK4126 power-down mode and initializes the digital filter. The AK4126 should be
reset once by bringing PDN pin = “L” upon power-up. When PDN pin = “L”, the SDTO output is “L”. The SDTO valid
time is 100ms. Until then, the SDTO outputs “L”. (SDTO shows SDTO1, SDTO2 and SDTO3. SDTI shows SDTI1,
SDTI2 and SDTI3.)
Case 1
External clocks
(Input port)
Don’t care
Input Clocks 1
Input Clocks 2
Don’t care
SDTI
Don’t care
Input Data 1
Input Data 2
Don’t care
External clocks
(Output port)
Don’t care
Output Clocks 1
Output Clocks 2
Don’t care
PDN
< 100ms
< 100ms
(Internal state) Power-down
SDTO
Normal
operation
PLL lock &
fs detection
“0” data
PD
Normal data
PLL lock &
fs detection
“0” data
Normal
operation
Power-down
Normal data
“0” data
UNLOCK
Figure 12. System Reset
Case 2
External clocks
(Input port)
(No Clock)
SDTI
External clocks
(Output port)
Input Clocks
Don’t care
(Don’t care)
Input Data
Don’t care
(Don’t care)
Output Clocks
Don’t care
PDN
< 100ms
(Internal state) Power-down
SDTO
PLL Unlock
“0” data
PLL lock &
fs detection
Normal
operation
Power-down
Normal data
“0” data
UNLOCK
Figure 13. System Reset 2
MS0544-E-00
2006/09
- 19 -
ASAHI KASEI
[AK4126]
„ Internal Reset Function for Clock Change
The change of the clock supplied to the AK4126 is shown in Figure 14. SDTO shows SDTO1, SDTO2 and SDTO3.
External clocks
(Input port
or Output port)
Clocks 1
Don’t care
Clocks 2
PDN pin
< 100ms
(Internal state) Normal operation Power-down PLL lock &
fs detection
SDTO
Normal data
SMUTE (Note2,
recommended)
Att.Level
Normal operation
Note1
Normal data
(1)
(1)
0dB
-∞dB
(1) Soft mute cycle. (See Table 6)
E.g. SMT1 pin = “L”, SMT0 pin = “L”, fso = 48kHz
Soft mute cycle: 1024/fso = 21.3ms
Note 1. The data on SDTO may cause a clicking noise. To prevent this, set SDTI to “0” from GD before PDN pin goes
“L”, which will cause the data on SDTO to remain “0”.
Note 2. SMUTE can also be used to remove the unknown data.
Figure 14. Sequence of changing clocks
„ UNLOCK pin
The UNLOCK pin outputs “L” when the internal PLL is locked. When the internal PLL is unlocked, the UNLOCK pin
outputs “H”. When PDN pin = “L”, the UNLOCK pin outputs “H”.
MS0544-E-00
2006/09
- 20 -
ASAHI KASEI
[AK4126]
„ PLL Loop Filter
The C1 and R should be connected in series and attached between FILT pin and AVSS in parallel with C2. (See Figure 15,
Table 8 and Table 9) Please be careful the noise onto the FILT pin. When using IBICK, the value of an external element
doesn't depend on the IBICK input frequency.
AK4126
FILT
R
C2
C1
AVSS
Figure 15. PLL Loop Filter
1. When using ILRCK
PLL2
L
PLL1
L
L
L
L
H
PLL0
L
ILRCK
R [Ω]
8k ∼ 96kHz
1.8k ± 5%
8k ∼ 192kHz
1k ± 5%
H
16k ∼ 192kHz
1.5k ± 5%
8k ∼ 192kHz
1k ± 5%
L
16k ∼ 192kHz
1.5k ± 5%
Table 8. PLL Loop Filter (ILRCK Mode)
C1 [µF]
0.68 ± 30%
1.0 ± 30%
0.68 ± 30%
1.0 ± 30%
0.68 ± 30%
C2 [nF]
0.68 ± 30%
2.2 ± 30%
0.68 ± 30%
2.2 ± 30%
0.68 ± 30%
- Note. Smaller value can be selected for the capacitors (C1, C2) in case of ILRCK range from 16kHz to 192kHz.
- Note. Tolerance of R, C1, and C2 includes the temperature characteristics.
2. When using IBICK
PLL2
H
PLL1
x
PLL0
ILRCK
R [Ω]
C1 [µF]
x
8k ∼ 192kHz
470 ± 5%
0.22 ± 30%
Table 9. PLL Loop Filter (IBICK Mode, “x”: Don’t care)
C2 [nF]
1.0 ± 30%
- Note. The IBCIK must be continuous except when the clocks are changed.
- Note. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible.
- Note. Tolerance of R, C1, and C2 includes the temperature characteristics.
MS0544-E-00
2006/09
- 21 -
ASAHI KASEI
[AK4126]
SYSTEM DESIGN
Figure 16 shows the system connection diagram. An evaluation board is available which demonstrates application circuits,
the optimum layout, power supply arrangements and measurement results.
• Input PORT: Slave mode, IBICK lock mode (64fsi), 24 bit MSB justified
• Output PORT: Slave mode, 24 bit MSB justified
• Dither = OFF, De-emphasis = OFF, PM = 6ch mode
3.3V
C1: 0.1µ
C2: 10µ
+
470Ω
C2
C1
0.22µ
1n
+
C2
59
58
57
56
55
54
53
52
51
50
49
NC
TST9
PLL0
PLL1
PLL2
DVSS
DVDD
TST8
TST7
NC
AVSS
60
TST10
TST11
61
FILT
62
AVDD
63
NC
C1
64
1 NC
fsi
64fsi
NC 48
2 TEST0
TEST4 47
3 ILRCK
OLRCK 46
4 IBICK
OBICK 45
5 DVDD
DVDD 44
6 DVSS
DVSS 43
7 TST0
TST6 42
fso
64fso
C1
C1
DSP1
8 SDTI1
SDTO1 41
Top View
9 SDTI2
SDTO2 40
10 SDTI3
SDTO3 39
11 IDIF0
ODIF0 38
12 IDIF1
ODIF1 37
13 IDIF2
TEST3 36
14 TST1
TEST2 35
15 TST2
TEST1 34
TST4
UNLOCK
DVDD
DVSS
SMUTE
DITHER
PDN
SMT0
SMT1
DEM0
DEM1
PM
OBIT0
OBIT1
TST5
NC 33
TST3
16 NC
DSP2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C1
+
C2
uP
Notes:
- All digital input pins should be not left floating.
- AVSS and DVSS must be connected to the same ground plane.
Figure 16. Typical Connection Diagram
MS0544-E-00
2006/09
- 22 -
ASAHI KASEI
[AK4126]
1. Grounding and Power Supply Decoupling
The AK4126 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD
are supplied separately, the power up sequence is not critical. AVSS and DVSS must be connected to the same
ground plane. Decoupling capacitors should be as near to the AK4126 as possible, with the small value ceramic
capacitor being the nearest.
2. Jitter Tolerance
Figure 17 shows the jitter tolerance to ILRCK and IBICK for AK4126. The jitter frequency and the jitter amplitude shown
in Figure 17 define the jitter quantity. When the jitter amplitude is 0.01Uipp or less, the AK4126 operate normally
regardless of the jitter frequency.
AK4125
AK4126 Jitter
Jitter Tolerance
Tolerance
10.00
Amplitude [UIpp]
1.00
(3)
0.10
(2)
0.01
(1)
0.00
1
10
100
1000
10000
Jitter Frequency [Hz]
(1) Normal operation
(2) There is a possibility that the distortion degrades. (It may degrade up to about −50dB.)
(3) There is a possibility that the output data is lost.
Note:
- When PLL2-0 = “L/L/L”, “L/L/H”, “L/H/L”, the jitter amplitude is for ILRCK and 1UI (Unit Interval) is one
cycle of ILRCK. When FSI = 48kHz, 1UI is 1/48kHz = 20.8µs.
- When PLL2-0 = “H/*/*” (*: Don’t care), the jitter amplitude is for IBICK and 1UI (Unit Interval) is one cycle of
IBICK. When FSI = 48kHz, 1UI is 1/(64 x 48kHz) = 326ns.
Figure 17. Jitter Tolerance
MS0544-E-00
2006/09
- 23 -
ASAHI KASEI
[AK4126]
Tracking to the Input Sampling Frequency
When the ILRCK is generated by an external PLL, it may take a time to settle after changing the input sampling frequency
because the response of an external PLL to the frequency change is slow. AK4126 operates normally up to 23%/sec speed
and the output data becomes incorrect at the speed of the frequency change over 23%/sec.
3. Digital Filter Response Example
Table 10 shows the examples of digital filter response performed by the AK4126.
Ratio
FSO/FSI [kHz]
4.000
1.000
0.919
0.725
0.667
0.544
0.500
0.500
0.459
0.363
0.333
0.250
0.250
0.230
0.167
0.181
0.167
0.181
192/48.0
48.0/48.0
44.1/48.0
32.0/44.1
32.0/48.0
48.0/88.2
48.0/96.0
44.1/88.2
44.1/96.0
32.0/88.2
32.0/96.0
48.0/192.0
44.1/176.4
44.1/192.0
32.0/192.0
32.0/176.4
8/48.0
8/44.1
Stopband
Attenuation [dB]
22.000
26.000
−121.2
22.000
26.000
−121.2
20.000
24.100
−121.4
14.088
17.487
−115.3
13.688
17.488
−116.9
19.250
26.232
−114.6
20.900
27.000
−100.2
19.202
24.806
−100.2
18.700
25.000
−103.3
12.863
18.665
−102.0
12.500
18.900
−103.6
17.600
30.200
−104.0
16.170
27.746
−104.0
15.860
28.240
−103.3
11.200
19.600
−73.2
10.278
17.987
−73.2
2.800
4.900
−73.2
2.5695
4.4968
−73.2
Table 10. Digital Filter Example
Passband [kHz]
Stopband [kHz]
MS0544-E-00
Gain [dB]
−0.01@ 20k
−0.01@ 20k
−0.01@ 20k
−0.01@ 14.5k
−0.19@ 14.5k
−0.03@ 20k
−0.01@ 20k
−0.08@ 20k
−0.23@ 20k
−0.75@ 14.5k
−1.07@ 14.5k
−0.18@ 20k
−1.34@ 20k
−1.40@ 20k
−2.97@ 14.5k
−7.88@ 14.5k
−2.97@ 3.625k
−7.88@ 3.625k
2006/09
- 24 -
ASAHI KASEI
[AK4126]
PACKAGE
64pin LQFP(Unit:mm)
12.0±0.3
1.70max
0.10±0.10
10.0
1.40
33
48
32
64
17
0.5
12.0 ±0.3
49
0.17±0.05
1
16
0.21±0.05
0.10 M
1.0
0° ~10°
0.45±0.2
0.10
„ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0544-E-00
2006/09
- 25 -
ASAHI KASEI
[AK4126]
MARKING
AKM
AK4126VQ
XXXXXXX
1
XXXXXXX: Date code identifier
Revision History
Date (YY/MM/DD)
06/09/20
Revision
00
Reason
First Edition
Page
MS0544-E-00
Contents
2006/09
- 26 -
ASAHI KASEI
[AK4126]
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
a. A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
b. A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
MS0544-E-00
2006/09
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