AKM AKD4367

ASAHI KASEI
[AK4367]
AK4367
Low Power 24-Bit 2ch DAC with HP-AMP & Output Mixer
GENERAL DESCRIPTION
The AK4367 is 24bit DAC with built-in Headphone Amplifier. The AK4367 features an analog mixing
circuit that allows easy interfacing in mobile phone and portable communication designs. The integrated
headphone amplifier features “pop-free” power-on/off, a mute control and delivers 50mW of power at
16Ω. The AK4367 is housed in a 20pin QFN package, making it suitable for portable applications.
FEATURE
† Multi-bit ∆Σ DAC
† Sampling Rate: 8kHz∼48kHz
† 64x Oversampling
† On chip perfect filtering 8 times FIR interpolator
- Passband: 20kHz
- Passband Ripple: ±0.02dB
- Stopband Attenuation: 54dB
† Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz
† System Clock: 256fs/384fs/512fs
- AC Couple Input Available
† Audio I/F Format: MSB First, 2’s Compliment
- I2S, 24bit MSB justified, 24bit/20bit/16bit LSB justified
† Digital ATT
† Analog Mixing Circuit
† Mono Lineout
† µP Interface: 3-wire/I2C
† Bass Boost Function
† Headphone Amplifier
- Output Power: 50mW x 2ch @16Ω, 3.3V
- S/N: [email protected]
- Pop Noise Free at Power-ON/OFF and Mute
† Power Supply: 2.2V ∼ 3.6V
† Power Supply Current: [email protected] (@HP-AMP no-output)
† Ta: −40 ∼ 85°C
† Small Package: 20pin QFN
MS0247-E-02
2005/10
-1-
ASAHI KASEI
[AK4367]
LIN
MCLK
BICK
LRCK
SDATA
Audio
Interface
MIN
VDD
Clock
Divider
VCOM
VCOM
HDP
Amp
DAC
(Lch)
ATT
&
Bass
Boost
MUTE
DEM
&
Digital
Filter
HPL
MOUT
HDP
Amp
DAC
(Rch)
MUTE
HPR
PDN
HVDD
I2C
CAD0/CSN
SCL/CCLK
MUTET
Serial I/F
SDA/CDTI
RIN
VSS
Figure 1. AK4367 Block Diagram
MS0247-E-02
2005/10
-2-
ASAHI KASEI
[AK4367]
„ Ordering Guide
AK4367VN
AKD4367
−40 ∼ +85°C
20pin QFN (0.5mm pitch)
Evaluation board for AK4367
HVDD
VSS
VDD
MUTET
VCOM
14
13
12
11
5
20
LRCK
LIN
Top View
4
19
SDATA
RIN
3
18
CAD0/CSN
MIN
AK4367
2
17
SCL/CCLK
HPL
1
16
SDA/CDTI
HPR
15
„ Pin Layout
MS0247-E-02
10
MOUT
9
I2C
8
PDN
7
MCLK
6
BICK
2005/10
-3-
ASAHI KASEI
[AK4367]
PIN/FUNCTION
No.
4
Pin Name
SDA
CDTI
SCL
CCLK
CAD0
CSN
SDATA
5
LRCK
I
6
BICK
I
7
MCLK
I
8
PDN
I
9
I2C
I
10
MOUT
O
11
VCOM
O
12
MUTET
O
13
14
15
16
17
18
19
20
VDD
VSS
HVDD
HPR
HPL
MIN
RIN
LIN
O
O
I
I
I
1
2
3
I/O
I/O
I
I
I
I
I
I
Function
Control Data Input/Output Pin (I2C pin = “H”)
Control Data Input Pin (I2C pin = “L”)
Control Data Clock Pin (I2C pin = “H”)
Control Data Clock Pin (I2C pin = “L”)
Chip Address 0 Select Pin (I2C pin = “H”)
Control Data Chip Select Pin (I2C pin = “L”)
Audio Serial Data Input Pin
L/R Clock Pin
This clock determines which audio channel is currently being input on SDATA pin.
Serial Bit Clock Pin
This clock is used to latch audio data.
Master Clock Input Pin
Power-down & Reset Pin
When at “L”, the AK4367 is in power-down mode and is held in reset.
The AK4367 should always be reset upon power-up.
Control Mode Select Pin (Internal Pull-down Pin)
“H”: I2C Bus, “L”: 3-wire Serial
Mono Analog Output Pin
Common Voltage Output Pin
Normally connected to VSS pin with 0.1µF ceramic capacitor in parallel with a 2.2µF
electrolytic capacitor.
Mute Time Constant Control Pin
Connected to VSS pin with a capacitor for mute time constant.
Power Supply Pin
Ground Pin
Power Supply Pin for Headphone Amp
Rch Headphone Amp Output Pin
Lch Headphone Amp Output Pin
Mono Analog Input Pin
Rch Analog Input Pin
Lch Analog Input Pin
Note: All digital input pins except analog input pins (MIN, RIN and LIN) and internal pull-down pin must not be left
floating.
„ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
MOUT, MUTET, HPR, HPL, MIN, RIN, LIN
CAD0
MS0247-E-02
Setting
These pins should be open.
These pins should be connected to VSS.
2005/10
-4-
ASAHI KASEI
[AK4367]
ABSOLUATE MAXIMUM RATING
(VSS=0V; Note 1)
Parameter
Symbol
min
Power Supplies Analog, Digital
VDD
−0.3
HP-AMP
HVDD
−0.3
Input Current (any pins except for supplies)
IIN
Input Voltage
VIN
−0.3
Ambient Temperature
Ta
−40
Storage Temperature
Tstg
−65
Note 1. All voltages with respect to ground.
max
4.6
4.6
±10
VDD+0.3 or 4.6
85
150
Units
V
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMEND OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Symbol
min
typ
Power Supplies Analog, Digital
VDD
2.2
2.4
(Note 2)
HP-AMP
HVDD
2.2
2.4
Note 1. All voltages with respect to ground.
Note 2. VDD should be same voltage as HVDD.
max
3.6
3.6
Units
V
V
* AKM assumes no responsibility for usage beyond the conditions in this datasheet.
MS0247-E-02
2005/10
-5-
ASAHI KASEI
[AK4367]
ANALOG CHARACTERISTICS
(Ta=25°C; VDD=HVDD=2.4V, VSS=0V; fs=44.1kHz; BOOST OFF; Signal Frequency =1kHz; Measurement band
width=10Hz ∼ 20kHz; Headphone-Amp: Load impedance is a serial connection with RL =16Ω and CL=220µF. (Refer to
Figure 33); Mono output: RL =16Ω; unless otherwise specified)
Parameter
min
typ
max
Units
24
bit
DAC Resolution
Headphone-Amp: (HPL/HPR pins) (Note 3)
Analog Output Characteristics
THD+N
dB
−4.8dBFS Output, [email protected], 2.4V
−55
−45
dB
−3dBFS Output, [email protected], 3.3V
−55
dB
−3dBFS Output, [email protected], 3.3V
−57
D-Range −60dBFS Output, A-weighted, 2.4V
84
92
dB
94
dB
−60dBFS Output, A-weighted, 3.3V
S/N
A-weighted, 2.4V
84
92
dB
A-weighted, 3.3V
94
dB
Interchannel Isolation
60
80
dB
DC Accuracy
Interchannel Gain Mismatch
0.2
dB
Gain Drift
200
ppm/°C
Load Resistance
(Note 4)
16
Ω
Load Capacitance
300
Output Voltage
(Note 5)
1.02
1.13
1.24
Vpp
(−4.8dBFS Output)
Max Output Power
26
mW
RL=16Ω, 2.4V
50
mW
RL=16Ω, 3.3V
Mono Output: (MOUT pin) (Note 6)
Analog Output Characteristics:
THD+N
(0dBFS Output)
dB
−60
−50
S/N
(A-weighted)
84
92
dB
DC Accuracy
Gain Drift
200
ppm/°C
Load Resistance
(Note 4)
10
kΩ
Load Capacitance
25
pF
Output Voltage
(Note 7)
1.42
1.58
1.74
Vpp
Output Volume: (MOUT pin)
Step Size
1
2
3
dB
Gain Control Range
0
dB
−30
Note 3. DACL=DACR bits = “1”, MINL=MINR=LINL=RINR bits = “0”, ATTL=ATTR=0dB.
Note 4. AC Load
Note 5. Output voltage is proportional to VDD voltage. Vout = 0.47 x VDD(typ)@−4.8dBFS.
Note 6. DACM bit = “1”, DACL=DACR bits = “0”, LINM=RINM=MINM bits = “0”, ATTL=ATTR=ATTM=0dB, and
common mode signal is input to L/Rch of DAC.
Note 7. Output voltage is proportional to VDD voltage. Vout = 0.66 x VDD(typ).
MS0247-E-02
2005/10
-6-
ASAHI KASEI
[AK4367]
Parameter
min
typ
max
LINEIN: (LIN/RIN/MIN pins)
Analog Input Characteristics
Input Resistance (See Figure 31 and Figure 32.)
LIN pin
LINL bit = “1”, LINM bit = “1”
23
33
LINL bit = “1”, LINM bit = “0”
40
LINL bit = “0”, LINM bit = “1”
200
RIN pin
RINR bit = “1”, RINM bit = “1”
23
33
RINR bit = “1”, RINM bit = “0”
40
RINR bit = “0”, RINM bit = “1”
200
MIN pin
MINL bit = “1”, MINR bit = “1”, MINM bit = “1”
11
17
MINL bit = “1”, MINR bit = “0”, MINM bit = “0”
40
MINL bit = “0”, MINR bit = “1”, MINM bit = “0”
40
MINL bit = “0”, MINR bit = “0”, MINM bit = “1”
100
Gain
LIN/RIN→MOUT
−7
−6
−5
0
+1
MIN→MOUT
−1
+0.8
+1.8
+2.8
LIN/MIN→HPL, RIN/MIN→HPR
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
(Note 8)
VDD
1.8
3.0
HVDD
1.0
2.0
Power-Down Mode (PDN pin = “L”)
(Note 9)
1
100
Note 8. PMDAC=PMHPL=PMHPR=PMMO bits = “1”, MUTEN bit = “1” and HP-Amp output is off.
Note 9. All digital input pins including clock pins (MCLK, BICK and LRCK) are held at VSS.
Units
MS0247-E-02
2005/10
-7-
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
dB
dB
dB
mA
mA
µA
ASAHI KASEI
[AK4367]
FILTER CHARACTERISTICS
(Ta=25°C; VDD, HVDD=2.2 ∼ 3.6V; fs=44.1kHz; De-emphasis = “OFF”)
Parameter
Symbol
min
typ
max
Units
DAC Digital Filter: (Note 10)
Passband
PB
0
20.0
kHz
−0.05dB (Note 11)
22.05
kHz
−6.0dB
Stopband
(Note 11)
SB
24.1
kHz
Passband Ripple
PR
dB
±0.02
Stopband Attenuation
SA
54
dB
Group Delay
(Note 12)
GD
20.8
1/fs
Group Delay Distortion
0
µs
∆GD
DAC Digital Filter + Analog Filter: (Note 10) (Note 13)
Frequency Response
FR
dB
0 ∼ 20.0kHz
±0.5
Analog Filter: (Note 14)
Frequency Response
FR
dB
0 ∼ 20.0kHz
±1.0
BOOST Filter:
(Note 13) (Note 15)
Frequency Response
20Hz
FR
dB
5.76
MIN
100Hz
dB
2.92
1kHz
dB
0.02
20Hz
FR
dB
10.80
MID
100Hz
dB
6.84
1kHz
dB
0.13
20Hz
FR
dB
16.06
MAX 100Hz
dB
10.54
1kHz
dB
0.37
Note 10. BOOST OFF (BST1-0 bit = “00”)
Note 11. The passband and stopband frequencies scale with fs.
For example, PB=0.4535*fs(@±0.05dB), SB=0.546*fs(@−54dB).
Note 12. This is the calculated delay time caused by digital filtering. This time is measured from the setting of the 24bit
data of both channels to the input registers to the output of the analog signal.
Note 13. DAC Æ HPL, HPR, MOUT
Note 14. MIN Æ HPL/HPR/MOUT, LIN Æ HPL/MOUT, RIN Æ HPR/MOUT
Note 15. These frequency responses scale with fs. If high-level signal is input, the AK4367 clips at low frequency.
Boost Filter (fs=44.1kHz)
20
MAX
Level [dB]
15
MID
10
MIN
5
0
-5
10
100
1000
10000
Frequency [Hz]
Figure 2. Boost Frequency (fs=44.1kHz)
MS0247-E-02
2005/10
-8-
ASAHI KASEI
[AK4367]
DC CHARACTERISTICS
(Ta=25°C; VDD, HVDD=2.2 ∼ 3.6V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
Input Voltage at AC Coupling
(Note 16)
VAC
1.0
Low-Level Output Voltage
(Iout = 3mA)
VOL
Input Leakage Current
(Note 17)
Iin
Note 16. Only MCLK pin. (Figure 33)
Note 17. I2C pin has internal pull-down device, nominally 100kΩ.
typ
-
max
30%DVDD
0.4
±10
Units
V
V
Vpp
V
µA
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD, HVDD=2.2 ∼ 3.6V; CL = 20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Frequency
fCLK
2.048
24.576
MHz
Pulse Width Low
(Note 18)
tCLKL
0.4/fCLK
ns
Pulse Width High
(Note 18)
tCLKH
0.4/fCLK
ns
AC Pulse Width
(Note 21)
tACW
20
ns
LRCK Timing
Frequency
fs
8
44.1
48
kHz
Duty Cycle:
Duty
45
55
%
Serial Interface Timing (Note 19)
BICK Period
tBCK
1/(64fs)
ns
BICK Pulse Width Low
tBCKL
130
ns
Pulse Width High
tBCKH
130
ns
(Note 20)
tLRB
50
ns
LRCK Edge to BICK “↑”
(Note 20)
tBLR
50
ns
BICK “↑” to LRCK Edge
SDATA Hold Time
tSDH
50
ns
SDATA Setup Time
tSDS
50
ns
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK
200
ns
CCLK Pulse Width Low
tCCKL
80
ns
Pulse Width High
tCCKH
80
ns
CDTI Setup Time
tCDS
40
ns
CDTI Hold Time
tCDH
40
ns
CSN “H” Time
tCSW
150
ns
tCSS
50
ns
CSN “↑” to CCLK “↑”
tCSH
50
ns
CCLK “↑” to CSN “↑”
Note 18. Except AC coupling.
Note 19. Refer to “Serial Data Interface”.
Note 20. BICK rising edge must not occur at the same time as LRCK edge.
Note 21. Pulse width to ground level when MCLK is connected to a capacitor in series and a resistor is connected to
ground. (Refer to Figure 3.)
MS0247-E-02
2005/10
-9-
ASAHI KASEI
Parameter
Control Interface Timing (I2C Bus mode): (Note 22)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 23)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width
(Note 24)
[AK4367]
Symbol
min
typ
max
Units
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
4.7
4.0
4.7
4.0
4.7
0.25
4.0
0
-
100
1.0
0.3
50
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
tPD
150
-
-
ns
Note 22. I2C is a registered trademark of Philips Semiconductors.
Note 23. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 24. The AK4367 can be reset by bringing PDN pin = “L” to “H” only upon power up.
Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips
I2C patent to use the components in the I2C system, provided the system conform to the I2C
specifications defined by Philips.
MS0247-E-02
2005/10
- 10 -
ASAHI KASEI
[AK4367]
„ Timing Diagram
1/fCLK
tACW
1000pF
MCLK Input
tACW
Measurement Point
VAC
100kΩ
VSS
VSS
Figure 3. MCLK AC Coupling Timing
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 4. Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDATA
VIL
Figure 5. Serial Interface Timing
MS0247-E-02
2005/10
- 11 -
ASAHI KASEI
[AK4367]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
VIH
A4
VIL
Figure 6. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
CDTI
D3
D2
D1
VIH
D0
VIL
Figure 7. WRITE Data Input Timing
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Figure 8. I2C Bus Mode Timing
tPD
PDN
VIL
Figure 9. Power-down & Reset Timing
MS0247-E-02
2005/10
- 12 -
ASAHI KASEI
[AK4367]
OPERATION OVERVIEW
„ System Clock
The external clocks required to operate the AK4367 are MCLK(256fs/384fs/512fs), LRCK(fs) and BICK. The master
clock (MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter.
The frequency of MCLK is detected automatically, and the internal master clock becomes the appropriate frequency.
Table 1 shows system clock example.
LRCK
fs
8kHz
11.025kHz
12kHz
16kHz
22.05kHz
24kHz
32kHz
44.1kHz
48kHz
MCLK (MHz)
256fs
384fs
512fs
2.048
3.072
4.096
2.8224
4.2336
5.6448
3.072
4.608
6.144
4.096
6.144
8.192
5.6448
8.4672
11.2896
6.144
9.216
12.288
8.192
12.288
16.384
11.2896
16.9344
22.5792
12.288
18.432
24.576
Table 1. System Clock Example
BICK (MHz)
64fs
0.512
0.7056
0.768
1.024
1.4112
1.536
2.048
2.8224
3.072
All external clocks (MCLK, BICK and LRCK) should always be present whenever the DAC is in normal operation mode
(PMDAC bit = “1”). If these clocks are not provided, the AK4367 may draw excess current and will not operate properly
because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the DAC
should be placed in power-down mode (PMDAC bit = “0”). When MCLK is input with AC coupling, the MCKAC bit
should be set to “1”.
For low sampling rates, DR and S/N degrade because of the outband noise. DR and S/N are improved by setting DFS1 bit
to “1”. Table 2 shows S/N of DAC output for both the HP-amp and MOUT. When the DFS1 bit is “1”, MCLK needs
512fs.
DFS1
DFS0
0
0
1
0
1
x
S/N (fs=8kHz, A-weighted)
Over Sample
fs
MCLK
Rate
HP-amp
MOUT
64fs
256fs/384fs/512fs
56dB
56dB
8kHz∼48kHz
128fs
256fs/384fs/512fs
75dB
75dB
8kHz∼24kHz
256fs
512fs
92dB
90dB
8kHz∼12kHz
Table 2. Relationship among fs, MCLK frequency and S/N of HP-amp and MOUT
MS0247-E-02
Default
2005/10
- 13 -
ASAHI KASEI
[AK4367]
„ Serial Data Interface
The AK4367 interfaces with external system via the SDATA, BICK and LRCK pins. Five data formats are available and
are selected by setting DIF2, DIF1 and DIF0 bits (Table 3). Mode 0 is compatible with existing 16bit DACs and digital
filters. Mode 1 is a 20bit version of Mode 0. Mode 4 is a 24bit version of Mode 0. Mode 2 is similar to AKM ADCs and
many DSP serial ports. Mode 3 is compatible with the I2S serial data protocol. In Modes 2 and 3 with BICK≥48fs, the
following formats are also valid: 16-bit data followed by eight zeros (17th to 24th bits) and 20-bit data followed by four
zeros (21st to 24th bits). In all modes, the serial data is MSB first and 2’s complement format.
DIF2 bit
0
0
0
0
1
DIF1 bit
0
0
1
1
0
DIF0 bit
0
1
0
1
0
MODE
BICK
0: 16bit, LSB justified
32fs ≤ BICK ≤ 64fs
1: 20bit, LSB justified
40fs ≤ BICK ≤ 64fs
2: 24bit, MSB justified
48fs ≤ BICK ≤ 64fs
3: I2S Compatible
BICK=32fs or 48fs ≤ BICK ≤ 64fs
4: 24bit, LSB justified
48fs ≤ BICK ≤ 64fs
Table 3. Audio Data Format
Figure
Figure 10
Figure 11
Figure 12
Figure 13
Figure 11
5
1
Default
LRCK
BICK
(32fs)
SDATA
Mode 0
15
14
6
4
3
2
15
14
1
0
15
14
0
Don’t care
6
5
4
3
2
0
15
14
0
19
0
19
0
15
14
BICK
SDATA
Mode 0
Don’t care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 10. Mode 0 Timing
LRCK
BICK
SDATA
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19:MSB, 0:LSB
SDATA
Mode 4
Don’t care
23
22
21
20
23
22
21
20
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 11. Mode 1, 4 Timing
MS0247-E-02
2005/10
- 14 -
ASAHI KASEI
[AK4367]
Rch
Lch
LRCK
BICK
SDATA
15
14
0
19
18
4
1
0
23
22
8
3
4
Don’t
care
15
14
0
Don’t
care
19
18
4
1
0
Don’t
care
23
22
8
3
4
Don’t
care
15
14
Don’t
care
19
18
Don’t
care
23
22
16bit
SDATA
20bit
SDATA
1
0
1
0
24bit
Figure 12. Mode 2 Timing
Lch
LRCK
Rch
BICK
SDATA
16bit
SDATA
20bit
SDATA
24bit
15
14
0
19
18
4
1
0
23
22
8
3
4
1
0
15
14
6
5
4
3
2
Don’t
care
15
14
0
Don’t
care
19
18
4
1
0
Don’t
care
23
22
8
3
4
1
15
14
6
5
4
3
Don’t
care
15
Don’t
care
19
0
Don’t
care
23
2
1
BICK
(32fs)
SDATA
16bit
0
1
0
0
15
Figure 13. Mode 3 Timing
MS0247-E-02
2005/10
- 15 -
ASAHI KASEI
[AK4367]
„ Digital Attenuator
The AK4367 has a channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is placed before
the D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to −127dB or MUTE) for each channel (Table 4). At
DATTC bit = “1”, ATTL7-0 bits control both Lch and Rch attenuation levels. At DATTC bit = “0”, ATTL7-0 bits control
the Lch level and ATTR7-0 bits control the Rch level. When HPM bit = “1”, (L+R)/2 summation is done after volume
control.
ATTL7-0
Attenuation
ATTR7-0
FFH
0dB
Default
FEH
−0.5dB
FDH
−1.0dB
FCH
−1.5dB
:
:
:
:
02H
−126.5dB
01H
−127.0dB
00H
MUTE (−∞)
Table 4. Digital Volume ATT values
The ATS bit sets the transition time between set values of ATT7-0 bits as either 1061/fs or 7424/fs (Table 5). When ATS
bit = “0”, a soft transition between the set values occurs(1062 levels). It takes 1061/fs ([email protected]=44.1kHz) from
FFH(0dB) to 00H(MUTE). The ATTs are 00H when the PMDAC bit is “0”. When the PMDAC returns to “1”, the ATTs
fade to their current value. Digital attenuator is independent of the soft mute function.
ATT speed
0dB to MUTE
1 step
0
1061/fs
4/fs
Default
1
7424/fs
29/fs
Table 5. Transition time between set values of ATT7-0 bits
ATS
MOUT volume is controlled by ATTM3-0 bits when MMUTE bit = “0” (Table 6). Pop noise occurs when ATT3-0 bits
are changed.
MMUTE
0
1
ATTM3-0
Attenuation
0FH
0dB
0EH
−2dB
0DH
−4dB
0CH
−6dB
:
:
:
:
01H
−28dB
00H
−30dB
x
MUTE
Table 6. MOUT Volume ATT values
MS0247-E-02
Default
2005/10
- 16 -
ASAHI KASEI
[AK4367]
„ Soft Mute
Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by
−∞ during ATT_DATA×ATT transition time (Table 5) from the current ATT level. When the SMUTE bit is returned to
“0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT
transition time. If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source
without stopping the signal transmission.
SMUTE bit
ATT Level
ATS bit
ATS bit
(1)
(1)
(3)
Attenuation
-∞
GD
(2)
GD
Analog Output
Figure 14. Soft Mute Function
Notes:
(1) ATT_DATA×ATT transition time (Table 5). For example, this time is 3712LRCK cycles (3712/fs) at ATS bit =
“1” and ATT_DATA = “128”.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
MS0247-E-02
2005/10
- 17 -
ASAHI KASEI
[AK4367]
„ De-emphasis Filter
The AK4367 includes a digital de-emphasis filter (tc = 50/15µs) by IIR filter corresponding to three sampling frequencies
(32kHz, 44.1kHz and 48kHz). The de-emphasis filter is enabled by setting DEM1-0 bits (Table 7).
DEM1 bit
DEM0 bit
De-emphasis
0
0
44.1kHz
0
1
OFF
Default
1
0
48kHz
1
1
32kHz
Table 7. De-emphasis Filter Frequency Select
„ Bass Boost Function
By controlling BST1-0 bits, the low frequency boost signal can be output from DAC. The setting value is common in Lch
and Rch (Table 8).
BST1 bit
BST0 bit
BOOST
0
0
OFF
0
1
MIN
1
0
MID
1
1
MAX
Table 8. Low Frequency Boost Select
Default
„ System Reset
The AK4367 should be reset once by bringing PDN pin “L” upon power-up. After exiting reset, VCOM, DAC, HPL,
HPR and MOUT switch to the power-down state. The contents of the control register are maintained until the reset is
done.
DAC exits reset and power down state by MCLK after PMDAC bit is changed to “1”, and then DAC is powered up and
the internal timing starts clocking by LRCK “↑”. DAC is in power-down mode until MCLK and LRCK are input.
MS0247-E-02
2005/10
- 18 -
ASAHI KASEI
[AK4367]
„ Headphone Output
Power supply voltage for the Headphone-amp is supplied from the HVDD pin and centered on the MUTET voltage. The
Headphone-amp output load resistance is min.16Ω. When the MUTEN bit is “1” at PMHPL=PMHPR= “1”, the common
voltage rises to 0.45 x VDD. When the MUTEN bit is “0”, the common voltage of Headphone-amp falls and the outputs
(HPL and HPR pins) go to VSS.
A capacitor between the MUTET pin and ground reduces pop noise at power-up/down. It is
recommended that the capacitor with small variation of capacitance and low ESR (Equivalent Series
Resistance) over all temperature range, since the rise and fall time in Table 9 depend on the
capacitance and ESR of the external capacitor at MUTET pin.
In case only one path is connected,
DAC or LIN/RIN/MIN.
100k x C (typ)
200k x C (typ)
Table 9. Headphone-Amp Rise/Fall Time
tr: Rise Time up to VCOM/2
tf: Fall Time down to 0V
In case both paths are connected,
DAC and LIN/RIN/MIN.
120k x C (typ)
150k x C (typ)
[Example] : A capacitor between the MUTET pin and ground = 1.0µF, and only DAC path is connected:
Time constant of rise time: tr = 100kΩ x 1µF = 100ms(typ)
Time constant of fall time: tf = 200kΩ x 1µF = 200ms(typ)
When PMHPL and PMHPR bits are “0”, the Headphone-amp is powered-down, and the outputs (HPL and HPR pins) go
to VSS.
PMHPL/R bit
MUTEN bit
HPL/R pin
VCOM
VCOM/2
tf
tr
(1) (2)
(3)
(4)
Figure 15. Power-up/Power-down Timing for Headphone-amp
(1) Headphone-amp power-up (PMHPL and PMHPR bits = “1”). The outputs are still VSS.
(2) Headphone-amp common voltage rises up (MUTEN bit = “1”). Common voltage of Headphone-amp is rising. This
rise time depends on the capacitor value connected with the MUTET pin. The rise time up to VCOM/2 is tr = 100k x
C(typ) when the capacitor value on MUTET pin is “C”.
(3) Headphone-amp common voltage falls down (MUTEN bit = “0”). Common voltage of Headphone-amp is falling to
VSS. This fall time depends on the capacitor value connected with the MUTET pin. The fall time down to 0V is tf =
200k x C(typ) when the capacitor value on MUTET pin is “C”.
(4) Headphone-amp power-down (PMHPL, PMHPR bits = “0”). The outputs are VSS. If the power supply is switched off
or Headphone-amp is powered-down before the common voltage goes to VSS, some pop noise occurs.
MS0247-E-02
2005/10
- 19 -
ASAHI KASEI
[AK4367]
The cut-off frequency of Headphone-amp output depends on the external resistor and capacitor used. Table 10 shows the
cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is 16Ω.
Output powers are shown at HVDD = 2.4, 3.0 and 3.3V. The output voltage of headphone is 0.47 x VDD (Vpp)
@−4.8dBFS.
HP-AMP
R
C
Headphone
16Ω
AK4367
Figure 16. External Circuit Example of Headphone
R [Ω]
0
6.8
16
fc [Hz]
fc [Hz]
Output Power [mW]
BOOST=OFF
BOOST=MIN
2.4V
3.0V
3.3V
220
45
17
15
24
28
100
100
43
100
70
28
7
12
14
47
149
78
100
50
19
4
6
7
47
106
47
Table 10. Relationship of external circuit, output power and frequency response
C [µF]
MS0247-E-02
2005/10
- 20 -
ASAHI KASEI
[AK4367]
„ Power-Up/Down Sequence
1) DAC → HP-amp
Power Supply
(9)
(1)
>150ns
PDN pin
Don’t care
(2) >0
PMVCM bit
Don’t care
(3)
Don’t care
Don’t care
Clock Input
PMDAC bit
DAC Internal
State
Normal Operation
PD
PD
Normal Operation
PD
SDTI pin
DACL, DACR bit
(4) >0
PMHPL,
PMHPR bit
(4) >0
(5) >2ms
(5) >2ms
MUTEN bit
ATTL7-0
ATTR7-0 bit
(8) GD
(6)
00H(MUTE)
FFH(0dB)
00H(MUTE)
(9) 1061/fs (8)
FFH(0dB)
(9)
(8)
(7)
(9)
(6)
00H(MUTE)
(8)
(9)
(7)
HPL/R pin
Figure 17. Power-up/down sequence of DAC and HP-amp
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) PMVCM and PMDAC bits should be changed to “1” after PDN pin goes to “H”.
(3) External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PMDAC bit = “0”, these clocks can be
stopped. Headphone amp can operate without these clocks.
(4) DACL and DACR bits should be changed to “1” after PMDAC bit is changed to “1”.
(5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin
is 2.2µF) after DACL and DACR bits are changed to “1”.
(6) Rise time of headphone amp is determined by external capacitor (C) of MUTET pin. The rise time up to VCOM/2 is
tr = 100k x C(typ). When C=1µF, time constant is 100ms(typ).
(7) Fall time of headphone amp is determined by external capacitor (C) of MUTET pin. The fall time down to 0V is tf =
200k x C(typ). When C=1µF, time constant is 200ms(typ).
PMHPL, PMHPR, DACL and DACR bits should be changed to “0” after HPL and HPR pins go to VSS.
(8) Analog output corresponding to digital input has the group delay (GD) of 20.8/fs(=472µ[email protected]=44.1kHz).
(9) ATS bit sets transition time of digital attenuator. Default value is 1061/fs([email protected]=44.1kHz).
(10) Power supply should be switched off after headphone amp is powered down (HPL/R pins become “L”).
MS0247-E-02
2005/10
- 21 -
ASAHI KASEI
[AK4367]
2) DAC → MOUT
Power Supply
(1) >150ns
PDN pin
PMVCM bit
(2)
>0
Don’t care
(5)
Clock Input
PMDAC bit
DAC Internal
State
Don’t care
Don’t care
(4) >0
Normal Operation
PD(Power-down)
PD
Normal Operation
SDTI pin
DACM bit
(3) >0
PMMO bit
ATTL/R7-0 bit
MMUTE,
ATTM3-0 bit
FFH(0dB)
00H(MUTE)
(Hi-Z)
FFH(0dB)
0FH(0dB)
10H(MUTE)
(7) GD
MOUT pin
00H(MUTE)
(8) 1061/fs (7)
(6)
(8)
(7)
(8)
(6)
(6)
(Hi-Z)
Figure 18. Power-up/down sequence of DAC and MOUT
(1)
(2)
(3)
(4)
(5)
PDN pin should be set to “H” at least 150ns after the power is supplied.
PMVCM bit should be changed to “1” after PDN pin goes to “H”.
DACM bit should be changed to “1” after PMVCM bit is changed to “1”.
PMDAC and PMMO bits should be changed to “1” after DACM bit is changed to “1”.
External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PMDAC bit = “0”, these clocks can be
stopped. MOUT buffer can operate without these clocks.
(6) When PMMO bit is changed, pop noise is output from MOUT pin.
(7) Analog output corresponding to digital input has the group delay (GD) of 20.8/fs(=472µ[email protected]=44.1kHz).
(8) ATS bit sets transition time of digital attenuator. Default value is 1061/fs([email protected]=44.1kHz).
MS0247-E-02
2005/10
- 22 -
ASAHI KASEI
[AK4367]
3) LIN/RIN/MIN → HP-amp
Power Supply
(1) >150ns
PDN pin
(2) >0
PMVCM bit
Don’t care
(3) >0
LINL, MINL,RINR, MINR bit
PMHPL/R bit
(5) >0
(5) >2ms
MUTEN bit
(Hi-Z)
(4)
LIN/RIN/MIN pin
(Hi-Z)
(7)
(6)
(6)
HPL/R pin
Figure 19. Power-up/down sequence of LIN/RIN/MIN and HP-amp
(1) PDN pin should be set to “H” at least 150ns after the power is supplied. MCLK, BICK and LRCK can be stopped
when DAC is not used.
(2) PMVCM bit should be changed to “1” after PDN pin goes to “H”.
(3) LINL, MINL, RINR and MINR bits should be changed to “1” after PMVCM bit is changed to “1”.
(4) When LINL, MINL, RINR or MINR bit is changed to “1”, LIN, RIN or MIN pin is biased to 0.45 x VDD voltage.
(5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin
is 2.2µF) after LINL, MINL, RINR and MINR bits are changed to “1”.
(6) Rise time of headphone amp is determined by external capacitor (C) of MUTET pin. The rise time up to VCOM/2 is
tr = 100k x C(typ). When C=1µF, time constant is 100ms(typ).
(7) Fall time of headphone amp is determined by external capacitor (C) of MUTET pin. The fall time down to 0V is tf =
200k x C(typ). When C=1µF, time constant is 200ms(typ).
PMHPL, PMHPR, LINL, MINL, RINR and MINR bits should be changed to “0” after HPL and HPR pins go to VSS.
MS0247-E-02
2005/10
- 23 -
ASAHI KASEI
[AK4367]
4) LIN/RIN/MIN → MOUT
Power Supply
(1) >150ns
PDN pin
(2) >0
PMVCM bit
Don’t care
LINM, RINM, MINM bit
(3) >0
MUTEN bit
(5) >0
(5) >2ms
PMMO bit
(Hi-Z)
(4)
LIN/RIN/MIN pin
MMUTE,
ATTM3-0 bit
MOUT pin
(Hi-Z)
0FH(0dB)
10H(MUTE)
(Hi-Z)
(6)
(6)
(Hi-Z)
(6)
Figure 20. Power-up/down sequence of LIN/RIN/MIN and MOUT
(1) PDN pin should be set to “H” at least 150ns after the power is supplied. MCLK, BICK and LRCK can be stopped
when DAC is not used.
(2) PMVCM bit should be changed to “1” after PDN pin goes to “H”.
(3) LINM, RINM and MINM bits should be changed to “1” after PMVCM bit is changed to “1”.
(4) When LINM, RINM or MINM bit is changed to “1”, LIN, RIN or MIN pin is biased to 0.45 x VDD voltage.
(5) MUTEN and PMMO bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin is 2.2µF)
after LINM, RINM and MINM bits are changed to “1”.
(6) When PMMO bit is changed, pop noise is output from MOUT pin.
MS0247-E-02
2005/10
- 24 -
ASAHI KASEI
[AK4367]
„ Serial Control Interface
(1) 3-wire Serial Control Mode (I2C pin = “L”)
Internal registers may be written via to the 3 wire µP interface pins (CSN, CCLK and CDTI). The data on this interface
consists of Chip address (2bits, Fixed to “01”), Read/Write (1bit, Fixed to “1”, Write only), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK. For write
operations, data is latched after a low-to-high transition of 16th CCLK. The clock speed of CCLK is 5MHz(max). The
value of internal registers is initialized at PDN pin = “L”.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “01”)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 21. 3-wire Serial Control I/F Timing
MS0247-E-02
2005/10
- 25 -
ASAHI KASEI
[AK4367]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4367 supports the standard-mode I2C-bus (max: 100kHz). The AK4367 does not support a fast-mode I2C-bus
system (max: 400kHz).
(2)-1. WRITE Operations
Figure 22 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 28). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit
(R/W). The most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and CAD0
(device address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 and CAD0
pins) set these device address bits (Figure 23). If the slave address matches that of the AK4367, the AK4367 generates an
acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release
the SDA line (HIGH) during the acknowledge clock pulse (Figure 29). A R/W bit value of “1” indicates that the read
operation is to be executed. A “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4367. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 24). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 25). The AK4367 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 28).
The AK4367 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4367
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 08H prior to
generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 30) except for the START and STOP
conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
P
A
C
K
A
C
K
Figure 22. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
0
CAD0
R/W
A2
A1
A0
D2
D1
D0
(Those CAD0 should match with CAD0 pin)
Figure 23. The First Byte
0
0
0
A4
A3
Figure 24. The Second Byte
D7
D6
D5
D4
D3
Figure 25. Byte Structure after the second byte
MS0247-E-02
2005/10
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ASAHI KASEI
[AK4367]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4367. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 08H prior to generating a stop condition, the address
counter will “roll over” to 00H and the previous data will be overwritten.
The AK4367 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4367 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4367 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition,
the AK4367 ceases transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
A
C
K
Data(n+1)
Data(n+2)
A
C
K
A
C
K
Data(n+x)
A
C
K
P
A
C
K
A
C
K
Figure 26. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4367 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but instead generates a stop condition, the AK4367 ceases transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
A
C
K
S
T
O
P
R/W="1"
Data(n)
Data(n+1)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 27. RANDOM ADDRESS READ
MS0247-E-02
2005/10
- 27 -
ASAHI KASEI
[AK4367]
SDA
SCL
S
P
start condition
stop condition
Figure 28. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 29. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 30. Bit Transfer on the I2C-Bus
MS0247-E-02
2005/10
- 28 -
ASAHI KASEI
[AK4367]
„ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
Register Name
Power Management
Mode Control 0
Mode Control 1
Mode Control 2
DAC Lch ATT
DAC Rch ATT
Output Select 0
Output Select 1
MOUT ATT
D7
0
0
0
0
ATTL7
ATTR7
0
0
0
D6
0
MCKAC
0
0
ATTL6
ATTR6
0
0
0
D5
PMMO
HPM
D4
D3
D2
D1
D0
MUTEN
PMHPR
PMHPL
PMDAC
PMVCM
DIF2
MMUTE
SMUTE
DIF0
BST0
0
ATTL5
ATTR5
MINR
0
0
0
ATTL4
ATTR4
MINL
0
0
DIF1
BST1
ATS
ATTL3
ATTR3
RINR
MINM
ATTL2
ATTR2
LINL
RINM
DFS1
DEM1
BCKP
ATTL1
ATTR1
DACR
LINM
DFS0
DEM0
LRP
ATTL0
ATTR0
DACL
DACM
ATTM3
ATTM2
ATTM1
ATTM0
DATTC
All registers inhibit writing at PDN pin = “L”.
PDN pin = “L” resets the registers to their default values.
For addresses from 09H to 1FH, data must not be written.
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ASAHI KASEI
[AK4367]
„ Register Definitions
Addr
00H
Register Name
Power Management
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
PMMO
R/W
0
D4
D3
D2
D1
D0
MUTEN
PMHPR
PMHPL
PMDAC
PMVCM
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PMVCM: Power Management for VCOM Block
0: Power OFF (Default)
1: Power ON
PMDAC: Power Management for DAC Blocks
0: Power OFF (Default)
1: Power ON
When PMDAC bit is changed from “0” to “1”, DAC is powered-up to the current register values (ATT
value, sampling rate, etc).
PMHPL: Power Management for Lch of Headphone Amp
0: Power OFF (Default). HPL pin becomes VSS(0V).
1: Power ON
PMHPR: Power Management for Rch of Headphone Amp
0: Power OFF (Default). HPR pin becomes VSS(0V).
1: Power ON
MUTEN: Headphone Amp Mute Control
0: Mute (Default). HPL and HPR pins go to VSS(0V).
1: Normal operation. HPL and HPR pins go to 0.45 x VDD.
PMMO: Power Management for Mono Output
0: Power OFF (Default) MOUT pin becomes Hi-Z.
1: Power ON
All blocks can be powered-down by setting the PDN pin to “L” regardless of register values setup. All blocks can be
also powered-down by setting all bits of this address to “0”. In this case, control register values are maintained.
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ASAHI KASEI
Addr
01H
Register Name
Mode Control 0
R/W
Default
[AK4367]
D7
0
RD
0
D6
MCKAC
R/W
0
D5
HPM
R/W
0
D4
DIF2
R/W
0
D3
DIF1
R/W
1
D2
DIF0
R/W
0
D1
DFS1
R/W
0
D0
DFS0
R/W
0
D1
DEM1
R/W
0
D0
DEM0
R/W
1
DFS1-0: Oversampling Speed Select (Table 2)
Default: “00” (64fs)
DIF2-0: Audio Data Interface Format Select (Table 3)
Default: “010” (Mode 2)
HPM: Mono Output Select of Headphone
0: Normal Operation (Default)
1: Mono. (L+R)/2 signals from the DAC are output to both Lch and Rch of headphone.
MCKAC: MCLK Input Mode Select
0: CMOS input (Default)
1: AC coupling input
Addr
02H
Register Name
Mode Control 1
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
D4
MMUTE
SMUTE
R/W
0
R/W
0
D3
BST1
R/W
0
D2
BST0
R/W
0
DEM1-0: De-emphasis Filter Frequency Select (Table 7)
Default: “01” (OFF)
BST1-0: Low Frequency Boost Function Select (Table 8)
Default: “00” (OFF)
SMUTE: Soft Mute Control
0: Normal operation (Default)
1: DAC outputs soft-muted
MMUTE: Mute control for MOUT (Table 6)
0: Normal operation. ATTM3-0 bits control attenuation value. (Default)
1: Mute. ATTM3-0 bits are ignored.
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ASAHI KASEI
Addr
03H
Register Name
Mode Control 2
R/W
Default
[AK4367]
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
ATS
R/W
0
D2
DATTC
R/W
0
D1
BCKP
R/W
0
D0
LRP
R/W
0
LRP: LRCK Polarity Select
0: Normal (Default)
1: Invert
BCKP: BICK Polarity Select
0: Normal (Default)
1: Invert
DATTC: DAC Digital Attenuator Control Mode Select
0: Independent (Default)
1: Dependent
At DATTC bit = “1”, ATTL7-0 bits control both Lch and Rch attenuation level, while register values of
ATTL7-0 bits are not written to ATTR7-0 bits. At DATTC bit = “0”, ATTL7-0 bits control Lch level and
ATTR7-0 bits control Rch level.
ATS: Digital attenuator transition time setting (Table 5)
0: 1061/fs (Default)
1: 7424/fs
Addr
04H
05H
Register Name
DAC Lch ATT
DAC Rch ATT
R/W
Default
D7
ATTL7
ATTR7
R/W
0
D6
ATTL6
ATTR6
R/W
0
D5
ATTL5
ATTR5
R/W
0
D4
ATTL4
ATTR4
R/W
0
D3
ATTL3
ATTR3
R/W
0
D2
ATTL2
ATTR2
R/W
0
D1
ATTL1
ATTR1
R/W
0
D0
ATTL0
ATTR0
R/W
0
ATTL7-0: Setting of the attenuation value of output signal from DACL (Table 4)
ATTR7-0: Setting of the attenuation value of output signal from DACR (Table 4)
Default: “00H” (MUTE)
The AK4367 has channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is
placed before D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to −127dB or MUTE) of each
channel. Digital attenuator is independent of soft mute function.
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ASAHI KASEI
Addr
06H
[AK4367]
Register Name
Output Select 0
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
MINR
R/W
0
D4
MINL
R/W
0
D3
RINR
R/W
0
D2
LINL
R/W
0
D1
DACR
R/W
0
D0
DACL
R/W
0
DACL: DAC Lch output signal is added to Lch of headphone amp.
0: OFF (Default)
1: ON
DACR: DAC Rch output signal is added to Rch of headphone amp.
0: OFF (Default)
1: ON
LINL: Input signal to LIN pin is added to Lch of headphone amp.
0: OFF (Default)
1: ON
RINR: Input signal to RIN pin is added to Rch of headphone amp.
0: OFF (Default)
1: ON
MINL: Input signal to MIN pin is added to Lch of headphone amp.
0: OFF (Default)
1: ON
MINR: Input signal to MIN pin is added to Rch of headphone amp.
0: OFF (Default)
1: ON
40k(typ)
40k(typ)
LIN/RIN pin
LINL/RINR bit
40k(typ)
−
1.23R
R
+
MIN pin
MINL/MINR bit
R
DACL/DACR
DACL/DACR bit
−
HPL/HPR pin
+
HP-Amp
Figure 31. Summation circuit for headphone amp output
At HPM bit = “0”, gain of summation is +1.8dB for all input path.
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ASAHI KASEI
Addr
07H
[AK4367]
Register Name
Output Select 1
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
MINM
R/W
0
D2
RINM
R/W
0
D1
LINM
R/W
0
D0
DACM
R/W
0
DACM: DAC Lch and Rch outputs are added to MOUT buffer amp. Summation gain is −6dB for each channel.
0: OFF (Default)
1: ON
LINM: Input signal to LIN pin is added to MOUT buffer amp.
0: OFF (Default)
1: ON
RINM: Input signal to RIN pin is added to MOUT buffer amp.
0: OFF (Default)
1: ON
MINM: Input signal to MIN pin is added to MOUT buffer amp.
0: OFF (Default)
1: ON
200k(typ)
LIN pin
LINM bit
200k(typ)
RIN pin
RINM bit
100k(typ)
MIN pin
100k(typ)
MINM bit
200k(typ)
DACL
200k(typ)
DACR
−
MOUT pin
+
DACM bit
Figure 32. Summation circuit for MOUT
Gain of summation is 0dB for MIN and −6dB for LIN, RIN, DACL and DACR.
Addr
08H
Register Name
MOUT ATT
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
D2
D1
D0
ATTM3
ATTM2
ATTM1
ATTM0
R/W
0
R/W
0
R/W
0
R/W
0
ATTM3-0: Analog volume control for MOUT (Table 6)
Default: MMUTE bit = “0”, ATTM3-0 bits = “0000” (0dB)
Setting of ATTM3-0 bits is enabled at MMUTE bit is “0”.
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ASAHI KASEI
[AK4367]
SYSTEM DESIGN
Figure 33 shows the system connection diagram. An evaluation board [AKD4367] is available which demonstrates the
optimum layout, power supply arrangements and measurement results.
C
0.1u
0.1u
0.1u
R
C
20
19
18
17
16
LIN
RIN
MIN
HPL
HPR
R
16Ω
Headphone
0.1u
HVDD
15
VSS
14
VDD
13
SDATA
MUTET
12
LRCK
VCOM
11
I2C
MOUT
10
5
9
4
Top View
PDN
CSN
8
3
MCLK
CCLK
7
2
BICK
Audio
Controller
CDTI
6
Mode
Setting
1
16Ω
10u
Analog Supply
2.2 ∼ 3.6V
0.1u
1u
0.1u 2.2u
1000p
Figure 33. Typical Connection Diagram (In case of AC coupling to MCLK)
(3-wire serial mode)
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ASAHI KASEI
[AK4367]
1. Grounding and Power Supply Decoupling
The AK4367 requires careful attention to power supply and grounding arrangements. VDD and HVDD are usually
supplied from the analog power supply in the system. When VDD and HVDD are supplied separately, VDD must be
powered-up at the same time or earlier than HVDD. When the AK4367 is powered-down, HVDD must be powered-down
at the same time or later than VDD. VSS must be connected to the analog ground plane. System analog ground and digital
ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling
capacitors should be as close to the AK4367 as possible, with the small value ceramic capacitors being the nearest.
2. Voltage Reference
The input voltage to VDD sets the analog output range. A 0.1µF ceramic capacitor and a 10µF electrolytic capacitor is
connected between VDD and VSS, normally. VCOM is a signal ground of this chip (0.45 x VDD). An electrolytic 2.2µF
in parallel with a 0.1µF ceramic capacitor attached between VCOM and VSS eliminates the effects of high frequency
noise. No load current may be drawn from VCOM pin. All signals, especially clock, should be kept away from VDD and
VCOM in order to avoid unwanted coupling into the AK4367.
3. Analog Outputs
The analog outputs are single-ended outputs, and 0.47xVDD Vpp(typ)@−4.8dBFS for headphone amp and 0.66xVDD
Vpp(typ) for MOUT centered on the VCOM voltage. The input data format is 2’s compliment. The output voltage is a
positive full scale for 7FFFFFH(@24bit) and negative full scale for 800000H(@24bit). The ideal output is VCOM
voltage for 000000H(@24bit).
DC offsets on the analog outputs is eliminated by AC coupling since the analog outputs have a DC offset equal to VCOM
plus a few mV.
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ASAHI KASEI
[AK4367]
PACKAGE
0.
11
20pin QFN (Unit: mm)
±
4.20 ± 0.10
-0
22
0.
.6
9
4.00 ± 0.05
±
3
A
05
0.
4.00 ± 0.05
B
45.0°
M
S AB
0.22 +- 0.03
0.05
S
0.60 ± 0.10
0.90 ± 0.05
0.05
11
0.
0.22 ± 0.05
±
1.00
0.02TYP
0.005MIN 0.04MAX
35
0.
0.50
C0.7
45.0°
0.50
1.00
4.20 ± 0.10
3 - C0.2
0.05 S
Note: The black parts of back package should be open.
„ Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
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ASAHI KASEI
[AK4367]
MARKING
4367
XXXX
1
XXXX : Date code identifier (4 digits)
Revision History
Date (YY/MM/DD)
04/04/15
04/11/26
Revision
00
01
Reason
First Edition
Error correct
05/10/19
02
Description
change
Page
Contents
16
30
33
23-24
Table 6 Default: MUTE Æ 0dB
MMUTE Default: “1” Æ “0”
ATTM3-0 Default: MUTE Æ 0dB
Sequence: HP and MOUT were divided.
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support,
or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except
with the express written consent of the Representative Director of AKM. As used here:
a. A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function
or perform may reasonably be expected to result in loss of life or in significant injury or damage to person
or property.
b. A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing
it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold
AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
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