AKM AKD4371

[AK4371]
AK4371
DAC with built-in PLL & HP-AMP
GENERAL DESCRIPTION
The AK4371 is a 24-bit DAC with an integrated PLL and headphone amplifier. The PLL input frequency is
synchronized to typical mobile phone clock frequencies. The AK4371 features an analog mixing circuit
that allows easy interfacing in mobile phone and portable communication designs. The integrated
headphone amplifier features “pop-noise free” power-on/off, a mute control, and it delivers 40mW of
power into 16Ω. The AK4371 is packaged in a 32-pin QFN (4mm×4mm) package, ideal for portable
applications.
FEATURE
† Multi-bit ΔΣ DAC
† Sampling Rate
- 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz and 48kHz
† On chip perfect filtering 8 times FIR interpolator
- Passband: 20kHz
- Passband Ripple: ±0.02dB
- Stopband Attenuation: 54dB
† Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz
† System Clock
- PLL Mode (MCKI): 27MHz, 26MHz, 19.8MHz, 19.68MHz, 19.2MHz, 15.36MHz,
14.4MHz, 13MHz, 12MHz and 11.2896MHz
- PLL Mode (BICK or LRCK): 64fs, 32fs or fs
- EXT Mode: 256fs/384fs/512fs/768fs/1024fs
- Input Level: AC Couple Input Available
† Audio I/F Format: MSB First, 2’s Complement
- I2S, 24bit MSB justified, 24bit/20bit/16bit LSB justified
- Master/Slave Mode
† Digital Mixing: LR, LL, RR, (L+R)/2
† Bass Boost Function
† Digital ATT
† Analog Mixing Circuit: 6 Inputs (Single-ended or Full-differential)
† Stereo Lineout
- S/N: [email protected]
- Output Volume: +6 to –24dB (or 0 to –30dB), 2dB step
† Mono Hands-free Output
- Output Power: 0.8mW @ 600Ω 3.3V
- Output Volume: +6 to –24dB (or 0 to –30dB), 2dB step
† Headphone Amplifier
- Output Power: 40mW x 2ch @16Ω, 3.3V
- S/N: [email protected]
- Pop Noise Free at Power-ON/OFF and Mute
- Output Volume: 0 ~ –63dB & +12/+6/0 dB Gain
1.5dB step (0 ~ –30dB), 3dB step (–30 ~ –63dB)
† μP Interface: 3-wire/I2C
† Power Supply: 1.6V ∼ 3.6V
† Power Supply Current: 3.8mA @1.8V (6.8mW, DAC+HP, No output)
† Ta: −30 ∼ 85°C
† Small Package: 32pin QFN (4mm x 4mm, 0.4mm pitch)
† Register Compatible with AK4368
MS0596-E-00
2007/04
-1-
[AK4371]
■ Block Diagram
PVDD
BICK
LRCK
SDATA
VSS3
Audio
Interface
MCKO
MCKI
LIN3
AVDD
VSS1
VREF
VREF
VCOM
VCOM
PLL
DVDD
VSS2
LIN1/IN− LIN2
VCOC
DAC
Digital
Volume
Deemphasis
Bass
Boost
Digital
Filter
LOUT
(Lch)
ROUT
DAC
(Rch)
HF
Amp
PDN
I2C
MOUT
HDP
Amp
MUTE
HPL
HDP
Amp
MUTE
HPR
HVDD
MUTET
CAD0/CSN
SCL/CCLK
Serial I/F
SDA/CDTI
RIN1/IN+ RIN2
RIN3
Figure 1. Block Diagram
MS0596-E-00
2007/04
-2-
[AK4371]
■ Ordering Information
−30 ∼ +85°C
32pin QFN (0.4mm pitch)
Evaluation board for AK4371
AK4371VN
AKD4371
VSS1
HVDD
AVDD
VCOM
VREF
ROUT
LOUT
MOUT
24
23
22
21
20
19
18
17
■ Pin Layout
CSN/CAD0
RIN3
29
Top View
12
CCLK/SCL
LIN3
30
11
CDTI/SDA
RIN1/IN+
31
10
MCKO
LIN1/IN−
32
9
VSS3
8
13
VSS2
AK4371VN
7
28
VCOC
LIN2
6
PDN
PVDD
14
5
27
DVDD
RIN2
4
I2C
MCKI
15
3
26
LRCK
HPL
2
MUTET
BICK
16
1
25
SDATA
HPR
MS0596-E-00
2007/04
-3-
[AK4371]
■ Comparison with AK4368
1 Function
Function
AK4368
Analog Mixing
1-Stereo + 1-Mono
Single-ended Input
PLL Reference Clock
Internal VREF
Handsfree Amp
MCKI
256fs/512fs/1024fs,
12.288MHz(max)
No
No
HP-Amp Output Volume
No
HP-Amp Hi-Z Setting
3D Enhancement
ALC
Package
No
Yes
Yes
41BGA (4mm x 4mm, 0.5mm pitch)
MCKI at EXT Mode
AK4371
3-Stereo
Single-ended
or Full-differential Input
MCKI/BICK/LRCK
256fs/384fs/512fs/768fs/1024fs,
24.576MHz(max)
Yes
Yes
0 to –63dB & +12/+6/0dB
1.5dB step (0 to –30dB)
3dB step (–30 to –63dB)
Yes
No
No
32QFN (4mm x 4mm, 0.4mm pitch)
2 Register (difference from AK4368)
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
Register Name
Power Management 0
PLL Control
Clock Control
Mode Control 0
Mode Control 1
DAC Lch ATT
DAC Rch ATT
Headphone Out Select 0
Lineout Select 0
Lineout ATT
Reserved
Reserved
Reserved
Headphone Out Select 1
Headphone ATT
Lineout Select
Mono Mixing
Differential Select
MOUT Select
MOUT ATT
D7
PMVREF
FS3
PLL4
0
ATS
ATTL7
ATTR7
HPG1
0
0
REF7
0
0
D6
PMPLL
FS2
0
D5
PMLO
FS1
M/S
MONO1
DATTC
MONO0
BCKP
LMUTE
SMUTE
ATTL6
ATTR6
HPG0
LOG
0
REF6
0
0
ATTL5
ATTR5
ATTL4
ATTR4
LIN2HR
LIN2R
LIN2HL
LIN2L
0
REF5
ALC
0
0
REF4
RIN3HR
RIN3HL
0
RIN3R
0
0
RIN3M
0
HPZ
RIN3L
0
0
LIN3M
PMMO
D4
D3
D2
D1
D0
MUTEN
PMHPR
PMDAC
PMVCM
FS0
PLL3
BF
LRP
BST1
ATTL3
ATTR3
PMHPL
PLL2
PS0
DIF2
BST0
ATTL2
ATTR2
PLL1
PS1
DIF1
DEM1
ATTL1
ATTR1
PLL0
MCKO
DIF0
DEM0
ATTL0
ATTR0
RIN1HR
RIN1R
ATTS3
LIN1HL
LIN1L
ATTS2
DARHR
DARR
ATTS1
DALHL
DALL
ATTS0
MCKAC
ROTM1
0
LIN3HR
HMUTE
LIN3HL
ATTH4
LIN3R
L3M
0
RIN2M
MOG
LIN3L
L3HM
0
LIN2M
REF3
REF2
REF1
REF0
ROTM0
DP1
RIN2HR
ATTH3
LMAT1
DP0
RIN2HL
ATTH2
LMAT0
3D1
LIN1HR
ATTH1
RATT
3D0
RIN1HL
ATTH0
RIN2R
L2M
RIN2L
L2HM
LIN1R
L1M
RIN1L
L1HM
0
LDIFM
LDIFH
LDIF
RIN1M
LIN1M
DARM
DALM
MMUTE
ATTM3
These bits are added in the AK4371.
These bits are deleted in the AK4371.
ATTM2
ATTM1
ATTM0
MS0596-E-00
2007/04
-4-
[AK4371]
PIN/FUNCTION
No.
1
2
3
4
5
6
Pin Name
SDATA
BICK
LRCK
MCKI
DVDD
PVDD
I/O
I
I/O
I/O
I
-
Function
Audio Serial Data Input Pin
Audio Serial Data Clock Pin
Input / Output Channel Clock Pin
External Master Clock Input Pin
Digital Power Supply Pin, 1.6 ∼ 3.6V
Power Supply for PLL, 1.6 ∼ 3.6V. Normally connected to AVDD.
Output for Loop Filter of PLL Circuit
7
VCOC
O
This pin should be connected to VSS3 with one resistor and one capacitor in series.
8
VSS2
Ground Pin
9
VSS3
Ground Pin
10 MCKO
O
Master Clock Output Pin
SDA
I/O Control Data Input/Output Pin (I2C mode : I2C pin = “H”)
11
CDTI
I
Control Data Input Pin (3-wire serial mode : I2C pin = “L”)
SCL
I
Control Data Clock Pin (I2C mode : I2C pin = “H”)
12
CCLK
I
Control Data Clock Pin (3-wire serial mode : I2C pin = “L”)
CAD0
I
Chip Address 0 Select Pin (I2C mode : I2C pin = “H”)
13
CSN
I
Chip Select Pin (3-wire serial mode : I2C pin = “L”)
Power-down & Reset
14 PDN
I
When “L”, the AK4371 is in power-down mode and is held in reset.
The AK4371 should always be reset upon power-up.
Control Mode Select Pin
15 I2C
I
“H”: I2C Bus, “L”: 3-wire Serial
Mute Time Constant Control pin
16 MUTET
O
Connected to VSS1 pin with a capacitor for mute time constant.
17 MOUT
O
Mono Signal Output Pin
18 LOUT
O
Lch Stereo Line Output Pin
19 ROUT
O
Rch Stereo Line Output Pin
Reference Voltage Output Pin
20 VREF
O
Normally connected to VSS1 pin with a 0.22μF electrolytic capacitor.
Common Voltage Output Pin
21 VCOM
O
Normally connected to VSS1 pin with a 2.2μF electrolytic capacitor.
22 AVDD
Analog Power Supply Pin, 1.6 ∼ 3.6V
23 HVDD
Power Supply Pin for Headphone Amp, 1.6 ∼ 3.6V
24 VSS1
Ground Pin
25 HPR
O
Rch Headphone Amp Output
26 HPL
O
Lch Headphone Amp Output
27 RIN2
I
Rch Analog Input 2 Pin
28 LIN2
I
Lch Analog Input 2 Pin
29 RIN3
I
Rch Analog Input 3 Pin
30 LIN3
I
Lch Analog Input 3 Pin
I
Rch Analog Input 1 Pin (LDIF bit =“0” : Single-ended Input)
RIN1
31
IN+
I
Positive Line Input Pin (LDIF bit =“1” : Full-differential Input)
LIN1
I
Rch Analog Input 1 Pin (LDIF bit =“0” : Single-ended Input)
32
I
Negative Line Input Pin (LDIF bit =“1” : Full-differential Input )
IN−
Note 1. All digital input pins (I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN) must not
be left floating. MCKI pin can be left floating only when PDN pin = “L”.
MS0596-E-00
2007/04
-5-
[AK4371]
■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
LOUT, ROUT, MOUT, MUTET, HPR, HPL, RIN3,
LIN3, RIN2, LIN2, RIN1/IN+, LIN1/IN−
MCKI
MCKO
Setting
These pins should be open.
This pin should be connected to VSS2.
This pin should be open.
ABSOLUATE MAXIMUM RATING
(VSS1, VSS2, VSS3=0V; Note 2, Note 3)
Parameter
Symbol
min
max
Units
Power Supplies Analog
AVDD
4.6
V
−0.3
Digital
DVDD
4.6
V
−0.3
PLL
PVDD
4.6
V
−0.3
HP-Amp
HVDD
4.6
V
−0.3
Input Current (any pins except for supplies)
IIN
mA
±10
Analog Input Voltage (Note 4)
VINA
(AVDD+0.3) or 4.6
V
−0.3
Digital Input Voltage (Note 5)
VIND
(DVDD+0.3) or 4.6
V
−0.3
Ambient Temperature
Ta
85
−30
°C
Storage Temperature
Tstg
150
−65
°C
Note 2. All voltages with respect to ground.
Note 3. VSS1, VSS2 and VSS3 must be connected to the same analog ground plane.
Note 4. LIN1/IN−, RIN1/IN+, LIN2, RIN2, LIN3 and RIN3 pins. Max is smaller value between (AVDD+0.3)V and
4.6V.
Note 5. SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN and I2C pins. Max is smaller value
between (DVDD+0.3)V and 4.6V.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMEND OPERATING CONDITIONS
(VSS1, VSS2, VSS3=0V; Note 2)
Parameter
Symbol
min
typ
max
Units
Power Supplies Analog
AVDD
1.6
2.4
3.6
V
(Note 6)
Digital (Note 7)
DVDD
1.6
2.4
(AVDD+0.2) or 3.6
V
PLL
PVDD
1.6
2.4
3.6
V
HP-Amp
HVDD
1.6
2.4
3.6
V
Difference1
0
+0.3
V
AVDD−PVDD
−0.3
Difference2
0
+0.3
V
AVDD−HVDD
−0.3
Note 2. All voltages with respect to ground.
Note 6. When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. When the AK4371 is powered-down, DVDD should be powered-down at the same time or later than
AVDD. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or
earlier than HVDD. When the AK4371 is powered-down, AVDD should be powered-down at the same time or
later than HVDD.
Note 7. Max is smaller value between (AVDD+0.2)V and 3.6V.
* AKEMD assumes no responsibility for usage beyond the conditions in this datasheet.
MS0596-E-00
2007/04
-6-
[AK4371]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=PVDD=DVDD=HVDD=2.4V, VSS1=VSS2=VSS3=0V; fs=44.1kHz; EXT mode; BOOST OFF;
Slave Mode; Signal Frequency =1kHz; Measurement band width=20Hz ∼ 20kHz; Headphone-Amp: Load impedance is a
serial connection with RL =16Ω and CL=220μF. (Refer to Figure 45; unless otherwise specified)
Parameter
min
typ
max
Units
24
bit
DAC Resolution
Headphone-Amp: (HPL/HPR pins) (Note 8)
Analog Output Characteristics
THD+N
dB
−3dBFS Output, 2.4V, [email protected]
−50
−40
dB
0dBFS Output, 3.3V, [email protected]
−20
82
90
dB
D-Range
−60dBFS Output, A-weighted, 2.4V
92
dB
−60dBFS Output, A-weighted, 3.3V
S/N
A-weighted, 2.4V
82
90
dB
A-weighted, 3.3V
92
dB
Interchannel Isolation
60
80
dB
DC Accuracy
Interchannel Gain Mismatch
0.3
0.8
dB
Gain Drift
200
ppm/°C
Load Resistance (Note 9)
16
Ω
Load Capacitance
300
pF
1.04
1.16
1.28
Vpp
Output Voltage −3dBFS Output (Note 10)
0dBFS Output, 3.3V,
0.8
Vrms
[email protected]
Output Volume: (HPL/HPR pins)
Step Size
0.1
1.5
2.9
dB
0 ∼ –30dB
(HPG1-0 bits = “00”)
0.1
3
5.9
dB
–30 ∼ –63dB
Gain Control Range
Max (ATT4-0 bits = “00H”)
0
dB
(HPG1-0 bits = “00”)
Min (ATT4-0 bits = “1FH”)
dB
−63
Stereo Line Output: (LOUT/ROUT pins, RL=10kΩ) (Note 11)
Analog Output Characteristics:
THD+N (0dBFS Output)
dB
−60
−50
S/N
A-weighted, 2.4V
80
87
dB
A-weighted, 3.3V
90
dB
DC Accuracy
Gain Drift
200
ppm/°C
Load Resistance (Note 9)
10
kΩ
Load Capacitance
25
pF
Output Voltage (0dBFS Output) (Note 12)
1.32
1.47
1.61
Vpp
Output Volume: (LOUT/ROUT pins)
Step Size
1
2
3
dB
Gain Control Range
Max (ATTS3-0 bits = “FH”)
0
dB
(LOG1-0 bit = “0”)
Min (ATTS3-0 bits = “0H”)
dB
−30
Note 8. DALHL=DARHR bits = “1”, LIN1HL=RIN1HL=LIN2HL=RIN2HL=LIN3HL=RIN3HL
=LIN1HR=RIN1HR=LIN2HR=RIN2HR=LIN3HR=RIN3HR bits = “0”.
Note 9. AC load.
Note 10. Output voltage is proportional to AVDD voltage.
When PMVREF bit = “0”, Vout = 0.48 x AVDD(typ)@−3dBFS.
When PMVREF bit = “1”, Vout = 0.52 x AVDD(typ)@0dBFS.
Note 11. DALL=DARR bits = “1”, LIN1L=RIN1L=LIN2L=RIN2L=LIN3L=RIN3L
=LIN1R=RIN1R=LIN2R=RIN2R=LIN3R=RIN3R bits = “0”
Note 12. Output voltage is proportional to AVDD voltage.
When PMVREF bit = “0”, Vout = 0.61 x AVDD(typ)@0dBFS.
When PMVREF bit = “1”, Vout = 0.46 x AVDD(typ)@0dBFS
MS0596-E-00
2007/04
-7-
[AK4371]
Parameter
Mono Handsfree Output: (MOUT pin, RL=600Ω) (Note 13)
Analog Output Characteristics:
THD+N (0dBFS Output)
S/N
A-weighted, 2.4V
A-weighted, 3.3V
DC Accuracy
Gain Drift
Load Resistance (Note 9)
Load Capacitance
Output Voltage (0dBFS Output) (Note 14)
Output Volume: (MOUT pin)
Step Size
Gain Control Range
Max (ATTM3-0 bits = “FH”)
(MOG1-0 bit = “0”)
Min (ATTM3-0 bits = “0H”)
min
typ
max
Units
80
-
−60
87
90
−50
-
dB
dB
dB
600
1.32
200
1.47
25
1.61
ppm/°C
Ω
pF
Vpp
1
-
2
0
−30
3
-
dB
dB
dB
Note 13. DALM=DARM bits = “1”, LIN1M=RIN1M=LIN2M=RIN2M=LIN3M=RIN3M bits = “0”
Note 6. AC load.
Note 14., Output voltage is proportional to AVDD voltage.
When PMVREF bit = “0”, Vout = 0.61 x AVDD(typ)@0dBFS.
When PMVREF bit = “1”, Vout = 0.46 x AVDD(typ)@0dBFS
MS0596-E-00
2007/04
-8-
[AK4371]
Parameter
LINEIN: (LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 pins)
Analog Input Characteristics
Input Resistance (Figure 25, Figure 26, Figure 27, Figure 28)
LIN1 pin
LIN1HL=LIN1HR=LIN1L=LIN1R=LIN1M bits = “1”
LIN1HL bit = “1”, LIN1HR=LIN1L=LIN1R=LIN1M bits = “0”
LIN1HR bit = “1”, LIN1HL=LIN1L=LIN1R=LIN1M bits = “0”
LIN1L bit = “1”, LIN1HL=LIN1HR=LIN1R=LIN1M bits = “0”
LIN1R bit = “1”, LIN1HL=LIN1HR=LIN1L=LIN1M bits = “0”
LIN1M bit = “1”, LIN1HL=LIN1HR=LIN1L=LIN1R bits = “0”
RIN1 pin
RIN1HL=RIN1HR=RIN1L=RIN1R=RIN1M bits = “1”
RIN1HL bit = “1”, RIN1HR=RIN1L=RIN1R=RIN1M bits = “0”
RIN1HR bit = “1”, RIN1HL=RIN1L=RIN1R=RIN1M bits = “0”
RIN1L bit = “1”, RIN1HL=RIN1HR=RIN1R=RIN1M bits = “0”
RIN1R bit = “1”, RIN1HL=RIN1HR=RIN1L=RIN1M bits = “0”
RIN1M bit = “1”, RIN1HL=RIN1HR=RIN1L=RIN1R bits = “0”
LIN2 pin
LIN2HL=LIN2HR=LIN2L=LIN2R=LIN2M bits = “1”
LIN2HL bit = “1”, LIN2HR=LIN2L=LIN2R=LIN2M bits = “0”
LIN2HR bit = “1”, LIN2HL=LIN2L=LIN2R=LIN2M bits = “0”
LIN2L bit = “1”, LIN2HL=LIN2HR=LIN2R=LIN2M bits = “0”
LIN2R bit = “1”, LIN2HL=LIN2HR=LIN2L=LIN2M bits = “0”
LIN2M bit = “1”, LIN2HL=LIN2HR=LIN2L=LIN2R bits = “0”
RIN2 pin
RIN2HL=RIN2HR=RIN2L=RIN2R=RIN2M bits = “1”
RIN2HL bit = “1”, RIN2HR=RIN2L=RIN2R=RIN2M bits = “0”
RIN2HR bit = “1”, RIN2HL=RIN2L=RIN2R=RIN2M bits = “0”
RIN2L bit = “1”, RIN2HL=RIN2HR=RIN2R=RIN2M bits = “0”
RIN2R bit = “1”, RIN2HL=RIN2HR=RIN2L=RIN2M bits = “0”
RIN2M bit = “1”, RIN2HL=RIN2HR=RIN2L=RIN2R bits = “0”
LIN3 pin
LIN3HL=LIN3HR=LIN3L=LIN3R=LIN3M bits = “1”
LIN3HL bit = “1”, LIN3HR=LIN3L=LIN3R=LIN3M bits = “0”
LIN3HR bit = “1”, LIN3HL=LIN3L=LIN3R=LIN3M bits = “0”
LIN3L bit = “1”, LIN3HL=LIN3HR=LIN3R=LIN3M bits = “0”
LIN3R bit = “1”, LIN3HL=LIN3HR=LIN3L=LIN3M bits = “0”
LIN3M bit = “1”, LIN3HL=LIN3HR=LIN3L=LIN3R bits = “0”
RIN3 pin
RIN3HL=RIN3HR=RIN3L=RIN3R=RIN3M bits = “1”
RIN3HL bit = “1”, RIN3HR=RIN3L=RIN3R=RIN3M bits = “0”
RIN3HR bit = “1”, RIN3HL=RIN3L=RIN3R=RIN3M bits = “0”
RIN3L bit = “1”, RIN3HL=RIN3HR=RIN3R=RIN3M bits = “0”
RIN3R bit = “1”, RIN3HL=RIN3HR=RIN3L=RIN3M bits = “0”
RIN3M bit = “1”, RIN3HL=RIN3HR=RIN3L=RIN3R bits = “0”
Gain
LIN1/LIN2/LIN3/RIN1/RIN2/RIN3 Æ LOUT/ROUT
LIN1/LIN2/LIN3/RIN1/RIN2/RIN3 Æ HPL/HPR
LIN1/LIN2/LIN3/RIN1/RIN2/RIN3 Æ MOUT
MS0596-E-00
min
typ
max
Units
14
-
20
100
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
14
-
20
100
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
14
-
20
100
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
14
-
20
100
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
14
-
20
100
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
14
-
20
100
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
−1
−0.05
−1
0
+0.95
0
+1
+1.95
+1
dB
dB
dB
2007/04
-9-
[AK4371]
Parameter
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”) (Note 15)
AVDD+PVDD+DVDD
HVDD
Power-Down Mode (PDN pin = “L”) (Note 16)
min
typ
max
Units
-
3.8
1.2
1
5.5
2.5
100
mA
mA
μA
Note 15. PMDAC=PMHPL=PMHPR=PMLO bits = “1”, MUTEN bit = “1”, PMMO=MCKO bits = “0”, HP-Amp no
output.
PMDAC=PMHPL=PMHPR= “1”, PMLO=PMMO bits = “0”, AVDD+PVDD+DVDD+HVDD=4.0mA (typ)
@2.4V, 3.8mA (typ) @1.8V.
Note 16. All digital input pins are fixed to VSS2.
MS0596-E-00
2007/04
- 10 -
[AK4371]
FILTER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, PVDD, HVDD=1.6 ∼ 3.6V; fs=44.1kHz; De-emphasis = “OFF”)
Parameter
Symbol
min
typ
DAC Digital Filter: (Note 17)
Passband (Note 18)
PB
0
−0.05dB
22.05
−6.0dB
Stopband (Note 18)
SB
24.1
Passband Ripple
PR
Stopband Attenuation
SA
54
Group Delay (Note 19)
GD
22
Group Delay Distortion
0
ΔGD
DAC Digital Filter + Analog Filter: (Note 17, Note 20)
Frequency Response
FR
0 ∼ 20.0kHz
±0.5
Analog Filter: (Note 21)
Frequency Response
FR
0 ∼ 20.0kHz
±1.0
BOOST Filter: (Note 20, Note 22)
Frequency Response
20Hz
FR
5.76
MIN
100Hz
2.92
1kHz
0.02
20Hz
FR
10.80
MID
100Hz
6.84
1kHz
0.13
20Hz
FR
16.06
MAX 100Hz
10.54
1kHz
0.37
max
Units
20.0
±0.02
-
kHz
kHz
kHz
dB
dB
1/fs
µs
-
dB
-
dB
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
Note 17. BOOST OFF (BST1-0 bit = “00”)
Note 18. The passband and stopband frequencies scale with fs (system sampling rate).
For example, PB=0.4535fs(@−0.05dB). SB=0.546fs(@−54dB).
Note 19. This time is from setting the 24-bit data of both channels from the input register to the output of analog signal.
Note 20. DAC Æ HPL, HPR, LOUT, ROUT, MOUT
Note 21. LIN1/LIN2/LIN3/RIN1/RIN2/RIN3 Æ HPL/HPR/LOUT/ROUT/MOUT
Note 22. These frequency responses scale with fs. If high-level signal is input, the output clips at low frequency.
Boost Filter (fs=44.1kHz)
20
MAX
15
Gain [dB]
MID
10
MIN
5
0
-5
10
100
1000
10000
Frequency [Hz]
Figure 2. Boost Frequency (fs=44.1kHz)
MS0596-E-00
2007/04
- 11 -
[AK4371]
DC CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, PVDD, HVDD=1.6 ∼ 3.6V)
Parameter
Symbol
min
High-Level Input Voltage
2.2V≤DVDD≤3.6V
VIH
70%DVDD
1.6V≤DVDD<2.2V
VIH
80%DVDD
Low-Level Input Voltage
2.2V≤DVDD≤3.6V
VIL
1.6V≤DVDD<2.2V
VIL
Input Voltage at AC Coupling (Note 23)
VAC
0.4
High-Level Output Voltage
VOH
(Iout=−200μA)
DVDD−0.2
Low-Level Output Voltage
VOL
(Except SDA pin: Iout=200μA)
VOL
(SDA pin, 2.0V≤DVDD≤3.6V: Iout=3mA)
VOL
(SDA pin, 1.6V≤DVDD<2.0V: Iout=3mA)
Input Leakage Current
Iin
-
typ
-
max
30%DVDD
20%DVDD
-
Units
V
V
V
V
Vpp
V
-
0.2
0.4
20%DVDD
±10
V
V
V
μA
Note 23. MCKI is connected to a capacitor. (Figure 45)
MS0596-E-00
2007/04
- 12 -
[AK4371]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, PVDD, HVDD=1.6 ∼ 3.6V; CL = 20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
Master Clock Input Timing
Frequency (PLL mode)
fCLK
11.2896
27
MHz
(EXT mode)
fCLK
2.048
24.576
MHz
Pulse Width Low (Note 24)
tCLKL
0.4/fCLK
ns
Pulse Width High (Note 24)
tCLKH
0.4/fCLK
ns
AC Pulse Width (Note 25)
tACW
18.5
ns
LRCK Timing
Frequency
fs
8
44.1
48
kHz
Duty Cycle: Slave Mode
Duty
45
55
%
Master Mode
Duty
50
%
MCKO Output Timing (PLL mode)
Frequency
fCLKO
0.256
12.288
MHz
Duty Cycle (Except fs=32kHz, PS1-0= “00”)
dMCK
40
60
%
(fs=32kHz, PS1-0= “00”)
dMCK
33
%
Serial Interface Timing (Note 26)
Slave Mode (M/S bit = “0”):
BICK Period (Note 27)
(Except PLL Mode, PLL4-0 = “EH”, “FH”)
tBCK
312.5 or 1/(64fs)
1/(32fs)
ns
(PLL Mode, PLL4-0 bits = “EH”)
tBCK
1/(32fs)
ns
(PLL Mode, PLL4-0 bits = “EH”)
tBCK
1/(64fs)
ns
BICK Pulse Width Low
(Except PLL Mode, PLL4-0 = “EH”, “FH”)
tBCKL
100
ns
(PLL Mode, PLL4-0 bits = “EH”, “FH”)
tBCKL
0.4 x tBCK
ns
BICK Pulse Width High
(Except PLL Mode, PLL4-0 = “EH”, “FH”)
tBCKL
100
ns
(PLL Mode, PLL4-0 bits = “EH”, “FH”)
tBCKH
0.4 x tBCK
ns
tLRB
50
ns
LRCK Edge to BICK “↑” (Note 28)
tBLR
50
ns
BICK “↑” to LRCK Edge (Note 28)
SDATA Hold Time
tSDH
50
ns
SDATA Setup Time
tSDS
50
ns
Master Mode (M/S bit = “1”):
BICK Frequency (BF bit = “1”)
fBCK
64fs
Hz
(BF bit = “0”)
fBCK
32fs
Hz
BICK Duty
dBCK
50
%
tMBLR
50
ns
BICK “↓” to LRCK
−50
SDATA Hold Time
tSDH
50
ns
SDATA Setup Time
tSDS
50
ns
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK
200
ns
CCLK Pulse Width Low
tCCKL
80
ns
Pulse Width High
tCCKH
80
ns
CDTI Setup Time
tCDS
40
ns
CDTI Hold Time
tCDH
40
ns
CSN “H” Time
tCSW
150
ns
tCSS
50
ns
CSN “↑” to CCLK “↑”
tCSH
50
ns
CCLK “↑” to CSN “↑”
Note 24. Except AC coupling.
Note 25. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to
ground. Refer to Figure 3.
Note 26. Refer to “Serial Data Interface”.
Note 27. Min is longer value between 312.5ns or 1/(64fs) except for PLL Mode, PLL4-0 bits = “EH”, “FH”.
Note 28. BICK rising edge must not occur at the same time as LRCK edge.
MS0596-E-00
2007/04
- 13 -
[AK4371]
Parameter
Control Interface Timing (I2C Bus mode): (Note 29)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 30)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width (Note 31)
Symbol
min
typ
max
Units
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
tSP
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
tPD
150
-
-
ns
Note 29. I2C is a registered trademark of Philips Semiconductors.
Note 30. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 31. The AK4371 can be reset by bringing PDN pin = “L” to “H” only upon power up.
MS0596-E-00
2007/04
- 14 -
[AK4371]
■ Timing Diagram
1/fCLK
tACW
1000pF
tACW
Measurement
Point
MCKI Input
VAC
100kΩ
VSS2
VSS2
Figure 3. MCKI AC Coupling Timing
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
MCKO
50%
DVDD
tH
tL
dMCK=tH/(tH+tL) or tL/(tH+tL)
Figure 4. Clock Timing
MS0596-E-00
2007/04
- 15 -
[AK4371]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDATA
VIL
Figure 5. Serial Interface Timing (Slave Mode)
50%DVDD
LRCK
tMBLR
BICK
50%DVDD
tSDH
tSDS
VIH
SDATA
VIL
Figure 6. Serial Interface Timing (Master mode)
MS0596-E-00
2007/04
- 16 -
[AK4371]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
VIH
A4
VIL
Figure 7. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
D3
CDTI
D2
D1
VIH
D0
VIL
Figure 8. WRITE Data Input Timing
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Figure 9. I2C Bus Mode Timing
tPD
PDN
VIL
Figure 10. Power-down & Reset Timing
MS0596-E-00
2007/04
- 17 -
[AK4371]
OPERATION OVERVIEW
■ System Clock
There are the following six clock modes to interface with external devices (Table 1 and Table 2).
Mode
PLL Master Mode
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: BICK pin)
PLL Slave Mode 3
(PLL Reference Clock: LRCK pin)
EXT Master Mode
EXT Slave Mode
Mode
PLL Master Mode
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PMPLL bit
1
M/S bit
1
PLL3-0 bits
See Table 4
Figure
Figure 11
1
0
See Table 4
Figure 12
1
0
See Table 4
Figure 13
1
0
See Table 4
Figure 14
x
x
Figure 15
Figure 16
0
1
0
0
Table 1. Clock Mode Setting (x: Don’t care)
MCKO bit
0
1
0
1
MCKO pin
“L”
Selected by
PS1-0 bits
“L”
Selected by
PS1-0 bits
MCKI pin
Selected by
PLL4-0 bits
Selected by
PLL4-0 bits
PLL Slave Mode 2
(PLL Reference Clock: BICK pin)
0
“L”
GND
PLL Slave Mode 3
(PLL Reference Clock: LRCK pin)
0
“L”
GND
EXT Master Mode
0
“L”
Selected by
FS3-0 bits
EXT Slave Mode
Selected by
FS3-0 bits
Table 2. Clock pins state in Clock Mode
0
“L”
BICK pin
Output
(Selected by
BF bit)
LRCK pin
Input
(32fs ∼ 64fs)
Input
(1fs)
Input
(Selected by
PLL4-0 bits)
Input
(32fs ∼ 64fs)
Output
(Selected by
BF bit)
Input
(32fs ∼ 64fs)
Output
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
Input
(1fs)
■ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4371 is power-down mode (PDN pin = “L”) and exits reset state, the AK4371 is slave mode. After exiting reset state,
the AK4371 goes to master mode by changing M/S bit = “1”.
When the AK4371 is used by master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK
and BICK pins of the AK4371 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the
floating state.
M/S bit
Mode
0
Slave Mode
(default)
1
Master Mode
Table 3. Select Master/Slave Mode
MS0596-E-00
2007/04
- 18 -
[AK4371]
■ PLL Mode (PMPLL bit = “1”)
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL4-0 and FS3-0 bits (Table 4, Table 5, Table 6). The PLL lock time is shown in Table 4, whenever the AK4371 is
supplied to a stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes.
1) Setting of PLL Mode
Mode
PLL4
PLL3
PLL
2
PLL1
PLL0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Others
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Others
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Reference Clock
fs
(Note
32)
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 2
Type 2
Type 3
Type 4
Table 6
Table 6
Table 6
R,C at VCOC
C[F]
R[Ω]
PLL Lock
Time (typ)
MCKI 11.2896MHz
10k
22n
20ms
MCKI
14.4MHz
10k
22n
20ms
MCKI
12MHz
10k
47n
20ms
MCKI
19.2MHz
10k
22n
20ms
MCKI
15.36MHz
10k
22n
20ms
MCKI
13MHz
15k
330n
100ms
MCKI
19.68MHz
10k
47n
20ms
MCKI
19.8MHz
10k
47n
20ms
MCKI
26MHz
15k
330n
100ms
MCKI
27MHz
10k
47n
20ms
MCKI
13MHz
10k
22n
20ms
MCKI
26MHz
10k
22n
20ms
MCKI
19.8MHz
10k
22n
20ms
MCKI
27MHz
10k
22n
20ms
BICK
32fs
6.8k
47n
20ms
BICK
64fs
6.8k
47n
20ms
LRCK
fs
6.8k
330n
80ms
N/A
Note 32. Refer to Table5 about Type1-4
Note 33 : Clock jitter is lower in Mode10 ~13 than Mode5, 7, 8 and 9, respectively.
Note 34. Modes 14~16 are available at Slave Mode only.
Table 4. Setting of PLL Mode (*fs: Sampling Frequency)
(default)
2) Setting of sampling frequency in PLL Mode
When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 5.
Mode
FS3
FS2
FS1
FS0
0
1
2
4
5
6
8
9
10
3, 7,
11-15
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
Others
fs
Type 1
48kHz
24kHz
12kHz
32kHz
16kHz
8kHz
44.1kHz
22.05kHz
11.025kHz
Type 2
48.0007kHz
24.0004kHz
12.0002kHz
32.0005kHz
16.0002kHz
8.0001kHz
44.0995kHz
22.0498kHz
11.0249kHz
Type 3
47.9992kHz
23.9996kHz
11.9998kHz
31.9994kHz
15.9997kHz
7.9999kHz
44.0995kHz
22.0498kHz
11.0249kHz
Type 4
47.9997kHz
23.9999kHz
11.9999kHz
31.9998kHz
15.9999kHz
7.9999kHz
44.0995kHz
22.0498kHz
11.0249kHz
N/A
N/A
N/A
N/A
(default)
Table 5. Setting of Sampling Frequency (PLL reference clock input is MCKI pin)
MS0596-E-00
2007/04
- 19 -
[AK4371]
When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3-0 bits. (Table 6)
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency Range
0
0
0
1
0
(default)
32kHz < fs ≤ 48kHz
0
1
1
1
0
24kHz < fs ≤ 32kHz
0
0
2
1
1
16kHz < fs ≤ 24kHz
0
1
3
1
1
12kHz < fs ≤ 16kHz
1
0
4
1
0
8kHz ≤ fs ≤ 12kHz
Others
Others
N/A
Table 6. Setting of Sampling Frequency (PLL reference clock input is LRCK or BICK pin)
■ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In master mode (M/S bits = “1”), LRCK and BICK pins output “L” before the PLL is locked by setting PMPLL =
PMDAC bits = “0” Æ “1”. At that time, MCKO pin outputs an abnormal frequency clock at MCKO bit = “1”. When
MCKO bit = “0”, MCKO pin outputs “L”. After the PLL is locked, LRCK and BICK start to output the clocks (Table 7).
Master Mode (M/S bit = “1”)
Power Up
Power Down
PLL Unlock
(PMDAC bit= PMPLL bit= “1”) (PMDAC bit= PMPLL bit= “0”)
MCKI pin Refer to Table 4.
Input or
Refer to Table 4.
fixed to “L” or “H” externally
MCKO pin MCKO bit = “0”: “L”
“L”
MCKO bit = “0”: “L”
MCKO bit = “1”: Output
MCKO bit = “1”: Unsettling
BICK pin
BF bit = “1”: 64fs output
“L”
“L”
BF bit = “0”: 32fs output
LRCK pin Output
“L”
“L”
Table 7. Clock Operation in Master mode (PLL mode)
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In slave mode (M/S bits = “0”), an invalid clock is output from MCKO pin when MCKO bit = “1”, before the PLL is
locked by setting PMPLL = PMDAC bits = “0” Æ “1”. When MCKO bit = “0”, MCKO pin outputs “L”. After the PLL is
locked, MCKO starts to output the clocks (Table 9).
Slave Mode (M/S bit = “0”)
Power Up
Power Down
(PMDAC bit= PMPLL bit= “1”) (PMDAC bit= PMPLL bit= “0”)
MCKI pin Refer to Table 4.
Input or
fixed to “L” or “H” externally
MCKO pin MCKO bit = “0”: “L”
“L”
MCKO bit = “1”: Output
BICK pin
Input
Fixed to “L” or “H” externally
LRCK pin
Input
PLL Unlock
Refer to Table 4.
MCKO bit = “0”: “L”
MCKO bit = “1”: Unsettling
Input or
Fixed to “L” or “H”
externally
Fixed to “L” or “H” externally
Input or
Fixed to “L” or “H”
externally
Table 8. Clock Operation in Slave mode (PLL mode)
MS0596-E-00
2007/04
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[AK4371]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 13MHz, 14.4MHz, 15.36MHz, 19.2MHz, 19.68MHz,19.8MHz, 26MHz
or 27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The
MCKO output frequency is selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit. The BICK output
frequency is selected between 32fs or 64fs, by BF bit (Table 10).
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
AK4371
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTO
SDATA
Figure 11. PLL Master Mode
PS1
PS0
MCKO
0
0
256fs
(default)
0
1
128fs
1
0
64fs
1
1
32fs
Table 9. MCKO Frequency (PLL mode, MCKO bit = “1”)
BF bit
BICK Frequency
0
32fs
(default)
1
64fs
Table 10. BICK Output Frequency at Master Mode
MS0596-E-00
2007/04
- 21 -
[AK4371]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the
AK4371 is generated by an internal PLL circuit. Input frequency is selected by PLL4-0 bits (Table 4).
a) PLL reference clock: MCKI pin
BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not
matter. MCKO pin outputs the frequency selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit.
Sampling frequency can be selected by FS3-0 bits (Table 5).
The external clocks (MCKI, BICK and LRCK) should always be present whenever the DAC is in operation (PMDAC bit
= “1”). If these clocks are not provided, the AK4371 may draw excess current and it is not possible to operate properly
because utilizes dynamic refreshed logic internally. If the external clocks are not present, the DAC should be in the
power-down mode (PMDAC bits = “0”).
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
AK4371
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
32fs ~ 64fs
1fs
MCLK
BCLK
LRCK
SDTO
SDATA
Figure 12. PLL Slave Mode (PLL Reference Clock: MCKI pin)
b) PLL reference clock: BICK pin
Sampling frequency corresponds to 8kHz to 48kHz by changing FS3-0 bits (Table 6).
AK4371
DSP or μP
MCKI
MCKO
BICK
LRCK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDATA
Figure 13. PLL Slave Mode (PLL Reference Clock: BICK pin)
MS0596-E-00
2007/04
- 22 -
[AK4371]
c) PLL reference clock: LRCK pin
Sampling frequency corresponds to 8kHz to 48kHz by changing FS3-0 bits (Table 6).
AK4371
DSP or μP
MCKI
MCKO
BICK
LRCK
32fs ∼ 64fs
1fs
BCLK
LRCK
SDTO
SDATA
Figure 14. PLL Slave Mode (PLL Reference Clock: LRCK pin)
MS0596-E-00
2007/04
- 23 -
[AK4371]
■ EXT Mode (PMPLL bit = “0”: Default)
The AK4371 can be placed in external clock mode (EXT mode) by setting the PMPLL bit to “0”. In EXT mode, the
master clock can directly input to the DAC via the MCKI pin without going through the PLL. In this case, the sampling
frequency and MCKI frequency can be selected by FS3-0 bits (Table 11). In EXT mode, PLL4-0 bits are ignored. MCKO
output is enabled by controlling the MCKO bit. MCKO output frequency can be controlled by PS1-0 bits. If the sampling
frequency is changed during normal operation of the DAC (PMDAC bit = “1”), the change should occur after the input is
muted by SMUTE bit = “1”, or the input is set to “0” data.
LRCK and BICK are output from the AK4371 in master mode(Figure 15). The clock input to the MCKI pin should
always be present whenever the DAC is in normal operation (PMDAC bit = “1”). If these clocks are not provided, the
AK4371 may draw excessive current and will not operate properly because it utilizes these clocks for internal dynamic
refresh of registers. If the external clocks are not present, the DAC should be placed in power-down mode (PMDAC bit =
“0”).
AK4371
DSP or μP
MCKO
256fs, 384fs, 512fs,
768fs or 1024fs
MCKI
32fs, 64fs
BICK
1fs
LRCK
MCLK
BCLK
LRCK
SDTO
SDATA
Figure 15. EXT Master Mode
The external clocks required to operate the AK4371 in slave mode are MCKI, LRCK and BICK(Figure 16). The master
clock (MCKI) should be synchronized with the sampling clock (LRCK). The phase between these clocks does not matter.
All external clocks (MCKI, BICK and LRCK) should always be present whenever the DAC is in normal operation mode
(PMDAC bit = “1”). If these clocks are not provided, the AK4371 may draw excessive current and will not operate
properly, because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the
DAC should be placed in power-down mode (PMDAC bit = “0”).
AK4371
DSP or μP
MCKO
MCKI
BICK
LRCK
256fs, 384fs, 512fs,
768fs or 1024fs
32fs ~ 64fs
1fs
MCLK
BCLK
LRCK
SDTO
SDATA
Figure 16. EXT Slave Mode
MS0596-E-00
2007/04
- 24 -
[AK4371]
Mode
FS3
FS2
FS1
FS0
fs
MCKI
0
0
0
0
0
256fs
8kHz ∼ 48kHz
1
0
0
0
1
512fs
8kHz ∼ 48kHz
2
0
0
1
0
1024fs
8kHz ∼ 24kHz
4
0
1
0
0
256fs
8kHz ∼ 48kHz
5
0
1
0
1
512fs
8kHz ∼ 48kHz
6
0
1
1
0
1024fs
8kHz ∼ 24kHz
8
1
0
0
0
256fs
(default)
8kHz ∼ 48kHz
9
1
0
0
1
512fs
8kHz ∼ 48kHz
10
1
0
1
0
1024fs
8kHz ∼ 24kHz
12
1
1
0
0
384fs
8kHz ∼ 48kHz
13
1
1
0
1
768fs
8kHz ∼ 24kHz
Others
Others
N/A
N/A
Table 11. Relationship between Sampling Frequency and MCKI Frequency (EXT mode)
PS1
PS0
MCKO
0
0
256fs
(default)
0
1
128fs
1
0
64fs
1
1
32fs
Table 12. MCKO frequency (EXT mode, MCKO bit = “1”)
MCKI
pin
MCKO
pin
BICK
pin
LRCK
pin
Master Mode (M/S bit = “1”)
Power Up (PMDAC bit = “1”)
Power Down (PMDAC bit = “0”)
Refer to Table 11
Input or
fixed to “L” or “H” externally
MCKO bit = “0”: “L”
“L”
MCKO bit = “1”: Output
BF bit = “1”: 64fs output
“L”
BF bit = “0”: 32fs output
Output
“L”
Table 13. Clock Operation in Master mode (EXT mode)
Slave Mode (M/S bit = “0”)
Power Up (PMDAC bit = “1”)
Power Down (PMDAC bit = “0”)
MCKI pin Refer to Table 11
Input or
fixed to “L” or “H” externally
MCKO pin MCKO bit = “0”: “L”
“L”
MCKO bit = “1”: Output
BICK pin
Input
Fixed to “L” or “H” externally
LRCK pin Input
Fixed to “L” or “H” externally
Table 14. Clock Operation in Slave mode (EXT mode)
For low sampling rates, DR and S/N degrade because of the out-of-band noise. DR and S/N are improved by using higher
frequency for MCKI. Table 15 shows DR and S/N when the DAC output is to the HP-amp.
DR, S/N (BW=20kHz, A-weight)
fs=8kHz
fs=16kHz
256fs/384fs/512fs
56dB
75dB
768fs/1024fs
75dB
90dB
Table 15. Relationship between MCKI frequency and DR (and S/N) of HP-amp (2.4V)
MCKI
MS0596-E-00
2007/04
- 25 -
[AK4371]
■ Serial Data Interface
The AK4371 interfaces with external systems via the SDATA, BICK and LRCK pins. Five data formats are available,
selected by setting the DIF2, DIF1 and DIF0 bits (Table 16). Mode 0 is compatible with existing 16-bit DACs and digital
filters. Mode 1 is a 20-bit version of Mode 0. Mode 4 is a 24-bit version of Mode 0. Mode 2 is similar to AKM ADCs and
many DSP serial ports. Mode 3 is compatible with the I2S serial data protocol. In Modes 2 and 3 with BICK≥48fs, the
following formats are also valid: 16-bit data followed by eight zeros (17th to 24th bits) and 20-bit data followed by four
zeros (21st to 24th bits). In all modes, the serial data is MSB first and 2’s complement format.
When master mode and BICK=32fs(BF bit = “0”), the AK4371 cannot be set to Mode 1 Mode 2 or Mode 4.
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
Format
BICK
0: 16bit, LSB justified
32fs ≤ BICK ≤ 64fs
1: 20bit, LSB justified
40fs ≤ BICK ≤ 64fs
2: 24bit, MSB justified
48fs ≤ BICK ≤ 64fs
3: I2S Compatible
BICK=32fs or 48fs ≤ BICK ≤ 64fs
4: 24bit, LSB justified
48fs ≤ BICK ≤ 64fs
Table 16. Audio Data Format
Figure
Figure 17
Figure 18
Figure 19
Figure 20
Figure 18
(default)
LRCK
BICK
(32fs)
SDATA
Mode 0
15
14
6
5
4
3
2
15
14
1
0
15
14
0
Don’t care
6
5
4
3
2
1
0
15
14
0
19
0
19
0
15
14
BICK
SDATA
Mode 0
Don’t care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 17. Mode 0 Timing (LRP = BCKP bits = “0”)
LRCK
BICK
SDATA
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19:MSB, 0:LSB
SDATA
Mode 4
Don’t care
23
22
21
20
23
22
21
20
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 18. Mode 1, 4 Timing (LRP = BCKP bits = “0”)
MS0596-E-00
2007/04
- 26 -
[AK4371]
Rch
Lch
LRCK
BICK
SDATA
15
14
0
19
18
4
1
0
23
22
8
3
4
Don’t
care
15
14
0
Don’t
care
19
18
4
1
0
Don’t
care
23
22
8
3
4
Don’t
care
15
14
Don’t
care
19
18
Don’t
care
23
22
16bit
SDATA
20bit
SDATA
1
0
1
0
24bit
Figure 19. Mode 2 Timing (LRP = BCKP bits = “0”)
Lch
LRCK
Rch
BICK
SDATA
16bit
SDATA
20bit
SDATA
24bit
15
14
0
19
18
4
1
0
23
22
8
3
4
1
0
15
14
6
5
4
3
2
Don’t
care
15
14
0
Don’t
care
19
18
4
1
0
Don’t
care
23
22
8
3
4
1
15
14
6
5
4
3
Don’t
care
15
Don’t
care
19
0
Don’t
care
23
2
1
BICK
(32fs)
SDATA
16bit
0
1
0
0
15
Figure 20. Mode 3 Timing (LRP = BCKP bits = “0”)
MS0596-E-00
2007/04
- 27 -
[AK4371]
■ Digital Attenuator
The AK4371 has a channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is placed before
the D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to −127dB or MUTE) for each channel (Table 17). At
DATTC bit = “1”, ATTL7-0 bits control both channel’s attenuation levels. At DATTC bit = “0”, ATTL7-0 bits control
the left channel level and ATTR7-0 bits control the right channel level.
ATTL7-0
Attenuation
ATTR7-0
FFH
0dB
FEH
−0.5dB
FDH
−1.0dB
FCH
−1.5dB
:
:
:
:
02H
−126.5dB
01H
−127.0dB
00H
(default)
MUTE (−∞)
Table 17. Digital Volume ATT values
The ATS bit sets the transition time between set values of ATT7-0 bits as either 1061/fs or 7424/fs (Table 18). When the
ATS bit = “0”, a soft transition between the set values occurs(1062 levels). It takes 1061/fs ([email protected]=44.1kHz) from
FFH(0dB) to 00H(MUTE). The ATTs are 00H when the PMDAC bit is “0”. When the PMDAC returns to “1”, the ATTs
fade to their current value. The digital attenuator is independent of the soft mute function.
ATT speed
0dB to MUTE
1 step
0
1061/fs
4/fs
(default)
1
7424/fs
29/fs
Table 18. Transition time between set values of ATT7-0 bits
ATS
MS0596-E-00
2007/04
- 28 -
[AK4371]
■ Soft Mute
Soft mute operation is performed in the digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated
by −∞ during the ATT_DATA×ATT transition time (Table 18) from the current ATT level. When the SMUTE bit is
returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during
ATT_DATA×ATT transition time. If the soft mute is cancelled before attenuating to −∞ after starting the operation, the
attenuation is discontinued and is returned to the ATT level by the same cycle. The soft mute is effective for changing the
signal source without stopping the signal transmission.
SMUTE bit
ATT Level
ATS bit
ATS bit
(1)
(1)
(3)
Attenuation
-∞
GD
(2)
GD
Analog Output
Figure 21. Soft Mute Function
Notes:
(1) ATT_DATA×ATT transition time (Table 18). For example, this time is 3712LRCK cycles (3712/fs) at ATS bit =
“1” and ATT_DATA = “128”(-63.5dB).
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is discontinued
and it is returned to the ATT level by the same cycle.
MS0596-E-00
2007/04
- 29 -
[AK4371]
■ De-emphasis Filter
The AK4371 includes a digital de-emphasis filter (tc = 50/15μs), using an IIR filter corresponding to three sampling
frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter is enabled by setting DEM1-0 bits (Table 19).
DEM1 bit
DEM0 bit
De-emphasis
0
0
44.1kHz
0
1
OFF
(default)
1
0
48kHz
1
1
32kHz
Table 19. De-emphasis Filter Frequency Select
■ Bass Boost Function
By controlling the BST1-0 bits, a low frequency boost signal can be output from DAC. The setting value is common for
both channels (Table 20).
BST1 bit
BST0 bit
BOOST
0
0
OFF
(default)
0
1
MIN
1
0
MID
1
1
MAX
Table 20. Low Frequency Boost Select
■ Digital Mixing Function
MONO1-0 bits select the digital data mixing for the DAC (Table 21).
MONO1 bit
0
0
1
1
MONO0 bit
Lch
0
L
1
L
0
R
1
(L+R)/2
Table 21. Mixer Setting
Rch
R
L
R
(L+R)/2
(default)
■ System Reset
PDN pin should be held to “L” upon power-up. The AK4371 should be reset by bringing PDN pin “L” for 150ns or more.
All of the internal register values are initialized by the system reset. After exiting reset, VCOM, DAC, HPL, HPR, LOUT,
ROUT and MOUT switch to the power-down state. The contents of the control register are maintained until the reset is
completed.
The DAC exits reset and power down states by MCKI after the PMDAC bit is changed to “1”. The DAC is in power-down
mode until MCKI is input.
MS0596-E-00
2007/04
- 30 -
[AK4371]
■ Headphone Output (HPL, HPR pins)
The power supply voltage for the headphone-amp is supplied from the HVDD pin and is centered on the MUTET voltage.
The headphone-amp output load resistance is 16Ω (min). When the MUTEN bit is “1” at PMHPL=PMHPR= “1”, the
common voltage rises to 0.475 x AVDD. When the MUTEN bit is “0”, the common voltage of the headphone-amp falls
and the outputs (HPL and HPR pins) go to VSS1.
70k x C (typ)
tr: Rise Time up to VCOM/2
tf: Fall Time down to VCOM/2
60k x C (typ)
Table 22. Headphone-Amp Rise/Fall Time
[Example] : Capacitor between the MUTET pin and ground = 1μF:
Rise time up to VCOM/2: tr = 70k x 1μ = 70ms(typ).
Fall time down to VCOM/2: tf = 60k x 1μ = 60ms(typ).
When the PMHPL and PMHPR bits are “0”, the headphone-amp is powered-down, and the outputs (HPL and HPR pins)
go to VSS1.
PMHPL/R bit
MUTEN bit
HPL/R pin
VCOM
VCOM/2
tf
tr
(1) (2)
(3)
(4)
Figure 22. Power-up/Power-down Timing for the Headphone-Amp
(1) Headphone-amp power-up (PMHPL and PMHPR bits = “1”). The outputs are still at VSS1.
(2) Headphone-amp common voltage rises up (MUTEN bit = “1”). Common voltage of the headphone-amp is rising. This
rise time depends on the capacitor value connected with the MUTET pin. The rise time up to VCOM/2 is tr = 70k x
C(typ) when the capacitor value on MUTET pin is “C”.
(3) Headphone-amp common voltage falls down (MUTEN bit = “0”). Common voltage of the headphone-amp is falling
to VSS1. This fall time depends on the capacitor value connected with the MUTET pin. The fall time down to
VCOM/2 is tf = 60k x C(typ) when the capacitor value on MUTET pin is “C”.
(4) Headphone-amp power-down (PMHPL, PMHPR bits = “0”). The outputs are at VSS1. If the power supply is switched
off or the headphone-amp is powered-down before the common voltage goes to VSS1, some pop noise may occur.
MS0596-E-00
2007/04
- 31 -
[AK4371]
< External Circuit of Headphone-Amp >
The cut-off frequency of the headphone-amp output depends on the external resistor and capacitor used. Table 23 shows
the cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is
16Ω. Output powers are shown at AVDD = 2.4, 3.0 and 3.3V. The output voltage of the headphone-amp is 0.48 x AVDD
(Vpp) @−3dBFS.
HP-AMP
R
C
Headphone
16Ω
AK4371
Figure 23. External Circuit Example of Headphone
R [Ω]
0
6.8
16
C [μF]
fc [Hz]
BOOST=OFF
fc [Hz]
BOOST=MIN
Output Power [mW]
2.4V
3.0V
3.3V
220
45
17
21
33
40
100
100
43
100
70
28
10
16
20
47
149
78
100
50
19
5
8
10
47
106
47
Table 23. Relationship of external circuit, output power and frequency response (PMVREF bit = “0”)
< Wired OR with External Headphone-Amp >
When PMVCM=PMHPL=PMHPR bits = “0” and HPZ bit = “1”, Headphone-amp is powered-down and HPL/R pins are
pulled-down to VSS1 by 200kΩ (typ). In this setting, it is available to connect headphone-amp of AK4371 and external
single supply headphone-amp by “wired OR”.
PMVCM
x
0
1
1
PMHPL/R
0
0
1
1
HPMTN
HPZ
Mode
HPL/R pins
x
0
Power-down & Mute
VSS1
x
1
Power-down
Pull-down by 200kΩ
0
x
Mute
VSS1
1
x
Normal Operation
Normal Operation
Table 24. HP-Amp Mode Setting (x: Don’t care)
(default)
HPL pin
AK4371
Headphone
HPR pin
Another
HP-Amp
Figure 24. Wired OR with External HP-Amp
MS0596-E-00
2007/04
- 32 -
[AK4371]
< Analog Mixing Circuit for Headphone Output >
DALHL, LIN1HL, RIN1HL, LIN2HL, RIN2HL, LIN3HL and RIN3HL bits control each path switch of HPL output.
DARHR, LIN1HR, RIN1HR, LIN2HR, RIN2HR, LIN3HR and RIN3HR bits control each path switch of HPR output.
When L1HM=L2HM=L3HM bits = “0”, HPG1-0 bits = “00” (R1H= R2H= R3H= RDH= 100k) and ATTH4-0 bits =
“00H”(0dB), the mixing gain is +0.95dB(typ). When HPG1-0 bit = “01” (RDH= 50k), the mixing gain of DAC path is
+6.95dB(typ). When HPG1-0 bit = “10” (RDH= 25k), the mixing gain of DAC path is +12.95dB(typ). When L1HM,
L2HM and L3HM bits are “1”, LIN1/RIN1, LIN2/RIN2 and LIN3/RIN3 signals are output from HPL/R pins as (L+R)/2
respectively (R1H= R2H= R3H= 200k).
When LDIF=LDIFH=LIN1L=RIN1R bits = “1”, LIN1 and RIN1 pins becomes IN− and IN+ pins, respectively. IN+ and
IN− pins can be used as full-differential mono line input for analog mixing for headphone-amp. In this case, LIN1HL,
RIN1HL, LIN1HR and RIN1HR bits should be “0”.
If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to VCOM
voltage (= 0.475 x AVDD) externally. Figure 46 shows the external bias circuit example.
100k(typ)
Figure 27
LDIFH bit
R1H
LIN1 pin
LIN1HL bit
R1H
RIN1 pin
RIN1HL bit
R2H
LIN2 pin
LIN2HL bit
R2H
RIN2 pin
RIN2HL bit
R3H
LIN3 pin
LIN3HL bit
R3H
100k(typ)
RIN3 pin
1.11RH
RIN3HL bit
RDH
DAC Lch
DALHL bit
−
RH
+
−
HPL pin
+
HP-Amp
100k(typ)
Figure 27
LDIFH bit
R1H
LIN1 pin
LIN1HR bit
R1H
RIN1 pin
RIN1HR bit
R2H
LIN2 pin
LIN2HR bit
R2H
RIN2 pin
RIN2HR bit
R3H
LIN3 pin
LIN3HR bit
R3H
100k(typ)
RIN3 pin
1.11RH
RIN3HR bit
RDH
DAC Rch
DARHR bit
−
RH
+
−
+
HPR pin
HP-Amp
Figure 25. Summation circuit for HPL/R output
MS0596-E-00
2007/04
- 33 -
[AK4371]
■ Headphone Output Volume
HPL/HPR volume is controlled by ATTH4-0 bit when HMUTE bit = “0” (+12dB ∼ −51dB or +6dB ∼ −57dB or 0dB ∼
−63dB, 1.5dB or 3dB step, Table 25)
HMUTE
ATTH4-0
0
1
00H
01H
02H
03H
:
:
12H
13H
14H
15H
16H
:
:
1DH
1EH
1FH
x
HPG1-0 bits = “10”
(DAC Only)
+12dB
+10.5dB
+9dB
+7.5dB
:
:
−15dB
−16.5dB
−18dB
−21dB
−24dB
:
:
−45dB
−48dB
−51dB
MUTE
HPG1-0 bits = “01”
(DAC Only)
+6dB
+4.5dB
+3dB
+1.5dB
:
:
−21dB
−22.5dB
−24dB
−27dB
−30dB
:
:
−51dB
−54dB
−57dB
MUTE
HPG1-0 bits = “00”
0dB
−1.5dB
−3dB
−4.5dB
:
:
−27dB
−28.5dB
−30dB
−33dB
−36dB
:
:
−57dB
−60dB
−63dB
MUTE
STEP
(default)
1.5dB
3dB
Table 25. HPL/HPR Volume ATT values (x: Don’t care)
MS0596-E-00
2007/04
- 34 -
[AK4371]
■ Stereo Line Output (LOUT, ROUT pins)
The common voltage is 0.475 x AVDD. The load resistance is 10kΩ(min). When the PMLO bit is “1”, the stereo line
output is powered-up. DALL, LIN1L, RIN1L, LIN2L, RIN2L, LIN3L and RIN3L bits control each path switch of LOUT.
DARR, LIN1R, RIN1R, LIN2R, RIN2R, LIN3R and RIN3R bits control each path switch of ROUT. When L1M = L2M
= L3M bits = “0”, LOG bit = “0” (R1L = R2L = R3L= RDL = 100k) and ATTS3-0 bits is “0FH”(0dB), the mixing gain is
0dB(typ) for all paths. When the LOG bit = “1”(RDL= 50k), the DAC path gain is +6dB. When L1M = L2M = L3M bits =
“1”, LIN1/RIN1, LIN2/RIN2 and LIN3/RIN3 signals are output from LOUT/ROUT pins as (L+R)/2 respectively (R1L=
R2L= R3L = 200k).
If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to VCOM
voltage (= 0.475 x AVDD) externally. Figure 46 shows the external bias circuit example.
R1L
LIN1 pin
LIN1L bit
R1L
RIN1 pin
RIN1L bit
R2L
LIN2 pin
LIN2L bit
R2L
RIN2 pin
RIN2L bit
R3L
LIN3 pin
LIN3L bit
R3L
100k(typ)
RIN3 pin
RL
RIN3L bit
RDL
DAC Lch
DALL bit
−
RL
+
−
LOUT pin
+
R1L
LIN1 pin
LIN1R bit
R1L
RIN1 pin
RIN1R bit
R2L
LIN2 pin
LIN2R bit
R2L
RIN2 pin
RIN2R bit
R3L
LIN3 pin
LIN3R bit
R3L
100k(typ)
RIN3 pin
RL
RIN3R bit
RDL
DAC Rch
DARR bit
−
RL
+
−
+
ROUT pin
Figure 26. Summation circuit for stereo line output
MS0596-E-00
2007/04
- 35 -
[AK4371]
< Analog Mixing Circuit of Full-differential Mono input >
When LDIF=LIN1L=RIN1R bits = “1”, LIN1 and RIN1 pins becomes IN− and IN+ pins, respectively. IN− and IN+ pins
can be used as full-differential mono line input for analog mixing of LOUT/ROUT pins. It is not available to mix with
other signal source for LOUT/ROUT outputs.
If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to VCOM
voltage (= 0.475 x AVDD) externally. Figure 46 shows the external bias circuit example.
Figure 25
HPL/R pins
Figure 28
MOUT pin
LDIFH bit
R1L
IN− pin
100k(typ)
LDIFM bit
RL
LIN1L bit
100k(typ)
LDIF bit
−
RL
+
R1L
IN+ pin
−
LOUT pin
+
100k(typ)
RL
RIN1R bit
−
RL
+
−
+
ROUT pin
Figure 27. Summation circuit for stereo line output (Full-differential input, LOG bit = “0”)
■ Stereo Line Output (LOUT/ROUT pins) Volume
LOUT/ROUT volume is controlled by ATTS3-0 bits when LMUTE bit = “0” (+6dB ∼ −24dB or 0dB ∼ −30dB, 2dB step,
Table 26). Pop noise occurs when ATTS3-0 bits are changed.
LOG bit = “1”
LOG bit = “0”
(DAC Only)
FH
+6dB
0dB
EH
+4dB
−2dB
DH
+2dB
−4dB
CH
0dB
−6dB
:
:
:
:
:
:
1H
−22dB
−28dB
0H
−24dB
−30dB
x
MUTE
MUTE
(default)
Table 26. LOUT/ROUT Volume ATT values (x: Don’t care)
LMUTE
0
1
ATTS3-0
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2007/04
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[AK4371]
■ Mono Hands-free Output (MOUT pin)
The common voltage is 0.475 x AVDD. The load resistance is 600Ω(min). When the PMMO bit is “1”, the mono
Hands-free output is powered-up. DALM, DARM, LIN1M, RIN1M, LIN2M, RIN2M, LIN3M and RIN3M bits control
each path switch. When MOG bit = “0”(RDM=100k) and ATTM3-0 bits = “0FH”(0dB), the mixing gain is −6dB(typ) for
all paths. When MOG bit = “1”(RDM=50k) and ATTM3-0 bits = “0FH”(0dB), the mixing gain of output signal is 0dB.
When LDIF=LDIFM=LIN1L=RIN1R bits = “1”, LIN1 and RIN1 pins become IN− and IN+ pins respectively. IN− and
IN+ pins can be used as full-differential mono line input for analog mixing of MOUT pin. In this case, LIN1M and
RIN1M bits should be “0”.
If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to VCOM
voltage (= 0.475 x AVDD) externally. Figure 46 shows the external bias circuit example.
100k(typ)
Figure 27
LDIFM bit
100k(typ)
LIN1 pin
LIN1M bit
100k(typ)
RIN1 pin
RIN1M bit
100k(typ)
LIN2 pin
LIN2M bit
100k(typ)
RIN2 pin
RIN2M bit
100k(typ)
LIN3 pin
LIN3M bit
100k(typ)
50k(typ)
RIN3 pin
RM
RIN3M bit
RDM
DAC Lch
DALM bit
RDM
−
RM
+
−
+
MOUT pin
DAC Rch
DARM bit
Figure 28. Summation circuit for Mono Hands-free output
■ Mono Hands-free Output (MOUT pin) Volume
MOUT volume is controlled by ATTM3-0 bit when MMUTE bit = “0” (+6dB ∼ −24dB or 0dB ∼ −30dB, 2dB step, Table
27). Pop noise occurs when ATTM3-0 bits are changed.
MMUTE
0
1
MOG bit = “1”
MOG bit = “0”
(DAC Only)
FH
+6dB
0dB
EH
+4dB
−2dB
DH
+2dB
−4dB
CH
0dB
−6dB
:
:
:
:
:
:
1H
−22dB
−28dB
0H
−24dB
−30dB
x
MUTE
MUTE
Table 27. MOUT Volume ATT values (x: Don’t care)
ATTM3-0
MS0596-E-00
(default)
2007/04
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[AK4371]
■ Power-Up/Down Sequence (EXT mode)
1) DAC → HP-Amp
Power Supply
(10)
(1)
>150ns
PDN pin
Don’t care
(2) >0s
PMVCM bit
Don’t care
(3)
Don’t care
Don’t care
Clock Input
PMDAC bit
DAC Internal
State
PD
Normal Operation
PD
Normal Operation
PD
SDTI pin
DALHL,
DARHR bits
(4) >0s
PMHPL,
PMHPR bits
(4) >0s
(5) >2ms
(5) >2ms
MUTEN bit
ATTL7-0
ATTR7-0 bits
00H(MUTE)
FFH(0dB)
(8) GD (9) 1061/fs
(6)
FFH(0dB)
00H(MUTE)
(8)
(8) (9)
(7)
(6)
(9)
00H(MUTE)
(8) (9)
(7)
HPL/R pin
Figure 29. Power-up/down sequence of DAC and HP-amp (Don’t care: except Hi-Z)
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier
than HVDD. PDN pin should be set to “H” at least 150ns after power is supplied.
(2) PMVCM and PMDAC bits should be changed to “1” after PDN pin goes “H”.
(3) External clocks (MCKI, BICK, LRCK) are needed to operate the DAC. When the PMDAC bit = “0”, these clocks
can be stopped. The headphone-amp can operate without these clocks.
(4) DALHL and DARHR bits should be changed to “1” after PMVCM and PMDAC bit is changed to “1”.
(5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin
is 2.2μF) after the DALHL and DARHR bits are changed to “1”
(6) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to
VCOM/2 is tr = 70k x C(typ). When C=1μF, tr = 70ms(typ).
(7) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to
VCOM/2 is tf = 60k x C(typ). When C=1μF, tf = 60ms(typ).
PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to VSS1. After that, the DALHL and
DARHR bits should be changed to “0”.
(8) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499µ[email protected]=44.1kHz).
(9) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs([email protected]=44.1kHz).
(10) The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become “L”).
When AVDD and DVDD are supplied separately, DVDD should be powered-down at the same time or later than
AVDD. When AVDD and HVDD are supplied separately, AVDD should be powered-down at the same time or later
than HVDD.
MS0596-E-00
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[AK4371]
2) DAC → Lineout
Power Supply
(1) >150ns
PDN pin
PMVCM bit
(2)
>0s
Don’t care
(5)
Clock Input
Don’t care
Don’t care
(4) >0s
PMDAC bit
DAC Internal
State
PD
Normal Operation
PD(Power-down)
Normal Operation
SDTI pin
DALL,
DARR bits
(3) >0s
PMLO bit
ATTL/R7-0 bits
LMUTE,
ATTS3-0 bits
FFH(0dB)
00H(MUTE)
FFH(0dB)
0FH(0dB)
10H(MUTE)
(7) GD
LOUT/ROUT pins
00H(MUTE)
(8) 1061/fs (7)
(6)
(8)
(7)
(Hi-Z)
(8)
(6)
(6)
(Hi-Z)
Figure 30. Power-up/down sequence of DAC and LOUT/ROUT (Don’t care: except Hi-Z)
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier
than HVDD. PDN pin should be set to “H” at least 150ns after power is supplied.
(2) PMVCM bit should be changed to “1” after the PDN pin goes “H”.
(3) DALL and DARR bits should be changed to “1” after the PMVCM bit is changed to “1”.
(4) PMDAC and PMLO bits should be changed to “1” after DALL and DARR bits is changed to “1”.
(5) External clocks (MCKI, BICK, LRCK) are needed to operate the DAC. When the PMDAC bit = “0”, these clocks
can be stopped. The LOUT/ROUT buffer can operate without these clocks.
(6) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
(7) Analog output corresponding to the digital input has a group delay (GD) of 22/fs([email protected]=44.1kHz).
(8) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs([email protected]=44.1kHz).
MS0596-E-00
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[AK4371]
3) DAC → MOUT
Power Supply
(1) >150ns
PDN pin
(2)
>0s
PMVCM bit
Don’t care
(5)
Clock Input
Don’t care
Don’t care
(4) >0s
PMDAC bit
DAC Internal
State
PD
Normal Operation
PD(Power-down)
Normal Operation
SDTI pin
DALM,
DARM bits
(3) >0s
PMMO bit
ATTL/R7-0 bits
MMUTE,
ATTM3-0 bits
FFH(0dB)
00H(MUTE)
FFH(0dB)
0FH(0dB)
10H(MUTE)
(7) GD
MOUT pin
00H(MUTE)
(8) 1061/fs (7)
(6)
(8)
(7)
(Hi-Z)
(8)
(6)
(6)
(Hi-Z)
Figure 31. Power-up/down sequence of DAC and MOUT (Don’t care: except Hi-Z)
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier
than HVDD. PDN pin should be set to “H” at least 150ns after power is supplied.
(2) PMVCM bit should be changed to “1” after the PDN pin goes “H”.
(3) DALM and DARM bits should be changed to “1” after the PMVCM bit is changed to “1”.
(4) PMDAC and PMMO bits should be changed to “1” after DALM and DARM bits is changed to “1”.
(5) External clocks (MCKI, BICK, LRCK) are needed to operate the DAC. When the PMDAC bit = “0”, these clocks
can be stopped. The MOUT buffer can operate without these clocks.
(6) When the PMMO bit is changed, pop noise is output from MOUT pins.
(7) Analog output corresponding to the digital input has a group delay (GD) of 22/fs([email protected]=44.1kHz).
(8) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs([email protected]=44.1kHz).
MS0596-E-00
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[AK4371]
4) LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → HP-Amp
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LIN1HL, LIN2HL, LIN3HL
RIN1HR, RIN2HR, RIN3HL bits
(3) >0s
PMHPL/R bits
(5) >2ms
(5) >2ms
MUTEN bit
LIN1/RIN1/
LIN2/RIN2/
LIN3/RIN3 pins
(4)
(Hi-Z)
(Hi-Z)
(7)
(6)
(6)
HPL/R pins
Figure 32. Power-up/down sequence of LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 and HP-Amp
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier
than HVDD. PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be
stopped when DAC is not used.
(2) PMVCM bit should be changed to “1” after PDN pin goes “H”.
(3) LIN1HL, LIN2HL, LIN3HL, RIN1HR, RIN2HR and RIN3HR bits should be changed to “1” after PMVCM bit is
changed to “1”.
(4) When LIN1HL, LIN2HL, LIN3HL, RIN1HR, RIN2HR or RIN3HR bit is changed to “1”, LIN1, RIN1, LIN2, RIN2,
LIN3 or RIN3 pin is biased to 0.475 x AVDD.
(5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin
is 2.2μF) after LIN1HL, LIN2HL, LIN3HL, RIN1HR, RIN2HR and RIN3HR bits are changed to “1”.
(6) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to
VCOM/2 is tr = 70k x C(typ). When C=1μF, tr = 70ms(typ).
(7) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to
VCOM/2 is tf = 60k x C(typ). When C=1μF, tf = 60ms(typ).
PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to VSS1. After that, the LIN1HL,
LIN2HL, LIN3HL, RIN1HR, RIN2HR and RIN3HR bits should be changed to “0”.
MS0596-E-00
2007/04
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[AK4371]
5) LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → Lineout
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LIN1L, RIN1R,
LIN2L, RIN2R,
LIN3L, RIN3R bits
(3) >0s
PMLO bit
LIN1/RIN1/
LIN2/RIN2/
LIN3/RIN3 pins
LMUTE,
ATTS3-0 bits
LOUT/ROUT pins
(5) >2ms
(5) >2ms
(Hi-Z)
(4)
(Hi-Z)
0FH(0dB)
10H(MUTE)
(6)
(6)
(Hi-Z)
(6)
(Hi-Z)
Figure 33. Power-up/down sequence of LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 and Lineout
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier
than HVDD. PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be
stopped when DAC is not used.
(2) PMVCM bit should be changed to “1” after PDN pin goes “H”.
(3) LIN1L, LIN2L, LIN3L, RIN1R, RIN2R and RIN3R bits should be changed to “1” after PMVCM bit is changed to
“1”.
(4) When LIN1L, LIN2L, LIN3L, RIN1R, RIN2R or RIN3R bit is changed to “1”, LIN1, RIN1, LIN2, RIN2, LIN3 or
RIN3 pin is biased to 0.475 x AVDD.
(5) PMLO bit should be changed to “1” at least 2ms (in case external capacitance at VCOM pin is 2.2μF) after LIN1L,
LIN2L, LIN3L, RIN1R, RIN2R and RIN3R bits are changed to “1”.
(6) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
MS0596-E-00
2007/04
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[AK4371]
6) LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → MOUT
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LIN1M, RIN1M,
LIN2M, RIN2M,
LIN3M, RIN3M bits
(3) >0s
PMMO bit
LIN1/RIN1/
LIN2/RIN2/
LIN3/RIN3 pins
MMUTE,
ATTM3-0 bits
MOUT pin
(5) >2ms
(5) >2ms
(Hi-Z)
(4)
(Hi-Z)
0FH(0dB)
10H(MUTE)
(6)
(6)
(Hi-Z)
(6)
(Hi-Z)
Figure 34. Power-up/down sequence of LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 and MOUT
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier
than HVDD. PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be
stopped when DAC is not used.
(2) PMVCM bit should be changed to “1” after PDN pin goes “H”.
(3) LIN1M, LIN2M, LIN3M, RIN1M, RIN2M and RIN3M bits should be changed to “1” after PMVCM bit is changed
to “1”.
(4) When LIN1M, LIN2M, LIN3M, RIN1M, RIN2M or RIN3M bit is changed to “1”, LIN1, RIN1, LIN2, RIN2, LIN3
or RIN3 pin is biased to 0.475 x AVDD.
(5) PMMO bit should be changed to “1” at least 2ms (in case external capacitance at VCOM pin is 2.2μF) after LIN1M,
LIN2M, LIN3M, RIN1M, RIN2M or RIN3M bits are changed to “1”.
(6) When the PMMO bit is changed, pop noise is output from MOUT pins.
MS0596-E-00
2007/04
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[AK4371]
■ Serial Control Interface
(1) 3-wire Serial Control Mode (I2C pin = “L”)
Internal registers may be written to via the 3-wire μP interface pins (CSN, CCLK and CDTI). The data on this interface
consists of the Chip address (2-bits, Fixed to “01”), Read/Write (1-bit, Fixed to “1”, Write only), Register address (MSB
first, 5-bits) and Control data (MSB first, 8-bits). Address and data are clocked in on the rising edge of CCLK. For write
operations, the data is latched after a low-to-high transition of the 16th CCLK. CSN should be set to “H” once after 16
CCLKs for each address. The clock speed of CCLK is 5MHz(max). The value of the internal registers is initialized at
PDN pin = “L”.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “01”)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 35. 3-wire Serial Control I/F Timing
MS0596-E-00
2007/04
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[AK4371]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4371 supports fast-mode I2C-bus (max: 400kHz, Version 1.0).
(2)-1. WRITE Operations
Figure 36 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 42). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant six bits of the slave address are fixed as “001000”. The next bit is CAD0 (device address bit).
This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets this device address bit (Figure
37). If the slave address matches that of the AK4371, the AK4371 generates an acknowledgement and the operation is
executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the
acknowledge clock pulse (Figure 43). A R/W bit value of “1” indicates that the read operation is to be executed. A “0”
indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4371. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 38). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 39). The AK4371 generates an acknowledgement after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 42).
The AK4371 can perform more than one byte write operation per sequence. After receiving the third byte the AK4371
generates an acknowledgement and awaits the next data. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit
address counter is incremented by one, and the next data is automatically taken into the next address. If the address
exceeds 13H prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will
be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW(Figure 44) except for the START and STOP
conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 36. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
0
CAD0
R/W
A2
A1
A0
D2
D1
D0
(CAD0 should match with CAD0 pin)
Figure 37. The First Byte
0
0
0
A4
A3
Figure 38. The Second Byte
D7
D6
D5
D4
D3
Figure 39. Byte Structure after the second byte
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[AK4371]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4371. After a transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the writing cycle after receiving the first data word.
After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 13H prior to generating a stop condition, the address
counter will “roll over” to 00H and the previous data will be overwritten.
The AK4371 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4371 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would
access data from the address n+1. After receiving the slave address with R/W bit set to “1”, the AK4371 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledgement to the data but instead generates a stop
condition, the AK4371 ceases transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+2)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 40. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4371 then generates an
acknowledgement, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledgement to the data but instead generates a stop condition, the AK4371 ceases transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 41. RANDOM ADDRESS READ
MS0596-E-00
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[AK4371]
SDA
SCL
S
P
start condition
stop condition
Figure 42. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 43. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 44. Bit Transfer on the I2C-Bus
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2007/04
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[AK4371]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
Register Name
Power Management 0
PLL Control
Clock Control
Mode Control 0
Mode Control 1
DAC Lch ATT
DAC Rch ATT
Headphone Out Select 0
Lineout Select 0
Lineout ATT
Reserved
Reserved
Reserved
Headphone Out Select
Headphone ATT
Lineout Select
Mono Mixing
Differential Select
MOUT Select
MOUT ATT
D7
PMVREF
FS3
PLL4
0
ATS
ATTL7
ATTR7
HPG1
0
0
0
0
0
D6
PMPLL
FS2
0
D5
PMLO
FS1
M/S
MONO1
DATTC
MONO0
BCKP
LMUTE
SMUTE
ATTL6
ATTR6
HPG0
LOG
0
0
0
0
ATTL5
ATTR5
ATTL4
ATTR4
LIN2HR
LIN2R
LIN2HL
LIN2L
0
0
0
0
0
0
0
0
LIN3HR
HMUTE
LIN3R
L3M
0
RIN2M
MOG
RIN3HR
RIN3HL
0
RIN3R
0
0
RIN3M
0
HPZ
RIN3L
0
0
LIN3M
PMMO
D4
D3
D2
D1
D0
MUTEN
PMHPR
PMDAC
PMVCM
FS0
PLL3
BF
LRP
BST1
ATTL3
ATTR3
PMHPL
PLL2
PS0
DIF2
BST0
ATTL2
ATTR2
PLL1
PS1
DIF1
DEM1
ATTL1
ATTR1
PLL0
MCKO
DIF0
DEM0
ATTL0
ATTR0
RIN1HR
RIN1R
ATTS3
LIN1HL
LIN1L
ATTS2
DARHR
DARR
ATTS1
DALHL
DALL
ATTS0
0
0
0
0
0
0
0
0
0
0
0
0
LIN3HL
ATTH4
RIN2HR
ATTH3
RIN2HL
ATTH2
LIN1HR
ATTH1
RIN1HL
ATTH0
LIN3L
L3HM
0
LIN2M
RIN2R
L2M
RIN2L
L2HM
LIN1R
L1M
RIN1L
L1HM
0
LDIFM
LDIFH
LDIF
RIN1M
LIN1M
DARM
DALM
MMUTE
ATTM3
ATTM2
ATTM1
ATTM0
MCKAC
All registers inhibit writing at PDN pin = “L”.
PDN pin = “L” resets the registers to their default values.
For addresses from 14H to 1FH, data must not be written.
Unused bits must contain a “0” value.
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[AK4371]
■ Register Definitions
Addr
00H
Register Name
Power Management 0
R/W
Default
D7
PMVREF
R/W
0
D6
PMPLL
R/W
0
D5
PMLO
R/W
0
D4
D3
D2
D1
D0
MUTEN
PMHPR
PMHPL
PMDAC
PMVCM
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PMVCM: Power Management for VCOM Block
0: Power OFF (default)
1: Power ON
PMDAC: Power Management for DAC Blocks
0: Power OFF (default)
1: Power ON
When the PMDAC bit is changed from “0” to “1”, the DAC is powered-up to the current register values
(ATT value, sampling rate, etc).
PMHPL: Power Management for the left channel of the headphone-amp
0: Power OFF (default). HPL pin goes to VSS1(0V).
1: Power ON
PMHPR: Power Management for the right channel of the headphone-amp
0: Power OFF (default). HPR pin goes to VSS1(0V).
1: Power ON
MUTEN: Headphone Amp Mute Control
0: Mute (default). HPL and HPR pins go to VSS1(0V).
1: Normal operation. HPL and HPR pins go to 0.475 x AVDD.
PMLO: Power Management for Stereo Output
0: Power OFF (default) LOUT/ROUT pins go to Hi-Z.
1: Power ON
PMPLL: Power Management for PLL
0: Power OFF: EXT mode (default)
1: Power ON: PLL mode
PMVREF: Power Management for VREF
0: Power OFF (default)
1: Power ON
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”,
all blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default
value.
When PMVCM, PMDAC, PMHPL, PMHPR, PMLO, PMMO, PMPLL, PMVREF and MCKO bits are “0”, all
blocks are powered-down. The register values remain unchanged. Power supply current is 20μA(typ) in this case.
For fully shut down (typ. 1μA), PDN pin should be “L”.
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[AK4371]
Addr
01H
Register Name
PLL Control
R/W
Default
D7
FS3
R/W
1
D6
FS2
R/W
0
D5
FS1
R/W
0
D4
FS0
R/W
0
D3
PLL3
R/W
0
D4
D3
BF
R/W
0
D2
R/W
0
D1
PLL1
R/W
0
D0
PLL0
R/W
0
D2
PS0
R/W
0
D1
PS1
R/W
0
D0
MCKO
R/W
0
PLL2
FS3-0: Select Sampling Frequency
PLL mode: Table 5
EXT mode: Table 11
PLL4-0: Select PLL Reference Clock
PLL mode: Table 4
EXT mode: PLL4-0 bits are disabled
(PLL4 bit is D7 bit of 02H.)
Addr
02H
Register Name
Clock Control
R/W
Default
D7
PLL4
R/W
0
D6
0
RD
0
D5
M/S
R/W
0
MCKAC
R/W
0
MCKO: Control of MCKO signal
0: Disable (default)
1: Enable
PS1-0: MCKO Frequency
PLL mode: Table 9
EXT mode: Table 12
BF: BICK Period setting in Master Mode. In slave mode, this bit is ignored.
0: 32fs (default)
1: 64fs
MCKAC: MCKI Input Mode Select
0: CMOS input (default)
1: AC coupling input
M/S: Select Master/Slave Mode
0: Slave mode (default)
1: Master mode
PLL4-0: Select PLL Reference Clock
PLL3-0 bits are D3-0 bits of 01H.
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[AK4371]
Addr
03H
Register Name
Mode Control 0
R/W
Default
D7
0
RD
0
D6
D5
MONO1
MONO0
R/W
0
R/W
0
D4
BCKP
R/W
0
D3
LRP
R/W
0
D2
DIF2
R/W
0
D1
DIF1
R/W
1
D0
DIF0
R/W
0
D3
BST1
R/W
0
D2
BST0
R/W
0
D1
DEM1
R/W
0
D0
DEM0
R/W
1
DIF2-0: Audio Data Interface Format Select (Table 16)
Default: “010” (Mode 2)
LRP: LRCK Polarity Select in Slave Mode
0: Normal (default)
1: Invert
BCKP: BICK Polarity Select in Slave Mode
0: Normal (default)
1: Invert
MONO1-0: Digital Mixing Select (Table 21)
Default: “00” (LR)
Addr
04H
Register Name
Mode Control 1
R/W
Default
D7
ATS
R/W
0
D6
D5
D4
DATTC
LMUTE
SMUTE
R/W
0
R/W
1
R/W
0
DEM1-0: De-emphasis Filter Frequency Select (Table 19 )
Default: “01” (OFF)
BST1-0: Low Frequency Boost Function Select (Table 20)
Default: “00” (OFF)
SMUTE: Soft Mute Control
0: Normal operation (default)
1: DAC outputs soft-muted
LMUTE: Mute control for LOUT/ROUT (Table 26)
0: Normal operation. ATTS3-0 bits control attenuation value.
1: Mute. ATTS3-0 bits are ignored. (default)
DATTC: DAC Digital Attenuator Control Mode Select
0: Independent (default)
1: Dependent
At DATTC bit = “1”, ATTL7-0 bits control both channel attenuation levels, while register values of
ATTL7-0 bits are not written to the ATTR7-0 bits. At DATTC bit = “0”, the ATTL7-0 bits control the left
channel level and the ATTR7-0 bits control the right channel level.
ATS: Digital attenuator transition time setting (Table 18)
0: 1061/fs (default)
1: 7424/fs
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[AK4371]
Addr
05H
06H
Register Name
DAC Lch ATT
DAC Rch ATT
R/W
Default
D7
ATTL7
ATTR7
R/W
0
D6
ATTL6
ATTR6
R/W
0
D5
ATTL5
ATTR5
R/W
0
D4
ATTL4
ATTR4
R/W
0
D3
ATTL3
ATTR3
R/W
0
D2
ATTL2
ATTR2
R/W
0
D1
ATTL1
ATTR1
R/W
0
D0
ATTL0
ATTR0
R/W
0
ATTL7-0: Setting of the attenuation value of output signal from DACL (Table 17)
ATTR7-0: Setting of the attenuation value of output signal from DACR (Table 17)
Default: “00H” (MUTE)
Addr
07H
Register Name
Headphone Out Select 0
R/W
Default
D7
HPG1
R/W
0
D6
HPG0
R/W
0
D5
D4
D3
D2
D1
D0
LIN2HR
LIN2HL
RIN1HR
LIN1HL
DARHR
DALHL
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DALHL: DAC left channel output signal is added to the left channel of the headphone-amp.
0: OFF (default)
1: ON
DARHR: DAC right channel output signal is added to the right channel of the headphone-amp.
0: OFF (default)
1: ON
LIN1HL: Input signal to LIN1 pin is added to the left channel of the headphone-amp.
0: OFF (default)
1: ON
RIN1HR: Input signal to RIN1 pin is added to the right channel of the headphone-amp.
0: OFF (default)
1: ON
LIN2HL: Input signal to LIN2 pin is added to the left channel of the headphone-amp.
0: OFF (default)
1: ON
LIN2HR: Input signal to LIN2 pin is added to the right channel of the headphone-amp.
0: OFF (default)
1: ON
HPG1-0: DAC Æ HPL/R Gain (Table 25)
Default: “00”: +0.95dB
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[AK4371]
Addr
08H
Register Name
Lineout Select 0
R/W
Default
D7
0
RD
0
D6
LOG
R/W
0
D5
D4
D3
D2
D1
D0
LIN2R
LIN2L
RIN1R
LIN1L
DARR
DALL
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
D3
D2
D1
D0
ATTS3
ATTS2
ATTS1
ATTS0
R/W
0
R/W
0
R/W
0
R/W
0
DALL: DAC left channel output is added to the LOUT buffer amp.
0: OFF (default)
1: ON
DARR: DAC right channel output is added to the ROUT buffer amp.
0: OFF (default)
1: ON
LIN1L: Input signal to the LIN1 pin is added to the LOUT buffer amp.
0: OFF (default)
1: ON
RIN1R: Input signal to the RIN1 pin is added to the ROUT buffer amp.
0: OFF (default)
1: ON
LIN2L: Input signal to the LIN2 pin is added to the LOUT buffer amp.
0: OFF (default)
1: ON
LIN2R: Input signal to the LIN2 pin is added to the ROUT buffer amp.
0: OFF (default)
1: ON
LOG: DAC Æ LOUT/ROUT Gain
0: 0dB (default)
1: +6dB
Addr
09H
Register Name
Lineout ATT
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
ATTS3-0: Analog volume control for LOUT/ROUT (Table 27)
Default: LMUTE bit = “1”, ATTS3-0 bits = “0000” (MUTE)
Setting of ATTS3-0 bits is enabled at LMUTE bit is “0”.
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[AK4371]
Addr
0DH
Register Name
Headphone Out Select
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
RIN3HR
RIN3HL
LIN3HR
LIN3HL
RIN2HR
RIN2HL
LIN1HR
RIN1HL
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
D3
D2
ATTH2
R/W
0
D1
D0
ATTH0
R/W
0
RIN1HL: RIN1 signal is added to the left channel of the Headphone-Amp
0: OFF (default)
1: ON
LIN1HR: LIN1 signal is added to the right channel of the Headphone-Amp
0: OFF (default)
1: ON
RIN2HL: RIN2 signal is added to the left channel of the Headphone-Amp
0: OFF (default)
1: ON
RIN2HR: RIN2 signal is added to the right channel of the Headphone-Amp
0: OFF (default)
1: ON
LIN3HL: LIN3 signal is added to the left channel of the Headphone-Amp
0: OFF (default)
1: ON
LIN3HR: LIN3 signal is added to the right channel of the Headphone-Amp
0: OFF (default)
1: ON
RIN3HL: RIN3 signal is added to the left channel of the Headphone-Amp
0: OFF (default)
1: ON
RIN3HR: RIN3 signal is added to the right channel of the Headphone-Amp
0: OFF (default)
1: ON
Addr
0EH
Register Name
Headphone ATT
R/W
Default
D7
D6
D5
0
HPZ
HMUTE
RD
0
R/W
0
R/W
0
D4
ATTH4
R/W
0
ATTH3
R/W
0
ATTH1
R/W
0
ATTH4-0: Setting of the attenuation value of output signal from Headphone (Table 25)
Default: HMUTE bit = “0”, ATTH4-0 bits = “00H” (0dB)
Setting of ATTH4-0 bits is enabled at HMUTE bit is “0”.
HMUTE: Mute control for Headphone-Amp
0: Normal operation. ATTH4-0 bits control attenuation value. (default)
1: Mute. ATTH4-0 bits are ignored.
HPZ: Headphone-Amp Pull-down Control
0: Shorted to GND (default)
1: Pulled-down by 200kΩ (typ)
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[AK4371]
Addr
0FH
Register Name
Lineout Select
R/W
Default
D7
D6
D5
RIN3R
RIN3L
LIN3R
R/W
0
R/W
0
R/W
0
D4
LIN3L
R/W
0
D3
RIN2R
R/W
0
D2
RIN2L
R/W
0
D1
LIN1R
R/W
0
D0
RIN1L
R/W
0
RIN1L: RIN1 signal is added to the left channel of the Lineout
0: OFF (default)
1: ON
LIN1R: LIN1 signal is added to the right channel of the Lineout
0: OFF (default)
1: ON
RIN2L: RIN2 signal is added to the left channel of the Lineout
0: OFF (default)
1: ON
RIN2R: RIN2 signal is added to the right channel of the Lineout
0: OFF (default)
1: ON
LIN3L: LIN3 signal is added to the left channel of the Lineout
0: OFF (default)
1: ON
LIN3R: LIN3 signal is added to the right channel of the Lineout
0: OFF(default)
1: ON
RIN3L: RIN3 signal is added to the left channel of the Lineout
0: OFF (default)
1: ON
RIN3R: RIN3 signal is added to the right channel of the Lineout
0: OFF (default)
1: ON
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[AK4371]
Addr
10H
Register Name
Mono Mixing
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
L3M
R/W
0
D4
L3HM
R/W
0
D3
L2M
R/W
0
D2
L2HM
R/W
0
D1
L1M
R/W
0
D0
L1HM
R/W
0
L1HM: LIN1/RIN1 signal is added to Headphone-Amp as (L+R)/2.
0: OFF (default)
1: ON
L1M: LIN1/RIN1 signal is added to LOUT/ROUT as (L+R)/2.
0: OFF (default)
1: ON
L2HM: LIN2/RIN2 signal is added to Headphone-Amp as (L+R)/2.
0: OFF (default)
1: ON
L2M: LIN2/RIN2 signal is added to LOUT/ROUT as (L+R)/2.
0: OFF (default))
1: ON
L3HM: LIN3/RIN3 signal is added to Headphone-Amp as (L+R)/2.
0: OFF (default)
1: ON
L3M: LIN3/RIN3 signal is added to LOUT/ROUT as (L+R)/2.
0: OFF (default)
1: ON
Addr
11H
Register Name
Differential Select
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
D1
D0
LDIFM
LDIFH
LDIF
R/W
0
R/W
0
R/W
0
LDIF: Switch control from IN+/IN− pin to LOUT/ROUT.
0: OFF (default)
1: ON
When LDIF bit = “1”, LIN1 and RIN1 pins become IN+ and IN− pins respectively.
LDIFH: Switch control from IN+/IN− pin to Headphone-Amp. (Setting of LIDFH bit is enable at LDIF bit = “1”)
0: OFF (default)
1: ON
LDIFM: Switch control from IN+/IN− pin to MOUT. (Setting of LIDFM bit is enable at LDIF bit = “1”)
0: OFF (default)
1: ON
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[AK4371]
Addr
12H
Register Name
MOUT Select
R/W
Default
D7
RIN3M
R/W
0
D6
LIN3M
R/W
0
D5
RIN2M
R/W
0
D4
LIN2M
R/W
0
D3
RIN1M
R/W
0
D2
LIN1M
R/W
0
D1
DARM
R/W
0
D0
DALM
R/W
0
DALM: DAC left channel output signal is added to MOUT
0: OFF (default)
1: ON
DARM: DAC right channel output signal is added to MOUT
0: OFF (default)
1: ON
LIN1M: LIN1 signal is added to MOUT
0: OFF (default)
1: ON
RIN1M: RIN1 signal is added to MOUT
0: OFF (default)
1: ON
LIN2M: LIN2 signal is added to MOUT
0: OFF (default)
1: ON
RIN2M: RIN2 signal is added to MOUT
0: OFF (default)
1: ON
LIN3M: LIN3 signal is added to MOUT
0: OFF (default)
1: ON
RIN3M: RIN3 signal is added to MOUT
0: OFF (default)
1: ON
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[AK4371]
Addr
13H
Register Name
MOUT ATT
R/W
Default
D7
0
RD
0
D6
PMMO
R/W
0
D5
MOG
R/W
0
D4
D3
D2
D1
D0
MMUTE
ATTM3
ATTM2
ATTM1
ATTM0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
ATTM3-0: Setting of the attenuation value of output signal from MOUT (Table 27)
Default: MMUTE bit = “1”, ATTM3-0 bits = “0000” (MUTE)
Setting of ATTM3-0 bits is enabled at HMUTE bit is “0”.
MMUTE: Mute control for MOUT (Table 27)
0: Normal operation. ATTM3-0 bits control attenuation value.
1: Mute. ATTM3-0 bits are ignored. (default)
MOG: DAC Æ MOUT Gain
0: 0dB (default)
1: +6dB
PMMO: Power Management for Mono Output
0: Power OFF (default). MOUT pin goes to Hi-Z.
1: Power ON
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[AK4371]
SYSTEM DESIGN
Figure 45 shows the system connection diagram. An evaluation board [AKD4371] is available which demonstrates the
optimum layout, power supply arrangements and measurement results.
Handsfree
Analog Supply
+
1.6∼3.6V
10µ
0.1µ
0.22µ
Speaker
2.2µ
0.1µ
23
22
21
20
19
18
17
AVDD
VCOM
VREF
ROUT
LOUT
MOUT
16Ω
24
16Ω
HVDD
+
220µ
VSS1
220µ
+
+
SPK-Amp
25 HPR
MUTET 16
26 HPL
I2C
15
27 RIN2
PDN
14
1µ
28 LIN2
AK4371VN
CSN
13
29 RIN3
Top View
DVDD
PVDD
VCOC
5
6
7
VSS2
MCKI
9
8
LRCK
VSS3
4
32 LIN1
3
MCKO 10
BICK
11
31 RIN1
SDATA
12
CDTI
2
CCLK
30 LIN3
1
Headphone
0.1u
0.1u
Analog Ground
1000p
Rp
10
Cp
Digital Ground
Audio Controller
µP
Notes:
- VSS1, VSS2 and VSS3 of the AK4371 should be distributed separately from the ground of external controllers.
- All digital input pins (I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN) must
not be left floating.
- When the AK4371 is in EXT mode (PMPLL bit = “0”), a resistor and capacitor for the VCOC pin is not needed.
- When the AK4371 is in PLL mode (PMPLL bit = “1”), a resistor and capacitor for the VCOC pin should be
connected as shown in Table 4
- When the AK4371 is used in master mode, LRCK and BICK pins are floating before the M/S bit is changed to
“1”. Therefore, a 100kΩ pull-up resistor should be connected to the LRCK and BICK pins of the AK4371.
- When DVDD is supplied from AVDD via 10Ω series resistor, the capacitor larger than 0.1μF should not be
connected between DVDD and the ground.
Figure 45. Typical Connection Diagram (In case of AC coupling to MCKI)
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[AK4371]
AVDD
AK4371
110k
LIN1 pin
HP-Amp
LIN1HL bit
100k
Note: If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to
VCOM voltage (= 0.475 x AVDD) externally.
Figure 46. External Bias Circuit Example for Line Input Pin
1. Grounding and Power Supply Decoupling
The AK4371 requires careful attention to power supply and grounding arrangements. AVDD, PVDD and HVDD are
usually supplied from the analog power supply in the system and DVDD is supplied from AVDD via a 10Ω resistor.
Alternatively if AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. When the AK4371 is powered-down, DVDD should be powered-down at the same time or later than AVDD. When
AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier than HVDD. When
the AK4371 is powered-down, AVDD should be powered-down at the same time or later than HVDD. The power up
sequence of PVDD is not critical. VSS1, VSS2 and VSS3 must be connected to the analog ground plane. System analog
ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit
board. Decoupling capacitors should be as close to the AK4371 as possible, with the small value ceramic capacitors being
the nearest.
2. Voltage Reference
When PMVREF bit = “0”, the input voltage to AVDD sets the analog output range. Usually a 0.1μF ceramic capacitor is
connected between AVDD and VSS1. When PMVREF bit = “1”, VREF is the reference voltage of analog signal (typ.
0.855 x AVDD). The capacitor around 0.22μF attached between VREF and VSS1 eliminates the effects of high
frequency noise. VCOM is a signal ground of this chip (0.475 x AVDD). The electrolytic capacitor around 2.2μF attached
between VCOM anVSS1 eliminates the effects of high frequency noise, too. No load current may be drawn from VREF
and VCOM pin. All signals, especially clock, should be kept away from AVDD, VREF and VCOM in order to avoid
unwanted coupling into the AK4371.
3. Analog Outputs
The analog outputs are single-ended outputs, and 0.48 x AVDD Vpp(typ)@−3dBFS (PMVREF bit = “0”) for
headphone-amp and 0.61xAVDD Vpp(typ) @0dBFS (PMVREF bit = “0”) for LOUT/ROUT/MOUT centered on the
VCOM voltage. The input data format is 2’s compliment. The output voltage is a positive full scale for
7FFFFFH(@24bit) and negative full scale for 800000H(@24bit). The ideal output is VCOM voltage for
000000H(@24bit).
DC offsets on the analog outputs is eliminated by AC coupling since the analog outputs have a DC offset equal to VCOM
plus a few mV.
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[AK4371]
PACKAGE
32pin QFN (Unit: mm)
4.0 ± 0.1
2.4 ± 0.1
17
24
0.40 ± 0.10
25
2.4 ± 0.1
4.0 ± 0.1
16
A
Exposed
Pad
32
9
0.45 ± 0.10
8
1
0.22 ± 0.05
B
0.18 ± 0.05
0.05 M
C0.3
PIN #1 ID
0.65 MAX
0.4
0.00 MIN
0.05 MAX
0.08
Note) The exposed pad on the bottom surface of the package must be open or connected to the ground.
■ Package & Lead frame material
Package molding compound: Epoxy
Lead frame material:
Cu
Lead frame surface treatment: Solder (Pb free) plate
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[AK4371]
MARKING
4371
XXXX
1
XXXX: Date code (4 digit)
REVISION HISTORY
Date (YY/MM/DD)
07/04/13
Revision
00
Reason
First Edition
Page
Contents
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
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