AKM AKD4387

ASAHI KASEI
[AK4387]
AK4387
106dB 192kHz 24-Bit 2ch ∆Σ DAC
GENERAL DESCRIPTION
The AK4387 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit
architecture for its modulator the AK4387 delivers a wide dynamic range while preserving linearity for
improved THD+N performance. The AK4387 integrates a combination of SCF and CTF filters increasing
performance for systems with excessive clock jitter. The 24 Bit word length and 192kHz sampling rate
make this part ideal for a wide range of applications including DVD-Audio. The AK4387 is offered in a
space saving 16pin TSSOP package.
FEATURES
† Sampling Rate Ranging from 8kHz to 192kHz
† 128 times Oversampling (Normal Speed Mode)
† 64 times Oversampling (Double Speed Mode)
† 32 times Oversampling (Quad Speed Mode)
† 24-Bit 8 times FIR Digital Filter
† SCF with High Tolerance to Clock Jitter
† Single Ended Output Buffer
† Digital de-emphasis for 32k, 44.1k and 48kHz sampling
† Soft mute
† Digital Attenuator (Linear 256 steps)
2
† I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I S
† Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
† THD+N: -90dB
† Dynamic Range: 106dB
† Power supply: 4.5 to 5.5V
† Very Small Package: 16pin TSSOP
MCLK
DVDD
AVDD
CSN
CCLK
De-emphasis
Control
µP
Interface
VSS
Clock
Divider
VCOM
CDTI
LRCK
BICK
SDTI
DZF
Audio
Data
Interface
ATT
8X
Interpolator
∆Σ
Modulator
SCF
LPF
AOUTL
ATT
8X
Interpolator
∆Σ
Modulator
SCF
LPF
AOUTR
RSTN
MS0429-E-00
2005/09
-1-
ASAHI KASEI
[AK4387]
„ Ordering Guide
-20 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4387
AK4387ET
AKD4387
„ Pin Layout
MCLK
1
16
DZF
BICK
2
15
DVDD
SDTI
3
14
AVDD
LRCK
4
13
VSS
RSTN
5
12
VCOM
CSN
6
11
AOUTL
CCLK
7
10
AOUTR
CDTI
8
9
NC
Top
View
„ Compatibility with AK4384
1. Function
Functions
THD+N
Output Voltage
Slow Roll-Off Filter
Mode Setting
Zero Data Detect Pin
AK4384
-94dB
3.4Vpp
Available
Serial/Parallel
2 pins
2. Pin Configuration
AK4387
AK4384
MCLK
MCLK
BICK
BICK
SDTI
SDTI
LRCK
LRCK
RSTN
PDN
CSN
SMUTE/CSN
CCLK
ACKS/CCLK
CDTI
DIF0/CDTI
3. Register map
Addr Register Name
00H Control 1
01H Control 2
02H Control 3
03H Lch ATT
04H Rch ATT
D7
ACKS
DZFE
0
ATT7
ATT7
Pin#
1
2
3
4
5
6
7
8
Pin#
16
15
14
13
12
11
10
9
AK4387
-90dB
2.95Vpp
Not Available
Serial
1 pin
AK4384
DZFL
DZFR
VDD
VSS
VCOM
AOUTL
AOUTR
P/S
AK4387
DZF
DVDD
AVDD
VSS
VCOM
AOUTL
AOUTR
NC
D6
D5
D4
0
0
DIF2
1
0
DFS1
0
0
INVL
ATT6
ATT5
ATT4
ATT6
ATT5
ATT4
: Different points from AK4384
MS0429-E-00
D3
DIF1
DFS0
INVR
ATT3
ATT3
D2
DIF0
DEM1
DZFB
ATT2
ATT2
D1
PW
DEM0
0
ATT1
ATT1
D0
RSTN
SMUTE
0
ATT0
ATT0
2005/09
-2-
ASAHI KASEI
[AK4387]
PIN/FUNCTION
No.
1
Pin Name
MCLK
I/O
I
Function
Master Clock Input Pin
An external TTL clock should be input on this pin.
2
BICK
I
Audio Serial Data Clock Pin
3
SDTI
I
Audio Serial Data Input Pin
4
LRCK
I
L/R Clock Pin
5
RSTN
I
Reset Mode Pin
When at “L”, the AK4387 is in the power-down mode and is held in reset.
The AK4387 must be reset once upon power-up.
6
CSN
I
Chip Select Pin
7
CCLK
I
Control Data Clock Pin
8
CDTI
I
Control Data Input Pin
9
NC
No Connect pin
No internal bonding. This pin should be opened or connected to VSS.
10
AOUTR
O
Rch Analog Output Pin
11
AOUTL
O
Lch Analog Output Pin
12
VCOM
O
Common Voltage Pin, AVDD/2
Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a
10µF electrolytic cap.
13
VSS
Ground Pin
14
AVDD
Power Supply Pin
15
DVDD
Power Supply Pin
16
DZF
O
Lch and Rch Data Zero Input Detect Pin
Note: All input pins should not be left floating.
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter
Symbol
min
Power Supply
AVDD, DVDD
-0.3
Input Current (any pins except for supplies)
IIN
Input Voltage
VIND
-0.3
Ambient Operating Temperature
Ta
-20
Storage Temperature
Tstg
-65
max
6.0
±10
DVDD+0.3
85
150
Units
V
mA
V
°C
°C
Note 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Power Supply
(Note 2)
Symbol
AVDD, DVDD
min
4.5
typ
5.0
max
5.5
Units
V
Note 2. The power up sequence between AVDD and DVDD is not critical.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0429-E-00
2005/09
-3-
ASAHI KASEI
[AK4387]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data;
Measurement frequency=20Hz ∼ 20kHz; RL ≥5kΩ; External circuit: Figure 9 (Example 2); unless otherwise specified)
Parameter
min
Typ
max
Units
Resolution
24
Bits
Dynamic Characteristics
(Note 3)
THD+N
fs=44.1kHz
0dBFS
-90
-80
dB
BW=20kHz
-60dBFS
-42
dB
fs=96kHz
0dBFS
-90
dB
BW=40kHz
-60dBFS
-39
dB
fs=192kHz
0dBFS
-85
dB
BW=40kHz
-60dBFS
-39
dB
Dynamic Range (-60dBFS with A-weighted)
(Note 4)
98
106
dB
S/N
(A-weighted)
(Note 5)
98
106
dB
Interchannel Isolation (1kHz)
90
100
dB
Interchannel Gain Mismatch
0.2
0.5
dB
DC Accuracy
Gain Drift
100
ppm/°C
Output Voltage
(Note 6)
2.75
2.95
3.15
Vpp
Load Resistance
(Note 7)
5
kΩ
Load Capacitance
25
pF
Power Supplies
Power Supply Current (AVDD+DVDD)
17
27
mA
Normal Operation (RSTN pin = “H”, fs≤96kHz)
20
32
mA
Normal Operation (RSTN pin = “H”, fs=192kHz)
60
150
µA
Power-Down Mode (RSTN pin = “L”)
(Note 8)
Note 3. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
Note 4. 100dB at 16bit data.
Note 5. S/N does not depend on input bit length.
Note 6. Full-scale voltage (0dB). Output voltage scales with the voltage of AVDD,
AOUT (typ.@0dB) = 2.95Vpp × AVDD/5.
Note 7. For AC-load.
Note 8. All digital inputs including clock pins (MCLK, BICK and LRCK) are held AVDD, DVDD or VSS.
SHARP ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; AVDD=DVDD = 4.5 ∼ 5.5V; fs = 44.1kHz; DEM = OFF)
Parameter
Symbol
min
typ
max
Units
Digital filter
PB
0
20.0
kHz
Passband
±0.05dB (Note 9)
22.05
kHz
-6.0dB
Stopband
(Note 9)
SB
24.1
kHz
Passband Ripple
PR
dB
± 0.02
Stopband Attenuation
SA
54
dB
Group Delay
(Note 10)
GD
19.3
1/fs
Digital Filter + LPF
Frequency Response 20.0kHz fs=44.1kHz
FR
dB
± 0.03
40.0kHz fs=96kHz
FR
dB
± 0.03
80.0kHz fs=192kHz
FR
dB
± 0.03
Note 9. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
Note 10. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data
of both channels to input register to the output of analog signal.
MS0429-E-00
2005/09
-4-
ASAHI KASEI
[AK4387]
DC CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=4.5 ∼ 5.5V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
2.2
Low-Level Input Voltage
VIL
High-Level Output Voltage (Iout=-80µA)
VOH
AVDD-0.4
Low-Level Output Voltage
(Iout=80µA)
VOL
Input Leakage Current
Iin
-
typ
-
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=4.5 ∼ 5.5V, CL = 20pF)
Parameter
Symbol
min
typ
fCLK
2.048
11.2896
Master Clock Frequency
Duty Cycle
dCLK
40
LRCK Frequency
Normal Speed Mode
fsn
8
Double Speed Mode
fsd
60
Quad Speed Mode
fsq
120
Duty Cycle
Duty
45
Audio Interface Timing
BICK Period
Normal Speed Mode
tBCK
1/128fs
Double/Quad Speed Mode
tBCK
1/64fs
BICK Pulse Width Low
tBCKL
30
Pulse Width High
tBCKH
30
BICK rising to LRCK Edge
(Note 11)
tBLR
20
LRCK Edge to BICK rising
(Note 11)
tLRB
20
SDTI Hold Time
tSDH
20
SDTI Setup Time
tSDS
20
Control Interface Timing
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
tCSS
50
CSN “↓” to CCLK “↑”
tCSH
50
CCLK “↑” to CSN “↑”
Reset Timing
RSTN Pulse Width
(Note 12)
tPD
150
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. The AK4387 can be reset by bringing RSTN pin = “L”.
MS0429-E-00
max
0.8
0.4
± 10
Units
V
V
V
V
µA
max
36.864
60
Units
MHz
%
48
96
192
55
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2005/09
-5-
ASAHI KASEI
[AK4387]
„ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDS
tSDH
VIH
SDTI
VIL
Serial Interface Timing
MS0429-E-00
2005/09
-6-
ASAHI KASEI
[AK4387]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
VIH
A4
VIL
WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
WRITE Data Input Timing
tPD
RSTN
VIL
Power-down Timing
MS0429-E-00
2005/09
-7-
ASAHI KASEI
[AK4387]
OPERATION OVERVIEW
„ System Clock
The external clocks, which are required to operate the AK4387, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS bit
= “0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is
set automatically. (Table 2~4). After exiting reset (RSTN pin = “↑”), the AK4387 is in Auto Setting Mode. In Auto
Setting Mode (ACKS bit = “1”: Default), as MCLK frequency is detected automatically (Table 5), and the internal master
clock becomes the appropriate frequency (Table 6), it is not necessary to set DFS0/1.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4387 is in the normal operation
mode (RSTN pin = ”H”). If these clocks are not provided, the AK4387 may draw excess current and may fall into
unpredictable operation. This is because the device utilizes dynamic refreshed logic internally. The AK4387 should be
reset by RSTN pin = “L” after threse clocks are provided. If the external clocks are not present, the AK4387 should be in
the power-down mode (RSTN pin = “L”). After exiting reset at power-up etc., the AK4387 is in the power-down mode
until MCLK and LRCK are input.
DFS1
DFS0
Sampling Rate (fs)
0
0
Normal Speed Mode
8kHz~48kHz
0
1
Double Speed Mode
60kHz~96kHz
1
0
Quad Speed Mode
Default
120kHz~192kHz
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
384fs
12.2880MHz
16.9344MHz
18.4320MHz
MCLK
512fs
16.3840MHz
22.5792MHz
24.5760MHz
768fs
24.5760MHz
33.8688MHz
36.8640MHz
1152fs
36.8640MHz
N/A
N/A
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK
fs
88.2kHz
96.0kHz
128fs
11.2896MHz
12.2880MHz
MCLK
192fs
256fs
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
384fs
33.8688MHz
36.8640MHz
BICK
64fs
5.6448MHz
6.1440MHz
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
MS0429-E-00
2005/09
-8-
ASAHI KASEI
[AK4387]
LRCK
fs
176.4kHz
192.0kHz
MCLK
128fs
192fs
22.5792MHz 33.8688MHz
24.5760MHz 36.8640MHz
BICK
64fs
11.2896MHz
12.2880MHz
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MCLK
1152fs
512fs
256fs
128fs
Sampling Speed
Normal (fs≤32kHz)
Normal
Double
Quad
768fs
384fs
192fs
Table 5. Sampling Speed (Auto Setting Mode: Default)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
22.5792
24.5760
192fs
33.8688
36.8640
256fs
22.5792
24.5760
-
MCLK (MHz)
384fs
512fs
16.3840
22.5792
24.5760
33.8688
36.8640
-
768fs
24.5760
33.8688
36.8640
-
1152fs
36.8640
-
Sampling
Speed
Normal
Double
Quad
Table 6. System Clock Example (Auto Setting Mode)
„ Audio Serial Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0-2 as shown in Table 7 can select five serial
data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK.
Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
SDTI Format
16bit LSB Justified
20bit LSB Justified
24bit MSB Justified
24bit I2S Compatible
24bit LSB Justified
BICK
≥32fs
≥40fs
≥48fs
≥48fs
≥48fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
Default
Table 7. Audio Data Formats
MS0429-E-00
2005/09
-9-
ASAHI KASEI
[AK4387]
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDTI
Mode 0
15
14
6
1
0
5
14
3
4
15
2
16
1
17
15
0
31
0
14
6
5
14
1
4
15
3
16
2
1
17
0
31
15
14
0
1
0
1
0
1
BICK
(64fs)
SDTI
Mode 0
Don’t care
15
14
Don’t care
0
15
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
8
1
9
10
11
12
31
0
8
1
9
10
11
12
31
BICK
(64fs)
SDTI
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDTI
Mode 4
Don’t care
23
22
21
20
23
22
21
20
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1,4 Timing
LRCK
0
1
2
23
22
24
30
31
0
1
2
22
23
24
30
31
BICK
(64fs)
SDTI
23 22
1
0
23 22
Don’t care
1
0
Don’t care
23
22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
MS0429-E-00
2005/09
- 10 -
ASAHI KASEI
[AK4387]
LRCK
0
1
2
3
23
25
24
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
0
1
23 22
Don’t care
23 22
1
0
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
„ De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled
with DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always off.
DEM1
DEM0
Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF
48kHz
32kHz
Default
Table 8. De-emphasis Filter Control (Normal Speed Mode)
„ Output Volume
The AK4387 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE.
These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing
levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition
time of 1 level and all 256 levels is shown in Table 10.
Sampling Speed
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Transition Time
1 Level
255 to 0
4LRCK
1020LRCK
8LRCK
2040LRCK
16LRCK
4080LRCK
Table 9. ATT Transition Time
MS0429-E-00
2005/09
- 11 -
ASAHI KASEI
[AK4387]
„ Zero Detection
The AK4387 has channel-independent zeros detect function. When the input data at each channel is continuously zeros
for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input
data of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF pin
of both channels go to “L” at 2~3/fs after RSTN bit returns to “1”. Zero detect function can be disabled by DZFE bit. In
this case, DZF pins of both channels are always “L”. DZFB bit can invert the polarity of DZF pin.
„ Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by
-∞ during ATT_DATA×ATT transition time (Table 9) from the current ATT level. When the SMUTE bit is returned to
“0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT
transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source
without stopping the signal transmission.
SMUTE bit
ATT Level
(1)
(1)
(3)
Attenuation
-∞
GD
(2)
GD
AOUT
DZF pin
(4)
8192/fs
Notes:
(1) ATT_DATA×ATT transition time (Table 9). For example, in Normal Speed Mode, this time is 1020LRCK cycles
(1020/fs) at ATT_DATA=255.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to
“H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 5. Soft Mute and Zero Detection
MS0429-E-00
2005/09
- 12 -
ASAHI KASEI
[AK4387]
„ System Reset
The AK4387 should be reset once by bringing RSTN pin = “L” upon power-up. The AK4387 is powered up and the
internal timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4387 is in the
power-down mode until MCLK and LRCK are input.
„ Power-down
The AK4387 is placed in the power-down mode by bringing RSTN pin “L” and the anlog outputs become VCOM voltage
(AVDD/2). Figure 6 shows an example of the system timing at the power-down and power-up.
RSTN
Internal
State
Normal Operation
Power-down
D/A In
(Digital)
Normal Operation
“0” data
GD
D/A Out
(Analog)
(1)
GD
(2)
(3)
(3)
(1)
(4)
Clock In
Don’t care
MCLK, LRCK, BICK
DZF
External
MUTE
(6)
(5)
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are VCOM voltage (AVDD/2) at the power-down mode.
(3) Click noise occurs at the edge of RSTN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (RSTN pin = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pin is “L” in the power-down mode (RSTN pin = “L”).
Figure 6. Power-down/up Sequence Example
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ASAHI KASEI
[AK4387]
„ Reset Function
When RSTN bit =0, DAC is powered down but the internal register values are not initialized. The analog outputs go to
VCOM voltage and DZF pins go to “H”. Figure 7 shows the example of reset by RSTN bit.
RSTN bit
3~4/fs (6)
2~3/fs (6)
Internal
RSTN bit
Internal
State
Normal Operation
D/A In
(Digital)
“0” data
(1)
D/A Out
(Analog)
Normal Operation
Digital Block Power-down
GD
GD
(3)
(2)
(3)
(1)
(4)
Clock In
Don’t care
MCLK,LRCK,BICK
2/fs(5)
DZF
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage (AVDD/2).
(3) Click noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0” data is
input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN pin = “L”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN bit “1”.
Figure 7. Reset Sequence Example
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ASAHI KASEI
[AK4387]
„ Mode Control Interface
Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists
of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first,
5bits) and Control Data (MSB first, 8bits). AK4387 latches the data on the rising edge of CCLK, so data should clocked
in on the falling edge. The writing of data becomes valid by CSN “↑”. The clock speed of CCLK is 5MHz (max).
RSTN pin = “L” resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the
registers are not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “01”)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 8. Control I/F Timing
*The AK4387 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4387 is in the power down mode (RSTN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
„ Register Map
Addr
00H
01H
02H
03H
04H
Register Name
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
D7
ACKS
DZFE
0
ATT7
ATT7
D6
0
1
0
ATT6
ATT6
D5
0
0
0
ATT5
ATT5
D4
DIF2
DFS1
INVL
ATT4
ATT4
D3
DIF1
DFS0
INVR
ATT3
ATT3
D2
DIF0
DEM1
DZFB
ATT2
ATT2
D1
PW
DEM0
0
ATT1
ATT1
D0
RSTN
SMUTE
0
ATT0
ATT0
Notes:
For addresses from 05H to 1FH, data must not be written.
When RSTN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default
values. All data can be written to the register even if PW or RSTN bit is “0”.
The “0” register should be written “0”, the “1” register should be written “1” data.
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ASAHI KASEI
[AK4387]
„ Register Definitions
Addr
00H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Control 1
ACKS
0
0
DIF2
DIF1
DIF0
PW
RSTN
default
1
0
0
0
1
0
1
1
RSTN: Internal timing reset control
0: Reset. All registers are not initialized.
1: Normal Operation
When MCLK frequency or DFS changes, the click noise can be reduced by RSTN bit.
PW: Power down control
0: Power down. All registers are not initialized.
1: Normal Operation
DIF2-0: Audio data interface formats (see Table 7)
Initial: “010”, Mode 2
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0
are ignored. When this bit is “0”, DFS1-0 set the sampling speed mode.
Addr
01H
D7
D6
D5
D4
D3
D2
D1
D0
Control 2
Register Name
DZFE
1
0
DFS1
DFS0
DEM1
DEM0
SMUTE
default
0
0
0
0
0
0
1
0
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis Response (see Table 8)
Initial: “01”, OFF
DFS1-0: Sampling speed control
00: Normal speed
01: Double speed
10: Quad speed
When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise
occurs.
DZFE: Data Zero Detect Enable
0: Disable
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are
always “L”.
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ASAHI KASEI
Register Name
02H
[AK4387]
D7
D6
D5
D4
D3
D2
D1
D0
Control 3
0
0
0
INVL
INVR
DZFB
0
0
default
0
0
0
0
0
0
0
0
D5
ATT5
ATT5
1
D4
ATT4
ATT4
1
D3
ATT3
ATT3
1
D2
ATT2
ATT2
1
D1
ATT1
ATT1
1
D0
ATT0
ATT0
1
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
INVR: Inverting Lch Output Polarity
0: Normal Output
1: Inverted Output
INVL: Inverting Rch Output Polarity
0: Normal Output
1: Inverted Output
Addr
03H
04H
Register Name
Lch ATT
Rch ATT
default
D7
ATT7
ATT7
1
D6
ATT6
ATT6
1
ATT = 20 log10 (ATT_DATA / 255) [dB]
00H: Mute
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ASAHI KASEI
[AK4387]
SYSTEM DESIGN
Figure 9 and 10 show the system connection diagram. An evaluation board (AKD4387) is available in order to allow an
easy study on the layout of a surrounding circuit.
Master Clock
1
DZF
MCLK
Optional External
Mute Circuits
16
10
64fs
2
BICK
DVDD
15
24bit Audio Data
3
SDTI
AVDD
14
0.1u
fs
Reset & Power down
0.1u
4
LRCK
VSS
13
5
RSTN
VCOM
12
6
CSN
AOUTL
11
7
CCLK
AOUTR
10
8
CDTI
AK4387
10u
+
10u
Analog
Supply 5V
+
Lch Out
Mode
Setting
Digital Ground
NC
Rch Out
9
Analog Ground
Figure 9. Typical Connection Diagram (Example 1)
Master Clock
1
MCLK
64fs
2
BICK
DVDD
15
24bit Audio Data
3
SDTI
AVDD
14
fs
Reset & Power down
DZF
Optional External
Mute Circuits
16
0.1u
4
LRCK
VSS
13
5
RSTN
VCOM
12
6
CSN
AOUTL
11
7
CCLK
AOUTR
10
8
CDTI
AK4387
10u
+
10u
Analog
Supply 5V
+
Lch Out
Mode
Setting
Digital Ground
NC
Rch Out
9
Analog Ground
Figure 10. Typical Connection Diagram (Example 2)
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins should not be left floating.
- THD+N value at 192kHz decreases by around 3dB when using Example 2.
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ASAHI KASEI
[AK4387]
1. Grounding and Power Supply Decoupling
AVDD, DVDD and VSS are supplied from analog supply and should be separated from system digital supply.
Decoupling capacitor, especially 0.1µF ceramic capacitor for high frequency should be placed as near to AVDD, DVDD
as possible. The differential Voltage between AVDD and VSS pins set the analog output range.
2. Analog Outputs
The analog outputs are single-ended and centered around the VCOM voltage. The output signal range is typically
2.95Vpp ([email protected]=5V). The phase of the analog outputs can be inverted channel independently by INVL/INVR bits.
The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma
modulator beyond the audio passband. The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative
full scale for 800000H (@24bit). The ideal output is VCOM voltage for 000000H (@24bit).
DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few mV.
Figure 11 shows an example of the external LPF with 2Vrms output.
390p
3.3k
3.3k
+Vop
22u
3.0k
Analog
Out
3.9k
AOUT
22k
470p
-Vop
fc=108.6kHz, Q=0.706, g=-0.08dB at 40kHz
Figure 11. External 2nd order LPF Circuit Example (using op-amp with dual power supplies)
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ASAHI KASEI
[AK4387]
PACKAGE
16pin TSSOP (Unit: mm)
*5.0±0.1
9
A
8
1
0.13 M
6.4±0.2
*4.4±0.1
16
1.05±0.05
0.22±0.1
0.17±0.05
0.65
Detail A
0.5±0.2
0.1±0.1
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
„ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
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ASAHI KASEI
[AK4387]
MARKING
AKM
4387ET
XXYYY
1)
2)
3)
4)
Pin #1 indication
Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
Marketing Code : 4387ET
Asahi Kasei Logo
Revision History
Date (YY/MM/DD)
05/09/30
Revision
00
Reason
First Edition
Page
Contents
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or dev ices or systems containing them, may require an export
license or other official approv al under the law and regulations of the country of export pertaining
to customs and tariff s, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related dev ice or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representativ e Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for lif e support or maintenance
of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in
significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected
to result, whether directly or indirectly, in the loss of the saf ety or effectiveness of the dev ice
or system containing it, and which must therefore meet v ery high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in adv ance of the abov e content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
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