AKM AKD4536

ASAHI KASEI
[AK4536]
AK4536
16-Bit Mono CODEC with ALC & MIC/SPK-AMP
GENERAL DESCRIPTION
The AK4536 is a 16-bit mono CODEC with Microphone-Amplifier and Speaker-Amplifier. Input circuits
include a Microphone-Amplifier and an ALC (Automatic Level Control) circuit. Output circuits include a
Speaker-Amplifier and Mono Line Output. The AK4536 suits a moving picture of Digital Still Camera and
etc. The AK4536 is housed in a space-saving 28-pin QFN package.
FEATURE
1. 16-Bit Delta-Sigma Mono CODEC
2. Recording Function
• 1ch Mono Input
• 1st MIC Amplifier: 0dB or 20dB
• 2nd Amplifier with ALC: -8dB ∼ +27.5dB, 0.5dB Step
• ADC Performance: S/(N+D): 80dB, DR, S/N: 85dB
3. Playback Function
• Digital Volume: +12dB ∼ -115dB, 0.5dB Step, Mute
• Mono Line Output Performance: S/(N+D): 85dB, S/N: 95dB
• Mono Speaker-Amp
- Speaker-Amp Performance: S/(N+D): 50dB, S/N: 90dB (Po = 250mW)
- BTL Output
- ALC (Automatic Level Control) Circuit
- Output Power: 250mW @ 8Ω, SVDD=3.3V
• Beep Input
4. Power Management
5. Flexible PLL Mode:
• Frequencies: 11.2896MHz, 12MHz or 12.288MHz (MCKI pin)
1fs (FCK pin)
16fs, 32fs or 64fs (BICK pin)
• Input Level: CMOS or AC Coupling (MCKI pin)
6. EXT Mode:
• Frequencies: 256fs, 512fs or 1024fs (MCKI pin)
• Input Level: CMOS or AC Coupling (MCKI pin)
7. Sampling Rate:
• PLL Slave Mode: 7.35kHz ∼ 26kHz
• PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz or 24kHz
• EXT Slave Mode: 7.35kHz ∼ 26kHz (256fs or 512fs), 7.35kHz ∼ 13kHz (1024fs)
8. Serial µP Interface: 3-wire
9. Master / Slave Mode
10. Audio Interface Format: MSB First, 2’s compliment
• ADC: DSP Mode, 16bit MSB justified, I2S
• DAC: DSP Mode, 16bit MSB justified, 16bit LSB justified, I2S
11. Ta = -10 ∼ 70°C
12. Power Supply
• CODEC, Speaker-Amp: 2.4 ∼ 3.6V (typ. 3.3V)
13. Power Supply Current: 19mA (All Power ON)
14. Package: 28pin QFN
MS0174-E-00
2002/09
-1-
ASAHI KASEI
[AK4536]
n Block Diagram
AVSS AVDD
MICOUT
MPI
AIN
PMMIC
MIC
Power
Supply
PMADC
ALC1
(IPGA)
MIC
MIC-AMP
0dB or 20dB
ADC
HPF
PDN
ALC1A
PMAO
Audio
Interface
PMDAC
FCK
BICK
DACA
DAC
AOUT
BEEPA
SVDD
DACM
DATT
SDTO
ALC1M
SDTI
SVSS
DSP
and
uP
PMSPK
SPP
SPKAMP
ALC2
CSN
MIX
Control
Register
SPN
CCLK
CDTI
PMBP
PMPLL
PMXTL
XTO
PLL
XTI/MCKI
VCOM
BEEP
MIN
MOUT
VCOC
DVSS DVDD
Figure 1. AK4536 Block Diagram
MS0174-E-00
2002/09
-2-
ASAHI KASEI
[AK4536]
n Ordering Guide
AK4536VN
AKD4536
28pin QFN (0.5mm pitch)
−10 ∼ +70°C
Evaluation board for AK4536
MPI
MIC
MICOUT
AIN
BEEP
AOUT
MOUT
28
27
26
25
24
23
22
n Pin Layout
VCOM
1
21
MIN
AVSS
2
20
SVSS
AVDD
3
19
SVDD
VCOC
4
18
SPN
PDN
5
17
SPP
CSN
6
16
XTO
CCLK
7
15
MCKI/XTI
8
9
10
11
12
13
14
CDTI
SDTI
SDTO
FCK
BICK
DVDD
DVSS
Top View
MS0174-E-00
2002/09
-3-
ASAHI KASEI
[AK4536]
PIN/FUNCTION
No.
Pin Name
I/O
1
VCOM
O
2
3
AVSS
AVDD
-
4
VCOC
O
5
PDN
I
6
7
8
9
10
11
12
13
14
CSN
CCLK
CDTI
SDTI
SDTO
FCK
BICK
DVDD
DVSS
XTI
MCKI
XTO
SPP
SPN
SVDD
SVSS
MIN
MOUT
AOUT
BEEP
AIN
MICOUT
MIC
MPI
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I
I
I
I
O
I/O
I/O
I
I
O
O
O
I
O
O
I
I
O
I
O
Function
Common Voltage Output Pin, 0.45 x AVDD
Bias voltage of ADC inputs and DAC outputs.
Analog Ground Pin
Analog Power Supply Pin
Output Pin for Loop Filter of PLL Circuit
This pin should be connected to AVSS with one resistor and capacitor in series.
Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initialize the control register.
Chip Select Pin
Control Data Clock Pin
Control Data Input Pin
Audio Serial Data Input Pin
Audio Serial Data Output Pin
Frame Clock Pin
Audio Serial Data Clock Pin
Digital Power Supply Pin
Digital Ground Pin
X’tal Input Pin
External Master Clock Input Pin
X’tal Output Pin
Speaker Amp Positive Output Pin
Speaker Amp Negative Output Pin
Speaker Amp Power Supply Pin
Speaker Amp Ground Pin
ALC2 Input Pin
Mono Analog Output Pin
Mono Line Output Pin
Beep Signal Input Pin
IPGA (ALC1) Input Pin
Microphone Analog Output Pin
Microphone Input Pin (Mono Input)
MIC Power Supply Pin for Microphone
Note: All input pins except analog input pins (MIC, AIN, MIN and BEEP pins) should not be left floating.
MS0174-E-00
2002/09
-4-
ASAHI KASEI
[AK4536]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS, SVSS=0V; Note 1)
Parameter
Power Supplies:
Analog
Digital
Speaker-Amp
|AVSS – DVSS| (Note 2)
|AVSS – SVSS|
(Note 2)
Input Current, Any Pin Except Supplies
Analog Input Voltage
Digital Input Voltage
Ambient Temperature (powered applied)
Storage Temperature
Symbol
AVDD
DVDD
SVDD
∆GND1
∆GND2
IIN
VINA
VIND
Ta
Tstg
min
−0.3
−0.3
−0.3
−0.3
−0.3
−10
−65
max
4.6
4.6
4.6
0.3
0.3
±10
AVDD+0.3
DVDD+0.3
70
150
Units
V
V
V
V
V
mA
V
V
°C
°C
Note 1. All voltages with respect to ground.
Note 2. AVSS, DVSS and SVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS, SVSS=0V; Note 1)
Parameter
Power Supplies
Analog
(Note 3)
Digital
Speaker-Amp
Symbol
AVDD
DVDD
SVDD
min
2.4
2.4
2.4
typ
3.3
3.3
3.3
max
3.6
AVDD
3.6
Units
V
V
V
Note 1. All voltages with respect to ground
Note 3. The power up sequence between AVDD, DVDD and SVDD is not critical
It is recommended that DVDD and SVDD are the same voltage as AVDD in order to reduce the current at power
down mode.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0174-E-00
2002/09
-5-
ASAHI KASEI
[AK4536]
ANALOG CHRACTERISTICS
(Ta=25°C; AVDD, DVDD, SVDD=3.3V; AVSS=DVSS=SVSS=0V; fs=8kHz, BICK=64fs; Signal Frequency=1kHz;
16bit Data; Measurement frequency=20Hz ∼ 3.4kHz; EXT Slave Mode; unless otherwise specified)
min
typ
max
Units
Parameter
MIC Amplifier
Input Resistance
20
30
40
kΩ
Gain
(MGAIN bit = “0”)
0
dB
(MGAIN bit = “1”)
20
dB
MIC Power Supply: MPI pin
Output Voltage
(Note 4)
2.22
2.47
2.72
V
Output Current
1.25
mA
Input PGA Characteristics:
Input Resistance (Note 5)
5
10
15
kΩ
Step Size
0.1
0.5
0.9
dB
Gain Control Range
+27.5
dB
−8
ADC Analog Input Characteristics: MIC Gain=20dB, IPGA=0dB, ALC1=OFF, MIC à IPGA à ADC
Resolution
16
Bits
Input Voltage (MIC Gain=20dB,Note 6)
0.178
0.198
0.218
Vpp
70
80
dB
S/(N+D)
(−1dBFS) (Note 7)
77
85
dB
D-Range
(−60dBFS)
S/N
77
85
dB
DAC Characteristics:
Resolution
16
Bits
Mono Line Output Characteristics: RL=10kΩ, AOUT pin (DAC → AOUT)
1.78
1.98
2.18
Vpp
Output Voltage (Note 8)
75
85
dB
S/(N+D)
(0dBFS) (Note 7)
85
95
dB
D-Range
(-60dBFS)
85
95
dB
S/N
10
Load Resistance
kΩ
30
pF
Load Capacitance (Note 15)
Speaker-Amp Characteristics: RL=8Ω, BTL, MIN pin → SPP/SPN pin, ALC2=OFF
Output Voltage
SPKG = “0”
2.47
3.09
3.71
Vpp
(Note 9)
SPKG = “1”
3.20
4.00
4.80
Vpp
SPKG = “0”, 150mW Output
50
60
dB
S/(N+D)
SPKG = “1”, 250mW Output
20
50
dB
80
90
dB
S/N (Note 10)
Load Resistance
8
Ω
30
pF
Load Capacitance
BEEP Input: BEEP pin
1.98
Vpp
Maximum Input Voltage (Note 11)
14
20
26
Feedback Resistance
kΩ
Mono Input: MIN pin
2.18
Vpp
Maximum Input Voltage (Note 12)
12
24
36
Input Resistance (Note 13)
kΩ
Mono Output: MOUT pin (DAC→ MOUT)
1.78
1.98
2.18
Vpp
Output Voltage
(Note 14)
Load Resistance
10
kΩ
30
pF
Load Capacitance (Note 15)
MS0174-E-00
2002/09
-6-
ASAHI KASEI
Parameter
Power Supplies
Power Up (PDN = “H”)
All Circuit Power-up: (Note 16)
AVDD+DVDD
SVDD: Speaker-Amp Normal Operation
(SPPS bit = “1”, No Output)
Power Down (PDN = “L”) (Note 17)
AVDD+DVDD+SVDD
[AK4536]
min
typ
max
Units
10
15
mA
9
18
mA
10
200
µA
Note 4. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ)
Note 5. When IPGA Gain is changed, this typical value changes between 8kΩ and 11kΩ.
Note 6. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ)
Note 7. When a PLL reference clock is FCK pin in PLL Slave Mode, S/(N+D) is 60dB (typ).
Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)
Note 9. Input signal of MIN pin is 1.98Vpp.
Note 10. There are no relations with the setup of SPKG bit, and it is the same value.
Note 11. The maximum input voltage of the BEEP input shows output from AOUT.
Note 12. Maximum Input Voltage is proportional to AVDD voltage. Vin = 0.66 x AVDD (max)
Note 13. When ALC2 Gain is changed, this typical value changes between 22kΩ and 26kΩ.
Note 14. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)
Note 15. When the output pin drives a capacitive load, a resistor should be added in series between the output pin and
capacitive load.
Note 16. PLL Master Mode (X’tal = 12.288MHz) and PMMIC = PMADC = PMDAC = PMSPK = PMVCM = PMPLL =
PMXTL = PMAO = PMBP = M/S = “1”. And output current from MPI pin is 0mA. When the AK4536 is EXT
mode (PMPLL = PMXTL = M/S = “0”), “AVDD+DVDD” is typically 8mA.
Note 17. All digital input pins are fixed to DVDD or DVSS.
MS0174-E-00
2002/09
-7-
ASAHI KASEI
[AK4536]
FILTER CHRACTERISTICS
(Ta = 25°C; AVDD, DVDD, SVDD =2.4 ∼ 3.6V; fs=8kHz)
Parameter
Symbol
ADC Digital Filter (Decimation LPF):
PB
Passband
(Note 18) ±0.16dB
-0.66dB
−1.1dB
−6.9dB
Stopband
(Note 18)
SB
Passband Ripple
PR
Stopband Attenuation
SA
Group Delay
(Note 19)
GD
Group Delay Distortion
∆GD
ADC Digital Filter (HPF):
Frequency Response (Note 18) −3.0dB
FR
−0.5dB
−0.1dB
DAC Digital Filter:
Passband
(Note 18) ±0.12dB
PB
−6.2dB
Stopband
(Note 18)
SB
Passband Ripple
PR
Stopband Attenuation
SA
Group Delay
(Note 19)
GD
Group Delay Distortion
∆GD
DAC Digital Filter + Analog Filter:
Frequency Response: 0 ∼ 3.4kHz
FR
min
typ
max
Units
0
4.8
3.5
3.6
4.0
3.0
-
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
±0.1
68
17.1
0
-
1.25
3.56
8.14
-
Hz
Hz
Hz
0
4.4
4.0
3.6
-
16.9
0
kHz
kHz
kHz
dB
dB
1/fs
µs
±1.0
dB
±0.06
43
Note 18. The passband and stopband frequencies are proportional to fs (system sampling rate).
For example, ADC is PB=0.45*fs (@-1.1dB). A reference of frequency response is 1kHz.
Note 19. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the
16-bit data of a channel from the input register to the output register of the ADC. This time includes the group
delay of the HPF. For the DAC, this time is from setting the 16-bit data of a channel from the input register to the
output of analog signal.
DC CHRACTERISTICS
(Ta = 25°C; AVDD, DVDD, SVDD=2.4 ∼ 3.6V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
Input Voltage at AC Coupling
(Note 20)
High-Level Output Voltage
(Iout=−80µA)
Low-Level Output Voltage
(Iout= 80µA)
Input Leakage Current
Symbol
VIH
VIL
VAC
VOH
VOL
Iin
min
70%DVDD
50%DVDD
DVDD−0.4
-
typ
-
max
30%DVDD
0.4
±10
Units
V
V
Vpp
V
V
µA
Note 20. When AC coupled capacitor is connected to MCKI pin.
MS0174-E-00
2002/09
-8-
ASAHI KASEI
[AK4536]
SWITING CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD, SVDD=2.4 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
typ
max
PLL Master Mode (PLL Reference Clock = MCKI/XTI pin) (See Figure 3, Figure 4 and Figure 5)
Crystal Resonator Frequency
fCLK
11.2896
12.288
External Clock Frequency
fCLK
11.2896
12.288
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
AC Pulse Width (Note 23)
tACW
0.4/fCLK
FCK Frequency
fFCK
8
24
Pulse width High
tFCKH
tBCK
BICK Frequency (BCKO1-0 = “00”)
tBCK
1/16fFCK
(BCKO1-0 = “01”)
tBCK
1/32fFCK
(BCKO1-0 = “10”)
tBCK
1/64fFCK
BICK Duty
dBCK
50
0.5 x tBCK
tDBF
FCK “↑” to BICK “↑” (Note 21)
0.5 x tBCK
tDBF
FCK “↑” to BICK “↓” (Note 22)
80
tBSD
BICK “↑” to SDTO (BCKP = “0”)
80
tBSD
BICK “↓” to SDTO (BCKP = “1”)
60
tSDH
SDTI Hold Time
60
tSDS
SDTI Setup Time
Units
MHz
MHz
ns
ns
ns
kHz
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
ns
PLL Slave Mode (PLL Reference Clock = FCK pin) (See Figure 6, Figure 7, Figure 8 and Figure 9)
FCK Frequency
Pulse Width High
fFCK
tFCKH
7.35
tBCK-60
BICK Period
BICK Pulse Width Low
Pulse Width High
FCK “↑” to BICK “↑” (Note 21)
FCK “↑” to BICK “↓” (Note 22)
BICK “↑” to FCK “↑” (Note 21)
BICK “↓” to FCK “↑” (Note 22)
BICK “↑” to SDTO (BCKP = “0”)
BICK “↓” to SDTO (BCKP = “1”)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCKL
tBCKH
tFCKB
tFCKB
tBFCK
tBFCK
tBSD
tBSD
tSDH
tSDS
1/64fFCK
240
240
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
MS0174-E-00
8
26
1/fFCK-tBFCK
kHz
ns
1/16fFCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
80
80
60
60
2002/09
-9-
ASAHI KASEI
[AK4536]
Parameter
Symbol
min
typ
max
PLL Slave Mode (PLL Reference Clock = BICK pin) (See Figure 6, Figure 7, Figure 8 and Figure 9)
FCK Frequency
fFCK
7.35
26
Pulse width High
tFCKH
tBCK-60
1/fFCK-tBFCK
BICK Period (PLL2-0 = “001”)
tBCK
1/16fFCK
(PLL2-0 = “010”)
tBCK
1/32fFCK
(PLL2-0 = “011”)
tBCK
1/64fFCK
BICK Pulse Width Low
tBCKL
0.4 x tBCK
Pulse Width High
tBCKH
0.4 x tBCK
FCK “↑” to BICK “↑” (Note 21)
tFCKB
0.4 x tBCK
FCK “↑” to BICK “↓” (Note 22)
tFCKB
0.4 x tBCK
BICK “↑” to FCK “↑” (Note 21)
tBFCK
0.4 x tBCK
BICK “↓” to FCK “↑” (Note 22)
tBFCK
0.4 x tBCK
BICK “↑” to SDTO (BCKP = “0”)
tBSD
80
BICK “↓” to SDTO (BCKP = “1”)
tBSD
80
SDTI Hold Time
tSDH
60
SDTI Setup Time
tSDS
60
EXT Slave Mode (See Figure 10 and Figure 11)
MCKI Frequency: 256fs
512fs
1024fs
Pulse Width Low
Pulse Width High
AC Pulse Width (Note 23)
FCK Frequency (MCKI = 256fs or 512fs)
(MCKI = 1024fs)
Duty
BICK Period
BICK Pulse Width Low
Pulse Width High
FCK Edge to BICK “↑” ”
(Note 24)
BICK “↑” to FCK Edge
(Note 24)
FCK to SDTO (MSB) (Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
fCLK
fCLK
fCLK
tCLKL
tCLKH
tACW
fFCK
fFCK
duty
tBCK
tBCKL
tBCKH
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
0.4/fCLK
7.35
7.35
45
600
240
240
tFCKB
tBFCK
tFSD
tBSD
tSDH
tSDS
50
50
2.048
4.096
8.192
6.656
13.312
13.312
8
8
26
13
55
80
80
50
50
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 21. MSBS, BCKP bits = “00” or “11”
Note 22. MSBS, BCKP bits = “01” or “10”
Note 23. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to ground.
(Refer to Figure 3)
Note 24. BICK rising edge must not occur at the same time as FCK edge.
MS0174-E-00
2002/09
- 10 -
ASAHI KASEI
[AK4536]
Parameter
Symbol
min
Control Interface Timing:
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
150
50
tPD
tPDV
150
Reset Timing
PDN Pulse Width
PMADC “↑” to SDTO valid
(Note 25)
(Note 26)
typ
max
Units
ns
ns
ns
ns
ns
ns
ns
ns
1059
ns
1/fs
Note 25. The AK4536 can be reset by the PDN pin = “L”.
Note 26. This is the count of FCK “↑” from the PMADC bit = “1”.
MS0174-E-00
2002/09
- 11 -
ASAHI KASEI
[AK4536]
n Timing Diagram
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fFCK
FCK
50%DVDD
tFCKH
Figure 2. Clock Timing (PLL, Master mode)
1/fCLK
tACW
1000pF
MCKI Input
tACW
Measurement Point
100kΩ
AVSS
VAC
AVSS
Figure 3. MCKI AC Coupling Timing
MS0174-E-00
2002/09
- 12 -
ASAHI KASEI
[AK4536]
tFCKH
FCK
50%DVDD
tBCK
tDBF
dBCK
BICK
(BCKP = "0")
50%DVDD
BICK
(BCKP = "1")
50%DVDD
tBSD
SDTO
50%DVDD
MSB
tSDS
tSDH
VIH
SDTI
MSB
VIL
Figure 4. Audio Interface Timing (PLL, Master mode, MSBS = “0”)
tFCKH
FCK
50%DVDD
tBCK
tDBF
dBCK
BICK
(BCKP = "1")
50%DVDD
BICK
(BCKP = "0")
50%DVDD
tBSD
SDTO
MSB
tSDS
SDTI
50%DVDD
tSDH
MSB
VIH
VIL
Figure 5. Audio Interface Timing (PLL, Master mode, MSBS = “1”)
MS0174-E-00
2002/09
- 13 -
ASAHI KASEI
[AK4536]
1/fFCK
VIH
FCK
VIL
tFCKH
tBFCK
tBCK
VIH
BICK
(BCKP = "0")
VIL
tBCKH
tBCKL
VIH
BICK
(BCKP = "1")
VIL
Figure 6. Clock Timing (PLL, Slave mode, MSBS = 0)
tFCKH
VIH
FCK
VIL
tFCKB
VIH
BICK
VIL
(BCKP = "0")
VIH
BICK
(BCKP = "1")
VIL
tBSD
SDTO
MSB
tSDS
50%DVDD
tSDH
VIH
SDTI
MSB
VIL
Figure 7. Audio Interface Timing (PLL, Slave mode, MSBS = 0)
MS0174-E-00
2002/09
- 14 -
ASAHI KASEI
[AK4536]
1/fFCK
VIH
FCK
VIL
tFCKH
tBFCK
tBCK
VIH
BICK
(BCKP = "1")
VIL
tBCKH
tBCKL
VIH
BICK
(BCKP = "0")
VIL
Figure 8. Clock Timing (PLL, Slave mode, MSBS = 1)
tFCKH
VIH
FCK
VIL
tFCKB
VIH
BICK
VIL
(BCKP = "1")
VIH
BICK
(BCKP = "0")
VIL
tBSD
SDTO
MSB
tSDS
50%DVDD
tSDH
VIH
SDTI
MSB
VIL
Figure 9. Audio Interface Timing (PLL, Slave mode, MSBS = 1)
MS0174-E-00
2002/09
- 15 -
ASAHI KASEI
[AK4536]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fFCK
VIH
FCK
VIL
tFCKH
tFCKL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 10. Clock Timing (EXT, Slave mode)
VIH
FCK
VIL
tBFCK
tFCKB
VIH
BICK
VIL
tFSD
tBSD
SDTO
MSB
tSDS
50%DVDD
tSDH
VIH
SDTI
VIL
Figure 11. Audio Interface Timing (EXT, Slave mode)
MS0174-E-00
2002/09
- 16 -
ASAHI KASEI
[AK4536]
VIH
CSN
VIL
tCSS
tCCKL
tCCKH
VIH
CCLK
VIL
tCCK
tCDH
tCDS
VIH
CDTI
C1
C0
R/W
VIL
Figure 12. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
D2
D1
D0
VIL
Figure 13. WRITE Data Input Timing
VIH
CSN
VIL
tPDV
SDTO
50%DVDD
tPD
PDN
VIL
Figure 14. Power Down & Reset Timing
MS0174-E-00
2002/09
- 17 -
ASAHI KASEI
[AK4536]
OPERATION OVERVIEW
n Master Clock Source
The AK4536 requires a master clock (MCKI). This master clock is input to the AK4536 by connecting a X’tal oscillator to
XTI and XTO pins or by inputting an external CMOS-level clock to the XTI pin or by inputting an external clock that is
greater than 50% of the DVDD level to the XTI pin through a capacitor. When using a X’tal oscillator, there should be
capacitors between XTI/XTO pins and DVSS.
Master Clock
X’tal Oscillator
Status
PMXTL bit
Oscillator ON
1
Oscillator OFF
0
External Clock Direct Input (Figure 16)
Clock is input to MCKI pin.
0
MCKI pin is fixed to “L”.
0
MCKI pin is fixed to “H”.
0
MCKI pin is Hi-Z.
0
AC Coupling Input
(Figure 17)
Clock is input to MCKI pin.
1
Clock isn’t input to MCKI pin.
0
Table 1. Master Clock Status by PMXTL bit and MCKPD bit
(Figure 15)
MCKPD bit
0
1
0
0/1
0
1
0
1
(1) X’tal Oscillator
XTI
MCKPD="0"
C
25kΩ
PMXTL = "1"
C
XTO
AK4536
Figure 15. X’tal mode
- Note: The capacitor values depend on the X’tal oscillator used. (typ. 10 ∼ 30pF)
MS0174-E-00
2002/09
- 18 -
ASAHI KASEI
[AK4536]
(2) External Clock Direct Input
MCKI/XTI
External
Clock
MCKPD = "0"
25kΩ
PMXTL = "0"
XTO
AK4536
Figure 16. External Clock mode (Input: CMOS Level)
- Note: This clock level must not exceed DVDD level.
(3) AC Coupling Input
MCKI/XTI
External C
Clock
MCKPD = "0"
25kΩ
PMXTL = "1"
XTO
AK4536
Figure 17. External Clock mode (Input: ≥ 50%DVDD)
- Note: This clock level must not exceed DVDD level.
MS0174-E-00
2002/09
- 19 -
ASAHI KASEI
[AK4536]
n PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL2-0
and FS2-0 bits. The PLL lock time is shown in Table 3, whenever the AK4536 is supplied to a stable clocks after PLL is
powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes.
1) Select PLL/ EXT Mode
PMPLL bit
Mode
0
EXT Mode
1
PLL Mode
Table 2. Select PLL/EXT Mode
Default
2) Setting of PLL Mode
Mode
PLL2
bit
PLL1
bit
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
R and C of VCOC
pin
C[F]
R[Ω]
0
FCK pin
1fs
10k
470n
1
BICK pin
16fs
10k
4.7n
0
BICK pin
32fs
10k
4.7n
1
BICK pin
64fs
10k
4.7n
0
MCKI/XTI pin
11.2896MHz
10k
4.7n
1
MCKI/XTI pin
12.288MHz
10k
4.7n
0
MCKI/XTI pin
12MHz
10k
4.7n
1
N/A
N/A
Table 3. Setting of PLL Mode (*fs: Sampling Frequency)
PLL0
bit
PLL Reference
Clock Input Pin
Input
Frequency
PLL Lock
Time
(max)
160ms
2ms
2ms
2ms
40ms
40ms
40ms
-
Default
3) Setting of sampling frequency in PLL Mode.
When PLL2 bit is “1” (PLL reference clock input is XTI/MCKI pin), the sampling frequency is selected by FS2-0 bits as
defined in Table 4.
Mode
0
1
2
3
4
5
6
7
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
8kHz
Default
0
0
1
12kHz
0
1
0
16kHz
0
1
1
24kHz
1
0
0
N/A
1
0
1
11.025kHz
1
1
0
N/A
1
1
1
22.05kHz
Table 4. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL = “1”
When PLL2 bit is “0” (PLL reference clock input is FCK or BICK pin), the sampling frequency is selected by FS1-0
bits. (See Table 5). FS2 bit is ignored.
Mode
FS1 bit
FS0 bit
Sampling Frequency Range
0
0
0
Default
7.35kHz ≤ fs ≤ 10kHz
1
1
0
10kHz < fs ≤ 14kHz
0
2
1
14kHz < fs ≤ 20kHz
1
3
1
20kHz < fs ≤ 26kHz
Table 5. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL = “1”
MS0174-E-00
2002/09
- 20 -
ASAHI KASEI
[AK4536]
n PLL Unlock
1) PLL, Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, irregular frequency clocks are output from FCK and BICK pins after PMPLL bit = “0” à “1”. After that PLL
is unlocked, BICK and FCK pins output “L” for a moment. (See Table 6) Therefore a first period of FCK and BICK may
be irregular clock, but these clocks return to normal after a period of 1/fs.
BICK pin
FCK pin
Master Mode (M/S bit = “1”)
After that PMPLL “0” à “1”
PLL Unlock
Irregular clock output
“L” Output
Irregular clock output
“L” Output
Table 6. Clock Operation at Master & PLL Mode
PLL Lock
See Table 9
1fs Output
2) PLL, Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, ADC and DAC are output to abnormal data when the PLL is unlocked. For DAC, the output signal should be
muted by writing “0” to DACA and DACM bits in Addr=02H.
n Master Mode/Slave Mode
The M/S bit selects either master or slave modes. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4536 is power-down mode (PDN pin = “L”) and exits reset state, the AK4536 is slave mode. After exiting reset state,
the AK4536 goes master mode by changing M/S bit = “1”.
When the AK4536 is used by master mode, FCK and BICK pins are a floating state until M/S bit becomes “1”. FCK and
BICK pins of the AK4536 should be pulled-down or pulled-up by about 100kΩ resistor externally to avoid the floating
state.
M/S bit
Mode
0
Slave Mode
Default
1
Master Mode
Table 7. Select Master/Salve Mode
MS0174-E-00
2002/09
- 21 -
ASAHI KASEI
[AK4536]
n System Clock
There are the following three methods to interface with external devices. (See Table 8)
Mode
Pin
PLL
(PMPLL bit = “1”)
Master Mode (M/S bit = “1”)
MCKI/XTI
BICK
FCK
11.2896MHz/
16fs/32fs/64fs
fs
12MHz/
Output
Output
12.288MHz
Input
EXT
(PMPLL bit = “0”)
Slave Mode (M/S bit = “0”)
MCKI/XTI
BICK
GND
(MCKPD bit = “1”)
256fs/512fs/1024fs
Input
Table 8. Clock Operation
Don’t use (Note 27)
FCK
16fs/32fs/64fs
Input
fs
Input
≥ 32fs
Input
fs
Input
Note 27. If this mode is selected, the irregular clocks are output from FCK and BICK pins.
1) PLL, Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When the AK4536 is connected to X’tal oscillator or an external clock (11.2896MHz, 12MHz or 12.288MHz) is input to
MCKI pin, the BICK and FCK clocks are generated by an internal PLL circuit. The BICK is selected among 16fs, 32fs or
64fs, by BCKO1-0 bits. (See Table 9)
Audio interface format corresponds to Mode 0 (DSP Mode) only.
AK4536
DSP or µ P
XTO
MCKI/XTI
16fs, 32fs, 64fs
BICK
1fs
FCK
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 18. PLL & Master Mode
Mode
0
1
2
3
BCKO1 bit
BCKO0 bit
BICK Output Frequency
0
0
16fs
0
1
32fs
1
0
64fs
1
1
N/A
Table 9. Output Frequency of BICK at Master Mode
MS0174-E-00
Default
2002/09
- 22 -
ASAHI KASEI
[AK4536]
2) PLL, Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is input from BICK or FCK pins. The required clock to the AK4536 is generated by an internal
PLL circuit. Input frequency is selected by PLL2-0 bits. Sampling frequency corresponds to 7.35kHz ∼ 26kHz by changing
FS1-0 bits. (See Table 5)
Audio interface format corresponds to Mode 0 (DSP Mode) only.
AK4536
DSP or µP
XTO
MCKI/XTI
BICK
FCK
16fs, 32fs, 64fs
1fs
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 19. PLL & Slave Mode
The external clocks (BICK and FCK) should always be present whenever the ADC or DAC is in operation (PMADC bit =
“1” or PMDAC bit = “1”). If these clocks are not provided, the AK4536 may draw excess current and it is not possible to
operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and
DAC should be in the power-down mode (PMADC bit =PMDAC bit = “0”).
MS0174-E-00
2002/09
- 23 -
ASAHI KASEI
[AK4536]
3) EXT, Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4536 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit
is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI
(256fs, 512fs or 1024fs), FCK (fs) and BICK (32fs∼). The master clock (MCKI) should be synchronized with FCK. The
phase between these clocks does not matter. The frequency of MCLK is selected by FS1-0 bits. (See Table 10)
Mode
FS1 bit FS0 bit MCKI Input Frequency Sampling Frequency Range
0
0
0
256fs
7.35kHz ∼ 26kHz
1
0
1
1024fs
7.35kHz ∼ 13kHz
2
1
0
256fs
7.35kHz ∼ 26kHz
3
1
1
512fs
7.35kHz ∼ 26kHz
Table 10. MCKI Frequency at EXT, Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
* FS2 bit is ignored.
Default
Audio interface format corresponds to Mode 1, 2 or 3.
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
When the out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through AOUT amp at fs=8kHz is shown in Table 11.
S/N
(fs=8kHz, 20kHzLPF + A-weight)
256fs
83dB
512fs
93dB
1024fs
93dB
Table 11. Relationship between MCLK and S/N of AOUT
MCKI
The external clocks (MCKI, BICK and FCK) should always be present whenever the ADC or DAC is in operation
(PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4536 may draw excess current and it is
not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present,
the ADC and DAC should be in the power-down mode (PMADC bit = PMDAC bit = “0”).
In case of changing sampling frequency while DAC is normal operation, the change of sampling frequency should be done
after the input data is input to “0” or muted by DVOL7-0 bits.
AK4536
DSP or µP
XTO
256fs, 512fs or 1024fs
MCKI/XTI
BICK
FCK
MCLK
32fs, 64fs
1fs
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 20. EXT, Slave Mode
MS0174-E-00
2002/09
- 24 -
ASAHI KASEI
[AK4536]
n System Reset
Upon power-up, reset the AK4536 by bringing the PDN pin = “L”. This ensures that all internal registers reset to their
initial values.
The ADC enters an initialization cycle that starts when the PMADC bit is changed from “0” to “1”. The initialization cycle
time is 1059/fs, or [email protected]=8kHz. During the initialization cycle, the ADC digital data outputs of both channels are
forced to a 2's compliment, “0”. The ADC output reflects the analog input signal after the initialization cycle is complete.
The DAC does not require an initialization cycle.
n Audio Interface Format
Four types of data formats are available and are selected by setting the DIF1-0 bits. (See Table 13) In all modes, the serial
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. FCK and
BICK are output from AK4536 in master mode, but must be input to AK4536 in slave mode.
In Mode0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits.
When BCKP bit is “0”, SDTO data is output by rising edge of BICK, SDTI data is latched by falling edge of BICK.
When BCKP bit is “1”, SDTO data is output by falling edge of BICK, SDTI data is latched by rising edge of BICK.
MSB data position of SDTO and SDTI can be shifted by MSBS bit. The shifted period is a half of BICK.
MSBS bit BCKP bit
Data Input/Output Timing
0
0
Figure 21
0
1
Figure 23
1
0
Figure 22
1
1
Figure 24
Table 12. Relationship MSBS and BCKP bits between data I/O timing
In Mode 1-3, the SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the rising edge.
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, −1 at 16bit data is converted to −1 at 8-bit
data. And when the DAC playbacks this 8-bit data, −1 at 8-bit data will be converted to −256 at 16-bit data and this is a
large offset. This offset can be removed by adding the offset of 128 to 16-bit data before converting to 8-bit data.
Mode
DIF1
DIF0
SDTO (ADC)
SDTI (DAC)
BICK
0
0
0
DSP Mode
DSP Mode
≥ 16fs
1
2
3
0
1
1
1
0
1
MSB justified
MSB justified
≥ 32fs
MSB justified
MSB justified
≥ 32fs
I2S compatible I2S compatible
≥ 32fs
Table 13. Audio Interface Format
MS0174-E-00
Figure
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Default
2002/09
- 25 -
ASAHI KASEI
[AK4536]
FCK
15
0
1
8
2
8
9
10
11
12
13
14
15
0
1
8
2
8
9
10
11
12
13
14
15
0
BICK(16fs)
SDTO(o)
0
15 14
SDTI(i)
0
15 14
15
0
1
8
8
7
6
5
4
3
2
1
0
15 14
8
7
6
5
4
3
2
1
0
15 14
8
2
14
15
16
17
18
29
30
31
0
1
8
7
6
5
4
3
2
1
0
15
7
6
5
4
3
2
1
0
15
8
2
8
9
10
11
12
13
30
31
0
15
0
BICK(32fs)
SDTO(o)
15 14
SDTI(i)
15 14
8
2
1
0
2
1
0
Don’t Care
15 14
8
2
1
0
15 14
8
2
1
0
1/fs
Don’t Care
1/fs
15:MSB, 0:LSB
Figure 21. Mode 0 Timing (BCKP = “0”, MSBS = “0”)
FCK
15
0
1
8
2
8
9
10
11
12
13
14
15
0
1
8
2
8
9
10
11
12
13
14
BICK(16fs)
SDTO(o)
0
15 14
SDTI(i)
0
15 14
15
0
1
8
8
7
6
5
4
3
2
1
0
15 14
8
7
6
5
4
3
2
1
0
15 14
8
2
14
15
16
17
18
29
30
31
0
1
8
7
6
5
4
3
2
1
0
15
7
6
5
4
3
2
1
0
15
8
2
8
9
10
11
12
13
30
31
0
BICK(32fs)
SDTO(o)
15 14
SDTI(i)
15 14
8
2
1
0
2
1
0
Don’t Care
15 14
8
2
1
0
15 14
8
2
1
0
1/fs
Don’t Care
1/fs
15:MSB, 0:LSB
Figure 22. Mode 0 Timing (BCKP = “1”, MSBS = “0”)
MS0174-E-00
2002/09
- 26 -
ASAHI KASEI
[AK4536]
FCK
15
0
1
8
2
8
9
10
11
12
13
14
15
0
1
8
2
8
9
10
11
12
13
14
15
0
BICK(16fs)
SDTO(o)
0
15 14
SDTI(i)
0
15 14
15
0
1
8
8
7
6
5
4
3
2
1
0
15 14
8
7
6
5
4
3
2
1
0
15 14
8
2
14
15
16
17
18
29
30
31
0
1
8
7
6
5
4
3
2
1
0
15
7
6
5
4
3
2
1
0
15
8
2
8
9
10
11
12
13
30
31
0
15
0
BICK(32fs)
SDTO(o)
15 14
SDTI(i)
15 14
8
2
1
0
2
1
0
Don’t Care
15 14
8
2
1
0
15 14
8
2
1
0
1/fs
Don’t Care
1/fs
15:MSB, 0:LSB
Figure 23. Mode 0 Timing (BCKP = “0”, MSBS = “1”)
FCK
15
0
1
8
2
8
9
10
11
12
13
14
15
0
1
8
2
8
9
10
11
12
13
14
BICK(16fs)
SDTO(o)
0
15 14
SDTI(i)
0
15 14
15
0
1
8
8
7
6
5
4
3
2
1
0
15 14
8
7
6
5
4
3
2
1
0
15 14
8
2
14
15
16
17
18
29
30
31
0
1
8
7
6
5
4
3
2
1
0
15
7
6
5
4
3
2
1
0
15
8
2
8
9
10
11
12
13
30
31
0
BICK(32fs)
SDTO(o)
15 14
SDTI(i)
15 14
8
2
1
0
2
1
0
Don’t Care
15 14
8
2
1
0
15 14
8
2
1
0
1/fs
Don’t Care
1/fs
15:MSB, 0:LSB
Figure 24. Mode 0 Timing (BCKP = “1”, MSBS = “1”)
MS0174-E-00
2002/09
- 27 -
ASAHI KASEI
[AK4536]
FCK
0
1
2
3
8
9
10
11
12
13
14
15
0
1
2
3
8
9
10
11
12
13
14
15
0
1
BICK(32fs)
SDTO(o)
15 14 13
SDTI(i)
15 14 13
0
1
2
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
3
14
15
16
17
18
31
15
15
Don’t Care
0
1
2
3
14
15
16
17
18
31
0
1
BICK(64fs)
SDTO(o)
15 14 13
SDTI(i)
Don’t Care
15:MSB, 0:LSB
2
1
0
15
15 14
1
Don’t Care
0
Data
1/fs
Figure 25. Mode 1 Timing
FCK
0
1
2
8
9
10
11
12
13
14
15
0
1
2
8
9
10
11
12
13
14
15
0
1
BICK(32fs)
SDTO(o)
15 14
8
7
6
5
4
3
2
1
0
SDTI(I)
15 14
8
7
6
5
4
3
2
1
0
0
1
2
3
14
15
16
17
18
31
15
15
Don’t Care
0
1
2
3
14
14
15
16
17
18
31
0
1
BICK(64fs)
SDTO(o)
15 14 13
13 2
1
0
SDTI(i)
15 14 13
13 2
1
0
15
Don’t Care
Don’t Care
15
15:MSB, 0:LSB
Data
1/fs
Figure 26. Mode 2 Timing
MS0174-E-00
2002/09
- 28 -
ASAHI KASEI
[AK4536]
FCK
0
1
2
3
4
9
10
11
12
13
14
15
0
1
2
3
1
2
3
4
9
10
11
12
13
14
15
16
17
18
14
15
0
1
31
0
1
BICK(32fs)
SDTO(o)
15 14 13
SDTI(i)
15 14 13
0
1
2
3
4
7
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
14
15
16
17
18
31
0
4
BICK(64fs)
SDTO(o)
15 14 13
2
1
0
SDTI(i)
15 14 13
2
1
0
15:MSB, 0:LSB
Don’t Care
Don’t Care
Data
1/fs
Figure 27. Mode 3 Timing
n Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.25Hz (@fs=8kHz)
and scales with sampling rate (fs).
n MIC Gain Amplifier
AK4536 has a Gain Amplifier for Microphone input. This gain is 0dB or 20dB, selected by the MGAIN bit. The typical
input impedance is 30kΩ.
MGAIN bit
Input Gain
0
0dB
1
+20dB
Table 14. Input Gain
Default
n MIC Power
The MPI pin supplies power for the Microphone. This output voltage is typically 0.75 x AVDD and the maximum output
current is 1.25mA.
MS0174-E-00
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ASAHI KASEI
[AK4536]
n Manual Mode
The AK4536 becomes a manual mode at ALC1 bit = “0”. This mode is used in the case shown below.
1. After exiting reset state, set up the registers for the ALC1 operation (ZTM1-0, LMTH and etc)
2. When the registers for the ALC1 operation (Limiter period, Recovery period and etc) are changed.
For example; When the change of the sampling frequency.
3. When IPGA is used as a manual volume.
n MIC-ALC Operation
The ALC (Automatic Level Control) of MIC input is done by ALC1 block when ALC1 bit is “1”.
[1] ALC1 Limiter Operation
When the ALC1 limiter is enabled, and IPGA output exceeds the ALC1 limiter detection level (LMTH), the IPGA value is
attenuated by the amount defined in the ALC1 limiter ATT step (LMAT1-0 bits) automatically.
When the ZELM bit = “1”, the timeout period is set by the LTM1-0 bits. The operation for attenuation is done continuously
until the input signal level becomes LMTH or less. If the ALC1 bit does not change into “0” after completing the
attenuation, the attenuation operation repeats while the input signal level equals or exceeds LMTH.
When the ZELM bit = “0”, the timeout period is set by the ZTM1-0 bits. This enables the zero-crossing attenuation
function so that the IPGA value is attenuated at the zero-detect points of the waveform.
[2] ALC1 Recovery Operation
The ALC1 recovery refers to the amount of time that the AK4536 will allow a signal to exceed a predetermined limiting
value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits to define the wait period
used after completing an ALC1 limiter operation. If the input signal does not exceed the “ALC1 Recovery Waiting Counter
Reset Level”, the ALC1 recovery operation starts. The IPGA value increases automatically during this operation up to the
reference level (REF6-0 bits). The ALC1 recovery operation is done at a period set by the WTM1-0 bits. Zero crossing is
detected during WTM1-0 period, the ALC1 recovery operation waits WTM1-0 period and the next recovery operation
starts.
During the ALC1 recovery operation, when input signal level exceeds the ALC1 limiter detection level (LMTH), the
ALC1 recovery operation changes immediately into an ALC1 limiter operation.
In the case of “(Recovery waiting counter reset level) ≤ IPGA Output Level < Limiter detection level” during the ALC1
recovery operation, the wait timer for the ALC1 recovery operation is reset. Therefore, in the case of “(Recovery waiting
counter reset level) > IPGA Output Level”, the wait timer for the ALC1 recovery operation starts.
The ALC1 operation corresponds to the impulse noise. When the impulse noise is input, the ALC1 recovery operation
becomes faster than a normal recovery operation.
MS0174-E-00
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ASAHI KASEI
[AK4536]
[3] Example of ALC1 Operation
Table 15 shows the examples of the ALC1 setting.
fs=8kHz
Operation
-4dBFS
Don’t use
Enable
16ms
Register Name
Comment
LMTH
LTM1-0
ZELM
ZTM1-0
Limiter detection Level
Limiter operation period at ZELM = 1
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be the same data
00
16ms
as ZTM1-0 bits
Maximum gain at recovery operation
47H
+27.5dB
Gain of IPGA
47H
+27.5dB
Limiter ATT Step
00
1 step
Recovery GAIN Step
0
1 step
ALC1 Enable bit
1
Enable
Table 15. Examples of the ALC1 Setting
WTM1-0
REF6-0
IPGA6-0
LMAT1-0
RATT
ALC1
Data
1
00
0
00
fs=16kHz
Data
Operation
1
-4dBFS
00
Don’t use
0
Enable
01
16ms
01
16ms
47H
47H
00
0
1
+27.5dB
+27.5dB
1 step
1 step
Enable
The following registers should not be changed during the ALC1 operation. These bits should be changed, after the ALC1
operation is finished by ALC1 bit = “0” or PMMIN bit = “0”.
• LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms @ fs= 8kHz
Limiter and Recovery Step = 1
Maximum Gain = +27.5dB
Limiter Detection Level = -4dBFS
Manual Mode
ALC2 bit = “1” (default)
WR (ZTM1-0, WTM1-0, LTM1-0)
(1) Addr=06H, Data=00H
WR (REF6-0)
(2) Addr=08H, Data=47H
WR (IPGA6-0)
* The value of IPGA should be
(3) Addr=09H, Data=47H
the same or smaller than REF’s
WR (ALC1= “1”, LMAT1-0, RATT, LMTH, ZELM)
(4) Addr=07H, Data=61H
ALC1 Operation
Note : WR : Write
Figure 28. Registers set-up sequence at the ALC1 operation
MS0174-E-00
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ASAHI KASEI
[AK4536]
n Digital Output Volume
The AK4536 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVOL7-0 bits. The
volume is included in front of a DAC block, a input data of DAC is changed from +12 to –115dB with MUTE. This volume
has a soft transition function. It takes 1061/fs (=133ms @ fs = 8kHz) from 00H to FFH.
DVOL7-0
Gain
00H
+12.0dB
01H
+11.5dB
02H
+11.0dB
•
•
18H
0dB
Default
•
•
FDH
−114.5dB
FEH
−115.0dB
FFH
MUTE (−∞)
Table 16. Digital Output Volume Code Table
n BEEP Input
When the PMBP bit is set to “1”, the beep input is powered-up. And when the BEEPS bit is set to “1”, the input signal from
the BEEP pin is output to Speaker-Amp. When the BEEPA bit is set to “1”, the input signal from the BEEP pin is output to
the mono line output amplifier. The external resister Ri adjusts the signal level of BEEP input. The internal feedback
resistance is 20k ± 30%Ω.
Rf = 20kΩ
Ri
-
BEEP
+
Figure 7. Block Diagram of BEEP pin
MS0174-E-00
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ASAHI KASEI
[AK4536]
n Speaker Output
The output signal from DAC is input to the Speaker-amp via the ALC2 circuit. This Speaker-amp is a mono output
controlled by BTL and a gain of the Speaker-Amp is set by SPKG bit. When SPKG bit is “0”, output power is a maximum
of [email protected] and SVDD = 3.3V. When SPKG bit is “1”, output power is a maximum of [email protected] and SVDD =
3.3V.
Speaker blocks (MOUT, ALC2 and Speaker-amp) can be powered-up/down by controlling the PMSPK bit. When the
PMSPK bit is “0”, the MOUT, SPP and SPN pins are placed in a Hi-Z state.
When the PMSPK bit is “1” and SPPS bit is “0”, the Speaker-amp enters power-save-mode. In this mode, the SPP pin is
placed in a Hi-Z state and the SPN pin goes to SVDD/2 voltage. And then the Speaker output gradually changes to the
SVDD/2 voltage and this mode can reduce pop noise at power-up. When the AK4536 is powered-down, pop noise can be
also reduced by first entering power-save-mode.
PMSPK bit
SPPS bit
SPP pin
SPN pin
Hi-Z
Hi-Z
Hi-Z
SVDD/2
SVDD/2
Hi-Z
Figure 29. Power-up/Power-down Timing for Speaker-Amp
n MONO LINE OUTPUT (AOUT pin)
A signal of DAC is output from AOUT pin. When the DACA bi is “0”, this output is OFF and the AOUT pin is forced to
VCOM voltage. The load resistance is 10kΩ(min). When PMAO bit is “0”, the mono line output enters power-down and
the output is placed in a Hi-Z state.
MS0174-E-00
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ASAHI KASEI
[AK4536]
n SPK-ALC Operation
The ALC (Automatic Level Control) operation of speaker output is done by ALC2 block when ALC2 bit is “1”. Input
resistance of the ALC2 is 24kΩ (typ) and centered around VCOM voltage. The ALC2 level diagram is shown in Figure 30.
The limiter detection level is proportional to SVDD voltage. The output level is limited by the ALC2 circuit when the input
signal exceeds –5.2dBV ([email protected]=SVDD=3.3V). When a continuous signal of –5.2dBV or greater is input to
the ALC2 circuit, the change period of the ALC2 limiter operation is 250µs ([email protected]=8kHz) and the attenuation level is
0.5dB/step.
The ALC2 recovery operation uses zero crossings and gains of 1dB/step. The ALC2 recovery operation is done until the
input level of the Speaker-amp goes to –7.2dBV([email protected]=SVDD=3.3V). Maximum gain of the ALC2
recovery operation is +18dB.
When the input signal is between –5.2dBV and –7.2dBV, the ALC2 limiter or recovery operations are not done.
When the PMSPK bit changes from “0” to “1”, the initilization cycle (512/fs = 64ms @fs=8kHz at ROTM bit = “0”) starts.
The ALC2 is disabled during the initilization cycle and the ALC2 starts after completing the initilization cycle.
The ROTM bit is set during the PMSPK bit = “0”.
When the ALC2 is disable, a gain of the ALC2 block is fixed to –2dB. Therefore, a gain of internal speaker block is +4dB
(Full-differential output) at SPKG bit = “0”, and it is +6.24dB (Full-differential output) at SPKG bit = “1”.
Parameter
ALC2 Limiter operation
ALC2 Recovery operation
−5.2dBV
−7.2dBV
fs=8kHz
2/fs = 250µs
512/fs=64ms
fs=16kHz
2/fs = 125µs
512/fs=32ms
No
Yes (Timeout = Period Time)
Operation Start Level
Period
Zero-crossing Detection
ATT/GAIN
0.5dB step
1dB step
Table 17. Limiter /Recovery of ALC2 (ROTM bit = “0”)
FS-2.1dB = -5.2dBV
0.8dBV
0dBV
-3.1dBV
-3.1dBV
FS
+6.0dB
-2.1dB
-1.2dBV
+6.0dB
-5.2dBV
Full-differential
Single-ended
+3.9dB
-8dB
-10dBV
-11.1dBV
FS-12dB
+7.9dB
-15.1dBV
-15.1dBV
FS-4.1dB = -7.2dBV
+15.9dB
-8dB
-20dBV
-23.1dBV
-30dBV
DVOL
DAC
ALC2
SPK-AMP
Figure 30. Speaker-Amp Output Level Diagram (SVDD=3.3V, DVOL=−8.0dB, SPKG bit = “0”)
* FS = Full Scale
MS0174-E-00
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ASAHI KASEI
[AK4536]
n Serial Control Interface
Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface
consists of a 2-bit Chip address (Fixed to “10”), Read/Write (Fixed to “1”), Register address (MSB first, 5bits) and Control
data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling
edge. The clock speed of CCLK is 5MHz (max). The value of internal registers is initialized at PDN pin = “L”.
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A2 A0 D7 D6 D5 D4 D3 D2 D1 D0
“1” “0” “1”
C1-C2:
R/W:
A4-A0:
D7-D0:
Chip Address (C1 = “1”, C0 = “0”); Fixed to “10”
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
Register Address
Control data
Figure 31. Serial Control I/F Timing
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ASAHI KASEI
[AK4536]
n Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Input PGA Control
Digital Volume Control
D7
0
0
SPPS
0
0
0
0
0
0
0
DVOL7
D6
PMVCM
0
BEEPS
0
PLL2
0
ROTM
ALC2
REF6
IPGA6
DVOL6
D5
PMBP
0
ALC2S
0
PLL1
0
ZTM1
ALC1
REF5
IPGA5
DVOL5
D4
PMSPK
0
DACA
0
PLL0
MSBS
ZTM0
ZELM
REF4
IPGA4
DVOL4
D3
PMAO
M/S
DACM
SPKG
BCKO1
BCKP
WTM1
LMAT1
REF3
IPGA3
DVOL3
D2
PMDAC
MCKPD
MPWR
BEEPA
BCKO0
FS2
WTM0
LMAT0
REF2
IPGA2
DVOL2
D1
PMMIC
PMXTL
MICAD
ALC1M
DIF1
FS1
LTM1
RATT
REF1
IPGA1
DVOL1
D0
PMADC
PMPLL
MGAIN
ALC1A
DIF0
FS0
LTM0
LMTH
REF0
IPGA0
DVOL0
The PDN = “L” resets the registers to their default values.
Note: Unused bits must contain a “0” value.
Note: Only write to address 00H to 0AH.
MS0174-E-00
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ASAHI KASEI
[AK4536]
n Register Definitions
Addr
00H
Register Name
Power Management 1
Default
D7
0
0
D6
PMVCM
0
D5
PMBP
0
D4
PMSPK
0
D3
PMAO
0
D2
PMDAC
0
D1
PMMIC
0
D0
PMADC
0
PMADC: ADC Block Power Control
0: Power down (Default)
1: Power up
When the PMADC bit changes from “0” to “1”, the initialization cycle ([email protected]) starts. After
initializing, digital data of the ADC is output.
PMMIC: MIC In Block (MIC-Amp and ALC1) Power Control
0: Power down (Default)
1: Power up
PMDAC: DAC Block Power Control
0: Power down (Default)
1: Power up
PMAO: Mono Line Out Power Control
0: Power down (Default)
1: Power up
PMSPK: Speaker Block Power Control
0: Power down (Default)
1: Power up
PMBP: BEEP In Power Control
0: Power down (Default)
1: Power up
PMVCM: VCOM Block Power Control
0: Power down (Default)
1: Power up
Each block can be powered-down respectively by writing “0” in each bit. When the PDN pin is “L”, all blocks are
powered-down.
When PMPLL and PMXTL bits and all bits in 00H address are “0”, all blocks are powered-down. The register values
remain unchanged.
When any of the blocks are powered-up, the PMVCM bit must be set to “1”. When PMPLL and PMXTL bits and all
bits in 00H address are “0”, PMVCM bit can write to “0”.
When BEEP signal is output from Speaker-Amp (Signal path: BEEP pin à SPP/SPN pins) or Mono Lineout-Amp
(Signal path: BEEP pin à AOUT pin) only, the clocks may not be present. When ADC, DAC, ALC1 or ALC2 is in
operation, the clocks must always be present.
MS0174-E-00
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ASAHI KASEI
Addr
01H
Register Name
Power Management 2
Default
[AK4536]
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
M/S
0
D2
MCKPD
1
D1
PMXTL
0
D0
PMPLL
0
PMPLL: PLL Block Power Control Select
0: PLL is Power down and External is selected. (Default)
1: PLL is Power up and PLL Mode is selected.
PMXTL: X’tal Oscillation Block Power Control
0: Power down (Default)
1: Power up
MCKPD: MCKI pin pull down control
0: Master Clock input enable
1: Pull down by 25kΩ (Default)
M/S: Select Master / Slave Mode
0: Slave Mode (Default)
1: Master Mode
MS0174-E-00
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ASAHI KASEI
Addr
02H
Register Name
Signal Select 1
Default
[AK4536]
D7
SPPS
0
D6
BEEPS
0
D5
ALC2S
0
D4
DACA
0
D3
DACM
0
D2
MPWR
0
D1
MICAD
0
D0
MGAIN
1
MGAIN: 1st MIC-amp Gain control
0: 0dB
1: +20dB (Default)
MICAD: Switch Control from MIC In to ADC.
0: OFF (Default)
1: ON
When MICAD bit is “1”, the ALC1 output signal is input to ADC.
MPWR: Power Supply Control for Microphone
0: OFF (Default)
1: ON
When PMMIC bit is “1”, MPWR bit is enabled.
DACM: Switch Control from DAC to mono amp.
0: OFF (Default)
1: ON
When PMSPK bit is “1”, DACM bit is enabled. When PMSPK bit is “0”, MOUT pin is Hi-Z state.
DACA:
Switch Control from DAC to mono line amp
0: OFF (Default)
1: ON
When PMAO bit is “1”, DACA bit is enabled. When PMAO bit is “0”, the AOUT pin goes Hi-Z state.
ALC2S: ALC2 output to Speaker-Amp Enable
0: OFF (Default)
1: ON
When ALC2S bit is “1”, the ALC2 output signal is input to Speaker-Amp.
BEEPS: BEEP pin to Speaker-Amp Enable
0: OFF (Default)
1: ON
When BEEPS bit is “1”, the beep signal is input to Speaker-Amp.
SPPS: Speaker-amp Power-Save-Mode
0: Power Save Mode (Default)
1: Normal Operation
When SPPS bit is “1”, the Speaker-amp is in power-save-mode and the SPP pin becomes Hi-z and SPN pin is
set to SVDD/2 voltage. When the PMSPK bit = “1”, this bit is valid. After the PDN pin changes from “L” to
“H”, the PMSPK bit is “0”, which powers down Speaker-amp.
MS0174-E-00
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ASAHI KASEI
Addr
03H
Register Name
Signal Select 2
Default
[AK4536]
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
SPKG
0
D2
BEEPA
0
D1
ALC1M
0
D0
ALC1A
0
ALC1A:
Switch Control from ALC1 output signal to mono line output amp.
0: OFF (Default)
1: ON
When PMAO bit is “1”, ALC1A bit is enabled. When PMAO bit is “0”, the AOUT pin goes Hi-Z state.
ALC1M:
Switch Control from ALC1 output signal to mono amp.
0: OFF (Default)
1: ON
When PMSPK bit is “1”, ALC1M is enabled. When PMSPK bit is “0”, the MOUT pin goes Hi-Z state.
BEEPA:
Switch Control from beep signal to mono line output amp.
0: OFF (Default)
1: ON
When PMAO bit is “1”, BEEPA is enabled. When PMAO bit is “0”, the AOUT pin goes Hi-Z state.
SPKG:
Select Speaker-Amp Output Gain
0: 0dB (Default)
1: +2.24dB
ALC1M
IPGA
ALC2S
DACM
MIX
ALC2
SPK
DAC
BEEPS
BEEP
ALC1A
DACA
AOUT
BEEPA
Figure 32. Speaker and Mono Lineout-Amps switch control
MS0174-E-00
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ASAHI KASEI
Addr
04H
[AK4536]
Register Name
Mode Control 1
Default
DIF1-0:
D7
0
0
D6
PLL2
0
D5
PLL1
0
D4
PLL0
0
D3
BCKO1
0
D2
BCKO0
0
D1
DIF1
1
D0
DIF0
0
Audio Interface Format (See Table 18)
Mode
DIF1 bit
DIF0 bit
SDTO (ADC)
SDTI (DAC)
BICK
0
0
0
DSP Mode
DSP Mode
≥ 16fs
1
2
3
0
1
1
1
0
1
MSB justified
LSB justified
≥ 32fs
MSB justified
MSB justified
≥ 32fs
I2S compatible I2S compatible
≥ 32fs
Table 18. Audio Interface Format
Figure
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Default
BCKO1-0: Select BICK frequency (See Table 19)
Mode
0
1
2
3
PLL2-0:
BCKO1 bit
BCKO0 bit
BICK Frequency
0
0
16fs
Default
0
1
32fs
1
0
64fs
1
1
N/A
Table 19. Output Frequency of BICK at Master Mode
Select input frequency at PLL mode (See Table 20)
Mode
0
1
2
3
4
5
6
7
PLL2 bit
0
0
0
0
1
1
1
1
PLL1 bit PLL0 bit PLL Reference Clock Input
Input Frequency
0
0
FCK pin
1fs
0
1
BICK pin
16fs
1
0
BICK pin
32fs
1
1
BICK pin
64fs
0
0
MCKI/XTI pin
11.2896MHz
0
1
MCKI/XTI pin
12.288MHz
1
0
MCKI/XTI pin
12MHz
1
1
N/A
N/A
Table 20. Setting of PLL Mode (*fs: Sampling Frequency)
MS0174-E-00
Default
2002/09
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ASAHI KASEI
Addr
05H
[AK4536]
Register Name
Mode Control 2
Default
D7
0
0
D6
0
0
D5
0
0
D4
MSBS
0
D3
BCKP
0
D2
FS2
0
D1
FS1
0
D0
FS0
0
FS2-0: Setting of Sampling Frequency (See Table 21 and Table 22) and MCKI Frequency (See Table 23)
These bits are selected to sampling frequency at PLL mode and MCKI frequency at EXT mode.
Mode
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
0
8kHz
1
0
0
1
12kHz
2
0
1
0
16kHz
3
0
1
1
24kHz
4
1
0
0
N/A
5
1
0
1
11.025kHz
6
1
1
0
N/A
7
1
1
1
22.05kHz
Table 21. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL = “1”
Default
Mode
FS1 bit
FS0 bit
Sampling Frequency Range
0
0
0
Default
7.35kHz ≤ fs ≤ 10kHz
1
1
0
10kHz < fs ≤ 14kHz
0
2
1
14kHz < fs ≤ 20kHz
1
3
1
20kHz < fs ≤ 26kHz
Table 22. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL = “1”
* FS2 bit is ignored.
Mode
FS1 bit FS0 bit MCKI Input Frequency
Sampling Frequency Range
0
0
0
256fs
7.35kHz ∼ 26kHz
1
0
1
1024fs
7.35kHz ∼ 13kHz
2
1
0
256fs
7.35kHz ∼ 26kHz
3
1
1
512fs
7.35kHz ∼ 26kHz
Table 23. MCKI Frequency at EXT, Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
* FS2 bit is ignored.
Default
BCKP, MSBS: “00” (Default) (See Table 26)
MSBS bit BCKP bit
Data Input/Output Timing
0
0
Figure 21
Default
0
1
Figure 23
1
0
Figure 22
1
1
Figure 24
Table 24. Relation between MSBS, BCKP bits and data I/O timing
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ASAHI KASEI
Addr
06H
[AK4536]
Register Name
Timer Select
Default
D7
0
0
D6
ROTM
0
D5
ZTM1
0
D4
ZTM0
0
D3
WTM1
0
D2
WTM0
0
D1
LTM1
0
D0
LTM0
0
LTM1-0: ALC1 limiter operation period at zero crossing disable (ZELM bit = “1”) (see Table 25)
The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is done by
the period specified by the LTM1-0 bits. Default is “00” (0.5/fs).
ALC1 Limiter Operation Period
8kHz
16kHz
0
0
0.5/fs
Default
63µs
31µs
0
1
1/fs
125µs
63µs
1
0
2/fs
250µs
125µs
1
1
4/fs
500µs
250µs
Table 25. ALC1 Limiter Operation Period at zero crossing disable (ZELM bit=“1”)
LTM1 bit
LTM0 bit
WTM1-0: ALC1 Recovery Waiting Period (see Table 26)
A period of recovery operation when any limiter operation does not occur during the ALC1 operation.
Default is “00” (128/fs).
ALC1 Recovery Operation Waiting Period
8kHz
16kHz
0
128/fs
16ms
8ms
1
256/fs
32ms
16ms
0
512/fs
64ms
32ms
1
1024/fs
128ms
64ms
Table 26. ALC1 Recovery Operation Waiting Period
WTM1 bit
0
0
1
1
WTM0 bit
Default
ZTM1-0: ALC1 Zero crossing timeout Period (see Table 27)
When the IPGA perform zero crossing or timeout, the IPGA value is changed by the µP WRITE operation,
ALC1 recovery operation or ALC1 limiter operation (ZELM bit = “0”). Default is “00” (128/fs).
ZTM1 bit
0
0
1
1
ROTM:
Zero Crossing Timeout Period
8kHz
16kHz
0
128/fs
16ms
8ms
1
256/fs
32ms
16ms
0
512/fs
64ms
32ms
1
1024/fs
128ms
64ms
Table 27. Zero Crossing Timeout Period
ZTM0 bit
Default
Period time for ALC2 Recovery operation, ALC2 Zero Crossing Timeout and ALC2 initializing cycle.
0: 512/fs (Default)
1: 1024/fs
The ROTM bit is set during the PMSPK bit = “0”.
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ASAHI KASEI
Addr
07H
[AK4536]
Register Name
ALC Mode Control 1
Default
LMTH:
D6
ALC2
1
D5
ALC1
0
D4
ZELM
0
D3
LMAT1
0
D2
LMAT0
0
D1
RATT
0
D0
LMTH
0
ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (see Table 28 )
The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about ±2dB.
Default is “0”.
LMTH bit
0
1
RATT:
D7
0
0
ALC1 Limiter Detection Level
ALC1 Recovery Waiting Counter Reset Level
ADC Input ≥ −6.0dBFS
−6.0dBFS > ADC Input ≥ −8.0dBFS
ADC Input ≥ −4.0dBFS
−4.0dBFS > ADC Input ≥ −6.0dBFS
Table 28. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
Default
ALC1 Recovery GAIN Step (see Table 29)
During the ALC1 recovery operation, the number of steps changed from the current IPGA value is set. For
example, when the current IPGA value is 30H and RATT bit = “1” is set, the IPGA changes to 32H by the
ALC1 recovery operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value
exceeds the reference level (REF6-0 bits), the IPGA value does not increase.
RATT bit
GAIN STEP
0
1
Default
1
2
Table 29. ALC1 Recovery Gain Step Setting
LMAT1-0: ALC1 Limiter ATT Step (see Table 30)
During the ALC1 limiter operation, when IPGA output signal exceeds the ALC1 limiter detection level set by
LMTH, the number of steps attenuated from the current IPGA value is set. For example, when the current IPGA
value is 47H and the LMAT1-0 bits = “11”, the IPGA transition to 43H when the ALC1 limiter operation starts,
resulting in the input signal level being attenuated by 2dB (=0.5dB x 4). When the attenuation value exceeds
IPGA = “00” (−8dB), it clips to “00”.
LMAT1 bit LMAT0 bit
ATT STEP
0
0
1
0
1
2
1
0
3
1
1
4
Table 30. ALC1 Limiter ATT Step Setting
Default
ZELM:
Enable zero crossing detection at ALC1 Limiter operation
0: Enable (Default)
1: Disable
When the ZELM bit = “0”, the IPGA of each L/R channel perform a zero crossing or timeout independently and
the IPGA value is changed by the ALC1 operation. The zero crossing timeout is the same as the ALC1 recovery
operation. When the ZELM bit = “1”, the IPGA value is changed immediately.
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ASAHI KASEI
[AK4536]
ALC1: ALC1 Enable Flag
0: ALC1 Disable (Default)
1: ALC1 Enable
When ALC1 bit is “1”, the ALC1 operation is enabled.
ALC2: ALC2 Enable Flag
0: ALC2 Disable
1: ALC2 Enable (Default)
After completing the initializing cycle (512/fs = 64ms @fs=8kHz at ROTM bit = “0”), the ALC2 operation is
enabled. When the PMSPK bit changes from “0” to “1” or PDN pin changes from “L” to “H”, the initilization
cycle starts.
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ASAHI KASEI
Addr
08H
[AK4536]
Register Name
ALC Mode Control 2
Default
D7
0
0
D6
REF6
0
D5
REF5
1
D4
REF4
1
D3
REF3
0
D2
REF2
1
D1
REF1
1
D0
REF0
0
REF6-0: Reference value at ALC1 Recovery Operation (see Table 31)
During the ALC1 recovery operation, if the IPGA value exceeds the setting reference value by gain operation,
then the IPGA does not become larger than the reference value. For example, when REF7-0 = “30H”, RATT =
2step, IPGA = 2FH, even if the input signal does not exceed the “ALC1 Recovery Waiting Counter Reset
Level”, the IPGA does not change to 2FH + 2step = 31H, and keeps 30H. Default is “36H”.
DATA (HEX)
GAIN (dB)
STEP
47
+27.5
46
+27.0
45
+26.5
•
•
36
+19.0
Default
•
•
10
+0.0
•
•
0.5dB
06
−5.0
05
−5.5
04
−6.0
03
−6.5
02
−7.0
01
−7.5
00
−8.0
Table 31. Setting Reference Value at ALC1 Recovery Operation
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ASAHI KASEI
Addr
09H
Register Name
Input PGA Control
Default
[AK4536]
D7
0
0
D6
IPGA6
0
D5
IPGA5
0
D4
IPGA4
1
D3
IPGA3
0
D2
IPGA2
0
D1
IPGA1
0
D0
IPGA0
0
IPGA6-0: Input Analog PGA (see Table 32)
Default: “10H” (0dB)
During the ALC1 operation, the writing value in IPGA6-0 bits is ignored.
In a manual mode, IPGA can be set to any values in Table 32.The ZTM1-0 bits set zero crossing timeout period
when IPGA value is changed. When the control register is written from the µP, the zero crossing counter is reset
and its counter starts. When the signal zero crossing or zero crossing timeout, the written value from the µP
becomes valid.
DATA (HEX)
GAIN (dB)
STEP
47
+27.5
46
+27.0
45
+26.5
•
•
36
+19.0
•
•
10
+0.0
•
•
0.5dB
06
−5.0
05
−5.5
04
−6.0
03
−6.5
02
−7.0
01
−7.5
00
−8.0
Table 32. Input Gain Setting
Addr
0AH
Register Name
Digital Volume Control
Default
D7
DVOL7
0
D6
DVOL6
0
D5
DVOL5
0
D4
DVOL4
1
Default
D3
DVOL3
1
D2
DVOL2
0
D1
DVOL1
0
D0
DVOL0
0
DVOL7-0: Output Digital Volume (see Table 33)
The AK4536 has a digital output volume (256 levels, 0.5dB step, Mute). The gain can be set by the DVOL7-0
bits. The volume is included in front of a DAC block, a input data of DAC is changed from +12 to –115dB with
MUTE. This volume has a soft transition function. It takes 1061/fs (=133ms @ fs = 8kHz) from 00H to FFH.
DVOL7-0
Gain
00H
+12.0dB
01H
+11.5dB
02H
+11.0dB
•
•
18H
0dB
Default
•
•
FDH
−114.5dB
FEH
−115.0dB
FFH
MUTE (−∞)
Table 33. Digital Volume Code Table
MS0174-E-00
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ASAHI KASEI
[AK4536]
SYSTEM DESIGN
Figure 33 shows the system connection diagram. An evaluation board [AKD4536] is available which demonstrates the
optimum layout, power supply arrangements and measurement results.
C
10µ
0.1µ
+
4.7n 10k
2.4∼3.6V
1 VCOM
1µ
AOUT 23
MOUT 22
BEEP 24
AIN 25
R
MIN 21
2 AVSS
SVSS 20
3 AVDD
SVDD 19
+
0.1µ
4 VCOC
10µ
SPN 18
Top View
5 PDN
SPP 17
6 CSN
XTO 16
Analog Supply
2.4∼3.6V
8Ω (Speaker)
C
13 DVDD
12 BICK
11 FCK
9 SDTI
10 SDTO
MCKI/XTI 15
8 CDTI
7 CCLK
C
14 DVSS
0.1µ
MIC 27
MPI 28
Analog Supply
+
2.2µ
C
1µ
MICOUT 26
1µ
2.2k
0.1µ
10
+
10µ
DSP or µP
Figure 33. Typical Connection Diagram
Notes:
- AVSS, DVSS and SVSS of the AK4536 should be distributed separately from the ground of external controllers.
- All digital input pins except pull-down pin should not be left floating.
- Value of R and C in Figure 33 should depend on system.
- When the AK4536 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed.
- When the AK4536 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 34.
Mode
PLL2
bit
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
Rp and Cp of
VCOC pin
Cp[F]
Rp[Ω]
0
0
FCK pin
1fs
10k
470n
0
1
BICK pin
16fs
10k
4.7n
1
0
BICK pin
32fs
10k
4.7n
1
1
BICK pin
64fs
10k
4.7n
0
0
MCKI/XTI pin
11.2896MHz
10k
4.7n
0
1
MCKI/XTI pin
12.288MHz
10k
4.7n
1
0
MCKI/XTI pin
12MHz
10k
4.7n
1
1
N/A
N/A
Table 34. Setting of PLL Mode (*fs: Sampling Frequency)
PLL1
bit
PLL0
bit
PLL Reference
Clock Input Pin
MS0174-E-00
Input
Frequency
2002/09
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ASAHI KASEI
[AK4536]
1. Grounding and Power Supply Decoupling
The AK4534 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and SVDD are
usually supplied from the system’s analog supply. If AVDD, DVDD and SVDD are supplied separately, the correct power
up sequence should be observed. AVSS, DVSS and SVSS of the AK4536 should be connected to the analog ground plane.
System analog ground and digital ground should be connected together near to where the supplies are brought onto the
printed circuit board. Decoupling capacitors should be as near to the AK4536 as possible, with the small value ceramic
capacitor being the nearest.
2. Voltage Reference
VCOM is a signal ground of this chip. A 2.2µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor attached to
the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All
signals, especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted coupling into
the AK4536.
3. Analog Inputs
The Mic and Beep inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp for the Mic
input and 0.6 x AVDD Vpp for the Beep input, centered around the internal common voltage (approx. 0.45 x AVDD).
Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2πRC). The AK4536 can accept
input voltages from AVSS to AVDD.
4. Analog Outputs
The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and
a negative full scale for 8000H(@16bit). Mono output from the MOUT pin and Mono Line Output from the AOUT pin are
centered at 0.45 x AVDD (typ). The Speaker-Amp output is centered at SVDD/2.
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ASAHI KASEI
[AK4536]
CONTROL SEQUENCE
n Clock Set up
When ADC, DAC, ALC1 and ALC2 are used, the clocks must be supplied.
1. When X'tal is used in PLL & Master mode.
Example:
: Audio I/F Format: DSP Mode, BCKP = MSBS = “0”
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode : 11.2896MHz
Sampling Frequency:8kHz
Power Supply
(1)
PDN pin
(2)
(1) Power Supply & PDN pin = “L” à “H”
(3)
PMVCM bit
(Addr:00H, D6)
(2)Addr:01H, Data:0CH
Addr:04H, Data:48H
Addr:05H, Data:00H
(4)
MCKPD bit
(Addr:01H, D2)
PMXTL bit
(Addr:01H, D1)
(5)
20ms(typ)
(3)Addr:00H, Data:40H
PMPLL bit
(Addr:01H, D0)
BICK, FCK
40msec(max)
(6)
(4)Addr:01H, Data:0BH
Output
(7)
1msec(max)
BICK and FCK output
Figure 34. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin = “L” à “H”
“L” time (1) of 150ns or more is needed to reset the AK4536.
(2) DIF1-0, PLL2-0, FS2-0, BCKO1-0, MSBS, BCKP and M/S bits should be set during this period.
(3) Power UpVCOM: PMVCM bit = “0” à “1”
VCOM should first be powered up before the other block operates.
(4) Release the pulled-down of the XTI pin: MCKPD bit = “1” → “0”
Power Up X’tal: PMXTL bit = “0” → “1”
Power Up the PLL: PMPLL bit = “0” → “1”
(5) It takes X’tal oscillator 20ms(typ) to be stable after PMXTL bit=“1”. This time depends on X’tal. PLL lock time
is 40ms(max) after PMPLL bit changes from “0” to “1”.
(6) The AK4536 starts to output the FCK and BICK clocks after the PLL becomes stable. The normal operation of
the block which a clock is necessary for becomes possible.
(7) The irregular frequencies are output from FCK and BICK pins in this section.
MS0174-E-00
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ASAHI KASEI
[AK4536]
2. When an external master clock is used in PLL & Master mode.
Example:
Audio I/F Format: DSP Mode, BCKP = MSBS = “0”
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKI pin: CMOS Level
Sampling Frequency:8kHz
Power Supply
(1)
PDN pin
(2)
(3)
PMVCM bit
(1) Power Supply & PDN pin = “L” à “H”
(Addr:00H,D6)
(4)
MCKPD bit
(Addr:01H,D2)
(2)Addr:01H, Data:0CH
Addr:04H, Data:48H
Addr:05H, Data:00H
(5)
PMXTL bit
(Addr:01H,D0)
"L" or "H"
"L"
PMPLL bit
(Addr:01H,D5)
(3)Addr:00H, Data:40H
(6)
MCKI
Input
(4)Addr:01H, Data:09H
M/S bit
(Addr:01H,D3)
40msec(max)
(7)
BICK, FCK
BICK and FCK output
Output
(8)
1msec(max)
Figure 35. Clock Set Up Sequence (2)
<Example>
(1) After Power Up, PDN pin “L” à “H”
“L” time (1) of 150ns or more is needed to reset the AK4536.
(2) DIF1-0, PLL2-0, FS2-0, BCKO1-0, MSBS, BCKP and M/S bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” à “1”
VCOM should first be powered up before the other block operates.
(4) Release the pulled-down of the XTI pin: MCKPD bit = “1” → “0”
Power Down X’al: PMXTL bit = “0”
(5) When MCKI pin is input by AC coupling: PMXTL bit = “1”
When MCKI pin is input by CMOS Level: PMXTL bit = “0”
(6) When PMPLL bit changes from “0” to “1”, the PLL starts after the clocks is supplied to MCKI pin. The PLL lock
time is 40ms(max).
(7) The AK4536 starts to output the FCK and BICK clocks after the PLL becomes stable. The normal operation of the
block which a clock is necessary for becomes possible.
(8) The irregular frequencies are output from FCK and BICK pins in this section.
MS0174-E-00
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ASAHI KASEI
[AK4536]
3. When the external clocks (FCK and BICK pins) is used in PLL & Slave mode.
Power Supply
(1)
Example:
PDN pin
(2)
Audio I/F Format : DSP Mode, BCKP = MSBS = “0”
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 8kHz
(3)
PMVCM bit
(Addr:00H,D6)
MCKPD bit
4fs
(1)ofPower Supply & PDN pin = “L” à “H”
(4) "H"
(Addr:01H,D2)
PMXTL bit
(Addr:01H,D1)
(2) Addr:04H, Data:30H
Addr:05H, Data:00H
(4) "L"
PMPLL bit
(Addr:01H,D0)
(3) Addr:00H, Data:40H
FCK, BICK
Input
(5)
(4) Addr:01H, Data:05H
Internal Clock
(6)
BICK and FCK input
Figure 36. Clock Set Up Sequence (3)
<Example>
(1) After Power Up, PDN pin “L” à “H”
“L” time(1) of 150ns or more is needed to reset the AK4536.
(2) DIF1-0, FS2-0, PLL2-0, MSBS and BCKP bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” à “1”
VCOM should first be powered up before the other block operates.
(4) Pull down the XTI pin: MCKPD bit = “1”
Power Down X’tal: PMXTL bit = “0”
(5) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (FCK or BICK pin) is supplied.
PLL lock time is 160ms(max) when FCK is a PLL reference clock. And PLL lock time is 2ms(max) when BICK
is a PLL reference clock.
(6) The AK4536 starts to output the FCK and BICK clocks after the PLL becomes stable. The normal operation of the
block which a clock is necessary for becomes possible.
MS0174-E-00
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ASAHI KASEI
[AK4536]
4. EXT mode (Slave mode)
Power Supply
Example
: Audio I/F Format:MSB justified (ADC and DAC)
(1)
Input MCKI frequency: 1024fs
MCKI pin: CMOS Level
Sampling Frequency:8kHz
PDN pin
(2)
(3)
PMVCM bit
(1) Power Supply & PDN pin = “L” à “H”
(Addr:00H,D6)
MCKPD bit
(2) Addr:04H, Data:02H
Addr:05H, Data:01H
(Addr:01H,D2)
(4)
PMXTL bit
(Addr:01H,D1)
"L" or "H"
"L"
PMPLL bit
(Addr:01H,D0)
(3) Addr:00H, Data:40H
"L"
(5)
MCKI pin
Input
(4) Addr:01H, Data:00H
(5)
FCK pin
BICK pin
Input
MCKI, BICK and FCK input
Figure 37. Clock Set Up Sequence (4)
<Example>
(1) After Power Up, PDN pin “L” à “H”
“L” time (1) of 150ns or more is needed to reset the AK4536.
(2) DIF1-0 and FS1-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” à “1”
VCOM should first be powered up before the other block operates.
(4) Release the pulled-down of the XTI pin: MCKPD bit = “1” à “0”
Power down PLL: PMPLL bit = “0”
When MCKI pin is input by AC coupling: PMXTL bit = “1”
When MCKI pin is input by CMOS Level: PMXTL bit = “0”
(5) After the MCKI, FCK and BICK are supplied, the normal operation of the block which a clock is necessary for
becomes possible
MS0174-E-00
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ASAHI KASEI
[AK4536]
n MIC Input Recording
Example:
FS2-0 bits
(Addr:05H,D2-0)
MIC Control
(Addr:02H,D2-0)
ALC1 Control
1
XXX
XXX
(1)
001
XXH
XXH
XXH
(2) Addr:02H, Data:07H
47H
(3) Addr:06H, Data:00H
47H
(4) Addr:08H, Data:47H
61H or 21H
(5) Addr:09H, Data:47H
(5)
XXH
(6)
(Addr:07H)
ALC1 State
00H
(4)
(Addr:09H)
ALC1 Control
4
(1) Addr:05H, Data:00H
(3)
(Addr:08H)
ALC1 Control
3
X1X
(2)
(Addr:06H)
ALC1 Control
2
PLL Master Mode
Audio I/F Format:DSP Mode, BCKP=MSBS=“0”
Sampling Frequency:8kHz
Pre MIC AMP:+20dB
MIC Power On
ALC1 setting:Refer to Figrure 28
ALC2 bit=“1”(default)
ALC1 Disable
ALC1 Enable
ALC1 Disable
(6) Addr:07H, Data:61H
PMADC bit
(Addr:00H,D0)
(7) Addr:00H, Data:43H
(7)
PMMIC bit
1059 / fs
(Addr:00H,D1)
ADC Internal
State
(8)
Power Down
Recording
Initialize Normal State Power Down
(8) Addr:00H, Data:40H
Figure 38. MIC Input Recording Sequence
<Example>
This sequence is an example of ALC1 setting at fs=8kHz. If the parameter of the ALC1 is changed, please refer to
“Figure 28. Register set-up sequence at the ALC1 operation.”
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS2-0 bits). When the AK4536 is PLL mode, MIC and ADC should be powered-up
in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up MIC input (Addr: 02H)
(3) Set up Timer Select for ALC1 (Addr: 06H)
(4) Set up REF value for ALC1 (Addr: 08H)
(5) Set up IPGA value for ALC1 (Addr: 09H)
(6) Set up LMTH, RATT, LMAT1-0, ALC1 bits (Addr: 07H)
(7) Power Up MIC and ADC: PMMIC bit = PMADC bit = “0” → “1”
The initialization cycle time of ADC is [email protected]=8kHz.
After the ALC1 bit is set to “1” and MIC block is powered-up, the ALC1 operation starts.
(8) Power Down MIC and ADC: PMMIC bit = PMADC bit = “1” → “0”
When the registers for the ALC1 operation are not changed, ALC1 bit may be keeping “1”. The ALC1 operation
is disabled because the MIC block is powered-down. If the registers for the ALC1 operation are also changed
when the sampling frequency is changed, it should be done after the AK4536 goes to the manual mode (ALC1 bit
= “0”) or MIC block is powered-down (PMMIC bit = “0”).
MS0174-E-00
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ASAHI KASEI
[AK4536]
n Speaker-amp Output
Example:
FS2-0 bits
(Addr:05H,D2-0)
XXX
PLL, Master Mode
Audio I/F Format :DSP Mode, BCKP=MSBS= “0”
Sampling Frequency: 8kHz
Digital Volume: -8dB
ALC2 : Enable
XXX
(1)
DACM bit
(1) Addr:05H, Data:00H
(Addr:02H,D3)
(2)
ALC2S bit
(2) Addr:02H, Data:28H
(Addr:02H,D5)
ALC2 bit
(Addr:07H,D6)
DOL7-0 bits
(Addr:0AH,D7-0)
0
(3) Addr:07H, Data:40H
X
(3)
0001100
(4) Addr:0AH, Data:28H
XXXXXXX
(4)
PMDAC bit
(5) Addr:00H, Data:54H
(Addr:00H,D2)
(5)
(8)
PMSPK bit
(6) Addr:02H, Data:A8H
(Addr:00H,D4)
SPPS bit
Playback
(Addr:02H,D7)
(6)
SPP pin
SPN pin
Hi-Z
Hi-Z
(7)
Normal Output
SVDD/2
Hi-Z
Normal Output SVDD/2
(7) Addr:02H, Data:28H
Hi-Z
(8) Addr:00H, Data:40H
Figure 39. Speaker-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS2-0 bit). When the AK4536 is PLL mode, DAC and Speaker-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC à SPK-Amp”
DACM = ALC2S bit: “0” à “1”
(3) Set up the ALC2 Enable/Disable (ALC2 bit)
(4) Set up the digital volume (Addr = 0AH)
(5) Power Up of DAC and Speaker-Amp: PMDAC bit = PMSPK bit = “0” → “1”
(6) Exit the power-save-mode of Speaker-Amp: SPPS bit = “0” → “1”
The initializing time of Speaker amp is 512/fs =64ms ( @ fs=8kHz, ROTM bit = “0”)
(7) Enter the power-save-mode of Speaker-Amp: SPPS bit = “1” → “0”
(8) Power Down DAC and Speaker-Amp: PMDAC bit = PMSPK bit = “1” → “0”
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ASAHI KASEI
[AK4536]
n Stop of Clock
Master clock can be stopped when ADC, DAC, ALC1 and ALC2 don’t operate.
1. When X’tal is used in PLL & Master mode.
Example:
PMXTL bit
Audio I/F Format: DSP Mode, BCKP = MSBS = “0”
BICK frequency at Master Mode : 64fs
Input Master Clock Select at PLL Mode : 11.2896MHz
Sampling Frequency:8kHz
(Addr:01H,D1)
(1)
PMPLL bit
(Addr:01H,D0)
(1) Addr:01H, Data:0CH
MCKPD bit
(Addr:01H,D2)
Figure 40. Stop of Clock Sequence (1)
<Example>
(1) Power down X’tal and PLL: PMXTL bit = PMPLL bit = “1” → “0”
Pull down the XTI pin: MCKPD bit = “0” → “1”
2. When an external clock is used in PLL & Master mode
Example:
(1)
Audio I/F Format: DSP Mode, BCKP = MSBS = “0”
BICK frequency at Master Mode : 64fs
MCKI pin: CMOS Level
Input Master Clock Select at PLL Mode : 11.2896MHz
Sampling Frequency:8kHz
PMPLL bit
(Addr:01H,D5)
(2)
PMXTL bit
"H" or "L"
(1) (2)Addr:01H, Data:0CH
(Addr:01H,D1)
(2)
MCKPD bit
(2) Stop an external MCKI
(Addr:01H,D7)
(3)
External MCKI
Input
Figure 41. Stop of Clock Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Pull down the MCKI pin: MCKPD bit = “0” → “1”
Power down X’tal: PMXTL bit = “1” → “0”
When the external master clock becomes Hi-Z or the external master clock is input by AC couple, MCKI pin
should be pulled down. When the external master clock is input by AC couple, X’tal should be
powered-down.
(3) Stop an external master clock
MS0174-E-00
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ASAHI KASEI
[AK4536]
3. PLL & Slave mode
Example
: Audio I/F Format : DSP Mode, BCKP = MSBS = “0”
(1)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 8kHz
PMPLL bit
(Addr:01H,D5)
(2)
External BICK
Input
(1) Addr:01H, Data:04H
(2)
External FCK
Input
(2) Stop the external clocks
Figure 42. Stop of Clock Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and FCK clocks.
4. EXT mode
(1)
MCKPD bit
Example
: Audio I/F Format :MSB justified(ADC and DAC)
(Addr:01H,D7)
(1)
PMXTL bit
Input MCKI frequency:1024fs
MCKI pin: CMOS Level
Sampling Frequency:8kHz
"H" or "L"
(Addr:01H,D1)
(2)
External MCKI
Input
External BICK
Input
External FCK
Input
(1) Addr:01H, Data:04H
(2)
(2) Stop the external clocks
(2)
Figure 43. Stop of Clock Sequence (4)
<Example>
(1) Pull down the MCKI pin: MCKPD bit = “0” → “1”
Power down X’tal: PMXTL bit = “1” → “0”
When the external master clock becomes Hi-Z or the external master clock is input by AC couple, MCKI pin
should be pulled down. When the external master clock is input by AC couple, X’tal should be
powered-down.
(2) Stop the external MCKI, BICK and FCK clocks
n Power down
Power down VCOM (PMVCM= “1” → “0”) after all blocks except VCOM are powered down and a master clock stops.
The AK4536 is also powered-down by PDN pin = “L”. When PDN pin = “L”, the registers are initialized.
MS0174-E-00
2002/09
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ASAHI KASEI
[AK4536]
PACKAGE
5.2 ± 0.20
5.0 ± 0.10
28
22
22
15
10
14
8
- 0.00
0.80 + 0.20
- 0.28
0.78 + 0.17
0.05 M
0.02 + 0.03
0.05
0.
7
14
0.50
±
45
15
0.21 ± 0.05
0.22 ± 0.05
25
- 0.02
8
28
1
45
7
0.
21
21
5.2 ± 0.20
5.0 ± 0.10
1
0.60 ± 0.10
2
-C
0.
6
0.
4
+
0
- 0 .10
.2
0
28pin QFN (Unit: mm)
Note) The part of black at four corners on reverse side must not be soldered and must be open.
n Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder plate (Pb free)
MS0174-E-00
2002/09
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ASAHI KASEI
[AK4536]
MARKING
4536
XXXX
1
XXXX : Date code identifier (4 digits)
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
a. A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
b. A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
MS0174-E-00
2002/09
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