AKM AKD4566

ASAHI KASEI
AKM CONFIDENTIAL
= Preliminary =
[AK4566]
AK4566
20bit Stereo CODEC with built-in IPGA & HP-AMP
FEATURE
The AK4566 is a 20bit CODEC with built-in Input PGA and Headphone Amplifier. The AK4566 includes
microphone/line input selector and ALC circuit for input, and Mono line output buffer, analog volume and
stereo headphone amplifier for output which is suitable for portable applications. The AK4566 also
features an analog mixing circuit that allows easy interfacing in mobile phone and portable
communication designs. The integrated headphone amplifier features “click-free” power-on/off, a mute
control and delivers 8.7mW of power into 16Ω load via 6.8Ω series resistor. The AK4566 is housed in a
28pin QFN package, making it suitable for portable applications.
FEATURE
2ch 20bit ADC
- S/N: 88dB
- Single-ended input
- 2 stereo inputs selector
- Analog input PGA: +32dB ∼ -19dB, Mute, 0.5dB step (MIC input)
+20dB ∼ -31dB, Mute, 0.5dB step (LINE input)
- Digital HPF for DC-offset cancellation
- I/F format: 20bit MSB justified, I2S
2ch 20bit DAC
- I/F Format: I2S, 20bit MSB justified, 20bit/16bit LSB justified
- Digital ATT: 0dB ∼ -127dB, Mute, 0.5dB step (soft transition)
- Soft mute
- Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz
- Bass Boost Function
Sampling Rate: 8kHz ∼ 48kHz
System clock: 256fs/384fs/512fs
- Input level: CMOS or 1Vpp Analog Input
Analog Mixing Circuit
Mono Lineout
- Analog volume: 0dB ∼ -30dB, Mute, 2dB step
Headphone Amplifier
- Output Power: 8.7mW x 2ch @16Ω load & 6.8Ω series resistor
- S/N: 90dB
µP Interface: 3-wire
Power management
Power supply: 2.7V ∼ 3.6V
Power dissipation: 16mA
Ta: -40 ∼ 85°C
Small Package: 28pin QFN (5.2mm x 5.2mm, 0.5mm pitch)
REV 0.5
2002/2
-1-
AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
AVDD
VREF
VREF
VCOM
VCOM
DVDD
IPGA & ADC
AINL1
AINL2
IPGA
MCLK
ADC
HPF
BICK
AINR1
AINR2
HP-amp
Audio I/F
Controller
DAC
HPL
LRCK
SDTO
HP-Amp
DAC
BOOST
DATT
SDTI
HPR
Control
MOUT
CSN
CCLK
Register
MOUT
CDTI
LIN
RIN
MIN
PDN
HVDD
HVSS
MUTET
AVSS
DVSS
Figure 1. Block diagram
REV 0.5
2002/2
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AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
n Ordering Guide
AK4566VN
AKD4566
-40 ∼ +85°C
28pin QFN (0.5mm pitch)
Evaluation board for AK4566
AINL1
AINR1
AINL2
AINR2
AVDD
AVSS
VCOM
28
27
26
25
24
23
22
n Pin Layout
PDN
1
21
VREF
CSN
2
20
LIN
CCLK
3
19
RIN
CDTI
4
18
MIN
LRCK
5
17
MOUT
MCLK
6
16
MUTET
BICK
7
15
HPL
8
9
10
11
12
13
14
SDTI
SDTO
DVDD
DVSS
HVSS
HVDD
HPR
Top View
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2002/2
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AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
PIN/FUNCTION
No.
Pin Name
I/O
1
PDN
I
2
3
4
CSN
CCLK
CDTI
I
I
I
5
LRCK
I
6
MCLK
I
7
BICK
I
8
SDTI
I
9
SDTO
O
10
11
12
13
DVDD
DVSS
HVSS
HVDD
-
14
HPR
O
15
HPL
O
16
MUTET
O
17
MOUT
O
18
19
20
MIN
RIN
LIN
I
I
I
21
VREF
O
22
VCOM
O
23
24
25
26
27
28
AVSS
AVDD
AINR2
AINL2
AINR1
AINL1
I
I
I
I
Function
Power-down Pin
When at “L”, the AK4566 is in power-down mode and is held in reset. The AK4566
should always be reset upon power-up.
Control Data Chip Select Pin
Control Clock Input Pin
Control Data Input Pin
L/R Clock Pin
This clock determines which audio channel is currently being output on SDTO pin and
input on SDTI pin.
Master Clock Input Pin
Serial Bit Clock Pin
This clock is used to latch audio data.
Audio Data Input Pin
Audio Data Output Pin
SDTO pin goes to DVSS when PDN pin is “L”.
Digital Power Supply Pin
Digital Ground Pin
Ground Pin for Headphone Amplifier
Power Supply Pin for Headphone Amplifier
Rch Headphone Amplifier Output Pin
HPR pin goes to HVSS when PDN pin is “L”.
Lch Headphone Amplifier Output Pin
HPL pin goes to HVSS when PDN pin is “L”.
Mute Time Constant Control Pin
A capacitor for mute time constant should be connected between MUTET pin and HVSS
pin. MUTET pin goes to HVSS when PDN pin is “L”.
Mono Analog Output Pin
MOUT pin goes to Hi-Z when PDN pin is “L”.
Mono Analog Input Pin
Rch Analog Input Pin
Lch Analog Input Pin
Reference Voltage Output Pin, 2.1V (typ, respect to AVSS)
Normally connected to AVSS pin with 0.1µF ceramic capacitor in parallel with a 4.7µF
electrolytic capacitor. VREF pin goes to AVSS when PDN pin is “L”.
Common Voltage Output Pin, 1.25V (typ, respect to AVSS)
Normally connected to AVSS pin with 0.1µF ceramic capacitor in parallel with a 2.2µF
electrolytic capacitor. VCOM pin goes to AVSS when PDN pin is “L”.
Analog Ground Pin
Analog Power Supply Pin
Rch Analog Input 2 Pin for ADC (MIC Input)
Lch Analog Input 2 Pin for ADC (MIC Input)
Rch Analog Input 1 Pin for ADC (LINE Input)
Lch Analog Input 1 Pin for ADC (LINE Input)
Note: No digital input pins must be left floating.
REV 0.5
2002/2
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
ABSOLUATE MAXIMUM RATING
(AVSS, DVSS, HVSS=0V; Note 1)
Parameter
Symbol
AVDD
Power Supplies Analog
DVDD
Digital
HVDD
HP-AMP
∆GND1
|AVSS – HVSS|
(Note 2)
|AVSS – DVSS|
(Note 2)
∆GND2
Input Current (any pins except for supplies)
IIN
Analog Input Voltage
(Note 3)
VINA
Digital Input Voltage
(Note 4)
VIND
Ambient Temperature
Ta
Storage Temperature
Tstg
Note 1. All voltages with respect to ground.
Note 2. AVSS, DVSS and HVSS must be connected to the same analog
Note 3. Max is smaller value between (AVDD+0.3) and 4.6V.
Note 4. Max is smaller value between (DVDD+0.3) and 4.6V.
min
-0.3
-0.3
-0.3
-0.3
-0.3
-40
-65
max
4.6
4.6
4.6
0.3
0.3
±10
(AVDD+0.3) or 4.6
(DVDD+0.3) or 4.6
85
150
Units
V
V
V
V
V
mA
V
V
°C
°C
ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMEND OPERATING CONDITIONS
(AVSS, DVSS, HVSS=0V; Note 1)
Parameter
Symbol
min
typ
max
Units
Power Supplies Analog
AVDD
2.5
3.0
3.6
V
Digital
(Note 5)
DVDD
2.5 or (AVDD-0.3)
3.0
3.6 or (AVDD+0.3)
V
HP-AMP
HVDD
2.5
3.0
3.6
V
Note 1. All voltages with respect to ground.
Note 5. Min is larger value between 2.5V and (AVDD-0.3). Max is smaller value between 3.6V and (AVDD+0.3).
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
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2002/2
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=HVDD=3.0V, AVSS =DVSS=HVSS=0V; fs=44.1kHz; BOOST OFF; Signal Frequency
=1kHz; Measurement band width=20Hz ∼ 20kHz; unless otherwise specified)
Parameter
min
Typ
max
Units
20
bit
ADC Resolution
(AINL1,
AINR1
pins)
(LINE
IN)
IPGA Characteristics:
Input Voltage
1.5
Vpp
Input Resistance
25
50
kΩ
Step Size
0.5
dB
Gain Control Range
-31
+20
dB
IPGA Characteristics: (AINL2, AINR2 pins) (MIC IN)
Input Voltage
1.5
Vpp
Input Resistance
6
12.5
kΩ
Step Size
0.5
dB
Gain Control Range
-19
+32
dB
ADC Characteristics:
(Note 6)
S/(N+D)
(-1dB Input)
82
dB
D-Range
(-60dB Input, A-weighted))
88
dB
S/N
(A-weighted)
88
dB
Interchannel Isolation
80
dB
Interchannel Gain Mismatch
0.2
dB
Power Supply Rejection
(Note 11)
50
dB
20
bit
DAC Resolution
Headphone-Amp: (HPL/HPR pins) (Note 7) Load impedance is a serial connection with RL =22.8Ω and CL=100µF.
S/(N+D)
(0dBFS Output)
50
dB
D-Range
(-60dBFS Output, A-weighted)
90
dB
S/N
(A-weighted)
90
dB
Interchannel Isolation
80
dB
Interchannel Gain Mismatch
0.2
dB
Load Resistance
(Note 8)
20
Ω
Load Capacitance (C1 in Figure 2)
30
pF
(C2 in Figure 2)
(Note 9)
300
pF
Output Voltage
1.5
Vpp
Power Supply Rejection
(Note 11)
50
dB
Mono Output: (MOUT pin)
(Note 10)
S/(N+D)
(0dBFS Output)
80
dB
S/N
(A-weighted)
88
dB
Load Resistance
(Note 8)
10
kΩ
Load Capacitance
30
pF
Output Voltage
1.5
Vpp
Power Supply Rejection
(Note 11)
50
dB
Output Volume: (MOUT pin)
Step Size
2
dB
Gain Control Range
-30
0
dB
Note 6. The signal inputs are AINL1/AINR1 or AINL2/AINR2. The value of IPGA is set to 0dB. On-chip HPF cancels the
offset of IPGA and ADC.
Note 7. DACL=DACR= “1”, MINL=MINR=LIN=RIN= “0”, and ATTL=ATTR=0dB.
Note 8. AC Load
Note 9. The resistor larger than 6.8Ω is inserted in series.
Note 10. DACM= “1”, LINM=RINM=MINM= “0”, ATTL=ATTR=ATTM=0dB, and common mode signal is input to
L/Rch of DAC.
Note 11. PSR is applied to AVDD, DVDD and HVDD with 1kHz, 50mVpp.
REV 0.5
2002/2
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AKM CONFIDENTIAL
ASAHI KASEI
Parameter
min
[AK4566]
typ
max
Units
Analog Input: (LIN/RIN/MIN pins)
Input Resistance
50
kΩ
Gain
dB
-6
LIN/RIN→MOUT
dB
0
MIN→MOUT, LIN/MIN→HPL, RIN/MIN→HPR
Power Supplies
Power Supply Current
Normal Operation (PDN= “H”)
mA
16
AVDD + DVDD + HVDD
(Note 12)
Power-Down Mode (PDN= “L”)
10
AVDD + DVDD + HVDD
(Note 13)
µA
Note 12. All blocks are powered-up (PMVCM=PMADC=PMDAC=PMHPL=PMHPR=PMMO= “1”), and HP-Amp is no
output. 10mA (typ) at playback only (PMVCM=PMDAC=PMHPL=PMHPR=PMMO= “1”, PMADC= “0”).
Note 13. All digital input pins including clock pins (MCLK, BICK and LRCK) are held at DVDD or DVSS. PDN pin is
held at DVSS.
HP-Amp
+
HPL, HPR
> 6.8
100uF
+
C1
C2
16Ω
Figure 2. Headphone amp output circuit
REV 0.5
2002/2
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
FILTER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, HVDD=2.5 ∼ 3.6V; fs=44.1kHz; DEM=OFF; BOOST=OFF)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (LPF):
kHz
17.4
Passband
(Note 15)
PB
0
±0.1dB
kHz
20.0
-1.0dB
kHz
21.1
-3.0dB
Stopband
(Note 15)
SB
27.0
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
65
dB
Group Delay
(Note 16)
GD
17.0
1/fs
Group Delay Distortion
0
∆GD
µs
ADC Digital Filter (HPF):
Hz
3.4
FR
Frequency Response (Note 15) -3dB
Hz
10
-0.5dB
Hz
22
-0.1dB
DAC Digital Filter: (Note 14)
Passband
(Note 15) ±0.01dB
PB
0
20.0
kHz
22.05
kHz
−6.0dB
Stopband
(Note 15)
SB
24.1
kHz
Passband Ripple
PR
dB
±0.06
Stopband Attenuation
SA
43
dB
Group Delay
(Note 16)
GD
16.8
1/fs
Group Delay Distortion
0
∆GD
µs
DAC Digital Filter + Analog Filter: (Note 14)(Note 17)
FR
dB
Frequency Response
0 ∼ 20.0kHz
±0.5
BOOST Filter:
(Note 17) (Note 18)
Frequency Response
20Hz
FR
dB
5.74
100Hz
dB
MIN
2.92
1kHz
dB
0
20Hz
FR
dB
5.94
100Hz
dB
MID
4.71
1kHz
dB
0.14
20Hz
FR
dB
16.04
dB
MAX 100Hz
10.55
1kHz
dB
0.3
Note 14. BOOST OFF (BST1-0 = “00”)
Note 15. The passband and stopband frequencies scale with fs.
For example (DAC), PB=0.4535*fs(@±0.05dB), SB=0.546*fs(@-43dB).
Note 16. This is the calculated delay time caused by digital filtering. This time is measured from the input of analog signal
to setting the 20 bit data of both channels on input register to the output register of ADC. This time also includes
group delay of HPF. For DAC, this time is from setting the 20 bit data of both channels on input register to the
output of analog signal.
Note 17. DACL à HPL, DACR à HPR, DACL/R à MOUT.
Note 18. These frequency responses scale with fs. If high-level signal is input, the AK4566 clips at low frequency.
REV 0.5
2002/2
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AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
Boost Frequency (fs=44.1kHz)
Output Level [dB]
0
MAX
-5
MID
-10
-15
-20
MIN
-25
0.01
0.1
1
10
Frequency [kHz]
Figure 3. Boost Frequency (fs=44.1kHz)
DC CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, HVDD = 2.5 ∼ 3.6V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
Input Voltage at AC Coupling (Note 19)
VAC
1.0
VOH
DVDD-0.4
High-Level Output Voltage (Iout = -100µA)
VOL
Low-Level Output Voltage (Iout = 100µA)
Input Leakage Current
Iin
Note 19. When AC coupled capacitor is connected to MCLK pin.
REV 0.5
typ
max
30%DVDD
-
0.4
±10
Units
V
V
Vpp
V
V
µA
2002/2
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, HVDD = 2.5 ∼ 3.6V: CL = 20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
MHz
24.576
2.048
fCLK
Frequency
Pulse Width Low
(Note 20)
ns
0.4/fCLK
tCLKL
Pulse Width High
(Note 20)
ns
0.4/fCLK
tCLKH
AC Pulse Width
(Note 21)
ns
0.4/fCLK
tACW
LRCK Timing
Frequency
kHz
44.1
48
8
fs
Duty Cycle
%
55
45
Duty
Serial Interface Timing (Note 22)
ns
325.5
tBCK
BICK Period
ns
130
tBCKL
BICK Pulse Width Low
ns
130
tBCKH
Pulse Width High
ns
50
tLRB
LRCK Edge to BICK “↑”
(Note 23)
ns
50
tBLR
BICK “↑” to LRCK Edge
(Note 23)
ns
80
tLRS
LRCK to SDTO(MSB)
ns
80
tBSD
BICK “↓” to SDTO
ns
50
tSDH
SDTI Hold Time
ns
50
tSDS
SDTI Setup Time
Control Interface Timing
CCLK Period
tCCK
200
ns
CCLK Pulse Width Low
tCCKL
80
ns
Pulse Width High
tCCKH
80
ns
CDTI Setup Time
tCDS
40
ns
CDTI Hold Time
tCDH
40
ns
CSN “H” Time
tCSW
150
ns
tCSS
50
ns
CSN “↑” to CCLK “↑”
tCSH
50
ns
CCLK “↑” to CSN “↑”
Power-down & Reset Timing
PDN Pulse Width
(Note 24)
tPD
150
ns
tPDV
2081
1/fs
PMADC “↑” to SDTO valid
(Note 25)
Note 20. Except AC coupling.
Note 21. Pulse width to ground level when MCLK is connected to a capacitor in series and a resistor is connected to ground.
(Refer to Figure 4.)
Note 22. Refer to “Serial Data Interface”.
Note 23. BICK rising edge must not occur at the same time as LRCK edge.
Note 24. The AK4566 can be reset by bringing PDN= “L” to “H” only upon power up.
Note 25. This is the count of LRCK “↑” from PMADC bit=”1”.
REV 0.5
2002/2
- 10 -
AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
n Timing Diagram
1/fCLK
tACW
1000pF
MCLK Input
tACW
Measurement Point
100kΩ
AVSS
AVSS
Figure 4. MCLK AC Coupling Timing
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 5. Clock Timing
REV 0.5
2002/2
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AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
VIH
LRCK
VIL
tLRB
tBLR
VIH
BICK
VIL
tLRS
tBSD
SDTO
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 6. Serial Interface Timing
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
C1
CDTI
tCDH
C0
R/W
VIH
A4
VIL
Figure 7. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
Figure 8. WRITE Data Input Timing
REV 0.5
2002/2
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AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
VIH
CSN
VIL
tPDV
SDTO
50%DVDD
tPD
PDN
VIL
Figure 9. Power-down & Reset Timing
REV 0.5
2002/2
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AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
OPERATION OVERVIEW
n System Clock
The external clocks required to operate the AK4566 are MCLK(256fs/384fs/512fs), LRCK(fs) and BICK. The master
clock (MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter. The
frequency of MCLK is detected automatically, and the internal master clock becomes the appropriate frequency. Table 1
shows system clock example.
LRCK
fs
8kHz
11.025kHz
12kHz
16kHz
22.05kHz
24kHz
32kHz
44.1kHz
48kHz
256fs
2.048
2.8224
3.072
4.096
5.6448
6.144
8.192
11.2896
12.288
MCLK (MHz)
384fs
3.072
4.2336
4.608
6.144
8.4672
9.216
12.288
16.9344
18.432
512fs
4.096
5.6448
6.144
8.192
11.2896
12.288
16.384
22.5792
24.576
BICK (MHz)
64fs
0.512
0.7056
0.768
1.024
1.4112
1.536
2.048
2.8224
3.072
Table 1. System Clock Example
All external clocks (MCLK, BICK and LRCK) should always be present whenever the ADC or DAC is in normal
operation mode (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4566 may draw excess
current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external
clocks are not present, ADC and DAC should be placed in the power-down mode (PMADC bit = PMDAC bit = “0”).
When MCLK is input with AC coupling, MCKAC bit should be set to “1”. When MCLK with AC coupling stops, MCKPD
bit should be set to “1”.
When low sampling rate, DR and S/N degrade because of the outband noise. DR and S/N are approved by setting DFS bit
to “1”. Table 2 shows S/N in the case DAC output to HP-amp and MOUT. When DFS bit is “1”, MCLK needs 512fs.
When sampling frequency is changed at normal operation mode of ADC or DAC (PMADC bit = “1” or PMDAC bit = “1”),
DAC output should be soft-muted or “0” data should be input to avoid click noise.
DFS
fs
MCLK
0
1
8kHz∼48kHz
8kHz∼24kHz
256fs/384fs/512fs
512fs
S/N (fs=8kHz, A-weighted)
HP-amp
MOUT
84dB
84dB
90dB
88dB
Default
Table 2. Relationship among fs, MCLK frequency and S/N of HP-amp and MOUT
REV 0.5
2002/2
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AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
n Serial Data Interface
The AK4566 interfaces with external system by using BICK, LRCK, SDTO and SDTI pins. Four data formats are
available and are selected by setting DIF1 and DIF0 bits (Table 3). Mode 0 of SDTI is compatible with existing 16bit
DACs and digital filters. Mode 1 of SDTI is a 20bit version of Mode 0. Mode 2 of SDTI is similar to AKM ADCs and
many DSP serial ports. Mode 3 is compatible with the I2S serial data protocol. In Mode 2 and 3 of SDTI, 16bit data
followed by four zeros also could be input, 18bit data followed by two zeros also could be input. In all modes, the serial
data is MSB first and 2’s complement format.
Mode
0
1
2
3
DIF1
0
0
1
1
DIF0
0
1
0
1
SDTO
20bit, MSB justified
20bit, MSB justified
20bit, MSB justified
IIS (I2S)
SDTI
16bit, LSB justified
20bit, LSB justified
20bit, MSB justified
IIS (I2S)
BICK
≥ 32fs
≥ 40fs
≥ 40fs
32fs or ≥ 40fs
LRCK
H/L
H/L
H/L
L/H
Default
Table 3. Audio Data Format
LRCK
0
1
2
16
17
18
19
20
21
31
0
1
2
16
17
18
19
20
21
31
0
1
BICK(64fs)
SDTO(o)
19 18
SDTI(i)
4
3
Don’t Care
0
1
2
1
0
15 14 13
2
8
9
10
19 18
12
11
11
12
1
13
14
3
Don’t Care
0
15
4
0
1
2
1
0
15 14 13
2
8
9
10
19
12
11
11
12
1
13
14
0
15
0
1
BICK(32fs)
SDTO(o)
19 18
SDTI(i)
15 14
12 11
8
10
9
8
7
6
5
4
19 18
6
5
4
3
2
1
0
15 14
7
12 11
8
10
9
8
7
6
5
4
19
6
5
4
3
2
1
0
15
7
Lch Data
Rch Data
Figure 10. Mode 0 Timing
LRCK
0
1
2
12
13
14
20
21
31
0
1
2
12
13
14
20
21
31
0
1
BICK(64fs)
SDTO(o)
SDTI(i)
19 18
Don’t Care
8
7
6
19 18
0
12
19 18
11
1
0
Don’t Care
Lch Data
8
7
6
0
19 18
12
19
11
1
0
Rch Data
Figure 11. Mode 1 Timing
REV 0.5
2002/2
- 15 -
AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
LRCK
0
1
2
15
16
17
18
19
20
30
31
0
1
2
15
16
17
18
19
20
30
31
0
1
BICK(64fs)
SDTO(o)
19 18
4
SDTI(i)
16bit
15 14
0
SDTI(i)
18bit
17 16
2
1
0
SDTI(i)
20bit
19 18
4
3
2
3
2
1
0
1
0
19 18
4
3
Don’t Care
15 14
0
Don’t Care
17 16
2
1
0
Don’t Care
19 18
4
3
2
Lch Data
2
1
0
1
19
0
Don’t Care
15
Don’t Care
17
Don’t Care
19
Rch Data
Figure 12. Mode 2 Timing
LRCK
0
1
2
3
16
17
18
19
20
21
30
31
0
1
2
3
16
17
18
19
20
21
30
31
0
1
BICK(64fs)
SDTO(o)
19 18
4
SDTI(i)
16bit
15 14
0
SDTI(i)
18bit
17 16
2
1
0
SDTI(i)
20bit
19 18
4
3
2
0
1
2
3
8
3
9
2
10
1
0
1
11
0
12
19 18
4
Don’t Care
15 14
0
Don’t Care
17 16
2
1
0
Don’t Care
19 18
4
3
2
13
14
15
0
1
2
3
8
3
2
1
0
Don’t Care
9
10
Don’t Care
1
11
Don’t Care
0
12
13
14
15
0
1
BICK(32fs)
SDTO(o)
4
19 18
SDTI(i)
0
15 14
12 11
8
7
10
9
8
7
6
5
4
19 18
6
5
4
3
2
1
0
15 14
Lch Data
12 11
8
7
10
9
8
7
6
5
4
6
5
4
3
2
1
0
Rch Data
Figure 13. Mode 3 Timing
n Digital High Pass Filter
The AK4566 has a Digital High Pass Filter (HPF) to cancel DC-offset in ADC and IPGA. The cut-off frequency of the
HPF is 3.4Hz at fs=44.1kHz. It also scales with the sampling frequency (fs).
REV 0.5
2002/2
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
n ALC Operation
[1] ALC Limiter Operation
During the ALC limiter operation, when either output level of Lch or Rch in IPGA exceeds ALC limiter detection level set
by LMTH bit, IPGA value is automatically attenuated by ALC limiter ATT step set by LMAT1-0 bits. Then the IPGA
value is changed commonly for Lch and Rch.
At ZELMN bit = “1”, timeout period is set by LTM1-0 bits. The operation for attenuation is done continuously until the
IPGA output signal level becomes LMTH or less. After finishing the operation for attenuation, unless ALC bit is changed
to “0”, the operation of attenuation repeats when the IPGA output signal level exceeds LMTH.
At ZELMN bit = “0”, timeout period is set by ZTM1-0 bits. The IPGA value is automatically attenuated with zero crossing
detection.
The ALC operation of the AK4566 corresponds to the impulse noise. If the impulse noise is supplied at ZELMN = “0”, the
ALC limiter operation becomes the faster period than a set of ZTM1-0 bits. In case of ZELMN = “1”, it becomes the same
period as LTM1-0 bits.
[2] ALC Recovery Operation
The ALC recovery operation waits until a time set by WTM1-0 bits after completing the ALC limiter operation. If the
output signal does not exceed recovery waiting counter reset level set by LMTH bit, the ALC recovery operation is done.
The IPGA value automatically increases by this operation up to the reference level set by REF6-0 bits with zero crossing
detection which timeout period is set by ZTM1-0 bits. Then the IPGA value is set for Lch and Rch commonly. The ALC
recovery operation is done at a period set by WTM1-0 bits. When zero cross is detected at the IPGA output during the wait
period set by WTM1-0 bits, the ALC recovery operation waits until WTM1-0 period and the next recovery operation is
done.
During the ALC recovery operation or the recovery waiting, when either output signal level of Lch or Rch in IPGA exceeds
the ALC limiter detection level set by LMTH bit, the ALC recovery operation changes into the ALC limiter operation
immediately.
In case of
(Recovery waiting counter reset level) ≤ (IPGA output level) < (Limiter detection level)
during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. Therefore, when
(Recovery waiting counter reset level) > (IPGA output level),
the waiting timer of ALC recovery operation starts.
The ALC operation of the AK4566 corresponds to the impulse noise. If the impulse noise is supplied, the ALC recovery
operation becomes the faster period than a set of ZTM1-0 or WTM1-0 bits.
Others:
When either channel enters the limiter operation during the waiting time of zero crossing, the present ALC recovery
operation stops, according as the small value of IPGA (a channel waiting zero crossing), the ALC limiter operation is done.
When both channels are waiting for the next ALC recovery operation, the ALC limiter operation is done from the IPGA
value of a point in time.
ZTM1-0 bits set zero crossing timeout and WTM1-0 bits set the ALC recovery operation period. When the ALC recovery
waiting time (WTM1-0 bits) is shorter than zero crossing timeout period (ZTM1-0 bits), the ALC recovery is operated by
the zero crossing timeout period. Therefore, in this case, the ALC recovery operation period is not constant.
REV 0.5
2002/2
- 17 -
AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
[3] ALC Operation Example
The following registers should not be changed during the ALC operation:
LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELMN.
Manual mode
WR (Power Management Control & Signal Select)
WR (ZTM1-0, WTM1-0, LTM1-0)
WR (LMAT1-0, RATT, LMTH)
WR (REF6-0)
WR (IPGA6-0)
* The value of IPGA should be the
same or smaller than REF’s.
WR (ALC= “1”,ZELMN)
ALC Operation
No
Finish ALC mode?
Yes
WR (ALC=”0”)
Finish ALC mode and return to Manual mode
Figure 14. Registers set-up sequence at ALC operation (WR=Write)
REV 0.5
2002/2
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
n IPGA Operation
[Write Operation at ALC Enabled]
The values of IPGA6-0 bits are ignored during ALC operation.
[Write Operation at ALC Disabled]
Channel independent zero crossing detection is used. If there is no zero crossings, then the level will change after a timeout.
The ZTM1-0 bits set the zero crossing timeout. When the IPGA7-0 bits are written by µP, the zero crossing counter is reset
and starts. When the IPGA output signal detects zero crossing or zero crossing timeout, the written value by µP becomes
valid.
When writing to the IPGA7-0 bits continually, the control register should be written by an interval more
than zero crossing timeout. If not, there is a possibility that each IPGA of L/R channels has a different gain.
[IPGA Gain after completing ALC operation]
The IPGA7-0 bits are not updated by the actual gain of IPGA changed during ALC operation. In order to set the actual gain
of IPGA with the IPGA7-0 bits, the IPGA7-0 bits should be written after zero crossing timeout period when completing
ALC operation (ALC bit= “1” à “0”).
REV 0.5
2002/2
- 19 -
AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
n Digital Attenuator
The AK4566 has channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is placed before
D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to -127dB or MUTE) of each channel (Table 19). At
DATTC= “1”, ATTL7-0 bits control both Lch and Rch attenuation level. At DATTC= “0”, ATTL7-0 bits control Lch
level and ATTR7-0 bits control Rch level.
ATS bit set the transition time between set values of ATT7-0 bits as either 1061/fs or 7424/fs (Table 15). At ATS= “0”, the
transition between set values is soft transition of 1062 levels. It takes 1061/fs ([email protected]=44.1kHz) from FFH(0dB) to
00H(MUTE). The ATTs are 00H when PMDAC bit is “0”. When PMDAC returns to “1”, the ATTs fade to their current
value. Digital attenuator is independent of soft mute function.
n Soft Mute
Soft mute operation is performed in the digital domain. When SMUTE bit goes to “1”, the output signal is attenuated by -∞
(“0”) via the cycle set by TM1-0 bit (Table 18). When SMUTE bit returns to “0”, the mute is cancelled and the output
attenuation gradually changes to 0dB via the cycle set by TM1-0 bits. If the soft mute is cancelled within the cycle set by
TM1-0 bits after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for
changing the signal source without stopping the signal transmission.
SMUTE bit
TM1-0 bit
TM1-0 bit
0dB
(1)
(3)
Attenuation
-∞
GD
(2)
GD
Analog Output
Figure 15. Soft Mute Function
NOTE:
(1) The output signal is attenuated until -∞ (“0”) by the cycle set by TM1-0 bits.
(2) Analog output corresponding to digital input have the group delay (GD).
(3) If the soft mute is cancelled within the cycle set by TM1-0 bits, the attenuation is discontinued and returned to
0dB(the setting value).
REV 0.5
2002/2
- 20 -
AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
n De-emphasis Filter
The AK4566 includes a digital de-emphasis filter (tc = 50/15µs) by IIR filter corresponding to three sampling frequencies
(32kHz, 44.1kHz and 48kHz). The de-emphasis filter is enabled by setting DEM1-0 bits (Table 16).
n Bass Boost Function
By controlling BST1-0 bits, the low frequency boost signal can be output from DAC. The setting value is common in Lch
and Rch (Table 17).
The cut-off frequency (fc) of HPF depends on the external resistor and capacitor values. Table 4 shows the relationship of
external resistor, capacitor, fc and output power, where load resistance of headphone is 16Ω. Output level of headphone
amp is 1.5Vpp (typ).
HP-AMP
R
C
Headphone
16Ω
AK4566
Figure 16. External Circuit Example of Headphone
fc [Hz]
fc [Hz]
Output Power [mW]
BOOST=OFF
BOOST=MID
47
148.6
65
6.8
8.7
100
69.8
27
47
105.8
43
16
4.4
100
49.7
20
Table 4. Relationship of external circuit, output power and frequency response
R [Ω]
C [µF]
Note: Cut-off frequency (fc) at BOOST=MID is approximate value.
n System Reset
The AK4566 should be reset once by bringing PDN “L” upon power-up. After exiting reset, VCOM, IPGA, ADC, DAC,
HPL, HPR and MOUT switch to the power-down state. The contents of the control register are maintained until the reset
is done.
ADC exits reset and power down state by MCLK after PMADC bit is changed to “1”, and then ADC is powered up and the
internal timing starts clocking by LRCK “↑”. ADC is in the power-down mode until MCLK and LRCK are input. DAC
also exits reset and power down state when MCLK and LRCK are input after PMDAC= “1”.
REV 0.5
2002/2
- 21 -
AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
n Power-Up/Down Sequence
1) ADC
Power Supply
(1) >150ns
PDN pin
HPLMT,
HPRMT bit
(2)
>0
PMVCM bit
Don’t care
(4)
Clock Input
Don’t care
PMADC bit
(3) >0
ADC Internal
State
Don’t care
(6) 2081/fs
PD(Power-down)
Init Cycle
(6) 2081/fs
Normal Operation
PD
(Hi-Z)
Normal Operation
(Hi-Z)
(5)
AIN pin
Init Cycle
(7) GD
(7) GD
(7) GD
SDTO pin
Figure 17. Power-up/down sequence of ADC
(1)
(2)
(3)
(4)
PDN pin should be set to “H” at least 150ns after the power is supplied.
HPLMT, HPRMT and PMVCM bits should be changed to “1” after PDN pin goes to “H”.
PMADC bit should be changed to “1” after HPLMT, HPRMT and PMVCM bits are changed to “1”.
External clocks (MCLK, BICK, LRCK) are needed to operate ADC. When PMADC= “0”, these clocks can be
stopped.
(5) When PMADC bit is changed to “1”, each AIN pin is biased to VCOM voltage. Rising time constant is determined by
input capacitor for AC coupling and input resistance. In case of AINL2/AINR2 and 1µF input capacitor, time constant
is
τ = 1µF x 12.5kΩ = 12.5ms (typ)
(6) The analog part of ADC is initialized during 2081/fs([email protected]=44.1kHz) after exiting the power-down state. SDTO
is “L” at that time.
(7) Digital output corresponding to analog input has the group delay (GD) of 17.0/fs(=385µ[email protected]=44.1kHz).
REV 0.5
2002/2
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AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
2) DAC → HP-amp
Power supply voltage for headphone amp is supplied from HVDD pin and centered around VCOM. Load resistance of
headphone output is min.20Ω. When PMHPL and PMHPR bit are “0”, headphone amplifiers are powered-down perfectly.
Then HPL and HPR pins are fixed to “L” (HVSS) and a capacitor of MUTET pin works to avoid pop noise.
Power Supply
(9)
(1)
>150ns
PDN pin
(2) >0
PMVCM bit
Don’t care
Don’t care
Don’t care
(4)
Clock Input
Don’t care
(3) >0
PMDAC bit
DAC Internal
State
Normal Operation
PD
PD
Normal Operation
PD
SDTI pin
PMHPL/R bit
HPLMT,
HPRMT bit
ATTL/R7-0 bit
00H(MUTE)
FFH(0dB)
(7) GD
(5)
00H(MUTE)
(8) 1061/fs (7)
(8)
FFH(0dB)
(7)
(6)
(5)
(8)
00H(MUTE)
(7)
(8)
(6)
HPL/R pin
Figure 18. Power-up/down sequence of DAC and HP-amp
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) HPLMT, HPRMT and PMVCM bits should be changed to “1” after PDN pin goes to “H”.
(3) PMDAC, PMHPL, PMHPR bits should be changed to “1” and HPLMT, HPRMT bits should be changed to “0” after
HPLMT, HPRMT, PMVCM bits are changed to “1”. Once PMHPL and PMHPR bits are changed to “1”, HPLMT
and HPRMT bits should be inverted from PMHPL and PMHPR bits respectively.
(4) External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PMDAC= “0”, these clocks can be
stopped. Headphone amp can operate without these clocks.
(5) Rise time of headphone amp is determined by external capacitor of MUTET pin. When C=1µF,
Rise Time of Headphone Amp: τ = 100ms
(6) Fall time of headphone amp is determined by output capacitor for AC coupling. When C=100µF,
Fall Time of Headphone Amp: τ = 200ms
(7) Analog output corresponding to digital input has the group delay (GD) of 16.8/fs(=381µ[email protected]=44.1kHz).
(8) ATS bit sets transition time of digital attenuator. Default value is 1061/fs([email protected]=44.1kHz).
(9) Power supply should be switched off after headphone amp is powered down (HPL/R pins become “L”).
REV 0.5
2002/2
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AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
3) DAC → MOUT
Power Supply
(1) >150ns
PDN pin
HPLMT,
HPRMT bit
(2)
>0
PMVCM bit
Don’t care
(4)
Clock Input
Don’t care
PMDAC bit
(3) >0
DAC Internal
State
Don’t care
Normal Operation
PD(Power-down)
PD
Normal Operation
SDTI pin
PMMO bit
ATTL/R7-0 bit
MMUTE,
ATTM3-0 bit
FFH(0dB)
00H(MUTE)
(Hi-Z)
FFH(0dB)
0FH(0dB)
10H(MUTE)
(6) GD
MOUT pin
00H(MUTE)
(7) 1061/fs (6)
(5)
(7)
(6)
(7)
(5)
(5)
(Hi-Z)
Figure 19. Power-up/down sequence of DAC and MOUT
(1)
(2)
(3)
(4)
PDN pin should be set to “H” at least 150ns after the power is supplied.
HPLMT, HPRMT and PMVCM bits should be changed to “1” after PDN pin goes to “H”.
PMDAC and PMMO bits should be changed to “1” after HPLMT, HPRMT and PMVCM bits are changed to “1”.
External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PMDAC= “0”, these clocks can be
stopped. MOUT buffer can operate without these clocks.
(5) When PMMO bit is changed to “1”, click noise is output from MOUT pin.
(6) Analog output corresponding to digital input has the group delay (GD) of 16.8/fs(=381µ[email protected]=44.1kHz).
(7) ATS bit sets transition time of digital attenuator. Default value is 1061/fs([email protected]=44.1kHz).
REV 0.5
2002/2
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AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
4) LIN/RIN/MIN → HP-amp, MOUT
Power Supply
(1) >150ns
PDN pin
(2) >0
PMVCM bit
Don’t care
(3) >0
PMHPL/R bit,
PMMO bit
HPLMT,
HPRMT bit
(4)
LIN/RIN/MIN pin
(Hi-Z)
(Hi-Z)
(6)
(5)
(5)
HPL/R pin
MMUTE,
ATTM3-0 bit
MOUT pin
10H(MUTE)
(Hi-Z)
0FH(0dB)
(7)
(7)
(7)
(Hi-Z)
Figure 20. Power-up/down sequence of LIN/RIN/MIN, HP-amp and MOUT
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) HPLMT, HPRMT and PMVCM bits should be changed to “1” after PDN pin goes to “H”.
(3) PMHPL, PMHPR, PMMO bits should be changed to “1” and HPLMT, HPRMT bits should be changed to “0” after
HPLMT, HPRMT, PMVCM bits are changed to “1”. Once PMHPL and PMHPR bits are changed to “1”, HPLMT
and HPRMT bits should be inverted from PMHPL and PMHPR bits respectively.
(4) When PMHPL, PMHPR or PMMO bit is changed to “1”, LIN, RIN and MIN are biased to VCOM voltage. Rising
time constant is determined by input capacitor for AC coupling and input resistance 50kΩ (typ). In case of 0.1µF input
capacitor, time constant is
τ = 0.1µF x 50kΩ = 5ms (typ)
(5) Rise time of headphone amp is determined by external capacitor of MUTET pin. When C=1µF,
Rise Time of Headphone Amp: τ = 100ms
(6) Fall time of headphone amp is determined by output capacitor for AC coupling. When C=100µF,
Fall Time of Headphone Amp: τ = 200ms
(7) When PMMO bit is changed to “1”, click noise is output from MOUT pin.
REV 0.5
2002/2
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AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
n Serial Control Interface
Internal registers may be written to the 3 wire µP interface pins (CSN, CCLK and CDTI). The data on this interface
consists of Chip address (2bits, Fixed to “10”), Read/Write (1bit, Fixed to “1”, Write only), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK. For write operations,
data is latched after a low-to-high transition of CSN. The clock speed of CCLK is 5MHz(max). The value of internal
registers is initialized at PDN= “L”.
CSN
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (Fixed to “10”)
R/W: Read/Write (Fixed to “1” : Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 21. Control Interface
REV 0.5
2002/2
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AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
n Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
Register Name
Power Management
Input Select
Timer Select
ALC Mode Control 1
ALC Mode Control 2
IPGA Control
Mode Control
DAC Control
Output Select 0
Output Select 1
DAC Lch ATT
DAC Rch ATT
MOUT ATT
D7
D6
HPRMT
HPLMT
0
0
0
0
0
0
0
0
REF6
IPGA6
MCKAC
MCKPD
TM1
0
0
ATTL7
ATTR7
0
TM0
0
0
ATTL6
ATTR6
0
D5
PMMO
0
ZTM1
ALC
REF5
IPGA5
0
D4
D3
D2
D1
D0
PMHPR
PMHPL
PMDAC
PMADC
PMVCM
ADM
ZTM0
INR2
WTM1
INR1
WTM0
ZELMN
LMAT1
LMAT0
REF4
IPGA4
ATS
REF2
IPGA2
DIF1
BST0
MINL
RINM
ATTL2
ATTR2
INL2
LTM1
RATT
REF1
IPGA1
DIF0
DEM1
LINL
LINM
ATTL1
ATTR1
INL1
LTM0
LMTH
REF0
IPGA0
DFS
DEM0
DACL
DACM
ATTL0
ATTR0
ATTM2
ATTM1
ATTM0
SMUTE
DATTC
MINR
0
ATTL5
ATTR5
0
RINR
0
ATTL4
ATTR4
REF3
IPGA3
HPM
BST1
DACR
MINM
ATTL3
ATTR3
MMUTE
ATTM3
All registers inhibit writing at PDN pin = “L”.
For addresses from 0DH to 1FH, data must not be written.
REV 0.5
2002/2
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AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
n Register Definitions
Addr
00H
Register Name
Power Management
Default
D7
D6
HPRMT
HPLMT
0
0
D5
PMMO
0
D4
D3
D2
D1
D0
PMHPR
PMHPL
PMDAC
PMADC
PMVCM
0
0
0
0
0
PMVCM: Power Management for VCOM Block
0: Power OFF (Default)
1: Power ON
PMADC: Power Management for IPGA and ADC Blocks
0: Power OFF (Default)
1: Power ON
MCLK should be present when PMADC bit= “1”.
PMDAC: Power Management for DAC Blocks
0: Power OFF (Default)
1: Power ON
When PMDAC bit is changed from “0” to “1”, DAC is powered-up to the current register values (ATT
value, sampling rate, etc).
PMHPL: Power Management for Lch of Headphone Amp
0: Power OFF (Default). HPL pin becomes HVSS(0V).
1: Power ON
PMHPR: Power Management for Rch of Headphone Amp
0: Power OFF (Default). HPR pin becomes HVSS(0V).
1: Power ON
PMMO: Power Management for Mono Output
0: Power OFF (Default) MOUT pin becomes Hi-Z.
1: Power ON
HPLMT: Mute for Lch of Headphone Amp
0: Normal operation (Default). MUTET pin is connected to VCOM pin internally.
1: Mute. MUTET pin is connected to HPL pin internally.
HPLMT: Mute for Rch of Headphone Amp
0: Normal operation (Default). MUTET pin is connected to VCOM pin internally.
1: Mute. MUTET pin is connected to HPR pin internally.
HPLMT
HPRMT
MUTET
0
0
Connected to VCOM
0
1
Connected to HPR
1
0
Connected to HPL
1
1
Connected to HPL,HPR
Table 5. MUTET internal connection
All blocks can be powered-down by setting PDN pin to “L” regardless of register values setup. All blocks can be also
powered-down by setting all power management bits to “0”. In this case, control register values are held.
REV 0.5
2002/2
- 28 -
AKM CONFIDENTIAL
ASAHI KASEI
Addr
01H
Register Name
Input Select
Default
D7
0
0
D6
0
0
D5
0
0
D4
ADM
0
[AK4566]
D3
INR2
0
D2
INR1
1
D1
INL2
0
D0
INL1
1
INL2-1: Select ON/OFF of IPGA Lch input.
0: OFF
1: ON
Default: INL2=0, INL1=1
INR2-1: Select ON/OFF of IPGA Rch input.
0: OFF
1: ON
Default: INR2=0, INR1=1
ADM: Mono Recording Mode
0: Stereo (Default)
1: MONO
When ADM= “1”, input signal to AINL1 or AINL2 pin is input to both Lch and Rch of ADC.
REV 0.5
2002/2
- 29 -
AKM CONFIDENTIAL
ASAHI KASEI
Addr
02H
Register Name
Timer Select
Default
D7
0
0
D6
0
0
D5
ZTM1
0
D4
ZTM0
0
[AK4566]
D3
WTM1
0
D2
WTM0
0
D1
LTM1
0
D0
LTM0
0
LTM1-0: ALC limiter operation period (Table 6)
When zero crossing is disabled (ZELMN = “1”), the IPGA value is changed immediately by ALC limiter
operation. When the IPGA value is changed continuously, the change is done by the period specified by
LTM1-0 bits. Default: “00”.
ALC Limiter Operation Period
8kHz
16kHz
44.1kHz
0
0.5/fs
Default
63µs
31µs
11µs
1
1/fs
125µs
63µs
23µs
0
2/fs
250µs
125µs
45µs
1
4/fs
500µs
250µs
91µs
Table 6. ALC Limiter Operation Period at zero crossing disable (ZELMN bit= “1”)
LTM1
0
0
1
1
LTM0
WTM1-0: ALC Recovery Waiting Period (Table 7)
WTM1-0 bits set a period of recovery operation when any limiter operation does not occur during ALC
operation. Default: “00”.
WTM1
WTM0
0
0
1
1
0
1
0
1
ALC Recovery Operation Waiting Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 7. ALC Recovery Operation Waiting Period
Default
ZTM1-0: ALC Zero Crossing Timeout Period (Table 8)
When IPGA output detects zero crossing or timeout, the IPGA value is changed by µP WRITE operation,
ALC recovery operation, or ALC limiter operation. Default: “00”.
ZTM1
ZTM0
0
0
1
1
0
1
0
1
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 8. Zero Crossing Timeout Period
REV 0.5
Default
2002/2
- 30 -
AKM CONFIDENTIAL
ASAHI KASEI
Addr
03H
Register Name
ALC Mode Control 1
Default
D7
0
0
D6
0
0
D5
ALC
0
[AK4566]
D4
D3
D2
ZELMN
LMAT1
LMAT0
0
0
0
D1
RATT
0
D0
LMTH
0
LMTH: ALC Limiter Detection Level / Recovery Waiting Counter Reset Level (Table 9)
LMTH
0
1
ALC Limiter Detection Level
ALC Recovery Waiting Counter Reset Level
ADC Input ≥ −6.0dBFS
−6.0dBFS > ADC Input ≥ −8.0dBFS
ADC Input ≥ −4.0dBFS
−4.0dBFS > ADC Input ≥ −6.0dBFS
Table 9. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
Default
RATT: ALC Recovery GAIN Step (Table 10)
During the ALC recovery operation, the number of steps changed from current IPGA value is set. For
example, when the current IPGA value is 3FH, RATT = “1” is set, IPGA changes to 41H by the ALC
recovery operation, the output signal level is gained by 1dB (=0.5dB x 2). When the IPGA value exceeds the
reference level (REF6-0 bits), the IPGA value does not increase.
RATT
GAIN STEP
0
1
Default
1
2
Table 10. ALC Recovery Gain Step Setting
LMAT1-0: ALC Limiter ATT Step (Table 11)
During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level set by
LMTH bit, LMAT1-0 bits set the number of steps attenuated from current IPGA value. For example, when
the current IPGA value is 3FH in the state of LMAT1-0 bit = “11”, it becomes IPGA = 3BH by the ALC
limiter operation, the input signal level is attenuated by 2dB (=0.5dB x 4). When the attenuation value
exceeds IPGA = “00H” (Mute), it clips to “00H”.
LMAT1
LMAT0
ATT STEP
0
0
1
Default
0
1
2
1
0
3
1
1
4
Table 11. ALC Limiter ATT Step Setting
ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation
0: Enable (Default)
1: Disable
In case of ZELMN = “0”, when IPGA output detects zero crossing or timeout, the IPGA value is changed by
ALC operation. Zero crossing timeout is the same as ALC recovery operation. In case of ZELMN = “1”, the
IPGA value is changed immediately.
ALC: ALC Enable Flag
0: ALC Disable (Default)
1: ALC Enable
ALC is enabled at ALC bit is “1”. Default: “0” (Disable).
REV 0.5
2002/2
- 31 -
AKM CONFIDENTIAL
ASAHI KASEI
Addr
04H
Register Name
ALC Mode Control 2
Default
D7
0
0
D6
REF6
0
D5
REF5
1
D4
REF4
1
[AK4566]
D3
REF3
1
D2
REF2
1
D1
REF1
1
D0
REF0
1
REF6-0: Reference Value at ALC Recovery Operation, 0.5dB step, 103 level, Default: “3FH” (Table 12)
During the ALC recovery operation, if the IPGA value exceeds the set reference value by gain operation,
IPGA does not become larger than the reference value. For example, when REF= “40H”, RATT= “1” (2
step) and IPGA= “3FH”, then IPGA is going to become 3FH + 2step = 41H, but IPGA becomes 40H in fact,
since REF=40H.
GAIN
AINL1, AINR1 AINL2, AINR2
(LINE IN)
(MIC IN)
67H
+20.0dB
+32.0dB
66H
+19.5dB
+31.5dB
65H
+19.0dB
+31.0dB
:
:
:
3FH
0dB
+12.0dB
Default
:
:
:
27H
-12.0dB
0dB
:
:
:
02H
-30.5dB
-18.5dB
01H
-31.0dB
-19.0dB
00H
MUTE (−∞)
MUTE (−∞)
Table 12. Reference Value Setting at ALC Recovery Operation
DATA
Addr
05H
Register Name
IPGA Control
Default
D7
0
0
D6
IPGA6
0
D5
IPGA5
1
D4
IPGA4
1
D3
IPGA3
1
D2
IPGA2
1
D1
IPGA1
1
D0
IPGA0
1
IPGA6-0: Input Analog PGA, 0.5dB step, 103 level, Default: “3FH” (Table 13)
DATA
67H
66H
65H
:
3FH
:
27H
:
02H
01H
00H
GAIN
AINL1, AINR1 AINL2, AINR2
(LINE IN)
(MIC IN)
+20.0dB
+32.0dB
+19.5dB
+31.5dB
+19.0dB
+31.0dB
:
:
0dB
+12.0dB
:
:
-12.0dB
0dB
:
:
-30.5dB
-18.5dB
-31.0dB
-19.0dB
MUTE (−∞)
MUTE (−∞)
Table 13. Input Gain Setting
REV 0.5
Default
2002/2
- 32 -
AKM CONFIDENTIAL
ASAHI KASEI
Addr
06H
Register Name
Mode Control
Default
D7
D6
MCKAC
MCKPD
0
0
D5
0
0
[AK4566]
D4
ATS
0
D3
HPM
0
D2
DIF1
1
D1
DIF0
0
D0
DFS
0
DFS: Sampling Speed Mode Select (Table 2)
DIF1-0: Audio Data Interface Format
Default: “10” (Mode 2)
HPM: Mono Output Select of Headphone
0: Normal Operation (Default)
1: Mono. (L+R)/2 signal from DAC is output to Lch and Rch of headphone.
Setting of HPM bit is enabled only at DACL=DACR= “1”.
DACL
0
1
HPM
x
0
1
HPL pin Output
No output from DAC
Output from Lch of DAC
Output (L+R)/2 from DAC
Default
Table 14. Mono Output Select of Headphone
(Note. Rch is same.)
ATS: Digital attenuator transition time setting (Table 15)
ATS
0
1
ATT speed
0dB to MUTE
1 step
1061/fs
4/fs
7424/fs
29/fs
Default
Table 15. Transition time between set values of ATT7-0 bits
MCKPD: MCLK Input Buffer Control
0: Enable (Default)
1: Disable
When MCLK input with AC coupling is stopped, MCKPD bit should be set to “1”.
MCKAC: MCLK Input Mode Select
0: CMOS input (Default)
1: AC coupling input
REV 0.5
2002/2
- 33 -
AKM CONFIDENTIAL
ASAHI KASEI
Addr
07H
Register Name
DAC Control
Default
D7
TM1
0
D6
TM0
0
D5
D4
SMUTE
DATTC
0
0
[AK4566]
D3
BST1
0
D2
BST0
0
D1
DEM1
0
D0
DEM0
1
DEM1-0: De-emphasis Filter Frequency Select
DEM1
DEM0
De-emphasis
0
0
44.1kHz
0
1
OFF
Default
1
0
48kHz
1
1
32kHz
Table 16. De-emphasis Filter Frequency Select
BST1-0: Low Frequency Boost Function Select
BST1
BST0
BOOST
0
0
OFF
Default
0
1
MIN
1
0
MID
1
1
MAX
Table 17. Low Frequency Boost Select
DATTC: DAC Digital Attenuator Control Mode Select
0: Independent (Default)
1: Dependent
At DATTC= “1”, ATTL7-0 bits control both Lch and Rch attenuation level, while register values of
ATTL7-0 bits are not written to ATTR7-0 bits. At DATTC= “0”, ATTL7-0 bits control Lch level and
ATTR7-0 bits control Rch level.
SMUTE: Soft Mute Control
0: Normal operation (Default)
1: DAC outputs soft-muted
TM1-0: Soft Mute Time Select
TM1
0
0
1
1
TM0
Cycle
Default
0
1024/fs
1
512/fs
0
256/fs
1
128/fs
Table 18. Soft Mute Time Setting
REV 0.5
2002/2
- 34 -
AKM CONFIDENTIAL
ASAHI KASEI
Addr
08H
Register Name
Output Select 0
Default
D7
0
0
D6
0
0
D5
MINR
0
[AK4566]
D4
RINR
0
D3
DACR
0
D2
MINL
0
D1
LINL
0
D0
DACL
0
DACL: DAC Lch output signal is added to Lch of headphone amp.
0: OFF (Default)
1: ON
LINL: Input signal to LIN pin is added to Lch of headphone amp.
0: OFF (Default)
1: ON
MINL: Input signal to MIN pin is added to Lch of headphone amp.
0: OFF (Default)
1: ON
DACR: DAC Rch output signal is added to Rch of headphone amp.
0: OFF (Default)
1: ON
RINR: Input signal to RIN pin is added to Rch of headphone amp.
0: OFF (Default)
1: ON
MINR: Input signal to MIN pin is added to Rch of headphone amp.
0: OFF (Default)
1: ON
R
LIN/RIN pin
LINL/RINR bit
R
R
MIN pin
MINL/MINR bit
R
-
DACL/DACR
DACL/DACR bit
HPL/HPR pin
+
HP-Amp
Figure 22. Summation circuit for headphone amp output
At HPM=0, gain of summation is 0dB for all input path.
REV 0.5
2002/2
- 35 -
AKM CONFIDENTIAL
ASAHI KASEI
Addr
09H
Register Name
Output Select 1
Default
D7
0
0
D6
0
0
D5
0
0
[AK4566]
D4
0
0
D3
MINM
0
D2
RINM
0
D1
LINM
0
D0
DACM
0
DACM: DAC Lch and Rch outputs are added to MOUT buffer amp. Summation gain is -6dB for each channel.
0: OFF (Default)
1: ON
LINM: Input signal to LIN pin is added to MOUT buffer amp.
0: OFF (Default)
1: ON
RINM: Input signal to RIN pin is added to MOUT buffer amp.
0: OFF (Default)
1: ON
MINM: Input signal to MIN pin is added to MOUT buffer amp.
0: OFF (Default)
1: ON
2R
LIN pin
2R
LINM bit
RIN pin
R
RINM bit
R
MIN pin
2R
MINM bit
DACL
2R
-
DACR
MOUT pin
+
DACM bit
Figure 23. Summation circuit for MOUT
Gain of summation is 0dB for MIN and -6dB for LIN, RIN, DACL and DACR.
REV 0.5
2002/2
- 36 -
AKM CONFIDENTIAL
ASAHI KASEI
Addr
0AH
0BH
Register Name
DAC Lch ATT
DAC Rch ATT
Default
D7
ATTL7
ATTR7
0
D6
ATTL6
ATTR6
0
D5
ATTL5
ATTR5
0
D4
ATTL4
ATTR4
0
[AK4566]
D3
ATTL3
ATTR3
0
D2
ATTL2
ATTR2
0
D1
ATTL1
ATTR1
0
D0
ATTL0
ATTR0
0
ATTL7-0: Setting of the attenuation value of output signal from DACL
ATTR7-0: Setting of the attenuation value of output signal from DACR
The AK4566 has channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is
placed before D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to -127dB or MUTE) of each
channel. Digital attenuator is independent of soft mute function.
ATTL/R7-0
Attenuation
FFH
0dB
FEH
−0.5dB
FDH
−1.0dB
FCH
−1.5dB
:
:
:
:
02H
−126.5dB
01H
−127.0dB
00H
Default
MUTE (−∞)
Table 19. Digital Volume ATT values
Addr
0CH
Register Name
MOUT ATT
Default
D7
0
0
D6
0
0
D5
0
0
D4
D3
D2
D1
D0
MMUTE
ATTM3
ATTM2
ATTM1
ATTM0
1
0
0
0
0
ATTM3-0: Analog volume control for MOUT
MMUTE: Mute control for MOUT
0: Normal operation. Attenuation value is controlled by ATTM3-0 bits.
1: Mute. ATTM3-0 bits are ignored. (Default)
MMUTE
0
1
ATTM3-0
Attenuation
0FH
0dB
0EH
−2dB
0DH
−4dB
0CH
−6dB
:
:
:
:
01H
−28dB
00H
−30dB
x
MUTE
Table 20. MOUT Volume ATT values
REV 0.5
Default
2002/2
- 37 -
AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
SYSTEM DESIGN
Figure 24 shows the system connection diagram. An evaluation board [AKD4566] is available which demonstrates the
optimum layout, power supply arrangements and measurement results.
+ 2.2µ
0.1µ
µP
VCOM 22
AVSS 23
AVDD 24
AINR2 25
AINL2 26
AINR1 27
AINL1 28
0.1µ
VREF 21
2 CSN
LIN 20
3 CCLK
MIN 18
Top View
5 LRCK
MOUT 17
6 MCLK
MUTET 16
14 HPR
13 HVDD
12 HVSS
11 DVSS
10 DVDD
8 SDTI
HPL 15
9 SDTO
7 BICK
0.1µ
0.1µ
DIR
10
Digital Ground
4.7µ
+
RIN 19
AK4566
4 CDTI
DSP
0.1µ
1 PDN
1µ
6.8 100µ Headphone
+
16
6.8 100µ
+
16
+ 10µ
Analog Supply: 2.5 ∼ 3.6V
Analog Ground
Figure 24. Typical Connection Diagram
REV 0.5
2002/2
- 38 -
ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
1. Grounding and Power Supply Decoupling
The AK4566 requires careful attention to power supply and grounding arrangements. AVDD is usually supplied from the
analog power supply in the system and DVDD is supplied from AVDD via a 10Ω resistor. Alternatively if AVDD, DVDD
and HVDD are supplied separately, the power up sequence is not critical. AVSS, DVSS and HVSS must be connected to
the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies
are brought onto the printed circuit board. Decoupling capacitors should be as close to the AK4566 as possible, with the
small value ceramic capacitors being the nearest.
2. Internal Voltage Reference
Internal voltage reference is output on the VREF pin (typ. 2.1V). An electrolytic capacitor 4.7µF in parallel with a 0.1µF
ceramic capacitor is attached between VREF and AVSS to eliminate the effects of high frequency noise. VCOM is
1.25V(typ) and is a signal ground of this chip. A 2.2µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor
should be connected between VCOM and AVSS to eliminate the effects of high frequency noise. A ceramic capacitor
should be connected to VCOM pin and located as close as possible to the AK4566. No load current may be drawn from
VREF and VCOM pins. All signals, especially clocks, should be kept away from the VCOM and VREF pins in order to
avoid unwanted coupling into the AK4566.
3. Analog Inputs
The analog inputs are single-ended and the input resistance 50kΩ (typ) for AINL1/AINR1 pins and 12.5kΩ (typ) for
AINL2/AINR2 pins. The input signal range is 1.5Vpp centered around VCOM voltage. Usually, the input signal cuts DC
with a capacitor. The cut-off frequency is fc=(1/2πRC). The AK4566 can accept input voltages from AVSS to AVDD. The
ADC output data format is 2’s complement. The DC offset including ADC own DC offset is removed by the internal HPF
([email protected]=44.1kHz).
4. Analog Outputs
The analog outputs are single-ended outputs and 1.5Vpp(typ) centered around the VCOM voltage. The input data format
is 2’s compliment. The output voltage is a positive full scale for 7FFFFH(@20bit) and negative full scale for
80000H(@20bit). The ideal output is VCOM voltage for 00000H(@20bit). If the noise generated by the delta-sigma
modulator beyond the audio band causes problems, attenuation by an external filter is required.
DC offsets on the analog outputs is eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few
mV.
REV 0.5
2002/2
- 39 -
AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
n Application Circuit Example
AVDD
VREF
VREF
VCOM
VCOM
DVDD
AK4566
IPGA & ADC
AINL1
AINL2
IPGA
AK4116
MCLK
ADC
BICK
AINR1
AINR2
HP-amp
MCKO
RX
BICK
XTI
S/PDIF
HPF
Audio I/F
Controller
DAC
LRCK
LRCK
SDTO
HPL
CSN
CCLK
DAUX
CDTI
HP-Amp
DAC
BOOST
SDTI
DATT
SDTO
CDTO
HPR
DSP
MOUT
BICK
CLKOUT
MOUT
LIN
LRCK
RIN
SDTI
MIN
PDN
HVDD
CSN
Control
CCLK
Register
CDTI
HVSS
SDTO
MUTET
AVSS
DVSS
uP
Figure 25. Application Circuit Example
REV 0.5
2002/2
- 40 -
AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
<Clock and Data Flow>
1) Analog Recording
AVDD
VREF
VREF
VCOM
VCOM
DVDD
AK4566
IPGA & ADC
AINL1
AINL2
IPGA
AK4116
MCLK
ADC
BICK
AINR1
AINR2
HP-amp
MCKO
RX
BICK
XTI
HPF
Audio I/F
Controller
DAC
LRCK
LRCK
SDTO
HPL
CSN
CCLK
DAUX
CDTI
HP-Amp
DAC
BOOST
SDTI
DATT
SDTO
CDTO
HPR
DSP
MOUT
BICK
CLKOUT
MOUT
LIN
LRCK
RIN
SDTI
MIN
PDN
HVDD
CSN
HVSS
Control
CCLK
Register
CDTI
SDTO
MUTET
AVSS
uP
DVSS
Figure 26. Clock and Data Flow at Analog Recording
(with DAC monitor)
REV 0.5
2002/2
- 41 -
AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
2) Digital Recording
AVDD
VREF
VREF
VCOM
VCOM
DVDD
AK4566
IPGA & ADC
AINL1
AINL2
IPGA
AK4116
MCLK
ADC
BICK
AINR1
AINR2
HP-amp
MCKO
RX
BICK
XTI
S/PDIF
HPF
Audio I/F
Controller
DAC
LRCK
LRCK
SDTO
HPL
CSN
CCLK
DAUX
CDTI
HP-Amp
DAC
BOOST
SDTI
DATT
SDTO
CDTO
HPR
DSP
MOUT
BICK
CLKOUT
MOUT
LRCK
LIN
SDTI
RIN
MIN
PDN
HVDD
CSN
HVSS
Control
CCLK
Register
CDTI
SDTO
MUTET
AVSS
uP
DVSS
Figure 27. Clock and Data Flow at Digital Recording
(with DAC monitor)
REV 0.5
2002/2
- 42 -
AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
3) Playback
AVDD
VREF
VREF
VCOM
VCOM
DVDD
AK4566
IPGA & ADC
AINL1
AINL2
IPGA
AK4116
MCLK
ADC
BICK
AINR1
AINR2
HP-amp
MCKO
RX
BICK
XTI
HPF
Audio I/F
Controller
DAC
LRCK
LRCK
SDTO
HPL
CSN
CCLK
DAUX
CDTI
HP-Amp
DAC
BOOST
SDTI
DATT
SDTO
CDTO
HPR
DSP
MOUT
BICK
CLKOUT
MOUT
LRCK
LIN
SDTI
RIN
MIN
PDN
HVDD
CSN
HVSS
Control
CCLK
Register
CDTI
SDTO
MUTET
AVSS
uP
DVSS
Figure 28. Clock and Data Flow at Playback
REV 0.5
2002/2
- 43 -
AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
PACKAGE
5.2 ± 0.20
5.0 ± 0.10
28
22
22
15
10
14
8
- 0.00
0.80 + 0.20
- 0.28
0.78 + 0.17
0.05 M
0.02 + 0.03
0.05
0.
7
14
0.50
±
45
15
0.21 ± 0.05
0.22 ± 0.05
25
- 0.02
8
28
1
45
7
0.
21
21
5.2 ± 0.20
5.0 ± 0.10
1
0.60 ± 0.10
2
-C
0.
6
0.
4
+
0
- 0 .10
.2
0
28pin QFN (Unit: mm)
Note: The black parts of back package should be open.
n Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
REV 0.5
2002/2
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
MARKING
4566
XXXX
1
XXXX : Date code identifier (4 digits)
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application
or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or
other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with
the express written consent of the Representative Director of AKM. As used here:
a. A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
b. A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing
it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise
places the product with a third party to notify that party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from
any and all claims arising from the use of said product in the absence of such notification.
REV 0.5
2002/2
- 45 -