AKM AKD4584

ASAHI KASEI
[AK4584]
AK4584
24Bit 96kHz Audio CODEC with DIT/DIR
GENERAL DESCRIPTION
AK4584 is a high-performance 24-bit CODEC for 96kHz consumer audio and digital recording
applications. The on-board analog-to-digital converter has an impressive dynamic range, thanks in part
to AKM’s Enhanced Dual-Bit architecture. The DAC features the newly developed Advanced Multi-Bit
architecture and achieves low out-of-band noise and high jitter tolerance through the use of Switched
Capacitor Filter (SCF) technology. The AK4584 also has a S/PDIF-AES/EBU digital audio transmitter
(DIT) and a digital audio receiver (DIR) that are compatible with 24-bit, 192kHz formats. The AK4584 can
automatically detect NON-PCM bit streams like AC-3, MPEG and DTS. Either the ADC or the digital
audio input can be routed directly to the digital audio output. The AK4584 has an input Programmable
Gain Amplifier and is well suited for computer DAWs, MiniDisc, DVD-R, hard disk and CD-R
recording/playback systems.
*AC-3 is a trademark of Dolby Laboratories. DTS is a trademark of Digital Theater Systems, Inc.
FEATURES
1. 24bit 2ch ADC
• fs: max 96kHz
• Single-end Input
• S/(N+D): 90dB
• Dynamic Range, S/N: 100dB
• Digital HPF for offset cancellation
• Input PGA with +18dB gain & 0.5dB step
• Input DATT with –72dB ATT
• I/F format: MSB justified or I2S
2. 24bit 2ch DAC
• fs: max 192kHz
• 24bit 8 times Digital Filter
- Ripple: ±0.005dB, Attenuation: 75dB
• Single-end Output
• S/(N+D): 94dB
• Dynamic Range, S/N: 104dB
• De-emphasis for 32kHz, 44.1kHz, 48kHz sampling
• Digital Attenuator with soft-transition
• Soft Mute
• Zero Detect Function
• I/F format: MSB justified, LSB justified or I2S
3. 3 Outputs 24 bit 192kHz DIT
• 3-Channel Transmission Outputs (2 Through outputs & DIT Output)
• 40 bits Channel Status Buffer
MS0118-E-00
2001/11
-1-
ASAHI KASEI
[AK4584]
4. 4 Inputs 24bit 192kHz DIR
• Supports AES3, IEC60958, S/PDIF, EIAJ CP1201
• Low Jitter Analog PLL
• PLL Lock Range: 32k ∼ 192kHz
• Clock Source: PLL or X’tal
• 4 Digital Receive Channel inputs
• Detect Function
- Non-PCM Bit Stream Detection
- DTS-CD Bit Stream Detection
- Validity Flag Detection
- Sampling Frequency Detection
- Unlock & Parity Error Detection
• 40 bits Channel Status Buffer
• Burst Preamble bit Pc, Pd Buffer for Non-PCM bit Stream
5. Support External Audio Clock Input
• Master Clock Input
- 256fs, 384fs, 512fs, 768fs (fs = 44.1kHz ∼ 48kHz)
- 256fs, 384fs (fs = 88.2kHz ∼ 96kHz)
- 128fs, 192fs (fs = 176.4kHz ∼ 192kHz)
6. Support Master & Slave Mode
7. Serial µP I/F: 4-wire serial
8. 5V operation
9. 3V Power Supply Pin for 3V I/F
10. 44pin LQFP Package
11. Ta: −10 to 70°C
MS0118-E-00
2001/11
-2-
ASAHI KASEI
[AK4584]
„ Block Diagram
INT0 INT1
RX1
RX2
RX3
RX4
R
RX1
RX2
TX1E
TX1
TX1
TX2E
TX2
TX2
OPS1-0
RX3
RX4
AVDD
AVSS
DVDD
DVSS
IPS1-0
DIR
R_LRCK
R_BICK
R_DATA
R_MCLK
T_LRCK
T_BICK
T_DATA
T_MCLK
PDN
DIT
TX3E
TX3
DZF
LIN
LIN
RIN
RIN
D_LRCK
A_LRCK
ADC
IPGA
DATT
HPF
A_BICK
A_DATA
Audio
Interface
D_BICK
D_DATA
D_MCLK
A_MCLK
DATT
SMUTE
LOUT
LOUT
ROUT
ROUT
LRCK
LRCK
BICK
SDTO
SDTI
DAC
BICK
SDTO
PVDD
PVSS
VREF
X'tal
OSC
MCLK
Selector
Divider
MCKI
M/S
TVDD
Control Register
MCKO2
XTI
SDTI
MCKO1
XTO
TX3
VCOM MCKO1 MCKO2 DMCK XTALE
CDTO CDTI CCLK CSN
Block Diagram
MS0118-E-00
2001/11
-3-
ASAHI KASEI
[AK4584]
„ Ordering Guide
−10 ∼ +70°C
44pin LQFP (0.8mm pitch)
Evaluation Board for AK4584
AK4584VQ
AKD4584
AVSS
AVDD
VREF
RIN
LIN
PVDD
R
PVSS
RX1
TEST1
RX2
„ Pin Layout
44 43 42 41 40 39 38 37 36 35 34
TEST2
1
33
ROUT
RX3
2
32
LOUT
NC
3
31
VCOM
RX4
4
30
DZF
PDN
5
29
M/S
INT0
6
28
LRCK
INT1
7
27
BICK
CDTI
8
26
SDTI
CDTO
9
25
SDTO
CCLK
10
24
MCKO2
CSN
11
23
MCKO1
AK4584VQ
Top View
MS0118-E-00
DMCK
XTI/MCKI
XTO
TVDD
DVSS
DVDD
TX3
XTALE
TX2
TX1
TEST3
12 13 14 15 16 17 18 19 20 21 22
2001/11
-4-
ASAHI KASEI
[AK4584]
PIN/FUNCTION
No.
Pin Name
I/O
1
2
3
4
TEST2
RX3
NC
RX4
I
I
I
I
5
PDN
I
6
7
8
9
10
11
12
13
14
INT0
INT1
CDTI
CDTO
CCLK
CSN
TEST3
TX1
TX2
O
O
I
O
I
I
I
O
O
15
XTALE
I
16
17
18
19
20
TX3
DVDD
DVSS
TVDD
XTO
XTI
MCKI
O
O
I
I
DMCK
I
21
22
Function
Test 2 Pin
(Internal pull-down pin)
Receiver Input 3 with Amp for 0.2Vpp
NC Pin
(No Internal bonding pin, Fixed to “AVSS”)
Receiver Input 4 with Amp for 0.2Vpp
Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initialize the control registers.
Interrupt 0 Pin
Interrupt 1 Pin
Control Data Input Pin
Control Data Output Pin
Control Data Clock Pin
Chip Select Pin
Test 3 Pin
(Fixed to AVSS)
Transmitter 1 Output Pin
Transmitter 2 Output Pin
X’tal Osc Enable Pin
“H” : Enable, “L” : Disable
Transmitter 3 Output Pin
Digital Power Supply Pin, 4.75 ∼ 5.25V
Digital Ground Pin
Output Buffer Power Supply Pin, 2.7 ∼ 5.25V
X’tal Output Pin
X’tal Input Pin
External Master Clock Input Pin
MCKO1 Disable Pin
“H” : MCKO1 “L” output, “L” : MCKO1 output
MS0118-E-00
2001/11
-5-
ASAHI KASEI
[AK4584]
23
24
25
26
27
28
MCKO1
MCKO2
SDTO
SDTI
BICK
LRCK
O
O
O
I
I/O
I/O
29
M/S
I
30
DZF
O
31
VCOM
O
32
33
34
35
LOUT
ROUT
AVSS
AVDD
O
O
-
36
VREF
I
37
38
39
RIN
LIN
PVDD
I
I
-
40
R
-
41
42
43
44
PVSS
RX1
TEST1
RX2
I
I
I
Master Clock Output 1 Pin
Master Clock Output 2 Pin
Audio Serial Data Output Pin
Audio Serial Data Input Pin
Audio Serial Data Clock Pin
Input / Output Channel Clock Pin
Master / Slave Mode Pin
“H” : Master Mode, “L” : Slave Mode
Zero Input Detect Pin
Common Voltage Output Pin, AVDD/2
Bias voltage of ADC inputs and DAC outputs.
Lch Analog Output Pin
Rch Analog Output Pin
Analog Ground Pin
Analog Power Supply Pin, 4.75 ∼ 5.25V
Voltage Reference Input Pin, AVDD
Used as a voltage reference by ADC & DAC. VREF is connected externally to
filtered AVDD.
Rch Analog Input Pin
Lch Analog Input Pin
PLL Power Supply Pin, 4.75 ∼ 5.25V
External Resistor Pin for PLL
13kΩ ± 1% resistor to PVSS externally.
PLL Ground Pin
Receiver Input 1 with Amp for 0.2Vpp
Test 1 Pin
(Internal pull-down pin)
Receiver Input 2 with Amp for 0.2Vpp
Note: All input pins except pull-down pins should not be left floating.
MS0118-E-00
2001/11
-6-
ASAHI KASEI
[AK4584]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS, PVSS=0V; Note 1)
Parameter
Power Supplies:
Analog
Digital
PLL
Output Buffer
|AVSS – DVSS|
(Note 2)
|AVSS – PVSS|
(Note 2)
Input Current, Any Pin Except Supplies
Analog Input Voltage (VREF, LIN, RIN pins)
Digital Input Voltage 1 (Except RX1-4, BICK, LRCK pins)
Digital Input Voltage 2 (RX1-4 pins)
Digital Input Voltage 3 (BICK, LRCK pins)
Ambient Temperature (powered applied)
Storage Temperature
Symbol
AVDD
DVDD
PVDD
TVDD
∆GND1
∆GND2
IIN
VINA
VIND1
VIND2
VIND3
Ta
Tstg
min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−10
−65
max
6.0
6.0
6.0
6.0
0.3
0.3
±10
AVDD+0.3
DVDD+0.3
PVDD+0.3
TVDD+0.3
70
150
Units
V
V
V
V
V
V
mA
V
V
V
V
°C
°C
Note: 1. All voltages with respect to ground.
Note: 2. AVSS, DVSS and PVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS, PVSS=0V; Note 1)
Parameter
Power Supplies
Analog
(Note 3)
Digital
PLL
Output Buffer
Voltage Reference
(Note 4)
Symbol
AVDD
DVDD
PVDD
TVDD
VREF
min
4.75
4.75
4.75
2.7
3.0
typ
5.0
5.0
5.0
3.0
-
max
5.25
AVDD
AVDD
DVDD
AVDD
Units
V
V
V
V
V
Note: 1. All voltages with respect to ground.
Note: 3. The power up sequence between AVDD, DVDD, PVDD and TVDD is not critical.
Note: 4. Normally, VREF voltage is the same as AVDD voltage.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0118-E-00
2001/11
-7-
ASAHI KASEI
[AK4584]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, PVDD, TVDD=5.0V; AVSS=DVSS=PVSS=0V; VREF=AVDD; fs=44.1kHz, 96kHz,
192kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=10Hz ∼ 20kHz at fs=44.1kHz,
10Hz ∼ 40kHz at fs=96kHz; 10Hz ∼ 80kHz at fs=192kHz; unless otherwise specified)
Parameter
min
typ
max
Units
Input PGA Characteristics:
Input Voltage (Note 5) fs=44.1kHz, AIN=0.6 x AVDD
2.8
3.0
3.2
Vpp
fs=96kHz, AIN=0.62 x AVDD
2.9
3.1
3.3
Vpp
Input Resistance
5
10
15
kΩ
Step Size
0.2
0.5
0.8
dB
Gain Control Range
0
18
dB
ADC Analog Input Characteristics: IPGA=0dB
Resolution
24
Bits
S/(N+D)
(-0.5dBFS)
fs=44.1kHz
84
90
dB
fs=96kHz
80
88
dB
DR
(-60dBFS)
fs=44.1kHz, A-weighted
94
100
dB
fs=96kHz
88
96
dB
S/N
fs=44.1kHz, A-weighted
94
100
dB
fs=96kHz
88
96
dB
Interchannel Isolation
90
100
dB
Interchannel Gain Mismatch
0.2
0.5
dB
Gain Drift
20
ppm/°C
Power Supply Rejection
(Note 6)
50
dB
DAC Analog Output Characteristics:
Resolution
24
Bits
S/(N+D)
(0dBFS)
fs=44.1kHz
88
94
dB
fs=96kHz
86
92
dB
fs=192kHz
84
dB
DR
(-60dBFS)
fs=44.1kHz, A-weighted
98
104
dB
fs=96kHz
90
98
dB
fs=192kHz
85
dB
S/N
fs=44.1kHz, A-weighted
98
104
dB
fs=96kHz
90
98
dB
fs=192kHz
85
dB
Interchannel Isolation
90
100
dB
Interchannel Gain Mismatch
0.2
0.5
dB
Gain Drift
20
ppm/°C
Output Voltage
(Note 7)
2.8
3.0
3.2
Vpp
Load Resistance
5
kΩ
Load Capacitance
25
pF
Power Supply Rejection
(Note 6)
50
dB
Note: 5. Full scale (0dB) of the input voltage at IPGA = 0dB.
Note: 6. PSR is applied to AVDD, DVDD, PVDD and TVDD with 1kHz, 50mVpp.VREF pin is held a constant voltage.
Note: 7. This voltage is proportional to VREF. Vout = 0.6 x VREF.
MS0118-E-00
2001/11
-8-
ASAHI KASEI
[AK4584]
Parameter
min
typ
max
Units
23
12
24
36
35
18
36
54
mA
mA
mA
mA
10
10
10
100
100
100
µA
µA
µA
Power Supplies
Power Supply Current
Normal Operation (PDN = “H”)
AVDD
PVDD
(fs=44.1kHz)
DVDD+TVDD
(fs=44.1kHz)
(fs=96kHz)
Power-down mode (PDN = “L”)
(Note 8)
AVDD
PVDD
DVDD+TVDD
Note: 8. All digital input pins are held DVDD or DVSS.
S/PDIF RECEIVER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, PVDD=4.75 ∼ 5.25V; TVDD=2.7 ∼ 5.25V)
Parameter
Symbol
min
Input Resistance
Zin
Input Voltage
VTH
200
Input Hysteresis
VHY
Input Sample Frequency
fs
32
MS0118-E-00
typ
10
50
-
Max
192
Units
kΩ
mVpp
mV
kHz
2001/11
-9-
ASAHI KASEI
[AK4584]
FILTER CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD=4.75 ∼ 5.25V; TVDD=2.7 ∼ 5.25V; fs=44.1kHz; DEM=OFF)
Parameter
Symbol
min
typ
max
ADC Digital Filter (Decimation LPF):
19.76
PB
0
Passband
(Note 9)
±0.005dB
20.02
-0.02dB
20.20
-0.06dB
22.05
-6.0dB
Stopband
SB
24.34
Passband Ripple
PR
±0.005
Stopband Attenuation
SA
80
Group Delay
(Note 10)
GD
31
Group Delay Distortion
∆GD
0
ADC Digital Filter (HPF):
Frequency Response (Note 9) -3dB
FR
0.9
-0.5dB
2.7
-0.1dB
6.0
DAC Digital Filter:
Passband
(Note 9)
±0.01dB
PB
0
20.0
-6.0dB
22.05
Stopband
SB
24.1
Passband Ripple
PR
±0.005
Stopband Attenuation
SA
75
Group Delay
(Note 10)
GD
30
DAC Digital Filter + SCF + SMF:
FR
Frequency Response:
−0.1
0 ∼ 20.0kHz
−0.2
∼ 40kHz (Note 11)
−1.0
∼ 80kHz (Note 12)
Units
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
Hz
Hz
Hz
kHz
kHz
kHz
dB
dB
1/fs
dB
dB
dB
Note: 9. The passband and stopband frequencies scale with fs. For example, 20.02kHz at −0.02dB is 0.454 x fs.
Note: 10. The calculated delay time induced by digital filtering. This time is from the input of an analog signal
to the setting of 24bit data both channels to the ADC output register for ADC.
For DAC, this time is from setting the 24bit data of both channels on DAC input register to the output of an
analog signal.
Note: 11. fs = 96kHz.
Note: 12. fs = 192kHz.
MS0118-E-00
2001/11
- 10 -
ASAHI KASEI
[AK4584]
DC CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD=4.75 ∼ 5.25V; TVDD=2.7 ∼ 5.25V)
Parameter
Symbol
min
High-Level Input Voltage
(Except XTI pin)
VIH
2.2
(XTI pin)
VIH
70%DVDD
Low-Level Input Voltage
(Except XTI pin)
VIL
(XTI pin)
VIL
Input Voltage at AC Coupling (XTI pin, Note 13)
VAC
40%DVDD
High-Level Output Voltage
(Except TX1-3, DZF pins : Iout=−400µA)
VOH
TVDD-0.5
(TX1-3 pin :
Iout=−400µA)
VOH
DVDD-0.5
(DZF pin :
Iout=−400µA)
VOH
AVDD-0.5
Low-Level Output Voltage
(Iout=400µA)
VOL
TX Output Voltage Level
(Note 14)
VOH
0.4
Input Leakage Current
Iin
-
typ
Max
Units
-
-
V
V
-
0.8
30%DVDD
-
V
V
Vpp
0.5
-
0.5
0.6
±10
V
V
V
V
V
µA
Note: 13. In case of connecting capacitance to XTI pin. (Refer to Figure 3)
Note: 14. Refer to Figure 7.
MS0118-E-00
2001/11
- 11 -
ASAHI KASEI
[AK4584]
SWITCHING CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD=4.75 ∼ 5.25V, TVDD=2.7 ∼ 5.25V; CL=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
Crystal Resonator
External Clock
max
Units
Frequency
Frequency
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
11.2896
11.2896
0.4/fCLK
0.4/fCLK
24.576
36.864
MHz
MHz
ns
ns
MCKO1 Output
Frequency
Duty Cycle (Note 15)
fMCK
dMCK
11.2896
40
50
24.576
60
MHz
%
MCKO2 Output
Frequency
Duty Cycle
fMCK
dMCK
5.6448
40
50
18.432
60
MHz
%
fPLL
32
192
kHz
fsn
fsd
fsq
32
88.2
176.4
45
48
96
192
55
kHz
kHz
kHz
%
%
PLL Clock Recover Frequency
LRCK Frequency
Normal Speed Mode (DFS0=“0”, DFS1=“0”)
Double Speed Mode (DFS0=“1”, DFS1=“0”)
Quad Speed Mode (DFS0=“0”, DFS1=“1”)
Duty Cycle
Slave mode
Master mode
Audio Interface Timing
Slave mode
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
(Note 16)
BICK “↑” to LRCK Edge
(Note 16)
LRCK to SDTO (MSB) (Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
Master mode
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
50
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
81
33
33
20
20
20
20
20
20
64fs
50
−20
−20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
ns
ns
Note: 15. Duty cycle is not guaranteed when using the external clock input.
Note: 16. BICK rising edge must not occur at the same time as LRCK edge.
MS0118-E-00
2001/11
- 12 -
ASAHI KASEI
[AK4584]
Parameter
Symbol
min
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
40
40
150
50
50
tPD
tPDV
150
Reset Timing
PDN Pulse Width
(Note 17)
RSTADN “↑” to SDTO valid (Note 18)
typ
516
max
Units
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
Note: 17. The AK4584 can be reset by bringing PDN pin = “L”.
Note: 18. This cycle is the number of LRCK rising edges from the RSTADN bit.
MS0118-E-00
2001/11
- 13 -
ASAHI KASEI
[AK4584]
„ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
fMCK
MCKO
50%TVDD
dMCK
dMCK
Clock Timing
MS0118-E-00
2001/11
- 14 -
ASAHI KASEI
[AK4584]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSD
tLRS
SDTO
50%TVDD
tSDH
tSDS
VIH
SDTI
VIL
Audio Interface Timing (Slave mode)
LRCK
50%TVDD
tMBLR
dBCK
BICK
50%TVDD
tBSD
SDTO
50%TVDD
tSDH
tSDS
VIH
SDTI
VIL
Audio Interface Timing (Master mode)
MS0118-E-00
2001/11
- 15 -
ASAHI KASEI
[AK4584]
VIH
CSN
VIL
tCSS
tCCKL
tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
VIH
VIL
Hi-Z
CDTO
WRITE/READ Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
CDTO
VIL
D2
D1
D0
VIH
VIL
Hi-Z
WRITE Data Input Timing
MS0118-E-00
2001/11
- 16 -
ASAHI KASEI
[AK4584]
VIH
CSN
VIL
VIH
CCLK
CDTI
VIL
A1
VIH
A0
VIL
tDCD
Hi-Z
CDTO
D7
D6
50%TVDD
READ Data Output Timing 1
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
VIL
tCCZ
CDTO
D2
D1
D0
Hi-Z
50%TVDD
READ Data Output Timing 2
MS0118-E-00
2001/11
- 17 -
ASAHI KASEI
[AK4584]
VIH
CSN
VIL
tPDV
50%TVDD
SDTO
tPD
PDN
VIL
Power Down & Reset Timing
MS0118-E-00
2001/11
- 18 -
ASAHI KASEI
[AK4584]
OPERATION OVERVIEW
„ Internal Signal Path
The input source of the DAC and SDTO can be switched between the outputs of the ADC, SDTI or the DIR. The input
source of the DIT can be switched between the outputs of ADC or SDTI. There is also a through/bypass path from the DIR
to the DIT that can be also selected. The Switch Names (DAC1-0 etc) in Figure 1 correspond to the register bits that control
the switch function. Refer to “Register Definitions” (Address 08H).
DAC1-0
HPF
IPGA ADC DATT
DEM
DATT
DAC
SMUTE
PCM1-0
SDTI
SDTO
DIR
DIT1-0
DIT
DIT1-0
Figure 1. Connection between Input Sources & Output Sources
„ Clock Operation Mode
The CM1-0 bits determine the clock source of the AK4584; either PLL or X’tal (including external clock source, Table 1).
In mode 2, the clock source is switched automatically from PLL to X’tal when the PLL loses lock. In mode 3, the clock
source is fixed to the external X’tal input, however the PLL is also operating enabling the monitoring of recovered data
such as C bits. For mode 2 and mode 3, the frequency of the X’tal should be different from that of the recovered frequency
from PLL. When XTL1-0 bits are “11”, the X’tal oscillator is stopped in mode 0. The default values are “01” for CM1-0
bits.
Since the signal path is not changed automatically when changing the CM1-0 bits, the output source should be selected by
changing register 08H.
Mode
0
1
2
3
CM1
0
0
CM0
0
1
UNLOCK
PLL
X’tal
Clock Source
ON
PLL
∗
OFF
ON
X’tal
0
ON
ON
PLL
1
0
1
ON
ON
X’tal
1
1
ON
ON
X’tal
ON: Oscillation (Power-up), OFF: STOP (Power-down)
∗ : OFF at XTALE pin = “L” and XTL1-0 bits = “11”, ON at others
Table 1. Clock Operation Mode Select
MS0118-E-00
Default
2001/11
- 19 -
ASAHI KASEI
[AK4584]
„ Master Clock Output
The AK4584 has two clock outputs, MCKO1 and MCKO2. These clocks are derived from either the recovered clock or the
X'tal oscillator. In PLL mode, the master clock output frequencies (MCKO1, MCKO2) are set by OCKS1-0 bits as shown
in Table 2. In the X’tal mode or external clock mode, the frequency of MCKO1 is the same as the X’tal or external clock.
MCKO2 outputs a half frequency of MCKO1 (Table 3). MCKO1 output can be disabled by the DMCK pin. MCKO1
output is “L” (Disable) when the DMCK pin = “H”, MCKO1 output is normal output when the DMCK pin = “L”. In PLL
mode, mode 0 does not support 96kHz. The default values of OCKS1-0 bits are “01”
Mode
0
1
2
3
OCKS1
0
0
1
1
OCKS0
0
1
0
1
MCKO1
512fs
256fs
128fs
64fs
MCKO2
256fs
128fs
64fs
32fs
fs
∼ 48kHz
∼ 96kHz
∼ 192kHz
∼ 192kHz
Default
Table 2. Master Clock Output Frequency Select (PLL Mode)
X’tal
MCKO1
MCKO2
11.2896MHz
11.2896MHz
5.6448MHz
12.288MHz
12.288MHz
6.144MHz
24.576MHZ
24.576MHz
12.288MHz
Table 3. Master Clock Output Frequency Select (X’tal Mode)
Table 4 is a connection example when using AK5394 and AK4394 in slave mode.
AK5394
AK4394
Clock Output
MCKO2
MCKO1
Normal Speed
256fs
512fs
Double Speed
128fs
256fs
Quad Speed
64fs
128fs
Table 4. Clock Select for AK5394 & AK4394
MS0118-E-00
2001/11
- 20 -
ASAHI KASEI
[AK4584]
„ System Clock
The master clock (MCLK) is derived from either a X’tal oscillator or the recovered clock from the AK4584’s PLL. MCLK
frequency is set by ICKS1-0 bits (Table 5) for X’tal mode and external clock mode. The sampling speed (normal, double
or quad speed modes) is selected by DFS1-0 bits (Table 6). The ADC is powered down during quad speed mode.
When using a X’tal oscillator, external loading capacitors between XTI/XTO pins and DVSS are required. An external
clock can be input to the XTI pin with the XTO pin left floating. The input can accept both CMOS and AC coupled clock
sources with 40%DVDD.
In slave mode, the LRCK clock input must be synchronized with MCLK, however the phase is not critical. All external
clocks (MCLK, BICK and LRCK) must be present unless PDN pin = “L” or all parts are powered down by control register,
otherwise excessive current may be produced by the internal dynamic logic. In master mode, the master clock (MCLK)
must be provided by a X’tal oscillator, external clock or internal PLL unless PDN pin = “L”.
Mode
0
1
2
3
MCLK
Normal
Double
Quad
ICKS1
ICKS0
(DFS1-0 = “00”) (DFS1-0 = “01”) (DFS1-0 = “10”)
0
0
256fs
N/A
N/A
0
1
384s
N/A
N/A
1
0
512fs
256fs
128fs
1
1
768fs
384fs
192fs
Table 5. Master Clock Input Frequency Select (X’tal Mode)
MCLK
Normal
256fs
384fs
512fs
768fs
MCLK
Normal
256fs
384fs
512fs
768fs
DFS1
DFS0
0
0
1
1
0
1
0
1
fs=44.1kHz
11.2896MHz
16.9344MHz
22.5792MHz
33.8688MHz
Sampling Rate
Normal Speed
Double Speed
Quad Speed
N/A
Table 6. Sampling Speed
MCLK
Double
128fs
192fs
256fs
384fs
Default
fs=88.2kHz
N/A
N/A
22.5792MHz
33.8688MHz
Default
MCLK
Quad
64fs
96fs
128fs
192fs
MCLK
MCLK
Double
Quad
fs=48kHz
fs=96kHz
12.288MHz
128fs
N/A
64fs
18.432MHz
192fs
N/A
96fs
24.576MHz
256fs
24.576MHz
128fs
36.864MHz
384fs
36.864MHz
192fs
Table 7. Master Clock Frequencies example
fs=176.4kHz
N/A
N/A
22.5792MHz
33.8688MHz
fs=192kHz
N/A
N/A
24.576MHz
36.864MHz
* X’tal mode supports from 11.2896MHz to 24.576MHz.
* Frequencies over 24.576MHz are supported in external clock mode only.
MS0118-E-00
2001/11
- 21 -
ASAHI KASEI
[AK4584]
„ Clock Source
(1) Using X’tal
XTI
AK4584
XTO
Figure 2. X’tal mode
- Note: External capacitance depends on the crystal oscillator (Typ. 10-40pF)
(2) Using external clock
XTI
C
External
Clock
XTI
External
Clock
XTO
AK4584
XTO
AK4584
Figure 3. (a) External Clock mode
Figure 3. (b) External Clock Mode
(Input : CMOS Level)
(Input : ≥ 40%DVDD)
- Note: Input clock must not exceed DVDD.
(3) Clock Operation Mode 0
XTI
AK4584
XTO
Figure 4. Off mode
„ 192kHz Clock Recovery
The on chip low jitter PLL has a wide lock range from 32kHz to 192kHz and a lock time of less than 20ms. The AK4584
also has a sampling frequency detect function that works by performing either a clock comparison against the X’tal
oscillator or by using the channel status. The AK4584 detects the following sampling frequencies : 32kHz, 44.1kHz,
48kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz. The PLL loses lock when the incoming sync interval is incorrect.
MS0118-E-00
2001/11
- 22 -
ASAHI KASEI
[AK4584]
„ Biphase Input
Four receiver inputs (RX1-4 pins) are available. Each input includes an unbalanced input amplifier and can accept input
signals of 200mV or more.
IPS1
0
0
1
1
IPS0
Input Data
0
RX1
1
RX2
0
RX3
1
RX4
Table 8. Recovery Data Select
Default
„ Biphase Output
The AK4584 can output the through data from the digital receiver inputs (RX1-4) to the TX1/2 pins. The TX3 pin can
output transmitter data (SDTI data, A/D converted data and through output from the DIR). The OPS1-0 bits can select the
source of the output from the TX1-2 pins and the DIT1-0 bits can select the source of the TX3 pin.
The first 5 bytes of C-bit (Channel Status) can be controlled by CT39-CT0 bits in the control registers. When CT0 bit = “0”
(consumer mode), bits20-23 (Audio channel) cannot be controlled directly. When the TCH bit is “1”, the AK4584 outputs
“1000” as CT20-23 bits for left channel and outputs “0100” at CT20-23 bits for right channel automatically. When TCH
bit is “0”, the AK4584 outputs “0000”.
The U bit (User Data) output has two formats. When the UDIT bit is “0”, the U bit is always “L”. When UDIT bit is “1”,
the recovered U bits are passed through the DIT (DIR-DIT loop mode of U bit). This mode is only available when the PLL
is locked. When PLL is unlocked, the U bit is set to “L”.
OPS1
0
0
1
1
DIT1
0
0
1
1
OPS0
Output Data
0
RX1
1
RX2
0
RX3
1
RX4
Table 9. Output Data Select for TX1/2
DIT0
Input Source
0
ADC
1
SDTI
0
DIR
1
N/A
Table 10. Output Data Select for TX3
Default
Default
Note: When the PLL loses lock, the V bit (Validity) data in the block immediately following loss-of-lock may not be
accurate. Disregard this data and use the following data blocks.
MS0118-E-00
2001/11
- 23 -
ASAHI KASEI
[AK4584]
„ Biphase signal input/output circuit
0.1uF
RX
75Ω
Coax
75Ω
AK4584
Figure 5. Consumer Input Circuit (Coaxial Input)
Note 1: Coax input only : if a coupling level to this input from the next RX input line
pattern exceeds 50mV, an incorrect operation may occur. In this case, it is possible to
lower the coupling level by adding this decoupling capacitor.
Note 2: Ground of the RCA connector and terminator should be connected to PVSS of the AK4584
with low impedance on PC board.
Optical Receiver
Optical
Fiber
470
RX
O/E
AK4584
Figure 6. Consumer Input Circuit (Optical Input)
When using coaxial input, the input level of the RX line is small. Care must be taken to reduce, crosstalk among RX input
lines by inserting a shield pattern between them.
The AK4584 includes a TX output buffer. The output level is 0.5V, +/−20% using the external resistor network shown
below. The T1 in Figure 7 is a 1:1 transformer.
330
TX
75Ω cable
100
DVSS
T1
Figure 7. TX External Resistor Network
MS0118-E-00
2001/11
- 24 -
ASAHI KASEI
[AK4584]
„ Sampling Frequency and Pre-emphasis Detection
The AK4584 has two methods for detecting the sampling frequency. The sampling frequency is detected by comparing the
recovered clock to the X’tal oscillator, and the detected frequency is reported on FS3-0 bits. XTL1-0 bits can select
reference X’tal frequency (Table 11). When XTL1-0 bits = “11” and XTALE pin = “L”, X’tal oscillator is stopped and the
sampling frequency is detected by the channel status sampling frequency information. The detected frequency is reported
on FS3-0 bits. The default values of FS3-0 bits are “0000”.
XTL1
0
0
1
1
XTL0
X’tal Frequency
0
11.2896MHz
1
12.288MHz
0
24.576MHz
1
Use channel status
Table 11. Reference X’tal Frequency
Except XTL1-0 bits=“11”
Register Output
fs
FS3
FS2
FS1
FS0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
Clock comparison
± 3%
± 3%
± 3%
± 3%
± 3%
± 3%
± 3%
Table 12. fs Information
44.1kHz
Reserved
48kHz
32kHz
88.2kHz
96kHz
176.4kHz
192kHz
Default
XTL1-0 bits=“11”
Consumer Mode
Pro Mode
(Note 1)
Byte3
Byte0
Byte4
Bit3,2,1,0
Bit7,6
Bit6,5,4,3
0000
01
0000
0001
(others)
0000
0010
10
0000
0011
11
0000
(1000)
00
1010
(1010)
00
0010
(1100)
00
1011
(1110)
00
0011
Note 1. In consumer mode, Byte3 Bit3-0 are copied to FS3-0.
The pre-emphasis information is detected and reported on the PEM bit. This information is extracted from channel 1
(default). It can be switched to channel 2 via the CS12 bit in the control register.
Byte0
Bit3,4,5
0
OFF
≠ 0X100
1
ON
0X100
Table 13. PEM in Consumer Mode
PEM bit
Byte0
Bit2,3,4
OFF
≠ 100
ON
100
Table 14. PEM in Pro Mode
PEM bit
0
1
Pre-emphasis
Pre-emphasis
MS0118-E-00
2001/11
- 25 -
ASAHI KASEI
[AK4584]
„ Error Handling
The following eight events will cause the INT1-0 pins go to “H”.
(1) UNOCK: “1” when PLL goes to an UNLOCK state.
The AK4584 loses lock when the distance between two preambles is not correct or when those preambles
are not correct.
(2) PAR:
“1” when parity error or biphase coding error is detected.
Updated every sub-frame cycle. Reading this register resets it.
(3) AUTO:
“1” when Non-Linear PCM Bit Stream is detected.
(4) DTSCD: “1” when DTS-CD Bit Stream is detected.
(5) AUDION:“1” when the “AUDIO” bit in recovered channel status indicates “1”.
(6) PEM:
“1” when “PEM” in recovered channel status indicates “1”.
Updated every block cycle.
(7) V:
“1” when validity flag is detected.
(8) FS:
“1” when FS3-0 bits change.
FS3-0 bits are changed, FS bit is “H” during 1 sub-frame.
The contents of FS3-0 bits are the frequency detection result by fs-bit of C-bit or X’tal (refer to Table 12),
this is compared last data every one block. Reading this register resets it.
INT1-0 pins output the OR’ed signal among those eight factors. However, each mask bit can mask each factor. When a bit
masks a factor, the factor does not affect INT1-0 pins operation (those masks do not affect those registers (UNLOCK,
PAR, etc.) themselves). Once INT0 pin goes to “H”, it maintains “H” for 1024 cycles (this value can be changed by
EFH1-0 bits) after the all factors are removed. Once the PAR bit and the FS bit go to “1”, it holds “1” until reading the
register.
While the AK4584 loses lock, the channel status bits are not updated and hold the previous data. In its initial state, INT0
pin outputs the OR’ed signal between UNLOCK and PAR bits. INT1 pin outputs the OR’ed signal among AUTO,
DTSCD, AUDION and VDIR bits.
INT1-0 pins are “L” when the PLL is OFF.
UNLOCK
1
0
0
0
0
0
0
0
PAR
x
1
0
0
0
0
0
0
AUTO
x
x
1
x
x
x
x
x
Register
DTSCD AUDION PEM VDIR
FS
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
x
x
x
x
x
1
x
x
x
x
x
1
x
x
x
x
x
1
x
x
x
x
x
1
Table 15. Error Handling (x : Don’t Care)
MS0118-E-00
Pin
SDTO
“L”
Previous Data
Output
Output
Output
Output
Output
Output
TX
Output
Output
Output
Output
Output
Output
Output
Output
2001/11
- 26 -
ASAHI KASEI
Error
(UNLOCK, PAR,..)
[AK4584]
(Error)
INT0 pin
Hold Time (max: 4096/fs)
INT1 pin
Hold Time = 0
Register
(PAR, FS)
Hold ”1”
Reset
Register
(others)
Command
MCKO,BICK,LRCK
(UNLOCK)
READ 0EH
Free Run
(fs: around 20kHz)
MCKO,BICK,LRCK
(except UNLOCK)
SDTO
(UNLOCK)
SDTO
(PAR error)
Previous Data
SDTO
(others)
Normal Operation
Figure 8. INT0/1 pin Timing
MS0118-E-00
2001/11
- 27 -
ASAHI KASEI
[AK4584]
PDN pin = "L" to "H"
Initialize
Read 0EH
No
INT0/1 pin = "H"
Yes
Release
Muting
Mute DAC Output
Read 0EH
Each Error Handling
No
INT0/1 pin = "H"
Yes
Figure 9. Error Handling Sequence Example
„ Non-PCM (AC-3, MPEG, etc.) and DTS-CD Bitstream Detection
The AK4584 has a Non-PCM steam auto-detect function. When the 32-bit mode Non-PCM preamble based on Dolby’s
“AC-3 Data Stream in IEC60958 Interface” is detected, the AUTO bit goes to “1”. The 96-bit sync code consists of
0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the AUTO to “1”. Once the
AUTO is set “1”, it will remain “1” until 4096 frames pass through the chip without an additional sync pattern being
detected. When those preambles are detected, the burst preambles Pc and Pd that follow the sync codes are stored to
registers. The AK4584 also has DTS-CD bit stream auto-detection. When the AK4584 detects DTS-CD bit streams, the
DTSCD bit goes to “1”. If the next sync code does not appear within 4096 flames, the DTSCD bit goes to “0” until when
the AK4584 detects the stream again.
MS0118-E-00
2001/11
- 28 -
[AK4584]
ASAHI KASEI
„ Audio Interface Format
Five serial modes are supported as shown in Table 16, and are selected by the DIF2-0 bits. In all modes, the serial data is
in MSB first, 2’s compliment format. The SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the
rising edge. The audio interface supports both master and slave modes. In master mode, BICK and LRCK are output with
the BICK frequency fixed to 64fs and the LRCK frequency fixed to fs.
When the format is equal or less than 20-bit (mode 0-1), LSBs in the sub-frame are truncated. In mode 2-4, the last 4LSBs
are auxiliary data (see Figure 10).
Mode 2, 3, 4 in SDTI input formats can be used for 16-20bit data by zeroing the unused LSBs.
sub-frame of IEC60958
0
3 4
preamble
7 8
11 12
27 28 29 30 31
Aux.
V
LSB
MSB
MSB
LSB
U
C
P
0
23
AK4584 Audio Data (SDTO, MSB First)
Figure 10. Bit Structure
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
SDTO
SDTI
24bit, MSB justified
16bit, LSB justified
24bit, MSB justified
20bit, LSB justified
24bit, MSB justified
24bit, MSB justified
24bit, I2S Compatible 24bit, I2S Compatible
24bit, MSB justified
24bit, LSB justified
Table 16. Audio Data Format
MS0118-E-00
LRCK
H/L
H/L
H/L
L/H
H/L
BICK
≥ 32fs
≥ 40fs
≥ 48fs
≥ 48fs
≥ 48fs
Default
2001/11
- 29 -
[AK4584]
ASAHI KASEI
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
23 22 21
15 14 13 12 11 10 9 8 23 22 21
15 14 13 12 11 10 9 8 23
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 2 3
17 18 19 20
23 22 21
7 6 5 4 3
31 0 1 2 3
17 18 19 20
31 0 1
BICK(64fs)
SDTO(o)
SDTI(i)
Don't Care
15 14 13 12
7 6 5 4 3
23 22 21
1 0
Don't Care
15 14 13 12
23
2 1 0
SDTO-23:MSB, 0:LSB
SDTI-15:MSB, 0:LSB
Lch Data
Rch Data
Figure 11. Mode 0 Timing
LRCK
0 1 2
12 13
24
12 13
31 0 1 2
24
31 0 1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
12 11
Don't Care
0
19
8
23 22
1 0
12 11
Don't Care
19
0
8
23
1 0
SDTO-23:MSB, 0:LSB
SDTI-19:MSB, 0:LSB
Lch Data
Rch Data
Figure 12. Mode 1 Timing
LRCK
0 1 2
20 21 22 23 24
31 0 1 2
20 21 22 23 24
31 0 1
BICK(64fs)
SDTO(o)
23 22
4 3 2 1 0
23 22
4 3 2 1 0
23
SDTI(i)
23 22
4 3 2 1 0 Don't Care 23 22
4 3 2 1 0
Don't Care 23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 13. Mode 2 Timing
MS0118-E-00
2001/11
- 30 -
[AK4584]
ASAHI KASEI
LRCK
21 22 23 24 25
0 1 2 3
0 1 2
21 22 23 24 25
0 1
BICK(64fs)
SDTO(o)
23 22
4 3 2 1 0
23 22
4 3 2 1 0
SDTI(i)
23 22
4 3 2 1 0
Don't Care 23 22
4 3 2 1 0
Don't Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 14. Mode 3 Timing
LRCK
0 1 2
24
8 9
31 0 1 2
8 9
24
31 0 1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
16 15
Don't Care
0
23
8
23 22
1 0
16 15
Don't Care
23
0
8
23
1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 15. Mode 4 Timing
MS0118-E-00
2001/11
- 31 -
[AK4584]
ASAHI KASEI
„ Master Mode and Slave Mode
The M/S pin selects between master and slave modes. M/S pin = “H” is master mode, M/S pin = “L” is slave mode. In
master mode, MCKO, BICK and LRCK are output. In slave mode, only MCKO is output from the AK4584 and dividing
MCKO externally provides BICK and LRCK.
MCKO1/2
BICK, LRCK
MCKO1 = Output
BICK = Input
Slave Mode
MCKO2 = Output
LRCK = Input
MCKO1 = Output
BICK = Output
Master Mode
MCKO2 = Output
LRCK = Output
Table 17. Master mode/Slave mode
„ Relationship Clock operation and Power down
When the AK4584 is powered down, the XTALE pin controls the master clock output. The DMCK pin disables the
MCKO1 output.
PDN pin
M/S pin
XTALE pin
CM1-0 bit
L
L
H
L
L
Default
Fixed to
“01”
H
H
L
H
Don’t Care
H
Available
MCKO1/2
MCKO1 = L
MCKO2 = L
MCKO1 = Output1)
MCKO2 = Output1)
MCKO1 = L
MCKO2 = L
MCKO1 = Output1)
MCKO2 = Output1)
MCKO1 = Output2)
MCKO2 = Output2)
BICK, LRCK
DIR, DIT, CODEC
BICK = Input
LRCK = Input
Power Down
BICK = L
LRCK = L
Power Down
BICK = Input
LRCK = Input
BICK = Output
LRCK = Output
Normal Operation
Table 18. Clock Operation
Note 1) : Since the DIR is powered down, a X’tal oscillator or the external clock can be selected for the clock source.
Note 2) : CM1-0 bits select the clock source. When changing between modes, there is a possibility
that the master clock output (MCKO) stops momentarily.
Note 3) : When PDN pin = “L”, XTI pin is fixed to “L” when XTALE pin = “L” and the external clock is not AC coupled.
„ Digital High Pass Filter
The ADC has a digital high-pass filter for DC offset cancellation. The cut-off frequency of the HPF is 0.9Hz at fs =
44.1kHz and also scales with sampling rate (fs).
MS0118-E-00
2001/11
- 32 -
[AK4584]
ASAHI KASEI
„ Input Volume
The AK4584 includes two channel-independent analog volumes (IPGA), each with 37 levels in 0.5dB increments. These
are located in front of the ADCs while digital volume controls (IATT) with 128 levels (including MUTE) are located after
the ADCs. Control of both of these volumes setting is handled the same register address. When the MSB of the register is
“1”, the IPGA changes and when the MSB = “0” the IATT changes.
The IPGA is an analog volume control that improves the S/N ratio compared with digital volume controls (Table 19).
Level changes only occur during zero-crossings to minimize switching noise. Channel independent zero-crossing detection
is used. If there is no zero-crossings, then the level will change after a time-out. The time-out period scales with fs. The
periods of 256/fs, 512/fs, 1024/fs and 2048/fs are selected by ZTM1-0 bits in normal speed mode. If new value is written
to the IPGA register before IPGA changes at the zero crossing or time-out, the previous value becomes invalid. The timer
(channel independent) for time-out is reset and the timer restarts for new IPGA value. The ZCEI bit in the control register
enable zero-crossing detection.
The IATT is a pseudo-log volume that is linear-interpolated internally. When changing the level, the transition between
ATT values has 8031 levels and is done by soft changes (zero crossings), eliminating any switching noise.
Input Gain Setting
0dB
+6dB
fs=44.1kHz, A-weight
100dB
98dB
Table 19. PGA+ADC S/N
ZTM1
0
0
1
1
+18dB
90dB
ZTM0
Normal Speed
Double Speed
0
256/fs
512/fs
1
512/fs
1024/fs
0
1024/fs
2048/fs
1
2048/fs
4096/fs
Table 20. Zero Crossing Timeout
Default
„ De-emphasis Control
The DAC includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. This filter corresponds to three frequencies
(32kHz, 44.1kHz, 48kHz). This setting is done via control register (DEM1-0 bits). This filter is always OFF at double
speed and quad speed modes.
DEM1
0
0
1
1
DEM0
Mode
0
44.1kHz
1
OFF
Default
0
48kHz
1
32kHz
Table 21. De-emphasis Control
„ Output Volume
The AK4584 includes channel independent digital output volumes (ATT) with 256 levels at 0.5dB steps including MUTE.
These volumes are in front of the DAC and can attenuate the input data from 0dB to −127dB and mute. When changing the
level, the transitions are executed by soft changes (zero crossings), eliminating any switching noise.
MS0118-E-00
2001/11
- 33 -
[AK4584]
ASAHI KASEI
„ Soft Mute Operation
Soft mute operation is performed in the digital domain of the DAC input. When the SMUTE bit goes to “1”, the output
signal is attenuated by −∞ during 1024 LRCK cycles. When the SMUTE bit is returned to “0”, the mute is cancelled and
the output attenuation gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK
cycles after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for
changing the signal source without stopping the signal transmission.
Soft mute function is independent of the output volume and cascade connected between both functions.
SMUTE
1024/fs
1024/fs
(1)
0dB
(3)
Attenuation
-∞
GD
(2)
GD
LOUT / ROUT
(4)
8192/fs
D Z F p in
Figure 16. Soft mute function and Zero detection function
(1) The output signal is attenuated by −∞ during 1024 LRCK cycles (1024/fs).
(2) Analog output delay from the digital input is called the group delay (GD).
(3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.
(4) When the input data of both channels is continuously zeros for 8192 LRCK cycles, DZF pin goes to “H”. DZF pin
immediately goes to “L” if input data of any channel is not zero after going DZF pin = “H”.
„ Zero Detection Function
The AK4584 DAC has a L/R channel-dependent zeros detect function. When the input data at both channels is
continuously zero for 8192 LRCK cycles, the DZF pin of each channel goes to “H”. The DZF pin of each channel
immediately goes to “L” if the input data of each channel is not zero after DZF pin = “H”. Zero detect function can be
disabled by the DZFE bit. In this case, the DZF pin is always “L”.
When the PDN pin is “L”, the DZF pin is always “L”. If PDN pin = “L” → “H”, DZF pin goes from “L” → “H”. When the
PWVRN bit is “0”, the DZF pin is “L”.
If the DZF pin goes to “H” when the RSTDAN bit becomes “0”, then the AK4584 is reset after 4~5/fs and goes to “L” at
6~7/fs after the RSTDAN bit becomes “1”. If after the RSTDAN bit becomes “0” and within 5/fs, the RSTDAN bit
becomes “1”, then the AK4584 will not be properly reset.
If the DZF pin goes to “H” when the PWDAN bit becomes “0”, then the AK4584 is reset after 4~5/fs and goes to “L” at
6~7/fs after the PWDAN bit becomes “1”. If the PWDAN bit becomes “0”, and the PWDAN bit becomes “1” within 5/fs,
then the AK4584 will not be properly reset.
When PDN pin becomes “H” and the PWDAN bit becomes “1” and the RSTDAN bit becomes “1”, 8192 counts start after
1/fs for the zero detect function.
MS0118-E-00
2001/11
- 34 -
[AK4584]
ASAHI KASEI
„ Reset and Power Down
The AK4584 has both a power-down mode for all circuits by pulling the PDN pin or a partial power-down mode that is
enabled via an internal register (see Table 22). The AK4584 should be reset once by bringing PDN pin = “L” upon
power-up.
PDN pin
L
H
PWDITN
x
0
x
x
x
x
x
PWVRN
x
x
0
x
x
x
x
PWADN PWDAN CM1-0
Function
x
x
x
All Power-down
x
x
x
DIT Power-down
x
x
x
VREF Power-down
0
x
x
ADC Power-down
x
0
x
DAC Power-down
x
x
00
X’tal Power-down
x
x
01
PLL Power-down
Table 22. Reset & Power Down
Register Initialization
Yes
No
No
No
No
No
No
„ Serial Control Interface
The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The data
on this interface consists of Chip address (2bits, C1/0 are fixed to “00”), Read/Write (1bit), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked
out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low
transition of CSN. For read operations, the CDTO output goes to high impedance after a low-to-high transition of CSN.
The maximum speed of CCLK is 5MHz. The chip address is fixed to “00”. The access to the chip address except for “00”
is invalid. PDN pin = “L” resets the registers to their default values.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
C1
C0
R/W
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
CCLK
CDTI
Write
Hi-Z
CDTO
CDTI
C1
C0
R/W
A4
A3
A2
A1
A0
Read
CDTO
Hi-Z
Hi-Z
C1 - C0 : Chip Address (Fixed to "00")
R/W :
READ / WRITE ("1" : WRITE, "0" : READ)
A4 - A0 : Register Address
D7 - D0 : Control Data
Figure 17. Control I/F Timing
MS0118-E-00
2001/11
- 35 -
[AK4584]
ASAHI KASEI
„ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
Register Name
Power Down Control
Reset Control
Clock & Format Control
Deem & Volume Control
Lch IPGA Control
Rch IPGA Control
Lch OATT Control
Rch OATT Control
In/Out Source Control
Clock Mode Control
DIR Control
DIT Control
INT0 Mask
INT1 Mask
Receiver Status 0
Receiver Status 1
RX Channel Status Byte 0
RX Channel Status Byte 1
RX Channel Status Byte 2
RX Channel Status Byte 3
RX Channel Status Byte 4
TX Channel Status Byte 0
TX Channel Status Byte 1
TX Channel Status Byte 2
TX Channel Status Byte 3
TX Channel Status Byte 4
Burst Preamble Pc Byte 0
Burst Preamble Pc Byte 1
Burst Preamble Pd Byte 0
Burst Preamble Pd Byte 1
D7
0
0
0
MSDTO
IPGL7
IPGR7
ATTL7
ATTR7
0
OCKS1
0
0
MAT0
MAT1
AUTO
0
CR7
CR15
CR23
CR31
CR39
CT7
CT15
CT23
CT31
CT39
PC7
PC15
PD7
PD15
D6
0
0
0
SMUTE
IPGL6
IPGR6
ATTL6
ATTR6
0
OCKS0
CS12
0
MDTS0
MDTS1
DTSCD
0
CR6
CR14
CR22
CR30
CR38
CT6
CT14
CT22
CT30
CT38
PC6
PC14
PD6
PD14
D5
0
0
0
DZFE
IPGL5
IPGR5
ATTL5
ATTR5
DAC1
ICKS1
OPS1
TX3E
MAN0
MAN1
AUDION
0
CR5
CR13
CR21
CR29
CR37
CT5
CT13
CT21
CT29
CT37
PC5
PC13
PD5
PD13
D4
TEST
0
DIF2
ZCEI
IPGL4
IPGR4
ATTL4
ATTR4
DAC0
ICKS0
OPS0
TX2E
MV0
MV1
VDIR
0
CR4
CR12
CR20
CR28
CR36
CT4
CT12
CT20
CT28
CT36
PC4
PC12
PD4
PD12
D3
PWDITN
0
DIF1
ZTM1
IPGL3
IPGR3
ATTL3
ATTR3
PCM1
CM1
IPS1
TX1E
MPE0
MPE1
PEM
FS3
CR3
CR11
CR19
CR27
CR35
CT3
CT11
CT19
CT27
CT35
PC3
PC11
PD3
PD11
D2
PWVRN
0
DIF0
ZTM0
IPGL2
IPGR2
ATTL2
ATTR2
PCM0
CM0
IPS0
UDIT
MUL0
MUL1
UNLOCK
FS2
CR2
CR10
CR18
CR26
CR34
CT2
CT10
CT18
CT26
CT34
PC2
PC10
PD2
PD10
D1
PWADN
RSTADN
DFS1
DEM1
IPGL1
IPGR1
ATTL1
ATTR1
DIT1
XTL1
EFH1
VDIT
MPR0
MPR1
PAR
FS1
CR1
CR9
CR17
CR25
CR33
CT1
CT9
CT17
CT25
CT33
PC1
PC9
PD1
PD9
D0
PWDAN
RSTDAN
DFS0
DEM0
IPGL0
IPGR0
ATTL0
ATTR0
DIT0
XTL0
EFH0
TCH
MFS0
MFS1
FS
FS0
CR0
CR8
CR16
CR24
CR32
CT0
CT8
CT16
CT24
CT32
PC0
PC8
PD0
PD8
PDN = “L” resets the registers to their default values.
„ Control Register Setup Sequence
When the PDN pin goes from “L” to “H” upon power-up etc., the AK4584 will be ready for normal operation by the next
sequence. In this case, all control registers are set to initial values and the AK4584 is in the reset state.
(1) Set the clock mode and the audio data interface mode.
(2) Cancel the reset state by setting RSTADN bit or RSTDAN bit to “1”. Refer to Control Register (01H).
(3) ADC output and DAC output should be muted externally until canceling each reset state, since in master mode there
is a possibility that the frequency and duty cycle of LRCK and BICK outputs may become distorted.
The clock mode should be changed after setting RSTADN bit and RSTDAN bit to “0”. At that time, the ADC and DAC
outputs should be muted externally since in master mode, there is a possibility that the frequency and duty of LRCK and
BICK outputs may become distorted.
MS0118-E-00
2001/11
- 36 -
[AK4584]
ASAHI KASEI
„ Register Definitions
Addr
00H
Register Name
Power Down Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
TEST
R/W
1
D3
PWDITN
R/W
1
D2
PWVRN
R/W
1
D1
PWADN
R/W
1
D0
PWDAN
R/W
1
PWDAN: DAC Power Down
0: Power down
1: Power up
“0” powers down only the DAC section and then places LOUT and ROUT immediately to a high-Z state. The
OATTs also go to “FFH”. But the contents of all register are not initialized and enabled to write to the registers.
After exiting the power down mode, the OATTs fade in the setting value of the control register (06H & 07H).
The analog output should be muted externally as some pop noise may occur when entering to and exiting from
this mode.
PWADN: ADC Power Down
0: Power down
1: Power up
“0” powers down only the ADC section and then the SDTO goes “L” immediately. The IPGAs also go “00H”.
But the contents of all register are not initialized and enabled to write to the registers. After exiting the power
down mode, the IPGAs fade in the setting value of the control register (04H & 05H). At that time, ADC output
“0” during first 516 LRCK cycles.
PWVRN: VREF Power Down
0: Power down
1: Power up
“0” powers down all sections and then both ADC and DAC do not operate. The contents of all register are not
initialized and enabled to write to the registers. When PWADN bit and PWDAN bit go “0” and PWVRN bit
goes “1”, only VREF section can be powered up.
PWDITN: DIT Power Down
0: Power down
1: Power up
“0” powers down only the DIT section. Therefore, TX3 pin output is disabled . TX1 pin and TX2 pin can
output the biphase signal. The contents of all register are not initialized and enabled to write to the registers.
TEST: TEST bit
Must be fixed to “1”
MS0118-E-00
2001/11
- 37 -
[AK4584]
ASAHI KASEI
Addr
01H
Register Name
Reset Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
0
RD
0
D1
RSTADN
R/W
0
D0
RSTDAN
R/W
0
RSTDAN: DAC Reset
0: Reset
1: Normal Operation
“0” resets the internal timing and immediately drives the LOUT and ROUT to the VCOM voltage. The OATTs
go to “FFH”. The contents of all registers are unaffected but are write-enabled. After exiting the power down
mode, the OATTs fade in based on the values of the control registers (06H & 07H). The analog outputs should
be muted externally as some pop noise may occur when entering to and exiting from this mode.
RSTADN: ADC Reset
0: Reset
1: Normal Operation
“0” resets the internal timing and SDTO immediately goes to “L”. The IPGAs go to “00H”. The contents of all
registers are unaffected but are write-enabled. After exiting the power down mode, the IPGAs fade in based on
the values of the control registers (04H & 05H). At that time, ADC output is “0” during first 516 LRCK cycles.
Addr
02H
Register Name
Clock and Format Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
DIF2
R/W
0
D3
DIF1
R/W
1
D2
DIF0
R/W
0
D1
DFS1
R/W
0
D0
DFS0
R/W
0
DFS1-0: Sampling Speed Control (see Table 6)
Initial values are “00”.
DIF2-0:
Audio Data Interface Modes (see Table 16)
Initial values are “010” (24bit MSB justified for both ADC and DAC).
MS0118-E-00
2001/11
- 38 -
[AK4584]
ASAHI KASEI
Addr
03H
Register Name
Deem and Volume Control
R/W
Default
D7
MSDTO
R/W
0
D6
SMUTE
R/W
0
D5
DZFE
R/W
0
D4
ZCEI
R/W
1
D3
ZTM1
R/W
1
D2
ZTM0
R/W
0
D1
DEM1
R/W
0
D0
DEM0
R/W
1
DEM1-0: De-emphasis Response (see Table 21)
Initial values are “01” (OFF).
ZTM1-0: Zero Crossing Time-out Period Select (see Table 20)
Initial values are “10” (1024/fs).
ZCEI: ADC IPGA Zero Crossing Enable
0: Input PGA gain changes occur immediately
1: Input PGA gain changes occur only on zero-crossing or after timeout.
Initial value is “1” (Enable).
DZFE: Data Zero Detect Enable
0: Disable
1: Enable
Zero detect function can be disabled by the DZFE bit. In this case, DZF pin is always “L”.
Initial value is “0” (Disable).
SMUTE: DAC Input Soft Mute Control
0: Normal operation
1: DAC outputs soft-muted
The soft mute is independent of the output ATT and performed digitally.
MSDTO: SDTO Mute Control
0: Disable
1: Enable
When MSDTO bit is “1”, SDTO outputs “L”. Initial value is “0” (Disable).
MS0118-E-00
2001/11
- 39 -
[AK4584]
ASAHI KASEI
Addr
04H
05H
Register Name
Lch IPGA Control
Rch IPGA Control
R/W
Default
D7
IPGL7
IPGR7
R/W
0
D6
IPGL6
IPGR6
R/W
1
D5
IPGL5
IPGR5
R/W
1
D4
IPGL4
IPGR4
R/W
1
D3
IPGL3
IPGR3
R/W
1
D2
IPGL2
IPGR2
R/W
1
D1
IPGL1
IPGR1
R/W
1
D0
IPGL0
IPGR0
R/W
1
IPGL/R7-0: ADC Input Gain Level (see Table 23)
Initial value is “7FH” (0dB).
Digital ATT with 128 levels operates when writing data of less than 7FH. This ATT is a linear ATT with 8032
levels internally and these levels are assigned to pseudo-log data with 128 levels. The transition between ATT
values has 8032 levels and is done by soft changes. For example, when ATT changes from 127 to 126, the
internal ATT value decreases from 8031 to 7775, one by one every fs cycle. It takes 8031 cycles
([email protected]=44.1kHz) from 127 to 0 (Mute).
The IPGAs are set to “00H” when PDN pin goes “L”. After returning to “H”, the IPGAs fade into the initial
value, “7FH” in 8031 cycles.
The IPGAs are set to “00H” when PWADN bit goes “0”. After returning to “1”, the IPGAs fade into the current
value. The ADC output is “0” during the first 516 cycles.
The IPGAs are set to “00H” when RSTADN bit goes to “0”. After returning to “1”, the IPGAs fade into the
current value. The ADC output is “0” during the first 516 cycles.
MS0118-E-00
2001/11
- 40 -
[AK4584]
ASAHI KASEI
Data
255 - 165
164
163
162
:
130
129
128
127
126
125
:
112
111
110
:
96
95
94
:
80
79
78
:
64
63
62
:
48
47
46
:
32
31
30
:
16
15
14
:
5
4
3
2
1
0
Internal
(DATT)
8031
7775
7519
:
4191
3999
3871
:
2079
1983
1919
:
1023
975
943
:
495
471
455
:
231
219
211
:
99
93
89
:
33
30
28
:
10
8
6
4
2
0
Gain (dB)
Step width (dB)
+18
+18
+17.5
+17
:
+1.0
+0.5
0
0
−0.28
−0.57
:
−5.65
−6.06
−6.34
:
−11.74
−12.15
−12.43
:
−17.90
−18.32
−18.61
:
−24.20
−24.64
−24.94
:
−30.82
−31.29
−31.61
:
−38.18
−38.73
−39.11
:
−47.73
−48.55
−49.15
:
−58.10
−60.03
−62.53
−66.05
−72.07
MUTE
0.5
0.5
0.5
0.5
0.5
0.5
0.28
0.29
:
0.51
0.41
0.28
:
0.52
0.41
0.28
:
0.53
0.42
0.29
:
0.54
0.43
0.30
:
0.58
0.46
0.32
:
0.67
0.54
0.38
:
0.99
0.83
0.60
:
1.58
1.94
2.50
3.52
6.02
IPGA
Analog volume with 0.5dB step
IATT
External 128 levels are converted to internal
8032 linear levels of DATT. Internal DATT
soft-changes between data.
DATT=2^m x (2 x l + 33) – 33
m: MSB 3-bits of data
l: LSB 4-bits of data
Table 23. IPGA Code Table
MS0118-E-00
2001/11
- 41 -
[AK4584]
ASAHI KASEI
Addr
06H
07H
Register Name
Lch OATT Control
Rch OATT Control
R/W
Default
D7
ATTL7
ATTR7
R/W
1
D6
ATTL6
ATTR6
R/W
1
D5
ATTL5
ATTR5
R/W
1
D4
ATTL4
ATTR4
R/W
1
D3
ATTL3
ATTR3
R/W
1
D2
ATTL2
ATTR2
R/W
1
D1
ATTL1
ATTR1
R/W
1
D0
ATTL0
ATTR0
R/W
1
ATTL/R7-0: DAC OATT Level (see Table 24)
Initial value is “FFH” (0dB).
The transition from initial to final levels has 7425 levels. It takes 7424/fs ([email protected]=44.1kHz)
from FFH(0dB) to 00H(MUTE). If PDN pin goes to “L”, the ATTs are initialized to FFH.
The ATTs are FFH when PWDAN bit = “0”. When PWDAN bit returns to “1”, the ATTs fade to their current
value.
The ATTs are FFH when RSTDAN bit = “0”. When RSTDAN bit returns to “1”, the ATTs fade to their current
value.
Digital attenuation is independent of the soft mute function.
ATTL/R7-0
Attenuation
FFH
0dB
FEH
−0.5dB
FDH
−1.0dB
FCH
−1.5dB
:
:
:
:
02H
−126.5dB
01H
−127dB
00H
MUTE (−∞)
Table 24. OATT Code Table
MS0118-E-00
2001/11
- 42 -
[AK4584]
ASAHI KASEI
Addr
08H
Register Name
In/Out Source Control
R/W
Default
DIT1-0:
D7
0
RD
0
D6
0
RD
0
D5
DAC1
R/W
0
D4
DAC0
R/W
0
D3
PCM1
R/W
0
D2
PCM0
R/W
0
D1
DIT1
R/W
0
D0
DIT0
R/W
0
Input Selector for DIT (see Table 10)
Initial values are “00”. When DIT1-0 bits are “10”, the selected input is sent to the TX3 output.
PCM1-0: Input Selector for SDTO (see Table 25)
Initial values are “00”.
PCM1
0
0
1
1
PCM0
Input Source
0
ADC
1
SDTI
0
DIR
1
N/A
Table 25. Input Selector for SDTO
Default
DAC1-0: Input Selector for DAC (see Table 26)
Initial values are “00”.
DAC1
0
0
1
1
Addr
09H
Register Name
Clock Mode Control
R/W
Default
DAC0
Input Source
0
ADC
1
SDTI
0
DIR
1
N/A
Table 26. Input Selector for DAC
D7
OCKS1
R/W
0
D6
OCKS0
R/W
1
D5
ICKS1
R/W
0
D4
ICKS0
R/W
0
Default
D3
CM1
R/W
0
D2
CM0
R/W
1
D1
XTL1
R/W
0
D0
XTL0
R/W
0
XTL1-0: X’tal Frequency Select (see Table 11)
Initial values are “00”.
CM1-0:
Master Clock Operation Mode Select (see Table 1)
Initial values are “01”.
ICKS1-0: Master Clock Input Frequency Select in X’tal Mode (see Table 5)
Initial values are “00”.
* 768fs is supported external clock mode.
OCKS1-0: Master Clock Output Frequency Select in PLL Mode (see Table 2)
Initial values are “01”.
MS0118-E-00
2001/11
- 43 -
[AK4584]
ASAHI KASEI
Addr
0AH
Register Name
DIR Control
R/W
Default
D7
0
RD
0
D6
CS12
R/W
0
D5
OPS1
R/W
0
D4
OPS0
R/W
0
D3
IPS1
R/W
0
D2
IPS0
R/W
0
D1
EFH1
R/W
0
D0
EFH0
R/W
1
EFH1-0: Interrupt 0 Pin Hold Count Select (Table 27)
Initial values are “01”.
LRCK of Table 27 is DIR’s LRCK, the hold time scales with 1/fs.
EFH1
0
0
1
1
IPS1-0:
EFH0
Hold Count
0
512LRCK
1
1024LRCK
0
2048LRCK
1
4096LRCK
Table 27. Hold Count Select
Default
Input Recovery Data Select (see Table 8)
Initial values are “00”.
OPS1-0: Output Through Data Select for TX1/2 (see Table 9)
Initial values are “00”.
CS12:
Channel Status Select
0: Channel 1
1: Channel 2
Selects which channel status is used to derive C-bit buffers, AUDION, PEM, FS.
MS0118-E-00
2001/11
- 44 -
[AK4584]
ASAHI KASEI
Addr
0BH
Register Name
DIT Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
TX3E
R/W
1
D4
TX2E
R/W
1
D3
TX1E
R/W
1
D2
UDIT
R/W
1
D1
VDIT
R/W
0
D0
TCH
R/W
0
TCH: Channel Number Select for DIT
0: Don’t care (bit20-23 = 0000)
1: Stereo (bit20-23 = 1000 : L channel, bit20-23 = 0100 : R channel)
Automatically sets the channel number of the DIT (bit20-23 of C-bit). Initial value is “0”.
For consumer mode (CT0 bit = “0”), CT20-23 bits of address 17H cannot be controlled directly.
VDIT: V-bit Control for DIT
0: Valid
1: Invalid
Initial value is “0”.
UDIT: U-bit Control for DIT
0: U-bit is fixed to “0”.
1: Recovered U-bit is used for DIT. (Loop mode for U-bit)
When DIR is unlocked , U-bit is “0”. Initial value is “1”.
TX1E: TX1 Output Enable
0: Disable, TX1 outputs “L”.
1: Enable
Initial value is “1”.
TX2E: TX2 Output Enable
0: Disable, TX2 outputs “L”.
1: Enable
Initial value is “1”.
TX3E: TX3 Output Enable
0: Disable, TX3 outputs “L”.
1: Enable
Initial value is “1”.
MS0118-E-00
2001/11
- 45 -
[AK4584]
ASAHI KASEI
Addr
0CH
Register Name
INT0 Mask
R/W
Default
D7
MAT0
R/W
1
D6
MDTS0
R/W
1
D5
MAN0
R/W
1
D4
MV0
R/W
1
D3
MPE0
R/W
1
D2
MUL0
R/W
0
D1
MPR0
R/W
0
D0
MFS0
R/W
1
MFS0:
Mask Enable for FS Bit
0: Mask disable
1: Mask enable
MPR0:
Mask Enable for PAR Bit
0: Mask disable
1: Mask enable
MUL0:
Mask Enable for UNLOCK Bit
0: Mask disable
1: Mask enable
MPE0:
Mask Enable for PEM Bit
0: Mask disable
1: Mask enable
MV0:
Mask Enable for VDIR Bit
0: Mask disable
1: Mask enable
MAN0: Mask Enable for AUDION Bit
0: Mask disable
1: Mask enable
MDTS0: Mask Enable for DTSCD Bit
0: Mask disable
1: Mask enable
MAT0:
Mask Enable for AUTO Bit
0: Mask disable
1: Mask enable
MS0118-E-00
2001/11
- 46 -
[AK4584]
ASAHI KASEI
Addr
0DH
Register Name
INT1 Mask
R/W
Default
D7
MAT1
R/W
0
D6
MDTS1
R/W
0
D5
MAN1
R/W
0
D4
MV1
R/W
0
D3
MPE1
R/W
1
D2
MUL1
R/W
1
D1
MPR1
R/W
1
D0
MFS1
R/W
1
MFS1:
Mask Enable for FS Bit
0: Mask disable
1: Mask enable
MPR1:
Mask Enable for PAR Bit
0: Mask disable
1: Mask enable
MUL1:
Mask Enable for UNLOCK Bit
0: Mask disable
1: Mask enable
MPE1:
Mask Enable for PEM Bit
0: Mask disable
1: Mask enable
MV1:
Mask Enable for VDIR Bit
0: Mask disable
1: Mask enable
MAN1: Mask Enable for AUDION Bit
0: Mask disable
1: Mask enable
MDTS1: Mask Enable for DTSCD Bit
0: Mask disable
1: Mask enable
MAT1:
Mask Enable for AUTO Bit
0: Mask disable
1: Mask enable
MS0118-E-00
2001/11
- 47 -
[AK4584]
ASAHI KASEI
Addr
0EH
Register Name
Receiver Status 0
R/W
Default
D7
AUTO
RD
0
D6
DTSCD
RD
0
D5
AUDION
RD
0
D4
VDIR
RD
0
D3
PEM
RD
0
D2
UNLOCK
RD
0
D1
PAR
RD
0
D0
FS
RD
0
FS:
Sampling Frequency Status
0: No change
1: Change
This bit is “1” when FS3-0 bits are changed. When this address is read, this bit is reset.
PAR: Parity Error or Bi-phase Error Status
0: No error
1: Error
This bit is “1” if a Parity Error or Biphase Error is detected in the sub-frame.
When this address is read, this bit is reset.
UNLOCK: PLL Lock Status
0: Lock
1: Unlock
When this address is read, this bit is not reset.
PEM: Pre-emphasis Bit Output
0: OFF
1: ON
This bit is made by encoding the channel status bits.
When this address is read, this bit is not reset.
VDIR: Validity Bit
0: Valid
1: Invalid
When this address is read, this bit is not reset.
AUDION: Audio Bit Output
0: Audio
1: Non audio
This bit is made by encoding channel status bits.
When this address is read, this bit is not reset.
DTSCD: DTS-CD Auto Detect
0: No detect
1: Detect
When this address is read, this bit is not reset.
AUTO:
Non-PCM Auto Detect
0: No detect
1: Detect
When this address is read, this bit is not reset.
MS0118-E-00
2001/11
- 48 -
[AK4584]
ASAHI KASEI
Addr
0FH
Register Name
Receiver Status 1
R/W
Default
FS3-0:
Addr
10H
11H
12H
13H
14H
Register Name
RX Channel Status Byte 0
RX Channel Status Byte 1
RX Channel Status Byte 2
RX Channel Status Byte 3
RX Channel Status Byte 4
R/W
Default
Addr
1AH
1BH
1CH
1DH
D5
0
RD
0
D4
0
RD
0
D3
FS3
RD
0
D2
FS2
RD
0
D1
FS1
RD
0
D0
FS0
RD
0
D7
CR7
CR15
CR23
CR31
CR39
D6
CR6
CR14
CR22
CR30
CR38
D5
CR5
CR13
CR21
CR29
CR37
D4
CR4
CR12
CR20
CR28
CR36
D3
CR3
CR11
CR19
CR27
CR35
D2
CR2
CR10
CR18
CR26
CR34
D1
CR1
CR9
CR17
CR25
CR33
D0
CR0
CR8
CR16
CR24
CR32
D2
CT2
CT10
CT18
CT26
CT34
D1
CT1
CT9
CT17
CT25
CT33
D0
CT0
CT8
CT16
CT24
CT32
D1
PC1
PC9
PD1
PD9
D0
PC0
PC8
PD0
PD8
RD
Not Initialized
Receiver Channel Status Byte 4-0
Register Name
TX Channel Status Byte 0
TX Channel Status Byte 1
TX Channel Status Byte 2
TX Channel Status Byte 3
TX Channel Status Byte 4
R/W
Default
CT39-0:
D6
0
RD
0
Sampling Frequency Detection (see Table 12)
Initial values are “0000”.
CR39-0:
Addr
15H
16H
17H
18H
19H
D7
0
RD
0
D7
CT7
CT15
CT23
CT31
CT39
D6
CT6
CT14
CT22
CT30
CT38
D5
CT5
CT13
CT21
CT29
CT37
D4
CT4
CT12
CT20
CT28
CT36
D3
CT3
CT11
CT19
CT27
CT35
R/W
0
Transmitter Channel Status Byte 4-0
In consumer mode (CT0 bit = “0”), bit20-23 (Audio channel) cannot be controlled directly.
Register Name
Burst Preamble Pc Byte 0
Burst Preamble Pc Byte 1
Burst Preamble Pd Byte 0
Burst Preamble Pd Byte 1
R/W
Default
D7
PC7
PC15
PD7
PD15
PC15-0:
Burst Preamble Pc Byte 1-0
PD15-0:
Burst Preamble Pd Byte 1-0
D6
PC6
PC14
PD6
PD14
D5
PC5
PC13
PD5
PD13
D4
PC4
PC12
PD4
PD12
D3
PC3
PC11
PD3
PD11
D2
PC2
PC10
PD2
PD10
RD
Not Initialized
MS0118-E-00
2001/11
- 49 -
[AK4584]
ASAHI KASEI
SYSTEM DESIGN
Figure 18 shows the system connection diagram. An evaluation board is available which demonstrates application circuits,
the optimum layout, power supply arrangements and measurement results.
[Measurement Condition]
• TVDD = 3.0V, Master mode, XTALE = “H”, DMCK = “L”
10µ
S/PDIF
sources
Analog 5V
5.1
Shield
10µ
0.1µ
13k
42
41
40
39
38
37
36
35
34
RX1
PVSS
R
PVDD
LIN
RIN
VREF
AVDD
AVSS
PDN Control
43
TEST1
Shield
44
RX2
Shield
1 TEST2
ROUT 33
2 RX3
LOUT 32
3 NC
VCOM 31
5.1
4 RX4
DZF 30 0.1µ
5 PDN
M/S 29
AK4584
6 INT0
MUTE
MUTE
2.2µ
LRCK 28
DMCK
MCKO1 23
XTI/MCKI
11 CSN
XTO
MCKO2 24
TVDD
10 CCLK
DVSS
SDTO 25
DVDD
9 CDTO
TX3
SDTI 26
XTALE
8 CDTI
TX2
BICK 27
TX1
7 INT1
TEST3
µP
0.1µ
12
13
14
15
16
17
18
19
20
21
22
Audio
DSP
0.1µ 0.1µ
C
10µ
S/PDIF out
C
10µ
Digital 3V
Note:
- X’tal Oscillation circuit is specified from 11.2896MHz to 24.576MHz. Capacitors “C” depend on the X’tal.
- AGND and DGND of the AK4584 should be distributed separately from the ground of external digital devices
(MPU, DSP etc.).
- When LOUT/ROUT drives a capacitive load, resistors should be added in series between LOUT/ROUT
and capacitive load.
- All input pins except pull-down pin (TEST1,2 pins) should not be left floating.
- To prevent coupling of TEST1, TEST2 and the RX signals, NC pins are connected PVSS.
Figure 18. Typical Connection Diagram
MS0118-E-00
2001/11
- 50 -
[AK4584]
ASAHI KASEI
1. Grounding and Power Supply Decoupling
The AK4584 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and PVDD are
usually supplied from the analog supply in the system. Alternatively if AVDD, DVDD and PVDD are supplied separately,
the power up sequence is not critical. TVDD is a power supply pin to interface with external ICs and is supplied from the
digital supply in the system. AVSS, DVSS and PVSS of the AK4584 must be connected to analog ground plane.
System analog ground and digital ground should be connected together near to where the supplies are brought onto the
printed circuit board. Decoupling capacitors should be as near to the AK4584 as possible, with the small value ceramic
capacitor being the nearest.
2. Voltage Reference Inputs
The differential voltage between VREF and AVSS sets the analog input/output range. VREF pin is normally connected to
AVDD with a 0.1µF ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 2.2µF parallel with
a 0.1µF ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be
drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VREF and VCOM pins in order
to avoid unwanted coupling into the AK4584.
3. Analog Inputs
ADC inputs are single-ended and the input resistance is 10kΩ (typ). The input signal range scales with the supply voltage
and nominally 0.6 x VREF Vpp (typ). Usually the input signal is AC coupled with capacitor. The cut-off frequency is fc =
1/(2πRC). The AK4584 can accept input voltages from AVSS to AVDD. The ADC output data format 2’s compliment.
The internal HPF removes the DC offset.
The AK4584 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of
64fs. The AK4584 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
4. Analog Outputs
The analog outputs are single-ended and centered around the VCOM voltage. The input signal range scales with the supply
voltage, nominally 0.6 x VREF Vpp. The DAC input data format is 2’s complement. The output voltage is a positive full
scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is 0V for 000000H(@24bit).
The internal analog filters remove most of the out-of-band noise generated by the DAC’s delta-sigma modulator.
5. XTI pin and XTO pin
(1) C depends on the X’tal (typ. 10 ∼ 40pF).
(2) When an external clock is supplied, the XTO pin is left floating and the clock source is connected to the XTI pin. The
input voltage should not exceed DVDD. When applying a CMOS level signal to the XTI pin, when XTALE pin = “L”
and PDN pin = “L”, the XTI pin is fixed to “L”. The means that the XTI pin can accept a CMOS level clock as well as
TTL level clock. The only restriction to this is the clock high level must be equal to or greater than 40% DVDD, not to
exceed DVDD. The low value of the clock must be 30% DVDD or lower, not to drop below DGND.
(3) When the XTI and the XTO pins are not used, leave the XTO pin floating and connect the XTI pin to DVSS.
MS0118-E-00
2001/11
- 51 -
[AK4584]
ASAHI KASEI
PACKAGE
44pin LQFP (Unit: mm)
12.80 ± 0.30
1.70max
10.00
33
0 ~ 0.2
23
34
12.80 ± 0.30
0.80
10.00
22
12
44
1
11
0.17 ± 0.05
0.37 ± 0.10
0° ~ 10°
0.15
0.60 ± 0.20
„ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0118-E-00
2001/11
- 52 -
[AK4584]
ASAHI KASEI
MARKING
AKM
AK4584VQ
XXXXXXX
1
XXXXXXX :
Date Code Identifier (7 digits)
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or
other official approval under the law and regulations of the country of export pertaining to customs and
tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
MS0118-E-00
2001/11
- 53 -