AKM AKD4631

ASAHI KASEI
[AKD4631-VN]
AKD4631-VN
AK4631-VN Evaluation board Rev.0
GENERAL DESCRIPTION
AKD4631-VN is an evaluation board for the AK4631VN, 16bit mono CODEC with MIC/SPK amplifier. The
AKD4631-VN can evaluate A/D converter and D/A converter separately in addition to loopback mode
(A/D → D/A). AKD4631-VN also has the digital audio interface and can achieve the interface with digital
audio systems via opt-connector.
„ Ordering guide
AKD4631-VN
--- Evaluation board for AK4631VN
(Cable for connecting with printer port of IBM-AT, compatible PC and control
software are packed with this. This control software does not support Windows NT.)
FUNCTION
• DIT/DIR with optical input/output
• BNC connector for an external clock input
• 10pin Header for serial control mode
5V
AVDD DVDD SVDD
3.3V
Regulator
GND
MIC-Jack
Control Data
MIC
10pin Header
BEEP/MIN/MOUT
AOUT
DSP
AK4631VN
10pin Header
SPK-Jack
AK4114
Opt In
Opt Out
Clock
Gen
Figure 1. AKD4631-VN Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
Evaluation Board Manual
„ Operation sequence
1) Set up the power supply lines.
1-1) When AVDD, DVDD, SVDD, and VCC are supplied from the regulator. (AVDD, DVDD, SVDD, and
VCC jack should be open.). See “Other jumper pins set up (page 10)”. <default>
[REG]
[AVDD]
[DVDD]
[SVDD]
[VCC]
[AVSS]
[AGND]
[DGND]
(red )
(orange)
(orange)
(blue)
(orenge)
(black)
(black)
(black)
= 5V
= open
= open
= open
= open
= 0V
= 0V
= 0V
: 3.3V is supplied to AVDD of AK4631-VN from regulator.
: 3.3V is supplied to DVDD of AK4631-VN from regulator.
: 3.3V is supplied to SVDD of AK4631-VN from regulator.
: 3.3V is supplied to logic block from regulator.
: for analog ground
: for analog ground
: for logic ground
1-2) When AVDD, DVDD, SVDD, and VCC are not supplied from the regulator. (AVDD, DVDD, SVDD, and
VCC jack should be junction.) See “Other jumper pins set up (page 10)”.
[REG]
[AVDD]
[DVDD]
[SVDD]
[VCC]
[AVSS]
[AGND]
[DGND]
(red)
(orange)
(orange)
(blue)
(orenge)
(black)
(black)
(black)
= “REG” jack should be open.
= 2.6 ∼ 3.6V : for AVDD of AK4631-VN (typ. 3.3V)
= 2.6 ∼ 3.6V : for DVDD of AK4631-VN (typ. 3.3V)
= 2.6 ∼ 5.25V : for SVDD of AK4631-VN (typ. 3.3V, 5.0V)
= 2.6 ∼ 3.6V : for logic (typ. 3.3V)
= 0V
: for analog ground
= 0V
: for analog ground
= 0V
: for logic ground
Each supply line should be distributed from the power supply unit.
AVDD and DVDD must be same voltage level.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK4631VN and AK4114 should be reset once bringing SW1, 2 “L” upon power-up.
„ Evaluation mode
In case of AK4631VN evaluation using AK4114, it is necessary to correspond to audio interface format for
AK4631VN and AK4114. About AK4631VN’s audio interface format, refer to datasheet of AK4631VN.
About AK4114’s audio interface format, refer to Table 2 in this manual.
Applicable Evaluation Mode
(1) Evaluation of loop-back mode (A/D → D/A) : PLL, Master Mode (Default)
(2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI
pin)
(3) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or
FCK pin)
(4) Evaluation of using DIR of AK4114 (opt-connector) : EXT, Slave Mode
(5) Evaluation of using DIT of AK4114 (opt-connector) : EXT, Slave Mode
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
(1) Evaluation of loop-back mode (A/D → D/A) : PLL, Master Mode (Default)
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4631-VN should be set to “0”.
X’tal of 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz can be set in X2. X’tal of 11.2896MHz
(Default) is set on the AKD4631-VN. Set “No.8 of SW3” to “H”.
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) through a RCA
connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1)
and R26 should be properly selected in order to much the output impedance of the clock generator.
JP6
JP17
XTE
MCKI
JP18
MKFS
JP21
MCLK_SEL
XTL DIR EXT 256fs 512fs 1024fs MCKO
b) Set up jumper pins of BICK clock
Output frequency (16fs/32fs/64fs) of BICK should be set by “BCKO1-0 bit” in the AK4631-VN.
There is no necessity for set up JP19.
JP20
BICK
INV
THR
JP29
BICK_INV
JP27
BICK
DIR ADC
INV
THR
JP19
BICK_SEL
64fs 32fs 16fs EXT
c) Set up jumper pins of FCK clock
JP28
FCK
JP22
FCK_SEL
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4631VN is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the
following.
JP30
JP26
4631_SDTI
SDTI
DIR
ADC
DAC/LOOP ADC
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
(2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin)
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4631VN should be set to “0”.
X’tal of 11.2896MHz (Default) is set on the AKD4631-VN. In this case, the AK4631VN corresponds to PLL
reference clock of 12.2896MHz. In this evaluation mode, the output clock from MCKO-pin of the AK4631VN
is supplied to a divider (U3: 74VHC4040), BICK and FCK clocks are generated by the divider. Then “MCKO
bit” in the AK4631VN should be set to “1”. When an external clock through a RCA connector (J8: EXT/BICK)
is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly
selected in order to match the output impedance of the clock generator.
JP17
XTE
JP6
MCKI
JP18
MKFS
JP21
MCLK_SEL
XTL DIR EXT 256fs 512fs 1024fs MCKO
b) Set up jumper pins of BICK clock
JP20
BICK
INV
JP27
BICK
DIR ADC
THR
JP29
BICK_INV
INV
THR
JP19
BICK_SEL
64fs 32fs 16fs EXT
c) Set up jumper pins of FCK clock
JP22
FCK_SEL
JP28
FCK
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4631-VN is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the
following.
JP30
JP26
4631_SDTI
SDTI
DIR
ADC
DAC/LOOP ADC
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
(3) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or FCK
pin)
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4631VN should be set to “1”. JP6 (MCKI) should be open.
b) Set up jumper pins of BICK clock
When an external clock through a RCA connector J8 (EXT/BICK) is supplied, select EXT on JP19
(MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to match the
output impedance of the clock generator.
JP17
XTE
JP20
BICK
JP21
MCLK_SEL
XTL DIR EXT
INV
THR
JP29
BICK_INV
JP27
BICK
DIR ADC
INV
THR
In this evaluation mode, the selected clock from JP21 (MCLK_SEL) is supplied to a divider (U3: 74VHC4040),
BICK and FCK clocks are generated by the divider. Input frequency of master clock is set up in turn “256fs”,
“512fs”, “1024fs” from left.
JP18
MKFS
JP18
MKFS
JP18
MKFS
256fs 512fs 1024fs MCKO
256fs 512fs 1024fs MCKO
256fs 512fs 1024fs MCKO
And input frequency of BICK is set up in turn “16fs”, “32fs”, “64fs” from left.
JP19
BICK_SEL
JP19
BICK_SEL
JP19
BICK_SEL
64fs 32fs 16fs EXT
64fs 32fs 16fs EXT
64fs 32fs 16fs EXT
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
c) Set up jumper pins of FCK clock
When an external clock through a RCA connector J9 (FCK) is supplied, select EXT on JP22 (FCK_SEL). JP24
(EXT2) and R27 should be properly selected in order to match the output impedance of the clock generator.
JP22
FCK_SEL
JP28
FCK
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4631VN is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the
following.
JP30
JP26
4631_SDTI
SDTI
DIR
ADC
<KM077301>
DAC/LOOP ADC
2005/01
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ASAHI KASEI
[AKD4631-VN]
(4) Evaluation of using DIR of AK4114 (opt-connector) : EXT, Slave Mode
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4631VN should be set to “0”.
JP6
MCKI
JP21
MCLK_SEL
JP18
MKFS
XTL DIR EXT
256fs 512fs 1024fs
JP17
XTE
b) Set up jumper pins of BICK clock
JP20
BICK
INV
THR
JP29
BICK_INV
JP27
BICK
DIR ADC
INV
JP19
BICK_SEL
THR 64fs 32fs 16fs EXT
c) Set up jumper pins of FCK clock
JP24 (EXT2) and R27 should be properly selected in order to match the output impedance of the clock generator.
JP28
FCK
DIR
JP22
FCK_SEL
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When D/A converter of the AK4631-VN is evaluated by using DIR of AK4114, the jumper pins should be set to
the following.
JP30
JP26
4631_SDTI
SDTI
DIR
DAC/LOOP ADC
ADC
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
(5) Evaluation of using DIT of AK4114 (opt-connector) : EXT, Slave Mode
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4631-VN should be set to “0”.
JP6
MCKI
JP21
MCLK_SEL
JP18
MKFS
XTL DIR EXT
256fs 512fs 1024fs
JP17
XTE
b) Set up jumper pins of BICK clock
JP20
BICK
INV
THR
JP27
BICK
DIR ADC
JP29
BICK_INV
INV
JP19
BICK_SEL
THR 64fs 32fs 16fs EXT
c) Set up jumper pins of FCK clock
JP24 (EXT2) and R27 should be properly selected in order to match the output impedance of the clock generator.
JP28
FCK
DIR
JP22
FCK_SEL
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When A/D converter of the AK4631-VN is evaluated by using DIR of AK4114, the jumper pins should be set to
the following.
JP30
JP26
4631_SDTI
SDTI
DIR
DAC/LOOP ADC
ADC
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
„ DIP Switch set up
[SW3] (MODE) : Mode Setting of AK4631-VN and AK4114
ON is “H”, OFF is “L”.
No.
Name
ON (“H”)
OFF (“L”)
1
DIF0
AK4114 Audio Format Setting
2
DIF1
See Table 2
3
CM2
Clock Operation Mode select
4
CM0
See Table 3
5
CM1
6
OCKS0
Master Clock Frequency Select
See Table 4
7
OCKS1
8
M/S
Master mode
Slave mode
Note. When the AK4631-VN is evaluated Master mode, “No.8 of SW3” is set to “H”.
Table 1. Mode Setting for AK4631-VN and AK4114
Resistor setting
for AK4631-VN Audio
Interface Format
Setting for AK4114 Audio Interface Format
DIF1 bit
DIF0 bit
DIF0
DIF1
DIF2
0
1
L
L
L
24bit, Left justified
16bit, Right justified
1
0
L
L
H
24bit, Left justified
24bit, Left justified
1
1
H
L
H
DAUX
SDTO
2
Default
2
24bit, I S
24bit, I S
Note. When the AK4631-VN is evaluated by using DIR/DIT of AK4114, “No.8 of SW3” is set to “L”.
Table 2. Setting for AK4114 Audio Interface Format
Mode
0
1
CM1
0
0
CM0
0
1
UNLOCK
PLL
X'tal
Clock source SDTO
ON
ON(Note)
PLL
RX
OFF
ON
X'tal
DAUX
0
ON
ON
PLL
RX
2
1
0
Default
1
ON
ON
X'tal
DAUX
3
1
1
ON
ON
X'tal
DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-down)
Note : When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is off.
Default setting is recommended.
Table 3. Clock Operation Mode select
No.
0
2
OCKS1
0
1
MCKO1
256fs
512fs
MCKO2
256fs
256fs
X’tal
256fs
512fs
Default
Table 4. Master Clock Frequency Select (Stereo mode)
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
„ Other jumper pins set up
1. JP1 (GND)
OPEN
SHORT
: Analog ground and Digital ground
: Separated.
: Common. (The connector “DGND” can be open.) <Default>
2. JP2 (AIN)
OPEN
SHORT
: Connection between MICOUT pin and AIN pin of the AK4631VN.
: No connection.
: Connection. <Default>
3. JP3 (AVDD_SEL) : AVDD of the AK4631VN
REG
: AVDD is supplied from the regulator (“AVDD” jack should be open). < Default >
AVDD
: AVDD is supplied from “AVDD ” jack.
4. JP9 (DVDD_SEL) : DVDD of the AK4631VN
AVDD
: DVDD is supplied from “AVDD”. < Default >
DVDD
: DVDD is supplied from “DVDD ” jack.
5. JP10 (LVC_SEL) : Logic block of LVC is selected supply line.
DVDD
: Logic block of LVC is supplied from “DVDD”. < Default >
VCC
: Logic block of LVC is supplied from “VCC ” jack.
6. JP11 (VCC_SEL) : Logic block is selected supply line.
LVC
: Logic is supplied from supply line of LVC. < Default >
VCC
: Logic block of LVC is supplied from “VCC ” jack.
7. JP4 (SVDD_SEL) : SVDD of the AK4631VN
REG
: SVDD is supplied from the regulator (“SVDD” jack should be open). < Default >
SVDD
: SVDD is supplied from “SVDD ” jack.
8. JP8 (MCKO_SEL) : Master Clock Frequency is selected clock from MCKO1 or MCKO2 of the AK4114.
MCKO1
: The check from MCKO1 of AK4114 is provided to MCKI of the AK4631VN. < Default >
MCKO2
: The check from MCKO2 of AK4114 is provided to MCKI of the AK4631VN.
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
„ The function of the toggle SW
[SW1] (DIR)
: Power control of AK4114. Keep “H” during normal operation.
Keep “L” when AK4114 is not used.
[SW2] (PDN)
: Power control of AK4631VN. Keep “H” during normal operation.
„ Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
„ Serial Control
The AK4631-VN can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2
(CTRL) with PC by 10 wire flat cable packed with the AKD4631-VN
Connect
PC
10 wire
flat cable
10pin
Connector
CSN
CCLK AKD4631-VN
CDTI
10pin Header
Figure 2. Connect of 10 wire flat cable
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
„ Analog Input / Output Circuits
(1) Input Circuits
a) MIC Input Circuit
J1
MIC-JACK
6
4
3
AVSS
J3
MIC
JACK
JP12
MIC_SEL
INT
RCA
2
3
1
MR-552LS
AVSS
Figure 3. MIC Input Circuit
(a-1) Analog signal is input to MIC pin via J1 connector.
JP12
MIC_SEL
RCA JACK
(a-2) Analog signal is input to MIC pin via J3 connector.
JP12
MIC_SEL
RCA JACK
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
(2) Output Circuits
a) AOUT Output Circuit
AOUT
+
C28
1
2
R20
220
1u
2
3
1
R21
20k
AVSS
J5 AOUT
MR-552LS
AVSS
Figure 4. AOUT Output Circuit
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
b) SPK Output Circuit
Note. When mini-jack is inserted or pulled out J2 (SPK-JACK) connector, JP13 (SPP_SEL) and JP14
(SPN_SEL) should be open, or “PMSPK bit” in the AK4631-VN should be set to “0”.
JP31
Dynamic
R15
10
J2
SPK-JACK
3
4
SVSS
SPP
6
JP13
D1
A
SVSS
K
DIODE ZENER
A
SVSS
K
DIODE ZENER
SPK1
SPP_SEL
JP14
D2
Dynamic(EXT)
Piezo(EXT)
Dynamic
CN5
Dynamic(EXT)
Piezo(EXT)
Dynamic
SPN_SEL
020S16
R
2
1
L
R17
10
SPN
Figure 5. SPK Output Circuit
(b-1) An external dynamic speaker is evaluated by using J2 (SPK-JACK) connector.
JP13
SPP_SEL
Dynamic
Dynamic(EXT)
Piezo(EXT)
JP14
SPN_SEL
JP31
Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
(b-2) An external Piezo speaker is evaluated by using J2 (SPK-JACK) connector.
JP13
SPP_SEL
Dynamic
Dynamic(EXT)
Piezo(EXT)
JP14
SPN_SEL
JP31
Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
(b-3) Analog signal of SPP/SPN pins are output from “Dynamic Speaker” on the evaluation (SPK1).
JP13
SPP_SEL
Dynamic
JP14
SPN_SEL
Dynamic(EXT)
JP31
Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
Piezo(EXT)
(3) BEEP/MIN/MOUT Input and Output Circuit
2
JP15
MIN/MOUT
OUT
IN
R16
20k
1
MOUT
+
J4
BEEP/MIN/MOUT
2
3
1
C24
1u
C25
0.1u
AVSS
MR-552LS
AVSS
2
C26
1u
JP16
1
+
R18
47k
MOUT
MIN
BEEP
MIN
R19
BEEP/MIN/MOUT
BEEP
20k
AVSS
Figure 6. BEEP/MIN/MOUT Input and Output Circuit
(3-1) Analog signal is input to MIN pin from J4 connector.
JP16
JP15
BEEP/MIN/MOUT
MIN/MOUT
IN
MOUT
MIN
BEEP
OUT
(3-2) Analog signal of MOUT pin is output from J4 connector.
JP15
MIN/MOUT
IN
JP16
BEEP/MIN/MOUT
MOUT
MIN
BEEP
OUT
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
(3-3) Analog signal of MOUT pin is input to MIN pin.
JP16
JP15
BEEP/MIN/MOUT
MIN/MOUT
IN
MOUT
MIN
BEEP
OUT
(3-4) Analog signal is input to BEEP pin from J4 connector.
JP16
JP15
BEEP/MIN/MOUT
MIN/MOUT
IN
MOUT
MIN
BEEP
OUT
∗ AKM assumes no responsibility for the trouble when using the above circuit examples.
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
Control Software Manual
„ Set-up of evaluation board and control software
1. Set up the AKD4631-VN according to previous term.
2. Connect IBM-AT compatible PC with AKD4631VN by 10-line type flat cable (packed with AKD4631-VN). Take
care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on
Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”.
In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows
NT.)
3. Insert the CD-ROM labeled “AK4631VN Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive and double-click the icon of “akd4631.exe” to set up the control program.
5. Then please evaluate according to the follows.
„ Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click “Write default” button.
3. Then set up the dialog and input data.
„ Explanation of each buttons
1. [Port Setup] :
2. [Write default] :
3. [All Write] :
4. [Function1] :
5. [Function2] :
6. [F3] :
7. [SAVE] :
8. [OPEN] :
9. [Write] :
Set up the printer port.
Initialize the register of AK4631-VN.
Write all registers that is currently displayed.
Dialog to write data by keyboard operation.
Dialog to write data by keyboard operation.
Dialog of sequential writing.
Save the current register setting.
Write the saved values to all register.
Dialog to write data by mouse operation.
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
„ Explanation of each dialog
1. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box:
Data Box:
Input registers address in 2 figures of hexadecimal.
Input registers data in 2 figures of hexadecimal.
If you want to write the input data to AK4631VN, click “OK” button. If not, click “Cancel” button.
2. [Function2 Dialog] : Dialog to evaluate IVOL
Address Box:
Input registers address in 2 figures of hexadecimal.
Start Data Box:
Input starts data in 2 figures of hexadecimal.
End Data Box:
Input end data in 2 figures of hexadecimal.
Interval Box:
Data is written to AK4631VN by this interval.
Step Box:
Data changes by this step.
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to AK4631VN, click “OK” button. If not, click “Cancel” button.
3. [Write Dialog] : Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the “Write” button corresponding to each register to set up the dialog. If you check the check box, data
becomes “H” or “1”. If not, “L” or “0”.
If you want to write the input data to AK4631VN, click “OK” button. If not, click “Cancel” button.
<KM077301>
2005/01
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ASAHI KASEI
[AKD4631-VN]
„ Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the
part that is not defined in the datasheet.
„ Attention on the operation
If you set up Function1 or Function2 dialog, input data to all boxes. Attention dialog is indicated if you input data or
address that is not specified in the datasheet or you click “OK” button before you input data. In that case set up the
dialog and input data once more again. These operations does not need if you click “Cancel” button or check the check
box.
<KM077301>
2005/01
- 19 -
ASAHI KASEI
[AKD4631-VN]
MEASUREMENT RESULTS EXAMPLE
1.AK4631 Mode: EXT mode (Slave)
[Measurement condition]
• Measurement unit: ROHDE & SCHWARZ, UPD05
• MCKI: 256fs, 512fs
• BICK: 64fs
• Bit: 16bit
• Sampling Frequency: 8kHz & 16kHz
• Measurement Frequency: 20 ∼ 3.4kHz (fs=8kHz), 20 ∼ 8kHz (fs=16kHz)
• Power Supply: AVDD=DVDD=3.3V,SVDD=3.3V/5.0V
• Temperature: Room
• Input Frequency: 1kHz
[Measurement Results]
1.ADC characteristics (MIC Gain = +20dB, IPGA=0dB, ALC1 = OFF, MIC Æ IPGA Æ ADC)
Result
MCKI clock
Sampling Frequency
S/(N+D) (-1dBFS)
D-Range (-60dBFS)
S/N
512fs
8kHz
84.6dB
86.1dB
86.1dB
256fs
16kHz
84.1dB
85.0dB
85.0dB
8kHz
85.2dB
88.6dB
88.6dB
16kHz
84.1dB
84.9dB
85.0dB
2. DAC characteristics (AOUT) (DAC Æ AOUT, DVOL = 0dB)
Result
MCKI clock
Sampling Frequency
S/(N+D) (0dBFS)
D-Range (-60dBFS)
S/N
512fs
8kHz
89.7dB
93.5dB
94.1dB
256fs
16kHz
89.0dB
91.1dB
92.2dB
8kHz
86.0dB
93.7dB
94.5dB
16kHz
91.9dB
95.3dB
95.3dB
3. Speaker-Amp characteristics (DAC → MOUT → MIN Æ SPP/SPN, ALC2=OFF)
Result
S/(N+D)
SVDD=3.3V SPKG1-0 = “00” (-0.5dBFS)
65.8dB
SPKG1-0 = “01” (-0.5dBFS)
67.8dB
RL=8Ω
74.5dB
SVDD=5.0V SPKG1-0 = “10” (-0.5dBFS)
SPKG1-0 = “11” (-0.5dBFS)
78.1dB
RL=50Ω
S/N
SVDD=3.3V SPKG1-0 = “00”
90.2dB
SPKG1-0 = “01”
90.4dB
RL=8Ω
90.3dB
SVDD=5.0V SPKG1-0 = “10”
SPKG1-0 = “11”
90.4dB
RL=50Ω
4. Loop-back (MIC Æ ADC Æ DAC Æ AOUT)
Result
MCKI clock
Sampling Frequency
S/(N+D) (-1dBFS)
D-Range (-60dBFS)
S/N
512fs
8kHz
84.4dB
85.9dB
86.0dB
256fs
16kHz
84.0dB
84.8dB
84.8dB
<KM077301>
8kHz
84.7dB
87.8dB
87.9dB
16kHz
84.0dB
84.5dB
84.6dB
2005/01
- 20 -
ASAHI KASEI
[AKD4631-VN]
2.AK4631 Mode: PLL SLAVE mode
[Measurement condition]
• Measurement unit: ROHDE & SCHWARZ, UPD05
• Bit: 16bit
• Sampling Frequency: 8kHz & 16kHz
• Measurement Frequency: 20 ∼ 3.4kHz (fs=8kHz), 20 ∼ 8kHz (fs=16kHz)
• Power Supply: AVDD=DVDD=SVDD=3.3V
• Temperature: Room
• Input Frequency: 1kHz
[Measurement Results]
2-1. PLL Reference clock : BICK or FCK pin
Loop-back (MIC Æ ADC Æ DAC Æ AOUT)
Result
PLL Reference clock
Sampling Frequency
S/(N+D) (-1dBFS)
D-Range (-60dBFS)
S/N
1fs (FCK pin)
8kHz
16kHz
65.1dB
72.2dB
86.3dB
85.0dB
86.4dB
85.0dB
16fs (BICK pin)
8kHz
16kHz
85.0dB
83.6dB
87.8dB
85.0dB
87.9dB
85.0dB
2-2. PLL Reference clock : MCKI pin
Loop-back (MIC Æ ADC Æ DAC Æ AOUT)
PLL Reference clock
Sampling Frequency
S/(N+D) (-1dBFS)
D-Range (-60dBFS)
S/N
Result
12.288MHz
8kHz
16kHz
84.5dB
83.4dB
86.3dB
85.1dB
86.6dB
85.2dB
3.AK4631 Mode: PLL MASTER mode
[Measurement condition]
• Measurement unit: ROHDE & SCHWARZ, UPD05
• MCKI: 12.288 MHz
• BICK: 16fs
• Bit: 16bit
• Sampling Frequency: 8kHz & 16kHz
• Measurement Frequency: 20 ∼ 3.4kHz (fs=8kHz), 20 ∼ 8kHz (fs=16kHz)
• Power Supply: AVDD=DVDD=SVDD=3.3V
• Temperature: Room
• Input Frequency:1kHz
[Measurement Results]
Loop-back (MIC Æ ADC Æ DAC Æ AOUT)
Result
8kHz
S/(N+D) (-1dBFS)
84.4dB
D-Range (-60dBFS)
86.1dB
S/N
86.4dB
16kHz
83.9dB
85.3dB
85.3dB
<KM077301>
2005/01
- 21 -
ASAHI KASEI
[AKD4631-VN]
4.PLOT DATA (EXT Slave mode)
4-1.ADC (MIC Æ ADC) PLOT DATA
Figure 8. THD+N vs. Input Level
Figure 9. THD+N vs. Input Frequency (Input Level = -1dBFS)
<KM077301>
2005/01
- 22 -
ASAHI KASEI
[AKD4631-VN]
Figure 10. Linearity
Figure 11. Frequency Response
<KM077301>
2005/01
- 23 -
ASAHI KASEI
[AKD4631-VN]
Figure 12. FFT Plot ( Input level=-1.0dBFS)
Figure 13. FFT Plot ( Input level=-60.0dBFS )
<KM077301>
2005/01
- 24 -
ASAHI KASEI
[AKD4631-VN]
Figure 14. FFT Plot ( “0” data input )
<KM077301>
2005/01
- 25 -
ASAHI KASEI
[AKD4631-VN]
4-2. DAC (DAC Æ AOUT) PLOT DATA
Figure 15. THD+N vs. Input Level
Figure 16. THD+N vs. Input Frequency (Input Level = 0dBFS)
<KM077301>
2005/01
- 26 -
ASAHI KASEI
[AKD4631-VN]
Figure 17. Linearity
Figure 18. Frequency Response
<KM077301>
2005/01
- 27 -
ASAHI KASEI
[AKD4631-VN]
Figure 19. FFT Plot ( Input level=0dBFS )
Figure 20. FFT Plot ( Input level=-60.0dBFS )
<KM077301>
2005/01
- 28 -
ASAHI KASEI
[AKD4631-VN]
Figure 21. FFT Plot ( “0” data input )
<KM077301>
2005/01
- 29 -
ASAHI KASEI
[AKD4631-VN]
Revision History
Date
04/01/25
Manual
Revision
KM077300
Board
Revision
0
Reason
Contents
First Edition
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
<KM077301>
2005/01
- 30 -
MOUT
25
26
27
28
29
30
SVSS
31
AVSS
CN1
32pin_4
32
E
REG
AVDD
DVDD
AVSS
SVDD
SVSS
DGND
T45_R
T45_O
T45_O
T45_BK
T45_BU
T45_BK
T45_BK
TP27 TP26 TP25
BEEP AOUT MOUT
1
1
REG_IN
1
AVSS
R1
2.2k
C7
0.22u
+
C6
1u
1
DVDD
1
1
1
AVSS
SVDD
SVSS
JP2
AIN TP28
AIN
TP31 TP30 TP29
MPI
MIC MICOUT
1
AVDD
1
1
E
1
1
2
C2
0.1u
C3
+
47u
1
GND
AVSS
REG
OUT
C1
0.1u
E
D
JP1
GND
REG_IN T1
TA48033F
IN
AOUT
C
BEEP
B
INT
A
1
1
D
D
TP32
VCOM
1
22
AVSS
SVSS
20
TP2 AVDD
R2
TP1
VCOC
10k
3
AVDD
SVDD
19
4
4
VCOC
SPN
18
5
C8
4.7n
5
PDN
SPP
17
6
AVSS
6
CSN
MCKO
16
7
CCLK
MCKI
15
AK4631VN
C11
0.1u
24
TP22
SVDD
C12
10u
TP20
SPN
R3 (short)
R5 (short)
23
JP4 REG
MIN SVDD_SEL
SVDD
L2
SVDD 1
SVSS
2
(short)
22
R4
(open)
DVDD
1
DVSS
TP19
MCKO
14
13
FCK
BICK
12
SDTO
11
10
TP21
SPP
TP8
PDN
21
SPN
20
SPP
19
4631_MCKO
18
4631_MCKI
C16
+
47u
C
SVSS
JP6 MCKI
1
51
SDTI
CDTI
R6
9
1
8
32pin_1
8
7
PDN
SVSS
TP23
SVSS
1
23
24
AOUT
MOUT
AIN
BEEP
26
25
28
27
21
1
AVSS
2
CN3
MIN
2
C
VCOM
1
1
3
AVSS
1
1
AVDD
(short)
C10
0.1u
1
1
+
C9
10u
1
47u
AVDD
2
C13
2
2
REG
+
1
TP3
AVSS
MICOUT
1
L1
C5
0.1u
TP24
MIN
1
+
REG
AVDD
C4
2.2u
AVSS
U1
MPI
CN2
JP3
AVDD_SEL
+
MIC
1
REG
17
MCKI
TP18
AVSS
32pin_3
C20
0.1u
B
B
TP9
CSN
TP10 TP11
CCLK CDTI
1
JP9
AVDD DVDD_SEL
DVDD
L4
1
1
R9
51
1
TP15
BICK
1
R10
51
R11
51
1
R12
470
C21
10u
R13
470
TP16
DVDD
DVDD
2
AVSS
+
(short)
DVDD
R40
(short)
DVDD
JP10
LVC_SEL
2
47u
1
R8
51
TP13 TP14
SDTO FCK
1
1
C22
1
R7
51
R1410
TP12
SDTI
+
AVDD
LVC
AVSS
VCC
16
15
14
13
12
A
A
B
C
Title
DVDD
4631_BICK
4631_FCK
4631_SDTO
4631_SDTI
CDTI
VCC
CCLK
1
(short)
CSN
47u
+
32pin_2
2
C23
CN4
D3.3V
2
11
L5
1
A
JP11
VCC_SEL
10
LVC
9
VCC(3.3V)
Size
A3
Date:
D
AKD4631-VN
Document Number
Rev
AK4631-VN
Wednesday, December 22, 2004 Sheet
E
0
1
of
5
A
B
C
D
E
J1
MIC-JACK
6
JP31
Dynamic
4
3
E
AVSS
J3
MIC
JACK
JP12
MIC_SEL
R15
10
INT
RCA
2
3
1
6
JP13
D1
A
AVSS
K
R16
20k
OUT
IN
1
C25
0.1u
A
SVSS
Dynamic(EXT)
Piezo(EXT)
Dynamic
SPK1
SPN_SEL
JP14
D2
MOUT
+
JP15
MIN/MOUT
DIODE ZENER
SVSS
C24
1u
2
J4
BEEP/MIN/MOUT
2
3
1
K
DIODE ZENER
020S16
CN5
Dynamic(EXT)
Piezo(EXT)
Dynamic
R
2
SPP_SEL
1
AVSS
MR-552LS
L
R17
10
AVSS
C26
1u
2
1
+
R18
47k
AVSS
E
3
4
SPN
MR-552LS
D
J2
SPK-JACK
SVSS
JP16
MOUT
MIN
BEEP
D
SPP
MIN
R19
BEEP/MIN/MOUT
BEEP
20k
+
C28
1
AOUT
R20
220
2
3
1
2
1u
R21
20k
MR-552LS
AVSS
AVSS
C
J5 AOUT
C
B
B
A
A
Title
Size
A3
Date:
A
B
C
D
AKD4631-VN
Document Number
Rev
Input/Output
Wednesday, December 22, 2004 Sheet
E
0
2
of
5
A
B
C
D
E
for
74HCU04,74AC74,74VHC4040,74HC14,74HC14,74HC541,74HCT04
12.288MHz
X1
1
C30
0.1u
C31
0.1u
C32
0.1u
C33
0.1u
C34
0.1u
C35
0.1u
C36
0.1u
2
2
E
1
D3.3V
E
+ C37
47u
R24
1M
U2A
1
U2B
2
3
74HCU04
JP17
XTE
C38
5p
4
74HCU04
C39
5p
D
D
EXT_MCLK
Q
10
6
12
D
11
CLK
PR
Q
5
U4B
74AC74
Q
CL
CLK
U4A
74AC74
Q
9
256fs
512fs
1024fs
MCKO
JP18
MKFS
U3
10
11
8
13
MCLK_SEL
C
D
3
CL
R25
short
VCC
1
XTL
DIR
EXT
DIR_MCLK
JP21
2
PR
4
VCC
CLK
RST
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
9
7
6
5
3
2
4
13
12
14
15
1
74VHC4040
JP19
BICK_SEL
64fs
32fs
16fs
EXT
1
B
2
3
1
MR-552LS
AVSS
J9
FCK
2
3
1
MR-552LS
AVSS
A
EXT_BICK
INV
C
JP22
2fs
1fs
EXT
EXT_FCK
FCK_SEL
B
R26
51
JP23
EXT1
R27
51
JP24
EXT2
A
Title
Size
A3
Date:
A
JP20
BICK
2
U5A
74HC14
MCKO
J8
EXT/BICK
THR
B
C
D
AKD4631-VN
Document Number
Rev
CLOCK
Wednesday, December 22, 2004
Sheet
E
0
3
of
5
A
B
C
D
E
C40 C41
0.1u 0.1u
D3.3V
L6
(short)
R28
10k
3
2
1
VCC
GND
OUT
0.1u
2
4
1
E
U5C
3
74HC14
D3.3V
+
TORX141
U5B
C43
10u
R29
470
D3
HSU119
6
5
74HC14
L
C44
0.1u
H
SW1
DIR
2
C45
0.1u
1
C42
3
PORT1
A
2
E
K
1
D3.3V
1
38
37
INT1
R
AVDD
40
39
R30
18k
VCOM
41
AVSS
42
RX0
43
NC
44
RX1
46
45
TEST1
NC
RX2
U6
16
15
14
13
12
11
10
9
47
SW3
1
2
3
4
5
6
7
8
RX3
DIF0
DIF1
DIF2
CM0
CM1
OCKS0
OCKS1
M/S
D
48
C46
0.47u
D
R31
1k
U7A
IPS0
INT0
36
1
2
LED1
ERF
K
A
D3.3V
74HC04
2
NC
OCKS0
35
OCKS0
3
DIF0
OCKS1
34
OCKS1
4
TEST2
CM1
33
CM1
5
DIF1
CM0
32
CM0
6
NC
PDN
31
7
DIF2
XTI
30
8
IPS1
XTO
29
9
P/SN
DAUX
28
10
XTL0
MCKO2
27
11
XTL1
BICK
26
DIR_BICK
12
VIN
SDTO
25
DIR_SDTI
RP1
CM0
CM1
OCKS0
OCKS1
M/S
47k
AK4114
C
C
C47
5p
1
9
8
7
6
5
4
3
2
1
C48
5p
2
X2
11.2896MHz
DAUX
2
1
C51
10u
D3.3V
LRCK
24
MCKO1
23
22
C50
0.1u
+
+
C49
0.1u
1
DVSS
DVDD
21
20
VOUT
UOUT
19
COUT
18
BOUT
17
TX1
16
15
DVSS
14
13
TX0
B
TVDD
B
DIR_FCK
JP25
MCKO_SEL
MCKO2
MCKO1
DIR_MCLK
2
C52
10u
D3.3V
PORT2
A
IN
VCC
GND
3
2
1
A
D3.3V
C53
0.1u
TOTX141
Title
Size
A3
Date:
A
B
C
D
AKD4631-VN
Document Number
Rev
DIR/DIT
Wednesday, December 22, 2004 Sheet
E
0
4
of
5
A
B
C
D
U8
U9
1
E
11
Y8
A8
9
12
Y7
A7
8
4631_MCKO
4631_MCKI
13
Y6
A6
7
EXT_MCLK
DAUX
14
Y5
A5
6
4631_SDTO
4631_SDTI
15
Y4
A4
5
16
Y3
A3
4
17
Y2
A2
3
18
Y1
A1
2
10
GND
G2
19
MCKO
E
LVC
DIR
20
VCC
E
M/S
C54
0.1u
19
G
2
GND
10
A1
B1
18
3
A2
B2
17
4
A3
B3
16
5
A4
B4
15
6
A5
B5
14
7
A6
B6
13
A7
B7
12
B8
11
RP2
RP3
7
6
5
4
3
2
1
JP26
4631_SDTI DAC/LOOP
47k
ADC
7
6
5
4
3
2
1
47k
D
D
VCC
8
4631_FCK
9
ADC
DIR
C55
0.1u
20
4631_BICK
JP27
BICK
1
G1
A8
JP28
FCK
74LVC245
74LVC541
ADC
DIR
EXT_BICK
DIR_BICK
EXT_FCK
DIR_FCK
C
C
2
1
LVC
JP29
U10A
+ C56
47u
1
INV
2
THR
74HC14
BICK_INV
R32
R34
R36
D3V
PORT4
1
2
3
4
5
B
10
9
8
7
6
10k
10k
10k
R33
R35
R37
U11
470
470
470
CSN
CCLK
CDTI
2
3
4
5
6
7
8
9
A1
A2
A3
A4
A5
A6
A7
A8
1
19
G1
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
18
17
16
15
14
13
12
11
CSN
CCLK
CDTI
PDN
4631_MCKI
MCLK
BICK
FCK
SDTI
VCC
10
9
8
7
6
ROM
B
R38
74HC541
CTRL
PORT3
1
2
3
4
5
D3V
10k
ADC
K
D3V
A
D4
HSU119
R39
10k
U5D
9
11
10
U2C
74HC14
5
6
1
C57
0.1u
10
74HCU04
5
3
11
U10C
10
5
74HC04
74HC04
13
6
U10E
11
74HC14
U7F
6
4
74HC14
U7E
4
U7C
U2E
U10B
8
74HC04
74HC04
74HCU04
11
9
U7B
3
2
8
12
74HCU04
U2D
9
U7D
U2F
13
74HCU04
SW2
PDN
A
U10D
12
74HC04
9
8
74HC14
10
A
74HC14
U10F
13
Title
12
74HC14
Size
A3
Date:
A
DIR_SDTI
DIR
U5E
8
74HC14
H
3
L
DAUX
JP30
SDTI
B
C
D
AKD4631-VN
Document Number
Rev
LOGIC
0
Wednesday, December 22, 2004 Sheet
E
5
of
5
AKD4631-VN L1 SILK
AKD4631-VN L2 SILK
AKD4631-VN L1
AKD4631-VN L2