ASAHI KASEI [AKD4641EN-A] AKD4641EN-A Evaluation board Rev.1 for AK4641EN GENERAL DESCRIPTION The AKD4641 is an evaluation board for the AK4641, 16bit stereo CODEC with built-in Microphone-amplifier and 16bit Mono CODEC for Bluetooth Interface. The AKD4641 can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D → D/A). The AKD4641 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide AKD4641EN-A --- Evaluation board for AK4641EN (Cable for connecting with printer port of IBM-AT, compatible PC and control software are packed with this. This control software does not support Windows NT.) FUNCTION • DIT/DIR with optical input/output • BNC connector for an external clock input • 10pin Header for I2C control mode • On board headphone-amp (MAX4410) and speaker-amp (LM4889) AVDD 5V Regulator BVDD DVDD AGND 3.3V Control Data 10pin Header MIC Jack AUXIN+ AUXIN- Clock Gen MOUT+ Bluetooth I/F MOUT+/- MOUT- 10pin Header AK4641 Audio I/F 10pin Header MOUT LOUT ROUT HP Jack DIR AK4114 HP-amp MAX4410 Opt In Opt Out SPK-amp LM4889 MOUT2 Figure 1. AKD4641 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual <KM082001> 2006/03 -1- ASAHI KASEI [AKD4641EN-A] Evaluation Board Manual Operation sequence 1) Set up the power supply lines. 1-1) When AVDD, BVDD, DVDD and VCC are supplied from the regulator. (AVDD, BVDD, DVDD and VCC jack should be open.). See “Other jumper pins set up (page 9)”. <default> [REG] (red) [AVDD] (orange) [BVDD] (orange) [DVDD] (orange) [VCC] (orange) [H/SVDD] (orange) [AGND] (black) [DGND] (black) = 5V = open = open = open = open = 3.3V = 0V = 0V : 3.3V is supplied to AVDD of AK4641 from regulator. : 3.3V is supplied to BVDD of AK4641 from regulator. : 3.3V is supplied to DVDD of AK4641 from regulator. : 3.3V is supplied to logic block from regulator. : for MAX4410 and LM4889 logic (typ.3.3V) : for analog ground : for logic ground 1-2) When AVDD, BVDD, DVDD and VCC are not supplied from the regulator. (AVDD, BVDD, DVDD and VCC jack should be open). See “Other jumper pins set up (page 9)”. [REG] (red) [AVDD] (orange) [BVDD] (orange) [DVDD] (orange) [VCC] (orange) [H/SVDD] (orange) [AGND] (black) [DGND] (black) = “REG” jack should be open. = 2.6 ∼ 3.6V : for AVDD of AK4641 (typ. 3.3V) = 2.6 ∼ 3.6V : for BVDD of AK4641 (typ. 3.3V) = 2.6 ∼ 3.6V : for DVDD of AK4641 (typ. 3.3V) = 2.6 ∼ 3.6V : for logic (typ. 3.3V) = 2.6 ∼ 3.6V : for MAX4410 and LM4889 logic (typ.3.3V) = 0V : for analog ground = 0V : for logic ground Each supply line should be distributed from the power supply unit. DVDD and VCC must be same voltage level. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK4641 and AK4114 should be reset once bringing SW1, 2 “L” upon power-up. Evaluation mode 1. Evaluation of 16bit stereo CODEC In case of AK4641 evaluation using AK4114, it is necessary to correspond to audio interface format for AK4641 and AK4114. About AK4641’s audio interface format, refer to datasheet of AK4641. About AK4114’s audio interface format, refer to Table 2 in this manual. (1-1) Evaluation of Recording block (MIC, ADC) using DIT of AK4114 (1-2) Evaluation of Playback block (HP, SPK, MOUT) using DIR of AK4114 (1-3) Evaluation of Loop Back (ADC → DAC) using 16bit Mono CODEC <default> (1-4) All interface signals including master clock are fed externally. <KM082001> 2006/03 -2- ASAHI KASEI [AKD4641EN-A] (1-1) Evaluation of Recording block (MIC, ADC) using DIT of AK4114 PORT2 (DIT) and X2 (X’tal) are used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX141). Nothing should be connected to PORT1 (DIR) and PORT3 (Audio I/F), J12 (EXT). JP25 (EXT) is short. CM0 is set “H ” and CM1 is set “L ” for SW1, AK4114 is set X’tal mode. JP24 XTI JP26 JP27 JP30 JP28 MCLK_SEL BICK1 BICK2 BICK_INV MCKO01 MCKO02 DIR PORT THR DIR JP29 LRCK1 DIR PORT JP31 JP32 JP33 LRCK2 SDTI1 SDTI2 PORT DIR DIR INV LOOP PORT DIT does not operate under fs = 32kHz, this mode corresponds to fs = 32kHz and over. (1-2) Evaluation of Playback block (HP, SPK, MOUT) using DIR of AK4114 PORT1 (DIR) is used. Nothing should be connected to PORT3 (Audio I/F) and J12 (EXT). X1 (X’tal) is removed. JP25 (EXT) is short. CM0 is set “L ” and CM1 is set “L ” for SW1, AK4114 is set PLL mode. JP24 XTI JP26 JP27 JP30 JP28 MCLK_SEL BICK1 BICK2 BICK_INV MCKO01 MCKO02 DIR PORT THR DIR JP29 LRCK1 DIR PORT JP31 JP32 JP33 LRCK2 SDTI1 SDTI2 PORT DIR DIR INV LOOP PORT DIR does not operate under fs = 32kHz, this mode corresponds to fs = 32kHz and over. <KM082001> 2006/03 -3- ASAHI KASEI [AKD4641EN-A] (1-3) Evaluation of Loop Back (ADC → DAC) using 16bit Mono CODEC <default> X2 (X’tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (Audio I/F). JP24 XTI JP26 JP27 JP30 JP28 MCLK_SEL BICK1 BICK2 BICK_INV MCKO01 MCKO02 DIR PORT THR DIR JP29 LRCK1 DIR INV PORT JP31 JP32 JP33 LRCK2 SDTI1 SDTI2 PORT DIR DIR LOOP PORT (1-4) All interface signals including master clock are fed externally. PORT3 (Audio I/F) and J12 (EXT) is used. Nothing should be connected to PORT1 (DIR). X2 (X’tal) is removed. JP25 (EXT) and R51 should be properly selected in order to much the output impedance of the clock generator. JP24 XTI JP26 JP27 JP30 JP28 MCLK_SEL BICK1 BICK2 BICK_INV MCKO01 MCKO02 DIR PORT THR DIR JP29 LRCK1 DIR PORT JP31 JP32 JP33 LRCK2 SDTI1 SDTI2 PORT DIR DIR INV LOOP PORT JP28 (BICK_INV) is jumper which decides polarity of BICK, set “THR” or “INV” for audio interface format. <KM082001> 2006/03 -4- ASAHI KASEI [AKD4641EN-A] 2. Evaluation of 16bit Mono CODEC (2-1) (2-2) (2-3) (2-4) (2-5) (2-6) Set up jumper pins of BBICK clock Set up jumper pins of BSYNC clock Set up jumper pins of two types of data formats Evaluation of ADC (AUXIN) using 16bit Mono CODEC Evaluation of DAC (MOUT) using 16bit Mono CODEC Evaluation of Loop Back (ADC → DAC) using 16bit Mono CODEC <default> (2-1) Set up jumper pins of BBICK clock Input frequency of BBICK can be set up in turn “32fs”,”64fs” or “128fs” from left. JP18 BBICK_SEL JP18 BBICK_SEL EXT 32fs 64fs 128fs EXT 32fs 64fs 128fs JP18 BBICK_SEL EXT 32fs 64fs 128fs (2-2) Set up jumper pins of BSYNC clock Input frequency of BSYNC can be set up in turn “2fs” or “1fs” from left. JP20 BSYNC_SEL1 JP20 BSYNC_SEL1 EXT 1fs EXT 2fs 1fs 2fs When an external clock through a BNC connector (J10: BBICK and J11: BSYNC) is supplied, select EXT on JP18 (BBICK_SEL) and JP20 (BSYNC_SEL) and short JP17 (XTE). JP22 (EXT1) and JP23 (EXT2) and R44 and R45 should be properly selected in order to much the output impedance of the clock generator. (2-3) Set up jumper pins of two types of data formats (2-3-1) Set up jumper pins of “I2S” <default> JP39 BBICK_INV JP21 BSYNC_SEL2 I2S THR SHORT INV (2-3-2) Set up jumper pins of “Short Format Sync” JP39 BBICK_INV JP21 BSYNC_SEL2 I2S THR SHORT <KM082001> INV 2006/03 -5- ASAHI KASEI [AKD4641EN-A] (2-3-3) Set up jumper pins of “MSB justified” JP39 BBICK_INV JP21 BSYNC_SEL2 I2S THR SHORT INV (2-4) Evaluation of ADC (AUXIN) using 16bit Mono CODEC PORT5 (Bth I/F) and X1 (X’tal) are used. Nothing should be connected to J10 (BBICK) and J11 (BSYNC). JP19 JP35 JP17 JP38 XTE BBICK2 CLK_SEL BBICK1 CLK EXT INT PORT INT JP40 BSYNC1 INT JP36 JP37 BSYNC2 SDTI PORT PORT PORT LOOP INT PORT (2-5) Evaluation of DAC (MOUT) using 16bit Mono CODEC PORT5 (Bth I/F) and X1 (X’tal) are used. Nothing should be connected to J10 (BBICK) and J11 (BSYNC). When an BSYNC through a PORT5 connector (Bth I/F) is supplied, open JP20 (BSYNC_SEL). JP19 JP35 JP17 JP38 XTE BBICK2 CLK_SEL BBICK1 CLK EXT INT PORT INT JP40 BSYNC1 INT JP36 JP37 BSYNC2 SDTI PORT PORT PORT LOOP INT PORT <KM082001> 2006/03 -6- ASAHI KASEI [AKD4641EN-A] (2-6) Evaluation of Loop Back (ADC → DAC) using 16bit Mono CODEC X1 (X’tal) are used. Nothing should be connected to PORT5 ( Bth -I/F ), J10 (BBICK) and J11 (BSYNC). JP19 JP17 XTE JP38 BBICK1 CLK_SEL CLK EXT INT JP35 BBICK2 PORT INT JP40 BSYNC1 INT JP36 JP37 BSYNC2 SDTI PORT PORT PORT LOOP INT PORT <KM082001> 2006/03 -7- ASAHI KASEI [AKD4641EN-A] DIP Switch set up [SW1] : Mode Setting of AK4114 ON is “H”, OFF is “L”. No. 1 2 3 4 5 6 7 Name ON (“H”) OFF (“L”) AK4114 Audio Format Setting DIF0 See Table 2 DIF2 CM0 AK4114 AUTO (X’tal / PLL) Mode CM1 OCKS1 Fixed to “L” TST2 NC Table 1. Mode Setting for AK4534 and AK4114 Mode 0 1 2 3 Mode 0 1 Default ON ON OFF ON OFF OFF OFF DIF2 DIF0 AK4114 DAUX AK4114 SDTO 0 0 24bit, MSB justified 16bit, LSB justified 0 1 24bit, MSB justified 24bit, LSB justified 1 0 24bit, MSB justified 24bit, MSB justified 1 1 24bit, I2S 24bit, I2S Table 2. Setting for AK4114 Audio Interface Format CM1 0 0 CM0 0 1 UNLOCK PLL X'tal Clock source SDTO ON ON(Note) PLL RX OFF ON X'tal DAUX 0 ON ON PLL RX 2 1 0 1 ON ON X'tal DAUX 3 1 1 ON ON X'tal DAUX ON: Oscillation (Power-up), OFF: STOP (Power-down) Note : When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is off. Table 3. Clock Operation Mode select No. 0 OCKS1 0 MCKO1 256fs MCKO2 256fs X’tal 256fs fs (max) 96 kHz 2 1 512fs 256fs 512fs 48 kHz Table 4. Master Clock Frequency Select (Stereo mode) <KM082001> 2006/03 -8- ASAHI KASEI [AKD4641EN-A] Other jumper pins set up 1. JP1 (GND): Analog ground and Digital ground OPEN : Separated. <default> SHORT : Common. (The connector “DGND” can be open.) 2. JP3 (AVDD_SEL): AVDD of the AK4641 REG : AVDD is supplied from the regulator (“AVDD” jack should be open). < default > AVDD : AVDD is supplied from “AVDD ” jack. 3. JP4 (BVDD_SEL): BVDD of the AK4641 AVDD : AVDD is supplied from “AVDD”. < default > BVDD : BVDD is supplied from “BVDD ” jack. 4. JP5 (DVDD_SEL): BVDD of the AK4641 BVDD : DVDD is supplied from “BVDD”. < default > DVDD : BVDD is supplied from “BVDD ” jack. 5. JP2 (D3.3V_SEL): VCC of logic DVDD : VCC is supplied from “DVDD”. < default > VCC : VCC is supplied from “VCC ” jack. 6. JP6 (LOUT/HP_SEL): Select analog signal of LOUT pin LOUT : Analog signal of LOUT pin is output from J1 (RCA) connector. < default > ROUT : Analog signal of LOUT pin is output from J2 (mini jack) connector. 7. JP7 (ROUT/HP_SEL): Select analog signal of ROUT pin LOUT : Analog signal of LOUT pin is output from J1 (RCA) connector. < default > ROUT : Analog signal of LOUT pin is output from J2 (mini jack) connector. 8. JP8 (SHDN_L): Left-Channel shutdown mode for MAX4410 OPEN : Left-Channel active mode. SHORT : Left-Channel shutdown mode. < default > 9. JP9 (SHDN_R): Right-Channel shutdown mode for MAX4410 OPEN : Right-Channel active mode. SHORT : Right-Channel shutdown mode. < default > 10. JP12 (MOUT2/SPK_SEL): Select analog signal of MOUT2 pin MOUT2 : Analog signal of MOUT2 pin is output from J7 (RCA) connector. < default > SPK : Analog signal of MOUT2 pin is output from speaker. 11. JP15 (SHDN_SPK): shutdown mode for LM4889 OPEN : Speaker active mode. SHORT : Speaker shutdown mode. < default > 12. JP34 (BSDTO): Please make use of open < default > <KM082001> 2006/03 -9- ASAHI KASEI [AKD4641EN-A] The function of the toggle SW Upper-side is “H” and lower-side is “L”. [SW1] (DIR): Power down of the AK4114. Keep “H” during normal operation. Keep “L” when the AK4114 is not used. [SW2] (PDN): Power down of the AK4641. Keep “H” during normal operation. Indication for LED [LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when the AK4114 has some error. I2C- bus Control Interface The AK4641 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4 (CTRL) with PC by 10 wire flat cable packed with the AKD4641. Connect PC 10 wire flat cable 10pin Connector CSN SCL SDA AKD4641 10pin Header Figure 2. Connect of 10 wire flat cable <KM082001> 2006/03 - 10 - ASAHI KASEI [AKD4641EN-A] Analog Input / Output Circuits 1. Input Circuits 1-1. MIC Input Circuit J4 MIC EXT EXT JP11 MIC INT INT Figure 3. MIC Input Circuit (1) Analog signal is input to INT pin via J4 connector. <default> JP11 MIC INT EXT (2) Analog signal is input to EXT pin via J4 connector. JP11 MIC INT EXT 1-2. AUXIN+ / AUXIN- Input Circuit J5 AUXIN+ + RCA C27 1u R29 47k J6 AUXIN- C29 1u + RCA AUXIN+ R30 47k AUXIN- Figure 4. AUXIN+ / AUXIN- Input Circuits <KM082001> 2006/03 - 11 - ASAHI KASEI [AKD4641EN-A] 2. Output Circuits 2-1. LOUT / ROUT Output Circuit C21 22u R19 220 + LOUT/HP_SEL JP6 LOUT LOUT R20 10k HP J1 LOUT RCA for HPL-amp ROUT/HP_SEL JP7 HP C23 22u R27 220 + ROUT for HPR-amp R28 10k ROUT J3 ROUT RCA Figure 5. LOUT /ROUT Output Circuit 2-2. MOUT2 Output + MOUT2/SPK_SEL JP12 MOUT2 C30 22u MOUT2 R32 10k SPK J7 R31 220 MOUT2 RCA for SPK-amp Figure 6. MOUT2 Output Circuit <KM082001> 2006/03 - 12 - ASAHI KASEI [AKD4641EN-A] 2-3. MOUT+/− Output Circuit C31 + JP13 MOUT+/-_SEL MOUT+ 22u R33 220 MOUT+ MOUT- R35 10k J8 MOUT+ RCA JP14 DIFF1 + C34 MOUT22u J9 MOUT 2 2 3 3 JP16 DIFF2 R41 100 1 1 R39 R40 10k 100 R42 10k Figure 7. MOUT+/− Output Circuit (1) Signal of MOUT+ pins are output from J8. JP14 DIFF1 JP13 MOUT+/-_SEL MOUT+ JP16 DIFF2 MOUT- (2) Signal of MOUT− pins are output from J8. JP13 MOUT+/-_SEL MOUT+ JP14 DIFF1 JP16 DIFF2 MOUT- (3) Signal of MOUT+ / - pins are output from J9. <default> JP13 MOUT+/-_SEL MOUT+ JP14 DIFF1 JP16 DIFF2 MOUT- ∗ AKM assumes no responsibility for the trouble when using the above circuit examples. <KM082001> 2006/03 - 13 - ASAHI KASEI [AKD4641EN-A] Control Software Manual Set-up of evaluation board and control software This evaluation board supports to I2C control. 1. Set up the AKD4641 according to previous term. 2. Connect IBM-AT compatible PC with AKD4641 by 10-line type flat cable (packed with AKD4641). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AK4641 Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “akd4641.exe” to set up the control program. 5. Then please evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Setup” button. 3. Click “Write default” button. 4. Then set up the dialog and input data. Explanation of each buttons 1. [Port Reset] : 2. [Write default] : 3. [All Read] : 4. [All Write] : 5. [Function1] : 6. [Function2] : 7. [Function3] : 8. [Function4] : 9. [Function5] : 10.[Write] : 11.[Read] : 12.[SAVE] : 13.[OPEN] : Set up the port. When this is pushed, the printer port or USB port is selected automatically. Initialize the register of the AK4641 Read all registers of the AK4641. Write all registers that is currently displayed Dialog to write data by keyboard operation. Dialog to evaluate IPGA and ATTL/ATTR. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Dialog to write data by mouse operation. Read data by mouse operation. Save the current register setting. Write the save values to all register. Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM082001> 2006/03 - 14 - ASAHI KASEI [AKD4641EN-A] Explanation of each dialog 1. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input register address in 2 figures of hexadecimal. Input register data in 2 figures of hexadecimal. If you want to write the input data to AK4641, click “OK” button. If not, click “Cancel” button. 2. [Function2 Dialog] : Dialog to evaluate IPGA and ATTL/ATTR This dialog corresponds to only addr=0BH and 0CH, 0DH. Address Box: Input register address in 2 figures of hexadecimal. Start Data Box: Input start data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4641 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4641, click “OK” button. If not, click “Cancel” button. 3. [Write Dialog] : Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the “Write” button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. If you want to write the input data to AK4641, click “OK” button. If not, click “Cancel” button. 4.[Save] and [Open] 4-1. [Save] Save the current register setting data. The extension of file name is “akr”. (Operation flow) (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is “akr”. 4 -2. [Open] The register setting data saved by [Save] is written to AK4643. The file type is the same as [Save]. (Operation flow) (1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button. <KM082001> 2006/03 - 15 - ASAHI KASEI [AKD4641EN-A] 5.[Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is “aks”. Figure 1. Window of [F3] <KM082001> 2006/03 - 16 - ASAHI KASEI [AKD4641EN-A] 6. [Function4 Dialog] The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the window as shown in Figure2 opens. Figure 2. [F4] window <KM082001> 2006/03 - 17 - ASAHI KASEI [AKD4641EN-A] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 3. Figure 3. [F4] window(2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The sequence file names can assign be saved. The file name is *.ak4. [OPEN] : The sequence file names assign that are saved in *.ak4 are loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change. <KM082001> 2006/03 - 18 - ASAHI KASEI [AKD4641EN-A] 7.[Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 4 opens. Figure 4. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 5. (2) Click [WRITE] button, then the register setting is executed. <KM082001> 2006/03 - 19 - ASAHI KASEI [AKD4641EN-A] Figure 5. [F5] windows(2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The register setting file names assign can be saved. The file name is *.ak5. [OPEN] : The register setting file names assign that are saved in *.ak5 are loaded. 7-3. Note (1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change. <KM082001> 2006/03 - 20 - ASAHI KASEI [AKD4641EN-A] Measurement Result 1. 16bit stereo CODEC [Measurement condition] • Measurement unit • MCLK • BICK • fs • Bit • Power Supply • Measurement Filter • Temperature : Audio Precision, System Two : 256fs : 64fs : 44.1kHz : 16bit : AVDD=BVDD=DVDD=3.3V : 20Hz ∼ 20kHz : Room [Measurement Results] 1.ADC (INT) characteristics (MIC Gain = +20dB, IPGA = 0dB, ALC1 = OFF, MIC Æ IPGA Æ ADC) [dB] THD+N 20kHzLPF (-1dB) DR 20kHzLPF + A-weighted 83.3 86.1 S/N 20kHzLPF + A-weighted 86.1 2.ADC (EXT) characteristics (MIC Gain = +20dB, IPGA = 0dB, ALC1 = OFF, EXT Æ IPGA Æ ADC) [dB] THD+N 20kHzLPF (-1dB) DR 20kHzLPF + A-weighted 83.3 86.1 S/N 20kHzLPF + A-weighted 86.1 3. ADC (AUXIN+ / AUXIN-) characteristics ( MICAD =0, AUXIN+/AUXIN- Æ ADC) [dB] THD+N 20kHzLPF (-1dB) 87.6 DR 20kHzLPF + A-weighted 91.1 S/N 20kHzLPF + A-weighted 91.1 4. DAC (LOUT/ROUT) characteristics (RL=10kΩ, DAC Æ LOUT/ROUT) L[dB] R[dB] THD+N 20kHzLPF (-3dB) 86.4 86.4 DR 20kHzLPF + A-weighted 89.4 89.5 S/N 20kHzLPF + A-weighted 90.7 91.0 5. DAC (MOUT+ / MOUT-) characteristics (RL=20kΩ, DAC Æ MOUT+ / MOUT-) MOGN=0[dB] MOGN=1[dB] THD+N 20kHzLPF (-3dB) 87.7 74.0 DR 20kHzLPF + A-weighted 90.9 76.8 S/N 20kHzLPF + A-weighted 93.0 77.0 6. DAC (MOUT2) characteristics (RL=10kΩ, DAC Æ MIX Æ MOUT2) [dB] THD+N 20kHzLPF (-3dB) 87.9 DR 20kHzLPF + A-weighted 90.7 S/N 20kHzLPF + A-weighted 92.7 <KM082001> 2006/03 - 21 - ASAHI KASEI [AKD4641EN-A] 2. 16bit Mono CODEC [Measurement condition] • Measurement unit • BBICK • fs • Bit • Power Supply • Measurement Filter • Temperature : ROHDE & SCHWARZ, UPD05 : 32fs : 8kHz : 16bit : AVDD=BVDD=DVDD=3.3V : 20Hz ∼ 4kHz : Room [Measurement Results] 1. ADC (AUXIN) characteristics ( MICAD =0, AUXIN Æ Mixer Æ ADC, AUX Volume = 0dB) [dB] THD+N 20kHzLPF (-1dB) 78.5 DR 20kHzLPF + A-weighted 88.7 S/N 20kHzLPF + A-weighted 88.9 2. DAC (MOUT) characteristics (RL=20kΩ, DAC Æ MOUT, ATT = 0dB) [dB] THD+N 20kHzLPF (-0dB) DR 20kHzLPF + A-weighted 78.9 91.4 S/N 20kHzLPF + A-weighted 92.0 3. Loop-back (AUXIN Æ ADC Æ DAC Æ MOUT) [dB] THD+N 20kHzLPF (-3dB) 76.7 DR 20kHzLPF + A-weighted 87.9 S/N 20kHzLPF + A-weighted 88.0 <KM082001> 2006/03 - 22 - ASAHI KASEI [AKD4641EN-A] 3. 16bit stereo CODEC PLOT DATA 3-1. ADC (MIC Æ IPGA Æ ADC) PLOT DATA AKM AK4641 ADC(INT) THD+N vs. Input Level VDD=3.3V, fs=44.1kHz, fin=1kHz -60 -62 -64 -66 -68 -70 -72 -74 -76 d B F S -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure 1. THD+N vs. Input Level AKM AK4641 ADC(INT) THD+N vs. Input Frequency VDD=3.3V, fs=44.1kHz, Input=-1dB -60 -62 -64 -66 -68 -70 -72 -74 -76 d B F S -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 2. THD+N vs. Input Frequency <KM082001> 2006/03 - 23 - ASAHI KASEI [AKD4641EN-A] AK M AK 4641 AD C (INT) Linearity V D D=3.3V, fs=44.1kHz, fin=1kHz +0 -10 -20 -30 -40 d B F S -50 -60 -70 -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dB r Figure 3. Linearity AK M AK 4641 A D C (INT) Frequency R esponse VD D =3.3V, fs=44.1kHz, Input=-1dB -0 -0.5 -1 -1.5 d B F S -2 -2.5 -3 -3.5 -4 -4.5 -5 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 4. Frequency Response <KM082001> 2006/03 - 24 - ASAHI KASEI [AKD4641EN-A] AKM AK4641 ADC(INT) FFT Plot VDD=3.3V, fs=44.1kHz, fin=1kHz, Input=-1dB +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 5. FFT Plot ( Input level=-1dBFS) AKM AK4641 ADC(INT) FFT Plot VDD=3.3V, fs=44.1kHz, fin=1kHz, Input=-60dB +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k Hz Figure 6. FFT Plot ( Input level=-60dBFS ) <KM082001> 2006/03 - 25 - ASAHI KASEI [AKD4641EN-A] AKM AK4641 ADC(INT) FFT Plot VDD=3.3V, fs=44.1kHz, Input=no signal +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 7. FFT Plot ( No signal ) <KM082001> 2006/03 - 26 - ASAHI KASEI [AKD4641EN-A] 3-2. DAC (DAC Æ Mono Out) PLOT DATA AKM AK4641 DAC(LOUT/ROUT) THD+N vs. Input Level VDD=3.3V, fs=44.1kHz, fin=1kHz -60 -62 -64 -66 -68 -70 -72 -74 -76 d B r A -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 8. THD+N vs. Input Level AKM AK4641 DAC(LOUT/ROUT) THD+N vs. Input Frequency VDD=3.3V, fs=44.1kHz, Input Level=-3dB -60 -62 -64 -66 -68 -70 -72 -74 -76 d B r A -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 9. THD+N vs. Input Frequency <KM082001> 2006/03 - 27 - ASAHI KASEI [AKD4641EN-A] AKM AK4641 DAC(LOUT/ROUT) Linearity VDD=3.3V, fs=44.1kHz, fin=1kHz +0 -10 -20 -30 -40 d B r A -50 -60 -70 -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 10 Linearity AK M AK 4641 D A C (LO UT/R O UT) Frequency R esponse VD D =3.3V, fs=44.1kHz, Input=-0dB + 0.5 + 0.4 + 0.3 + 0.2 d B r + 0.1 A -0.1 +0 -0.2 -0.3 -0.4 -0.5 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Hz Figure 11. Frequency Response <KM082001> 2006/03 - 28 - ASAHI KASEI [AKD4641EN-A] AKM AK4641 DAC(LOUT/ROUT) FFT Plot VDD=3.3V, fs=44.1kHz, fin=1kHz, Input Level=-3dB +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 12. FFT Plot ( Input level=-3dBFS ) AKM AK4641 DAC(LOUT/ROUT) FFT Plot VDD=3.3V, fs=44.1kHz, fin=1kHz, Input=-60dB +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k Hz Figure 13. FFT Plot ( Input level=-60.0dBFS ) <KM082001> 2006/03 - 29 - ASAHI KASEI [AKD4641EN-A] AKM AK4641 DAC(LOUT/ROUT) FFT Plot VDD=3.3V, fs=44.1kHz, Input=no signal +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 14. FFT Plot ( No signal ) AKM AK4641 DAC(LOUT/ROUT) FFT Plot VDD=3.3V, fs=44.1kHz, Input = no signal +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k Hz Figure 15. Out-of-band Noise <KM082001> 2006/03 - 30 - ASAHI KASEI [AKD4641EN-A] AK M A K4641 D AC (LO UT/R O UT) C rosstalk VD D =3.3V, fs=44.1kHz, Input=-0dB -60 -65 -70 -75 -80 -85 d B -90 -95 -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 16. Crosstalk Plot <KM082001> 2006/03 - 31 - ASAHI KASEI [AKD4641EN-A] 4. 16bit Mono CODEC PLOT DATA 4-1. ADC (AUXIN Æ Mixer Æ ADC) PLOT DATA Figure 17. THD+N vs. Input Level Figure 18. THD+N vs. Input Frequency <KM082001> 2006/03 - 32 - ASAHI KASEI [AKD4641EN-A] Figure 19. Linearity Figure 20. Frequency Response <KM082001> 2006/03 - 33 - ASAHI KASEI [AKD4641EN-A] Figure 21. FFT Plot ( Input level=-1dBFS) Figure 22. FFT Plot ( Input level=-60dBFS ) <KM082001> 2006/03 - 34 - ASAHI KASEI [AKD4641EN-A] Figure 23. FFT Plot ( No signal ) <KM082001> 2006/03 - 35 - ASAHI KASEI [AKD4641EN-A] 4-2. DAC (DAC Æ Mono Out ) PLOT DATA Figure 24. THD+N vs. Input Level Figure 25. THD+N vs. Input Frequency <KM082001> 2006/03 - 36 - ASAHI KASEI [AKD4641EN-A] Figure 26 Linearity Figure 27. Frequency Response <KM082001> 2006/03 - 37 - ASAHI KASEI [AKD4641EN-A] Figure 28. FFT Plot ( Input level=-0dBFS ) Figure 29. FFT Plot ( Input level=-60.0dBFS ) <KM082001> 2006/03 - 38 - ASAHI KASEI [AKD4641EN-A] Figure 30. FFT Plot ( No signal ) <KM082001> 2006/03 - 39 - ASAHI KASEI [AKD4641EN-A] Revision History Date (YY/MM/DD) 05/11/29 06/03/13 Manual Revision KM082000 KM082001 Board Revision 0 1 Reason First Edition Update Contents Change of a figure & circuit IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <KM082001> 2006/03 - 40 - A C D E REG(+5V) T1 TA48M33F AGND LOUT MOUT- AUXIN+ AUXIN- MOUT+ IN E GND JP1 GND DGND B REG OUT C1 0.1u C3 + 47u C2 0.1u E EXT AGND R1 2.2k D3.3V 2 + 1 C4 1u 28 29 30 31 32 33 C5 1u + L1 DGND R2 1 MPE 2 3 28 29 LOUT MOUT- 30 31 MOUT+ AIN AUXIN+ AUXIN- 32 33 35 MICOUT EXT 1 MDT U1 CN2 D 34 VCC Short 47u 36 + 34 36 JP2 DVDD D3.3V_SEL VCC(D3.3V) C6 35 CN1 DVDD0 D CN3 ROUT 27 27 ROUT MPI MOUT2 26 26 MOUT2 INT TST2 25 25 TST2 24 BBICK 23 BSYNC 22 4641_BSDTO 21 BSDTI 2.2k 2 C7 1u INT 3 + 51 R3 4 4 C8 2.2u C JP3 AVDD_SEL L2 1 C12 + AVDD Short BBICK 5 AK4641 AVSS 24 51 R4 BSYNC 23 C10 C11 10u 0.1u 6 2 VCOM C9 0.1u 5 + REG AVDD + 51 R5 6 AVDD BSDTO 22 7 BVDD BSDTI 21 8 BVSS DVSS 20 AVDD0 51 R6 7 47u C13 10u + C14 0.1u 8 AGND MCLK 18 BICK 17 16 DVDD1 19 14 15 4641_SDTI 4641_SDTO B R15 51 18 13 SDA R14 51 4641_MCKI 12 SCL JP5 DVDD_SEL BVDD DVDD L4 1 + 19 CN4 BVDD0 A R13 51 17 11 R12 51 TST1 R11 51 10 R10 51 4641_PDN AGND R9 51 4641_BICK R8 51 47u C19 LRCK SDTO 15 SDTI 14 SDA 13 12 SCL TST1 BVDD 16 + C16 10u BVDD0 2 Short 4641_LRCK 1 DVDD 10 AVDD L3 C18 VCOC R7 5.1k 11 JP4 BVDD_SEL 9 C17 470n PDN 9 AVDD0 B 20 C15 0.1u BVDD C + REG R16(short) DVDD1 2 DVDD Short 47u A DVDD0 Title AGND Size A3 Date: A B C D AKD4641 Document Number Rev AK4641 Friday, November 25, 2005 Sheet E A 1 of 6 A B + R19 220 LOUT C22 1u RCA R20 10k HP E C20 1u J1 LOUT + C21 22u D + LOUT/HP_SEL JP6 LOUT C R17 10k R18 10k R21 10k R22 10k E E R23 U2 ROUT/HP_SEL JP7 HP C23 22u R27 220 + ROUT ROUT R28 10k H/SVDD J3 ROUT R25 20k RCA R26 20k JP8 SHDN_L + C24 2.2u JP9 SHDN_R + C25 2.2u + EXT J4 MIC D EXT C26 2.2u 10 INL OUTL 8 13 INR OUTR 11 1 12 SHDNL SHDNR R24 9 2 3 5 6 4 SVDD PVDD C1P C1N PVSS PGND (short) 7 SVSS 14 JP10 SHDN (short) J2 HP SGND MAX4410 D JP11 MIC INT INT H/SVDD C27 1u + RCA 1 AUXIN+ + C28 47u 2 H/SVDD L5 (short) 2 R29 47k 1 J5 AUXIN+ J6 AUXINRCA R30 47k MOUT2/SPK_SEL JP12 MOUT2 C30 22u AUXIN- + C C29 1u + MOUT2 C31 C R33 220 MOUT+ 22u MOUT- J8 MOUT+ + + JP13MOUT+/-_SEL MOUT+ RCA R35 10k C33 0.47u + B MOUT2 RCA R32 10k SPK J7 R31 220 JP14 DIFF1 + C34 C32 100p R34 20k SPK1 U3 R36 20k H/SVDD MOUT- R37 20k 22u R39 R40 10k 100 2 3 JP15 SHDN_SPK 3 +IN -IN 2 1 BYPASS SHUTDOWN 6 VDD 7 GND + C35 1u Vo1 Vo2 5 8 R 2 B 1 L LM4889 1 2 3 4 R38 (short) J9 MOUT 020S16 CN5 R41 100 1 JP16 DIFF2 R42 10k H/SVDD C36 + 1u A A Title Size A3 Date: A B C D AKD4641 Document Number Rev Input/Output Friday, November 25, 2005 Sheet E A 2 of 6 A E B C D E E 4.096MHz X1 1 2 R43 1M U4A 1 U4B 2 3 74HCU04 JP17 XTE C37 15p 4 74HCU04 C38 15p D D MCLK_256fs 512fs 10 11 CLK C JP19 CLK_SEL EXT J10 BBICK U5 CLK RST Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1 74VHC4040 R44 51 256fs 128fs 64fs 32fs EXT 2fs 1fs JP18 EXT_BBICK C BBICK_SEL JP20 JP21 BSYNC_SEL2 I2S EXT EXT_BSYNC SHORT U6A BSYNC_SEL1 1 3 JP22 EXT1 2 74AC08 D3.3V 1 JP23 EXT2 Q 6 74AC74 PORT_BSYNC D 11 CLK U7B PR Q 12 Q 9 CL CLK 5 Q 8 74AC74 13 U7A 4 D 3 CL R45 51 2 10 B J11 BSYNC PR B U8A 1 2 74AC04 A A Title Size A3 Date: A B C D AKD4641 Document Number Rev CLOCK_Bth Wednesday, July 23, 2003 Sheet E A 3 of 6 A B C JP27 BICK1 DIR U12 11 4641_MCKI Y8 A8 12 4641_LRCK 13 DIR_MCLK2 DIR_BICK 2 Y7 A7 8 Y6 A6 7 E 1 1 G1 VCC 20 D3.3V C53 0.1u 74HC14 19 G2 GND 10 2 A1 Y1 18 THR JP29 LRCK1 DIR DIR_LRCK 14 Y5 A5 6 3 A2 Y2 17 15 Y4 A4 5 4 A3 Y3 16 16 Y3 A3 4 5 A4 Y4 15 17 Y2 A2 3 6 A5 Y5 14 18 Y1 A1 2 7 A6 Y6 13 10 GND G2 19 8 A7 Y7 12 20 VCC G1 1 9 A8 Y8 11 MCLK BICK LRCK SDTI VCC JP30 BICK2 DIR PORT PORT 4641_SDTI E U13 U19A 9 JP28 BICK_INV INV 4641_BICK DIR_MCLK1 MCKO2 PORT E D JP26 MCLK_SEL MCKO1 10 9 8 7 6 Audio I/F JP31 LRCK2 DIR PORT R53 100k PORT3 1 2 3 4 5 R52 D3.3V 10k SDTO JP32 SDTI1 LOOP D D DIR_SDTI DIR C54 0.1u 74HC541 74LVC541 C JP33 SDTI2 D3.3V C 4641_SDTO D3.3V U15 1 2 3 4 5 10 9 8 7 6 470 R56 10k R57 470 R58 10k R59 470 TST2N 2 3 5 6 11 10 14 13 1A 1B 2A 2B 3A 3B 4A 4B 1 15 A/B G CSN SCL SDA CDTO B 1Y 4 TST1 2Y 7 SCL 3Y 9 SDA 4Y 12 D3.3V 2 R55 1 10k D2 HSU119 R60 10k U9C 5 L 74LVC157 74HC14 H SW2 PDN 9 8 4641_PDN 74HC14 C55 0.1u 2 CTRL U9D 6 1 PORT4 R54 3 B D3.3V JP34 BSDTO A R61 1.8k A U16A BSDTO 1 R62 10k 2 Title 74LVC07 Size A3 Date: A B C D AKD4641 Document Number Rev LOGIC_AUDIO Wednesday, July 23, 2003 Sheet E 5 A of 6 A B E C 11 E U18 U17 BBICK D Y8 A8 9 1 E G1 VCC 20 D3.3V C56 0.1u MCLK_256fs BSYNC 12 Y7 A7 8 19 G2 GND 10 BSDTI 13 Y6 A6 7 2 A1 Y1 18 JP35 BBICK2 INT PORT 14 Y5 A5 6 3 A2 Y2 17 JP36 BSYNC2 INT PORT Y4 A4 5 A3 Y3 16 15 R63 100k 4 MCLK BBICK BSYNC BSDTI VCC PORT5 1 2 3 4 5 10 9 8 7 6 Bth I/F R64 PORT_BSYNC D D3.3V D 10k 16 A3 4 5 A4 Y4 15 Y3 17 Y2 A2 3 6 A5 Y5 14 18 Y1 A1 2 7 A6 Y6 13 10 GND G2 19 8 A7 Y7 12 20 VCC G1 1 9 A8 Y8 11 BSDTO JP37 SDTI PORT LOOP C57 0.1u 74HC541 74LVC541 C C 4641_BSDTO D3.3V JP39 BBICK_INV INV THR JP38 BBICK1 INT U19B 4 EXT_BBICK 3 PORT 74HC14 JP40 BSYNC1 INT EXT_BSYNC PORT B B U6B 6 5 6 U9E U11C U4C 4 5 6 11 U8B U16B 10 3 4 3 4 5 74HC04 74HCU04 74AC08 U11D U4D U6C 9 8 74HC14 U9F 9 8 13 12 74AC04 74LVC07 U8C U16C 5 6 5 6 9 74HC04 74HCU04 8 74HC14 U19C 10 U11E U4E 74AC08 11 10 11 U6D 11 13 5 12 13 12 6 9 8 U8D U16D 9 74HC14 U19D U11F U4F 12 10 74HC04 74HCU04 74AC04 74LVC07 8 9 U8E U16E 11 10 8 74AC04 74LVC07 11 10 13 74HCU04 74AC08 74HC04 74HC14 U19E A 11 10 74HC14 U19F 13 12 74LVC07 D3.3V U8F U16F 13 for 74AC02,74AC74,74HC04,74HC14,74HC14,74AC4040,74HCU04,74LVC07,74LVC157,74AC04 74AC04 74LVC07 13 A 12 74AC04 C58 0.1u 12 C59 0.1u C60 0.1u C61 0.1u C62 0.1u C63 0.1u C64 0.1u C65 0.1u C66 0.1u C67 0.1u +C68 47u Title Size 74HC14 A3 Date: A B C D AKD4641 Document Number Rev LOGIC_Bth Wednesday, July 23, 2003 Sheet E A 6 of 6 A B C D E C39 C40 0.1u 0.1u D3.3V L6 (short) R46 10k VCC GND OUT 0.1u C42 10u R47 470 2 D1 HSU119 E U9B 1 74HC14 D3.3V + TORX141 U9A 4 3 74HC14 L C43 0.1u H SW1 DIR 2 C44 0.1u 1 C41 3 2 1 3 PORT1 1 2 E 2 1 D3.3V 1 37 INT1 38 AVDD 39 40 R AVSS R48 18k VCOM 41 42 RX0 43 NC 44 RX1 46 45 TEST1 NC RX2 U10 14 13 12 11 10 9 8 47 SW3 1 2 3 4 5 6 7 RX3 DIF0 DIF2 CM0 CM1 OCKS1 TST2 D 48 C45 0.47u D R49 1k U11A IPS0 INT0 36 1 2 LED1 ERF 2 1 D3.3V 74HC04 MODE 2 NC OCKS0 35 3 DIF0 OCKS1 34 OCKS1 4 TEST2 CM1 33 CM1 5 DIF1 CM0 32 CM0 6 NC PDN 31 RP1 CM0 CM1 OCKS1 TST2 U11B 47k 3 4 TST2N AK4114 74HC04 C 7 DIF2 8 C C46 10p XTI 30 IPS1 XTO 29 9 P/SN DAUX 28 10 XTL0 MCKO2 27 11 XTL1 BICK 26 DIR_BICK 12 VIN SDTO 25 DIR_SDTI J12 JP24 XTI R5051 EXT 1 7 6 5 4 3 2 1 C47 10p R51 51 2 X2 11.2896MHz JP25 EXT SDTO DIR_MCLK2 LRCK 24 MCKO1 23 22 DVSS DVDD 21 C49 0.1u DIR_LRCK + 20 VOUT UOUT 19 COUT 18 BOUT 17 TX1 16 15 14 TVDD C48 0.1u + 13 TX0 B DVSS B DIR_MCLK1 C50 10u C51 10u D3.3V D3.3V PORT2 A IN VCC GND 3 2 1 A D3.3V C52 0.1u TOTX141 Title Size A3 Date: A B C D AKD4641 Document Number Rev DIR/DIT Wednesday, July 23, 2003 Sheet E A 4 of 6