AKM AKD4648

[AK4648]
AK4648
Stereo CODEC with MIC/HP/SPK-AMP
GENERAL DESCRIPTION
The AK4648 is a stereo CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier, and
Speaker-Amplifier. The AK4648 features analog mixing circuits and PLL that allows easy interfacing in
mobile phone and portable A/V player designs. The AK4648 is available in a CSP (3.7mm x 3.8mm),
utilizing less board space than competitive offerings.
FEATURES
1. Recording Function
• 4 Stereo Inputs Selector
• Stereo Mic Input (Full-differential or Single-ended)
• Stereo Line Input
• MIC Amplifier (+32dB/+26dB/+20dB or 0dB)
• Digital ALC (Automatic Level Control)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
• ADC Performance: S/(N+D): 83dB, DR, S/N: 86dB (MIC-Amp=+20dB)
S/(N+D): 88dB, DR, S/N: 95dB (MIC-Amp=0dB)
• Wind-noise Reduction Filter
• Stereo Separation Emphasis
• Programmable EQ
2. Playback Function
• Digital De-emphasis Filter (tc=50/15μs, fs=32kHz, 44.1kHz, 48kHz)
• 5-Band Equalizer
• Soft Mute
• Digital Volume (+12dB ∼ −115.0dB, 0.5dB Step, Mute)
• Digital ALC (Automatic Level Control)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
• Stereo Separation Emphasis
• Programmable EQ
• Stereo Line Output
- Performance: S/(N+D): 88dB, S/N: 92dB
• Stereo Headphone-Amp
- Support Pseudo Cap-less and Single-ended modes
- Analog Volume: + 3dB ~ - 33dB, 3dB Step
- S/(N+D): [email protected], S/N: 90dB
- Output Power: [email protected] (HVDD=3.6V)
[email protected] (HVDD=4.5V)
- Pop Noise Free at Power ON/OFF
• Stereo Speaker-Amp
- S/(N+D): 60dB @ 240mW, S/N: 90dB
- BTL
- Output Power: 820mW @ 8Ω, HVDD=3.6V, High Power Mono SPK Mode
1.6W @ 8Ω, HVDD=5V, High Power Mono SPK Mode
640mW @ 8Ω, HVDD=3.6V, Stereo SPK & Mono SPK Mode
1.0W @ 8Ω, HVDD=4.5V, Stereo SPK Mode
1.3W @ 8Ω, HVDD=5V, Mono SPK Mode
- Pop Noise Free at Power ON/OFF
• Analog Mixing: 4 Stereo Input
3. Power Management
MS0625-E-01
2007/06
-1-
[AK4648]
4. Master Clock:
(1) PLL Mode
• Frequencies:
- MCKI pin: 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz,
19.2MHz, 24MHz, 26MHz, 27MHz
- LRCK pin: 1fs
- BICK pin: 32fs or 64fs
(2) External Clock Mode
• Frequencies: 256fs, 512fs or 1024fs (MCKI pin)
5. Output Master Clock Frequencies: 32fs/64fs/128fs/256fs
6. Sampling Rate:
• PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• EXT Master/Slave Mode:
7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs)
7. μP I/F: I2C Bus (Ver 1.0, 400kHz Fast-Mode)
8. Master/Slave mode
9. Audio Interface Format: MSB First, 2’s complement
• ADC: 16bit MSB justified, I2S, DSP Mode
• DAC: 16bit MSB justified, 16bit LSB justified, 16-24bit I2S, DSP Mode
10. Ta = −30 ∼ 85°C
11. Power Supply:
• AVDD, DVDD: 2.6 ∼ 3.6V (typ. 3.3V)
• HVDD: 2.6 ∼ 5.0V (typ. 3.6V)
• TVDD (Digital I/O): 1.6 ∼ 3.6V (typ. 3.3V)
12. Package: CSP (3.7mm x 3.8mm, 0.5mm pitch)
13. Register Compatible with AK4643/4/5
MS0625-E-01
2007/06
-2-
[AK4648]
■ Block Diagram
AVDD VSS1
VCOM
DVDD
VSS3
TVDD
MPWR
PMMP
MPWR
MIC Power
Supply
PMADL
or PMMICL
LIN1
Internal
MIC
CAD0
Control
Register
A/D
MIC-Amp
LIN2
External
MIC
Wind-Noise Stereo
HPF Reduction Separation
SDA
PDN
PMADL or PMADR
RIN1
SCL
ALC
PMADR
or PMMICR
BICK
RIN2
LRCK
SDTO
PMAINR2
LIN3/MIN
Line In
RIN3/VCOC
Line In
RIN4
Audio
I/F
PMAINL2
SDTI
LIN4
PMAINR3
PMAINR4
PMAINL3
PMAINL4
PMMIN
PMLO
PMDAC
LOUT
Stereo Line Out
or
Mono Diff Out
D/A
Stereo
DATT 5-Band ALC
Separation
SMUTE EQ
HPF
ROUT
MCKO
PMPLL
PMHPL
PLL
VCOC
HPL
Headphone
MCKI
PMHPR
HPR
MUTET
PMHPC
Common Output
for HP-Amp
Common
HVCM
SPLP
Speaker
SPLN
PMSPL
SPRP
Speaker
SPRN
PMSPR
HVDD VSS2
(VCOC and RIN3 pins are shared by the same pin.)
Figure 1. Block Diagram
MS0625-E-01
2007/06
-3-
[AK4648]
■ Compatibility with the AK4643 and AK4645
1. Function
Function
Digital I/O of μP I/F
Analog Mixing for Playback
Input Selector for Recording
HP-Amp Hi-Z Setting for wired OR
PLL
Speaker-Amp
Headphone-Amp
Receiver-Amp
Bass Boost
5-band EQ
up I/F
Package
AK4643
2.6 to 3.6V
3 Stereo
3 Stereo
No
11.2896/12/12.288/
13.5/24/27MHz
Yes (Mono)
Yes
(Po=62mW @ 3.3V)
AK4645
1.6 to 3.6V
4 Stereo
4 Stereo
Yes
11.2896/12/12.288/13/
13.5/19.2/24/26/27MHz
No
←
Yes
Yes
No
3-wire/I2C
32QFN (5mm x 5mm)
No
←
←
←
←
MS0625-E-01
AK4648
←
←
←
←
←
Yes (Stereo)
Yes
(Po=40mW @ 3.6V)
Support Pseudo cap-less
←
No
Yes
I2C
CSP (3.7x 3.8mm)
2007/06
-4-
[AK4648]
2. Register (difference from the AK4643/5)
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Lch Input Volume Control
Lch Digital Volume Control
ALC Mode Control 3
Rch Input Volume Control
Rch Digital Volume Control
Mode Control 3
Mode Control 4
Power Management 3
Digital Filter Select
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
Power Management 4
Mode Control 5
Lineout Mixing Select
HP Mixing Select
SPK Mixing Select
EQ Control 250Hz/100Hz
EQ Control 3.5kHz/1kHz
EQ Control 10kHz
D7
PMSPR
HPZ
SPPSN
LOVL
PLL3
PS1
DVTM
0
REF7
IVL7
DVL7
RGAIN1
IVR7
DVR7
0
HPG3
INR1
GN1
F3A7
F3AS
F3B7
0
EQA7
EQA15
EQB7
0
EQC7
EQC15
F1A7
F1AS
F1B7
0
D6
PLL1
FS3
ZTM1
ALC
REF5
IVL5
DVL5
0
IVR5
DVR5
SMUTE
HPG1
0
0
F3A5
F3A13
F3B5
F3B13
EQA5
EQA13
EQB5
EQB13
EQC5
EQC13
F1A5
F1A13
F1B5
F1B13
D4
PMSPL
PMHPR
DACL
SPKG1
PLL0
MSBS
ZTM0
ZELMN
REF4
IVL4
DVL4
0
IVR4
DVR4
DVOLC
HPG0
MDIF2
FIL1
F3A4
F3A12
F3B4
F3B12
EQA4
EQA12
EQB4
EQB12
EQC4
EQC12
F1A4
F1A12
F1B4
F1B12
D3
PMLO
M/S
0
SPKG0
BCKO
BCKP
WTM1
LMAT1
REF3
IVL3
DVL3
0
IVR3
DVR3
0
IVOLC
MDIF1
EQ
F3A3
F3A11
F3B3
F3B11
EQA3
EQA11
EQB3
EQB11
EQC3
EQC11
F1A3
F1A11
F1B3
F1B11
D2
PMDAC
PMHPC
PMMP
MINL
0
FS2
WTM0
LMAT0
REF2
IVL2
DVL2
0
IVR2
DVR2
FBEQ
HPM
INR0
FIL3
F3A2
F3A10
F3B2
F3B10
EQA2
EQA10
EQB2
EQB10
EQC2
EQC10
F1A2
F1A10
F1B2
F1B10
D1
0
MCKO
0
SPKG2
DIF1
FS1
RFST1
RGAIN0
REF1
IVL1
DVL1
VBAT
IVR1
DVR1
DEM1
MINH
INL0
0
F3A1
F3A9
F3B1
F3B9
EQA1
EQA9
EQB1
EQB9
EQC1
EQC9
F1A1
F1A9
F1B1
F1B9
HPMTN
MINS
LOPS
PLL2
PS0
WTM2
0
REF6
IVL6
DVL6
LMTH1
IVR6
DVR6
LOOP
HPG2
INL1
GN0
F3A6
0
F3B6
0
EQA6
EQA14
EQB6
0
EQC6
EQC14
F1A6
0
F1B6
0
0
DIF0
FS0
RFST0
LMTH0
REF0
IVL0
DVL0
0
IVR0
DVR0
DEM0
DACH
PMADR
0
F3A0
F3A8
F3B0
F3B8
EQA0
EQA8
EQB0
EQB8
EQC0
EQC8
F1A0
F1A8
F1B0
F1B8
PMAINR4
PMAINL4
0
LOM
0
0
FBEQB3
FBEQD3
0
XXX
XXX
XXX
PMAINR3
PMAINL3
PMAINR2
PMAINL2
PMMICR
PMMICL
SPKMN
MICR3
MICL3
L4DIF
LOM3
RINR4
LINL4
RINR3
HPM3
RINH4
LINH4
RINH3
0
RINS4
LINS4
RINS3
FBEQB2 FBEQB1 FBEQB0 FBEQA3
FBEQD2 FBEQD1 FBEQD0 FBEQC3
0
0
0
FBEQE3
These bits are changed from the AK4645.
These bits are changed from the AK4643.
These bits are changed from the AK4643/5.
MIX
LINL3
LINH3
LINS3
FBEQA2
FBEQC2
FBEQE2
AIN3
RINR2
RINH2
RINS2
FBEQA1
FBEQC1
FBEQE1
LODIF
LINL2
LINH2
LINS2
FBEQA0
FBEQC0
FBEQE0
PMVCM
D5
PMMIN
PMHPL
DACS
MGAIN1
MS0625-E-01
D0
PMADL
PMPLL
MGAIN0
2007/06
-5-
[AK4648]
■ Ordering Guide
−30 ∼ +85°C
CSP (3.7mm x 3.8mm, 0.5mm pitch)
Evaluation board for AK4648
AK4648EC
AKD4648
■ Pin Layout
Top View
7
6
5
4
3
2
1
A
B
C
D
E
F
G
Top View
7
6
5
4
3
2
1
TEST
LIN4/IN4+
ROUT/LON
SPRP
HVDD
NC
A
VCOM
RIN2/IN2LOUT/LOP
SPRN
VSS2
SPLP
SPLN
B
AVDD
MIN/LIN3
LIN2/IN2+
RIN4/IN4HVCM
VSS2
C
LIN1/IN1VSS1
NC
NC
HPL
HPR
MUTET
D
MS0625-E-01
MPWR
VCOC/RIN3
NC
NC
DVDD
PDN
VSS3
E
CAD0
SCL
RIN1/IN1+
SDA
SDTO
TVDD
MCKI
F
NC
SDTI
LRCK
BICK
MCKO
TVDD
NC
G
2007/06
-6-
[AK4648]
PIN/FUNCTION
No.
A1, D4,
D5, E4,
E5, G1
G7
A2
A4
Pin Name
I/O
NC
-
HVDD
SPRP
ROUT
LON
LIN4
IN4+
O
O
O
I
I
A7
TEST
O
B1
B2
B3, C1
B4
SPLN
SPLP
VSS2
SPRN
LOUT
LOP
RIN2
IN2−
O
O
O
O
O
I
I
B7
VCOM
O
C2
C7
HVCM
RIN4
IN4−
LIN2
IN2+
MIN
LIN3
AVDD
O
I
I
I
I
I
I
-
D1
MUTET
O
D2
D3
D6
E1
HPR
HPL
VSS1
LIN1
IN1−
VSS3
O
O
I
I
-
E2
PDN
I
E3
DVDD
-
VCOC
O
RIN3
MPWR
MCKI
TVDD
SDTO
SDA
RIN1
IN1+
I
O
I
O
I/O
I
I
A5
A6
B5
B6
C4
C5
C6
D7
E6
E7
F1
F2, G2
F3
F4
F5
Function
No Connection Pin
This should be connected to ground (VSS1, VSS2 or VSS3 pin).
Headphone Amp Power Supply Pin, 2.6 ∼ 5.0V
Rch Speaker-Amp Positive Output Pin
Rch Stereo Line Output Pin (LODIF bit = “0”: Single-ended Stereo Output)
Negative Line Output Pin (LODIF bit = “1”: Full-differential Mono Output)
Lch Analog Input 4 Pin (L4DIF bit = “0”: Single-ended Input)
Positive Line Input 4 Pin (L4DIF bit = “1”: Full-differential Input)
Test Pin
This pin should be open.
Lch Speaker-Amp Negative Output Pin
Lch Speaker-Amp Positive Output Pin
Ground 2 Pin
Rch Speaker-Amp Negative Output Pin
Lch Stereo Line Output Pin (LODIF bit = “0”: Single-ended Stereo Output)
Positive Line Output Pin (LODIF bit = “1”: Full-differential Mono Output)
Rch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
Microphone Negative Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
Common Voltage Output Pin, 0.45 x AVDD
Bias voltage of ADC inputs and DAC outputs.
Headphone-Amp Common Voltage Output Pin
Rch Analog Input 4 Pin (L4DIF bit = “0”: Single-ended Input)
Negative Line Input 4 Pin (L4DIF bit = “1”: Full-differential Input)
Lch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
Microphone Positive Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
Mono Signal Input Pin (AIN3 bit = “0”: PLL is available.)
Lch Analog Input 3 Pin (AIN3 bit = “1”: PLL is not available.)
Analog Power Supply Pin, 2.6 ∼ 3.6V
Mute Time Constant Control Pin
Connected to VSS2 pin with a capacitor for mute time constant.
Rch Headphone-Amp Output Pin
Lch Headphone-Amp Output Pin
Ground 1 Pin
Lch Analog Input 4 Pin (MDIF1 bit = “0”: Single-ended Input)
Microphone Negative Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)
Ground 3 Pin
Power-Down Mode Pin
“H”: Power-up, “L”: Power-down, reset and initializes the control register.
Digital Power Supply Pin, 2.6 ∼ 3.6V
Output Pin for Loop Filter of PLL Circuit (AIN3 bit = “0”: PLL is available.)
This pin should be connected to VSS1 with one resistor and capacitor in series.
Rch Analog Input 3 Pin (AIN3 bit = “1”: PLL is not available.)
MIC Power Supply Pin
External Master Clock Input Pin
Digital I/O Power Supply Pin, 1.6 ∼ 3.6V
Audio Serial Data Output Pin
Control Data Input/Output Pin
Rch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)
Microphone Positive Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)
MS0625-E-01
2007/06
-7-
[AK4648]
PIN/FUNCTION (cont.)
No.
F6
F7
G3
G4
G5
G6
Pin Name
SCL
CAD0
MCKO
BICK
LRCK
SDTI
I/O
I
I
O
I/O
I/O
I
Function
Control Data Clock Pin
Chip Address Select Pin
Master Clock Output Pin
Audio Serial Data Clock Pin
Input / Output Channel Clock Pin
Audio Serial Data Input Pin
Note 1. All input pins except analog input pins (MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3, RIN4, and LIN4 pins)
should not be left floating.
Note 2. All analog input pins (MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3, LIN4, and RIN4 pins) should supply signal
via AC-coupling capacitor.
Note 3. Analog output pins (HPL, HPR, LOUT, and ROUT pins) except speaker output (SPLP, SPLN, SPRP and SPRN
pins ) and headphone output in Pseduo cap-less mode (HPL and HPR pins) should deliver signal via AC-couplling
capacitor.
■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
MPWR, VCOC/RIN3, HPR, HPL, MUTET,
RIN4/IN4−, LIN4/IN4+, ROUT/LON, LOUT/LOP,
MIN/LIN3, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−,
RIN1/IN1+, SPRP, SPRN, HVCM, SPLP, SPLN,
TEST
Setting
These pins should be open.
These pins should be connected to
VSS3.
These pins should be open.
MCKI, SDTI
MCKO, SDTO
MS0625-E-01
2007/06
-8-
[AK4648]
ABSOLUTE MAXIMUM RATINGS
(VSS1, VSS2, VSS3=0V; Note 4, Note 5)
Parameter
Symbol
min
Power Supplies:
Analog
AVDD
−0.3
(Note 5)
Digital
DVDD
−0.3
Digital I/O
TVDD
−0.3
Headphone-Amp
HVDD
−0.3
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage (Note 6)
VINA
−0.3
Digital Input Voltage (Note 7)
VIND
−0.3
Ambient Temperature (powered applied)
Ta
−30
Storage Temperature
Tstg
−65
Pd1
Maximum Power Disspation Ta = 85°C (Note 9)
Pd2
(Note 8)
Ta =70°C (Note 10)
max
6.0
6.0
6.0
6.0
±10
AVDD+0.3
TVDD+0.3
85
150
1.2
1.46
Units
V
V
V
V
mA
V
V
°C
°C
W
W
Note 4. All voltages with respect to ground.
Note 5. VSS1, VSS2, and VSS3 must be connected to the same analog ground plane.
Note 6. RIN4/IN4−, LIN4/IN4+, MIN/LIN3, RIN3, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, and RIN1/IN1+ pins
Note 7. PDN, SCL, SDA, SDTI, LRCK, BICK, MCKI, and CAD0 pins
Pull-up resistors at SDA and SCL pins should be connected to (TVDD+0.3) V or less voltage.
Note 8. In case that PCB wriring density is 300% or more. This power is the AK4648 internal dissipation that does not
include power of externally connected speaker and headphone.
Note 9. Stereo SPK Mode is not available.
Note 10. In case of Stereo SPK Mode, Ta (max) is 70°C and HVDD voltage range is from 2.6V to 4.6V.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
MS0625-E-01
2007/06
-9-
[AK4648]
RECOMMENDED OPERATING CONDITIONS
(VSS1, VSS2, VSS3=0V; Note 4)
Parameter
Symbol
min
typ
Power Supplies Analog
AVDD
2.6
3.3
(Note 11) Digital
DVDD
2.6
3.3
Digital I/O
TVDD
1.6
3.3
HP/SPK-Amp
HVDD
2.6
3.6
Difference
0
AVDD−DVDD
−0.3
max
3.6
3.6
DVDD
5.0
+0.3
Units
V
V
V
V
V
Note 4. All voltages with respect to ground.
Note 11. The power-up sequence among AVDD, DVDD, TVDD, and HVDD is not critical. PDN pin should be held to
“L” upon power-up. PDN pin should be set to “H” after all power supplies are powered-up.The AK4648 should be
operated by the recommended power-up/down sequence shown in “System Design (Grounding and Power Supply
Decoupling)” to avoid the pop noise at speaker output, line output and headphone output.
The AK4648 supports the following two cases of partial power ON/OFF. In these cases, the
PDN pin must be “L”.
1. TVDD=HVDD=ON: AVDD=DVDD can be power ON/OFF.
2. TVDD=ON: AVDD=DVDD=HVDD can be power ON/OFF.
When the power state is changed from OFF to ON in the above cases, the PDN pin should be
changed from “L” to”H” after all power supply pins are supplied. “L” time of 150ns or more is
needed to reset the AK4648.
* AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0625-E-01
2007/06
- 10 -
[AK4648]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, TVDD=3.3V, HVDD=3.6V; VSS1=VSS2=VSS3=0V; fs=44.1kHz, BICK=64fs; Signal
Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified)
min
typ
max
Units
Parameter
MIC Amplifier: LIN1/RIN1/LIN2/RIN2/LIN4/RIN4 pins & LIN3/RIN3 pins (AIN3 bit = “1”);
PMAINL2=PMAINR2=PMAINL3=PMAINR3=PMAINL4=PMAINR4 bits = “0”;
MDIF1=MDIF2 bits = “0” (Single-ended inputs)
Input
MGAIN1-0 bits = “00”
40
60
80
kΩ
Resistance MGAIN1-0 bits = “01”, “10”or “11”
20
30
40
kΩ
MGAIN1-0 bits = “00”
0
dB
MGAIN1-0 bits = “01”
+20
dB
Gain
MGAIN1-0 bits = “10”
+26
dB
MGAIN1-0 bits = “11”
+32
dB
MIC Amplifier: IN1+/IN1−/IN2+/IN2− pins; MDIF1 = MDIF2 bits = “1” (Full-differential input)
Input Voltage (Note 12)
MGAIN1-0 bits = “00”
1.155
Vpp
MGAIN1-0 bits = “01”
0.228
Vpp
MGAIN1-0 bits = “10”
0.114
Vpp
MGAIN1-0 bits = “11”
0.057
Vpp
MIC Power Supply: MPWR pin
Output Voltage (Note 13)
2.22
2.47
2.72
V
Load Resistance
0.5
kΩ
Load Capacitance
30
pF
ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2/LIN4/RIN4 pins & LIN3/RIN3 pins (AIN3 bit = “1”)
→ ADC → IVOL, IVOL=0dB, ALC=OFF
Resolution
16
Bits
(Note 15)
0.168
0.198
0.228
Vpp
Input Voltage (Note 14)
1.68
1.98
2.28
Vpp
(Note 16)
(Note 15, LIN1/RIN1/LIN2/RIN2)
71
83
dBFS
S/(N+D)
(Note 15, LIN3/RIN3/LIN4/RIN4)
83
dBFS
(−1dBFS)
(Note 16, except for LIN3/RIN3)
88
dBFS
(Note 16, LIN3/RIN3)
72
dBFS
(Note 15)
76
86
dB
D-Range (−60dBFS, A-weighted)
95
dB
(Note 16)
(Note 15)
76
86
dB
S/N (A-weighted)
95
dB
(Note 16)
(Note 15)
75
90
dB
Interchannel Isolation
100
dB
(Note 16)
(Note 15)
0.1
0.8
dB
Interchannel Gain Mismatch
0.1
0.8
dB
(Note 16)
Note 12. The voltage difference between IN1/2+ and IN1/2− pins. AC coupling capacitor should be inserted in series at
each input pin. Maximum input voltage of IN1+, IN1−, IN2+ and IN2− pins is proportional to AVDD voltage,
respectively.
Vin = = |(IN+) − (IN−)| = 0.35 x AVDD (max) @ MGAIN1-0 bits = “00”, 0.069 x AVDD (max.)@MGAIN1-0
bits = “01”, 0.035 x AVDD (max.)@MGAIN1-0 bits = “10”, 0.017 x AVDD (max.)@MGAIN1-0 bits = “11”.
When MGAIN1-0 bits = “00”, the full scale level can not be input to ADC. The input level is -6dBFS @ IVL/R =
0dB”. When the signal larger than above value is input to IN1+, IN1−, IN2+ or IN2− pin, ADC does not operate
normally.
Note 13. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ.)
Note 14. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ.)@MGAIN1-0 bits = “01” (+20dB),
Vin = 0.6 x AVDD(typ.)@MGAIN1-0 bits = “00” (0dB)
Note 15. MGAIN1-0 bits = “01” (+20dB)
Note 16. MGAIN1-0 bits = “00” (0dB)
MS0625-E-01
2007/06
- 11 -
[AK4648]
min
typ
max
Units
Parameter
DAC Characteristics:
Resolution
16
Bits
Stereo Line Output Characteristics: DAC → LOUT/ROUT pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit =
“0”, LODIF bit = “0”, RL=10kΩ (Single-ended); unless otherwise specified.
Output Voltage (Note 17)
LOVL bit = “0”
1.78
1.98
2.18
Vpp
LOVL bit = “1”
2.25
2.50
2.75
Vpp
78
88
dBFS
S/(N+D) (−3dBFS)
S/N (A-weighted)
82
92
dB
Interchannel Isolation
80
100
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Load Resistance
10
kΩ
Load Capacitance
30
pF
Mono Line Output Characteristics: DAC → LOP/LON pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit = “0”,
LODIF bit = “1”, RL=10kΩ for each pin (Full-differential)
Output Voltage (Note 18)
LOVL bit = “0”
3.52
3.96
4.36
Vpp
LOVL bit = “1”
5.00
Vpp
78
88
dBFS
S/(N+D) (−3dBFS)
S/N (A-weighted)
85
95
dB
Load Resistance (LOP/LON pins, respectively)
10
kΩ
Load Capacitance (LOP/LON pins, respectively)
30
pF
Note 17. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ.)@LOVL bit = “0”.
Note 18. Output voltage is proportional to AVDD voltage. Vout = (LOP) − (LON) = 0.59 x AVDD (typ.)@LOVL bit =
“0”, −6dBFS.
MS0625-E-01
2007/06
- 12 -
[AK4648]
min
typ
max
Units
Parameter
Headphone-Amp Characteristics in Single-ended mode:
DAC → HPL/HPR pins, ALC=OFF, IVOL=0dB, DVOL=0dB; VBAT bit = “0”; PMHPC bit = “0”; unless otherwise
specified.
Headphone Volume (HPG3-0 bits)
Volume Range
-33
+3
dB
Gain Step: +3dB to –33dB
1.5
3
4.5
dB
Output Voltage (Note 19)
1.58
1.98
2.38
Vpp
HPG = 0dB, 0dBFS, HVDD=3.6V, RL=22.8Ω
2.24
2.8
3.36
Vpp
HPG = +3dB, 0dBFS, HVDD=4.5V, RL=100Ω
HPG = +3dB, -2dBFS, HVDD=3.6V, RL=16Ω (Po=40mW)
0.8
Vrms
HPG = +3dB, 0dBFS, HVDD=4.5V, RL=16Ω (Po=62.5mW)
1.0
Vrms
S/(N+D)
60
70
dBFS
HPG = 0dB, −3dBFS, HVDD=3.6V, RL=22.8Ω
75
dBFS
HPG = +3dB, −3dBFS, HVDD=4.5V, RL=100Ω
HPG = +3dB, -2dBFS, HVDD=3.6V, RL=16Ω (Po=40mW)
60
dBFS
HPG = +3dB, 0dBFS, HVDD=4.5V, RL=16Ω (Po=62.5mW)
60
dBFS
(Note 20)
80
90
dB
S/N (A-weighted)
90
dB
(Note 21)
(Note 20)
65
75
dB
Interchannel Isolation
80
dB
(Note 21)
(Note 20)
0.1
0.8
dB
Interchannel Gain Mismatch
0.1
0.8
dB
(Note 21)
Load Resistance
16
Ω
C1 in Figure 2
30
pF
Load Capacitance
300
pF
C2 in Figure 2
Note 19. Output voltage is proportional to AVDD voltage.
Vout = 0.6 x AVDD(typ.) @ HPG = 0dB, 0.848 x AVDD(typ.) @ HPG = +3dB
Note 20. HPG = 0dB, HVDD=3.6V, RL=22.8Ω.
Note 21. HPG = +3dB, HVDD=4.5V, RL=100Ω.
HP-Amp
HPL/HPR pin
Measurement Point
47μF
6.8Ω
C1
0.22μF
C2
16Ω
10Ω
Figure 2. Example external output circuit of HP-Amp in Single-ended mode
MS0625-E-01
2007/06
- 13 -
[AK4648]
min
typ
max
Units
Parameter
Headphone-Amp Characteristics in Pseudo Cap-less mode:
DAC → HPL/HPR pins, ALC=OFF, IVOL=0dB, DVOL=0dB; VBAT bit = “0”; PMHPC bit = “1”; unless otherwise
specified.
Headphone Volume (HPG3-0 bits)
Volume Range
-33
+3
dB
Gain Step: +3dB to –33dB
1.5
3
4.5
dB
Output Voltage (Note 22)
1.58
1.98
2.38
Vpp
HPG = 0dB, 0dBFS, HVDD=3.6V, RL=22.8Ω
2.24
2.8
3.36
Vpp
HPG = +3dB, 0dBFS, HVDD=4.5V, RL=100Ω
HPG = +3dB, -2dBFS, HVDD=3.6V, RL=16Ω (Po=40mW)
0.8
Vrms
HPG = +3dB, 0dBFS, HVDD=4.5V, RL=16Ω (Po=62.5mW)
1.0
Vrms
S/(N+D)
30
50
dBFS
HPG = 0dB, −3dBFS, HVDD=3.6V, RL=22.8Ω
60
dBFS
HPG = +3dB, −3dBFS, HVDD=4.5V, RL=100Ω
HPG = +3dB, -2dBFS, HVDD=3.6V, RL=16Ω (Po=40mW)
45
dBFS
HPG = +3dB, 0dBFS, HVDD=4.5V, RL=16Ω (Po=62.5mW)
40
dBFS
(Note 23)
80
90
dB
S/N (A-weighted)
90
dB
(Note 24)
(Note 23)
40
50
dB
Interchannel Isolation
60
dB
(Note 24)
(Note 23)
0.1
0.8
dB
Interchannel Gain Mismatch
0.1
0.8
dB
(Note 24)
Load Resistance (Note 25)
16
Ω
C1 in Figure 3
30
pF
Load Capacitance
300
pF
C2 in Figure 3
Note 22. Output voltage is proportional to AVDD voltage.
Vout = 0.6 x AVDD(typ.) @ HPG = 0dB, 0.848 x AVDD(typ.) @ HPG = +3dB
Note 23. HPG = 0dB, HVDD=3.6V, RL=22.8Ω
Note 24. HPG = +3dB, HVDD=4.5V, RL=100Ω
Note 25. Load resistance is inserted between HPL pin (HPR pin) and HVCM pin.
HP-Amp
HPL/HPR pin
Measurement Point
6.8Ω
C1
0.22μF
C2
10Ω
16Ω
VCOM Amp for
HP-Amp
HVCM pin
C2
Note: Impedance between headphone and HVCM pin should be as lower as possible. If the impedance is
larger, crosstalk and distortion might be degraded.
Figure 3. Example external output circuit of HP-Amp in Pseudo Cap-less Mode
MS0625-E-01
2007/06
- 14 -
[AK4648]
min
typ
max
Parameter
Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, IVOL=0dB, DVOL=0dB, RL=8Ω, BTL,
HVDD=3.6V; unless otherwise specified.
Output Voltage (Note 26)
3.11
SPKG2-0 bits = “000”, −0.5dBFS (Po=150mW)
3.13
3.92
4.71
SPKG2-0 bits = “001”, −0.5dBFS (Po=240mW)
HVDD=3.6V, SPKG2-0 bits = “011”, Mono/Stereo SPK Mode;
-1.5dBFS (Po=0.6W)
HVDD=3.6V, SPKG2-0 bits = “011”, High Power Mono SPK Mode,
0dBFS (Po=0.8W)
HVDD=4.5V, SPKG2-0 bits = “011”, 0dBFS (Po=1W)
Line Input Æ SPLP/SPLN or SPRP/SPRN pins, HVDD=4.5V, SPKG2-0
bits = “011”, −2.3dBV Input (Po=1W)
S/(N+D)
SPKG2-0 bits = “000”, −0.5dBFS (Po=150mW)
SPKG2-0 bits = “001”, −0.5dBFS (Po=240mW)
HVDD=3.6V, SPKG2-0 bits = “011”, Mono/Stereo SPK Mode,
-1.5dBFS (Po=0.6W)
HVDD=3.6V, SPKG2-0 bits = “011”, High Power Mono SPK Mode,
0dBFS (Po=0.8W)
HVDD=4.5V, SPKG2-0 bits = “011”, 0dBFS (Po=1W)
Line Input Æ SPLP/SPLN or SPRP/SPRN pins, HVDD=4.5V, SPKG2-0
bits = “011”, Mono/Stereo SPK Mode, −2.3dBV Input (Po=1W)
Line Input Æ SPLP/SPLN or SPRP/SPRN pins, HVDD=5V, SPKG2-0
bits = “011”, Mono SPK Mode, −1.3dBV Input (Po=1.3W)
Line Input Æ SPLP/SPLN or SPRP/SPRN pins, HVDD=5V, SPKG2-0
bits = “011”, High Power Mono SPK Mode, −0.3dBV Input (Po=1.6W)
S/N (A-weighted)
Interchannel Gain Mismatch (SPKMN bit = “1”)
Interchannel Isolation (SPKMN bit = “1”)
Load Resistance
Load Capacitance
Units
Vpp
Vpp
-
2.27
-
Vrms
-
2.56
-
Vrms
-
2.83
-
Vrms
-
2.83
-
Vrms
20
60
60
-
dB
dB
-
20
-
dB
-
20
-
dB
-
20
-
dB
-
20
-
dB
-
20
-
dB
-
20
-
dB
80
8
-
90
0.5
90
-
30
dB
dB
dB
Ω
pF
Note 26. Output voltage is proportional to AVDD voltage.
Vout = 0.94 x AVDD (typ.)@SPKG2-0 bits = “000”, 1.19 x AVDD(typ.)@SPKG2-0 bits = “001”, 2.05 x
AVDD(typ.)@SPKG2-0 bits = “010”, 2.58 x AVDD(typ.) @ SPKG2-0 bits = “011”, 0.6 x AVDD (typ.) @
SPKG2-0 bits = “100”, 0.3 x AVDD (typ.) @ SPKG2-0 bits = “101” at Full-differential output.
Note 27. In case of measuring at SPLP (SPRP) and SPLN (SPRN) pins
MS0625-E-01
2007/06
- 15 -
[AK4648]
min
Parameter
Mono Input: MIN pin (AIN3 bit = “0”; External Input Resistance=20kΩ)
typ
max
Units
Maximum Input Voltage (Note 28)
Gain (Note 29)
MIN Æ LOUT/ROUT
LOVL bit = “0”
LOVL bit = “1”
MIN Æ HPL/HPR
HPG = 0dB
MIN Æ SPLP/SPLN or SPRP/SPRN
ALC bit = “0”, SPKG2-0 bits = “000”
ALC bit = “0”, SPKG2-0 bits = “001”
ALC bit = “0”, SPKG2-0 bits = “010”
ALC bit = “0”, SPKG2-0 bits = “011”
ALC bit = “0”, SPKG2-0 bits = “100”
ALC bit = “0”, SPKG2-0 bits = “101”
ALC bit = “1”, SPKG2-0 bits = “000”
ALC bit = “1”, SPKG2-0 bits = “001”
ALC bit = “1”, SPKG2-0 bits = “010”
ALC bit = “1”, SPKG2-0 bits = “011”
ALC bit = “1”, SPKG2-0 bits = “100”
ALC bit = “1”, SPKG2-0 bits = “101”
-
1.98
-
Vpp
−4.5
−24.5
0
+2
−20
+4.5
−15.5
dB
dB
dB
−0.07
-
+4.43
+6.43
+10.65
+12.65
0
-6
+6.43
+8.43
+12.65
+14.65
+2
-4
+8.93
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Note 28. Maximum voltage is in proportion to both AVDD and external input resistance (Rin).
Vin = 0.6 x AVDD x Rin / 20kΩ (typ.).
Note 29. The gain is in inverse proportion to external input resistance.
MS0625-E-01
2007/06
- 16 -
[AK4648]
min
Parameter
Stereo Input: LIN2/RIN2/LIN4/RIN4 pins; LIN3/RIN3 pins (AIN3 bit = “1”)
Maximum Input Voltage (Note 30)
Gain
LIN/RIN Æ LOUT/ROUT
LOVL bit = “0”
−4.5
LOVL bit = “1”
LIN/RIN Æ HPL/HPR
HPG = 0dB
−4.5
LIN/RIN Æ SPLP/SPLN or SPRP/SPRN (Note 33)
ALC bit = “0”, SPKG2-0 bits = “000”
−0.07
ALC bit = “0”, SPKG2-0 bits = “001”
ALC bit = “0”, SPKG2-0 bits = “010”
ALC bit = “0”, SPKG2-0 bits = “011”
ALC bit = “0”, SPKG2-0 bits = “100”
ALC bit = “0”, SPKG2-0 bits = “101”
ALC bit = “1”, SPKG2-0 bits = “000”
ALC bit = “1”, SPKG2-0 bits = “001”
ALC bit = “1”, SPKG2-0 bits = “010”
ALC bit = “1”, SPKG2-0 bits = “011”
ALC bit = “1”, SPKG2-0 bits = “100”
ALC bit = “1”, SPKG2-0 bits = “101”
Full-differential Mono Input: IN4+/− pins (L4DIF bit = “1”)
Maximum Input Voltage (Note 31)
Gain
LOVL bit = “0”
IN4+/− Æ LOUT/ROUT
−10.5
(LODIF bit = “0”)
LOVL bit = “1”
LOVL bit = “0”
IN4+/− Æ LOP/LON
−4.5
(LODIF bit = “1”, Note 32)
LOVL bit = “1”
HPG = 0dB
IN4+/− Æ HPL/HPR
−10.5
IN4+/− Æ SPLP/SPLN or SPRP/SPRN
ALC bit = “0”, SPKG2-0 bits = “000”
-6.09
ALC bit = “0”, SPKG2-0 bits = “001”
ALC bit = “0”, SPKG2-0 bits = “010”
ALC bit = “0”, SPKG2-0 bits = “011”
ALC bit = “0”, SPKG2-0 bits = “100”
ALC bit = “0”, SPKG2-0 bits = “101”
ALC bit = “1”, SPKG2-0 bits = “000”
ALC bit = “1”, SPKG2-0 bits = “001”
ALC bit = “1”, SPKG2-0 bits = “010”
ALC bit = “1”, SPKG2-0 bits = “011”
ALC bit = “1”, SPKG2-0 bits = “100”
ALC bit = “1”, SPKG2-0 bits = “101”
-
typ
max
Units
1.98
-
Vpp
0
+2
0
+4.5
+4.5
dB
dB
dB
+4.43
+6.43
+10.65
+12.65
0
-6
+6.43
+8.43
+12.65
+14.65
+2
-4
+8.93
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
3.96
-
Vpp
−6
−4
0
+2
−6
−1.5
+4.5
−1.5
dB
dB
dB
dB
dB
-1.59
+0.41
+4.63
+6.63
-6
-12
+0.41
+2.41
+6.63
+8.63
-4
-10
+2.91
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Note 30. Maximum input voltage is proportional to AVDD voltage. Vin = 0.6 x AVDD (typ.).
Note 31. Maximum input voltage is proportional to AVDD voltage. Vin = (IN4+) − (IN4−) = 1.2 x AVDD (typ.).
The signals with same amplitude and inverted phase should be input to IN4+ and IN4− pins, respectively.
Note 32. Vout = (LOP) − (LON) at LODIF bit = “1”.
Note 33. Signals with same amplitude and phase are input to LIN and RIN at SPKMN bit = “0”. When the input signal is
LIN or RIN, these values subtract 6.02dB from the above value.
MS0625-E-01
2007/06
- 17 -
[AK4648]
Parameter
Power Supplies:
Power Up (PDN pin = “H”)
All Circuit Power-up:
AVDD+DVDD+TVDD (Note 34)
HVDD: HP-Amp Normal Operation, No Output (Note 35)
Single-ended Mode (PMHPC bit = “0”)
Pseudo Cap-less Mode (PMHPC bit = “1”)
HVDD: SPK-Amp Normal Operation, No Output
Stereo & High Power Mono SPK Mode (Note 36)
Mono SPK Mode (Note 37)
Power Down (PDN pin = “L”) (Note 38)
AVDD+DVDD+TVDD+HVDD
min
typ
max
Units
-
16.7
25
mA
-
3.3
5.2
8
mA
mA
-
14.5
7.5
43
-
mA
mA
-
1
100
μA
Note 34. PLL Master Mode (MCKI=12.288MHz) and PMADL = PMADR = PMDAC = PMSPL=PMSPR=PMLO =
PMHPL = PMHPR = PMHPC = PMVCM = PMPLL = MCKO = PMMIN = PMMP = M/S bits = “1”. MPWR
pin outputs 0mA.
AVDD=12mA(typ.), DVDD=3mA(typ.), TVDD=1.7mA(typ.).
EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”): AVDD=11mA(typ.), DVDD=2.5mA(typ.),
TVDD=0.03mA(typ.).
Note 35. PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = PMMIN =HPMTN bits
= “1”
Note 36. PMADL = PMADR = PMDAC = PMSPL = PMSPR = PMLO = PMVCM = PMPLL = PMMIN = SPPSN bits =
“1”
Note 37. PMADL = PMADR = PMDAC = PMVCM = PMPLL = PMMIN = SPPSN bits = “1”, PMSPL bit or PMSPR bit
= “1”
Note 38. All digital input pins are held TVDD or VSS3.
MS0625-E-01
2007/06
- 18 -
[AK4648]
■ Power Consumption for each operation mode
Conditions: Ta=25°C; AVDD=DVDD=TVDD=3.3V; HVDD=3.6V, VSS1=VSS2=VSS3=0V; fs=44.1kHz, External
Slave Mode, BICK=64fs
PMVCM
PMMIN
PMSPL
PMSPR
PMLO
PMDAC
PMADL
PMHPL
PMHPR
PMHPC
PMADR
PMMICL
PMMICR
PMAINL2
PMAINR2
PMAINL3
PMAINR3
AVDD [mA]
DVDD [mA]
TVDD [mA]
HVDD [mA]
Total Power [mW]
Power Management Bit
01H
10H
All Power-down
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DAC Æ Lineout
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
5.3
1.9
0.03
0.3
24.9
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
4.7
1.9
0.03
0.3
33.8
1
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
4.7
1.9
0.03
5.2
40.6
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
4.7
1.9
0.03
7.5
48.9
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
5.1
1.9
0.03
14.5
75.4
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
2.5
0
0
3.3
20.1
1
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
2.5
0
0
5.2
27.0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
2.5
0
0
7.5
35.3
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
2.9
0
0
14.5
61.8
MIN Æ Lineout
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
2.6
0
0
0.3
9.7
LIN2/RIN2 Æ ADC
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
6.4
1.6
0.03
0.3
27.6
LIN1 (Mono) Æ ADC
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
4.2
1.4
0.03
0.3
19.7
1
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
0
9.4
3.1
0.03
3.3
53.2
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
9.4
3.1
0.03
5.2
60.1
00H
Mode
DAC Æ HP
(Note 39)
DAC Æ HP
(Note 40)
DAC Æ SPK
(Note 41)
DAC Æ SPK
(Note 42)
LIN2/RIN2 Æ HP
(Note 39)
LIN2/RIN2 Æ HP
(Note 40)
LIN2/RIN2 Æ SPK
(Note 41)
LIN2/RIN2 Æ SPK
(Note 42)
LIN2/RIN2 Æ ADC
&DACÆHP(Note 39)
LIN2/RIN2 Æ ADC
&DACÆHP(Note 40)
20H
Note 39. Single-ended Mode
Note 40. Pseudo Cap-less Mode
Note 41. Mono SPK (In case of using Lch SPK-Amp. When Rch SPK-Amp is used, PMSPL bit is “0” and PMSPR bit is
“1”.)
Note 42. Stereo SPK Mode or High Power Mono SPK Mode
Table 1. Power Consumption for each operation mode (typ.)
MS0625-E-01
2007/06
- 19 -
[AK4648]
FILTER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; TVDD=1.6 ∼ 3.6V; HVDD=2.6 ∼ 5.0V; fs=44.1kHz; DEM=OFF;
FIL1=FIL3=EQ=FBEQ=OFF)
Parameter
Symbol
min
typ
max
ADC Digital Filter (Decimation LPF):
Passband (Note 43)
PB
0
17.3
±0.16dB
19.4
−0.66dB
19.9
−1.1dB
22.1
−6.9dB
Stopband
SB
26.1
Passband Ripple
PR
±0.1
Stopband Attenuation
SA
73
Group Delay (Note 44)
GD
19
Group Delay Distortion
0
ΔGD
ADC Digital Filter (HPF): (Note 45)
Frequency Response (Note 43) −3.0dB
FR
0.9
2.7
−0.5dB
6.0
−0.1dB
DAC Digital Filter (LPF):
Passband (Note 43)
PB
0
19.6
±0.1dB
20.0
−0.7dB
22.05
−6.0dB
Stopband
SB
25.2
Passband Ripple
PR
±0.01
Stopband Attenuation
SA
59
Group Delay (Note 44)
GD
26
DAC Digital Filter (LPF) + SCF:
FR
Frequency Response: 0 ∼ 20.0kHz
±1.0
DAC Digital Filter (HPF): (Note 45)
Frequency Response (Note 43) −3.0dB
FR
0.9
2.7
−0.5dB
6.0
−0.1dB
Units
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
μs
Hz
Hz
Hz
kHz
kHz
kHz
kHz
dB
dB
1/fs
dB
Hz
Hz
Hz
Note 43. The passband and stopband frequencies with fs (system sampling rate).
For example, DAC is PB=0.454*fs (@−0.7dB). Each response refers to that of 1kHz.
Note 44. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the
16-bit data of both channels from the input register to the output register of the ADC. This time includes the
group delay of the HPF. For the DAC, this time is from setting the 16-bit data of both channels from the input
register to the output of analog signal. Group delay of DAC part is 25/fs(typ.) at PMADL=PMADR bits = “0”.
Note 45. When PMADL bit = “1” or PMADR bit = “1”, the HPF of ADC is enabled but the HPF of DAC is disabled.
When PMADL=PMADR bits = “0”, PMDAC bit = “1”, the HPF of DAC is enabled but the HPF of ADC is
disabled.
MS0625-E-01
2007/06
- 20 -
[AK4648]
DC CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; TVDD=1.6 ∼ 3.6V; HVDD=2.6 ∼ 5.0V)
Parameter
Symbol
min
High-Level Input Voltage
2.2V≤TVDD≤3.6V
VIH
70%TVDD
1.6V≤TVDD<2.2V
VIH
80%TVDD
Low-Level Input Voltage
2.2V≤TVDD≤3.6V
VIL
1.6V≤TVDD<2.2V
VIL
High-Level Output Voltage
VOH
(Iout=−200μA)
TVDD−0.2
Low-Level Output Voltage
VOL
(Except SDA pin: Iout=200μA)
(SDA pin, 2.0V≤TVDD≤3.6V: Iout=3mA)
VOL
VOL
(SDA pin, 1.6V≤TVDD<2.0V: Iout=3mA)
Input Leakage Current
Iin
-
typ
-
max
30%TVDD
20%TVDD
-
Units
V
V
V
V
V
-
0.2
0.4
20%TVDD
±10
V
V
V
μA
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; TVDD=1.6 ∼ 3.6V; HVDD=2.6 ∼ 5.0V; CL=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
MHz
Pulse Width Low
tCLKL
0.4/fCLK
ns
Pulse Width High
tCLKH
0.4/fCLK
ns
MCKO Output Timing
Frequency
fMCK
0.2352
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
%
256fs at fs=32kHz, 29.4kHz
dMCK
33
%
LRCK Output Timing
Frequency
fs
7.35
48
kHz
DSP Mode: Pulse Width High
tLRCKH
tBCK
ns
Except DSP Mode: Duty Cycle
Duty
50
%
BICK Output Timing
Period
BCKO bit = “0”
tBCK
1/(32fs)
ns
BCKO bit = “1”
tBCK
1/(64fs)
ns
Duty Cycle
dBCK
50
%
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
MHz
Pulse Width Low
tCLKL
0.4/fCLK
ns
Pulse Width High
tCLKH
0.4/fCLK
ns
MCKO Output Timing
Frequency
fMCK
0.2352
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
%
256fs at fs=32kHz, 29.4kHz
dMCK
33
%
LRCK Input Timing
Frequency
fs
7.35
48
kHz
DSP Mode: Pulse Width High
tLRCKH
tBCK−60
1/fs − tBCK
ns
Except DSP Mode: Duty Cycle
Duty
45
55
%
BICK Input Timing
Period
tBCK
1/(64fs)
1/(32fs)
ns
Pulse Width Low
tBCKL
0.4 x tBCK
ns
Pulse Width High
tBCKH
0.4 x tBCK
ns
MS0625-E-01
2007/06
- 21 -
[AK4648]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
PLL3-0 bits = “0011”
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Slave Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Input Timing
Frequency
256fs
fs
512fs
fs
1024fs
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Master Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Output Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Output Timing
Period
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
MS0625-E-01
min
typ
max
Units
7.35
tBCK−60
45
-
48
1/fs − tBCK
55
kHz
ns
%
1/(64fs)
130
130
-
1/(32fs)
-
ns
ns
ns
7.35
tBCK−60
45
-
48
1/fs − tBCK
55
kHz
ns
%
0.4 x tBCK
0.4 x tBCK
1/(32fs)
1/(64fs)
-
-
ns
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
7.35
7.35
tBCK−60
45
-
48
26
13
1/fs − tBCK
55
kHz
kHz
kHz
ns
%
312.5
130
130
-
-
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
-
tBCK
50
48
-
kHz
ns
%
-
1/(32fs)
1/(64fs)
50
-
ns
ns
%
2007/06
- 22 -
[AK4648]
Parameter
Symbol
Audio Interface Timing (DSP Mode)
Master Mode
tDBF
LRCK “↑” to BICK “↑” (Note 46)
tDBF
LRCK “↑” to BICK “↓” (Note 47)
tBSD
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
BICK “↓” to SDTO (BCKP bit = “1”)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
tLRB
LRCK “↑” to BICK “↑” (Note 46)
tLRB
LRCK “↑” to BICK “↓” (Note 47)
tBLR
BICK “↑” to LRCK “↑” (Note 46)
tBLR
BICK “↓” to LRCK “↑” (Note 47)
tBSD
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
BICK “↓” to SDTO (BCKP bit = “1”)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Audio Interface Timing (Right/Left justified & I2S)
Master Mode
tMBLR
BICK “↓” to LRCK Edge (Note 48)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
tLRB
LRCK Edge to BICK “↑” (Note 48)
tBLR
BICK “↑” to LRCK Edge (Note 48)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
min
typ
max
Units
0.5 x tBCK − 40
0.5 x tBCK − 40
−70
−70
50
50
0.5 x tBCK
0.5 x tBCK
-
0.5 x tBCK + 40
0.5 x tBCK + 40
70
70
-
ns
ns
ns
ns
ns
ns
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
50
50
-
80
80
-
ns
ns
ns
ns
ns
ns
ns
ns
−40
−70
-
40
70
ns
ns
−70
50
50
-
70
-
ns
ns
ns
50
50
-
-
80
ns
ns
ns
50
50
-
80
-
ns
ns
ns
Note 46. MSBS, BCKP bits = “00” or “11”.
Note 47. MSBS, BCKP bits = “01” or “10”.
Note 48. BICK rising edge must not occur at the same time as LRCK edge.
MS0625-E-01
2007/06
- 23 -
[AK4648]
Parameter
Control Interface Timing (I2C Bus):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 50)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width (Note 51)
PMADL or PMADR “↑” to SDTO valid (Note 52)
Symbol
min
typ
max
Units
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
tSP
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
tPD
tPDV
150
-
1059
-
ns
1/fs
Note 49. I2C is a registered trademark of Philips Semiconductors.
Note 50. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 51. AK4648 can be reset by the PDN pin = “L”.
Note 52. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
MS0625-E-01
2007/06
- 24 -
[AK4648]
■ Timing Diagram
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
50%TVDD
LRCK
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
50%TVDD
BICK
tBCKH
tBCKL
dBCK = tBCKH / tBCK x 100
tBCKL / tBCK x 100
1/fMCK
50%TVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Note 53. MCKO is not available at EXT Master mode.
Figure 4. Clock Timing (PLL/EXT Master mode)
tLRCKH
LRCK
50%TVDD
tDBF
BICK
(BCKP = "0")
50%TVDD
BICK
(BCKP = "1")
50%TVDD
tBSD
SDTO
MSB
tSDS
50%TVDD
tSDH
VIH
SDTI
VIL
Figure 5. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS bit = “0”)
MS0625-E-01
2007/06
- 25 -
[AK4648]
tLRCKH
LRCK
50%TVDD
tDBF
BICK
(BCKP = "1")
50%TVDD
BICK
(BCKP = "0")
50%TVDD
tBSD
SDTO
50%TVDD
MSB
tSDS
tSDH
VIH
SDTI
VIL
Figure 6. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS bit = “1”)
50%TVDD
LRCK
tMBLR
BICK
50%TVDD
tLRD
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 7. Audio Interface Timing (PLL/EXT Master mode, Except DSP mode)
MS0625-E-01
2007/06
- 26 -
[AK4648]
1/fs
VIH
LRCK
VIL
tLRCKH
tBLR
tBCK
VIH
BICK
(BCKP = "0")
VIL
tBCKH
tBCKL
VIH
BICK
(BCKP = "1")
VIL
Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS bit = “0”)
1/fs
VIH
LRCK
VIL
tLRCKH
tBLR
tBCK
VIH
BICK
(BCKP = "1")
VIL
tBCKH
tBCKL
VIH
BICK
(BCKP = "0")
VIL
Figure 9. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS bit = “1”)
MS0625-E-01
2007/06
- 27 -
[AK4648]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
= tLRCKL x fs x 100
VIH
BICK
VIL
tBCKH
tBCKL
fMCK
50%TVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 10. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin, Except DSP mode)
tLRCKH
VIH
LRCK
VIL
tLRB
VIH
BICK
VIL
(BCKP = "0")
VIH
BICK
(BCKP = "1")
VIL
tBSD
SDTO
MSB
tSDS
50%TVDD
tSDH
VIH
SDTI
MSB
VIL
Figure 11. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS bit = “0”)
MS0625-E-01
2007/06
- 28 -
[AK4648]
tLRCKH
VIH
LRCK
VIL
tLRB
VIH
BICK
VIL
(BCKP = "1")
VIH
BICK
(BCKP = "0")
VIL
tBSD
SDTO
50%TVDD
MSB
tSDS
tSDH
VIH
SDTI
MSB
VIL
Figure 12. Audio Interface Timing (PLL Slave mode, DSP mode, MSBS bit = “1”)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 13. Clock Timing (EXT Slave mode)
MS0625-E-01
2007/06
- 29 -
[AK4648]
VIH
LRCK
VIL
tLRB
tBLR
VIH
BICK
VIL
tBSD
tLRD
SDTO
50%TVDD
MSB
tSDH
tSDS
VIH
SDTI
VIL
Figure 14. Audio Interface Timing (PLL/EXT Slave mode, Except DSP mode)
VIH
SDA
VIL
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
2
Figure 15. I C Bus Mode Timing
PMADL bit
or
PMADR bit
tPDV
SDTO
50%TVDD
Figure 16. Power Down & Reset Timing 1
tPD
PDN
VIL
Figure 17. Power Down & Reset Timing 2
MS0625-E-01
2007/06
- 30 -
[AK4648]
OPERATION OVERVIEW
■ System Clock
There are the following five clock modes to interface with external devices. (Table 2 and Table 3.)
Mode
PMPLL bit
M/S bit
PLL3-0 bits
Figure
PLL Master Mode (Note 54)
1
1
Table 5
Figure 18
PLL Slave Mode 1
Table 5
Figure 19
1
0
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
Figure 20
Table 5
1
0
Figure 21
(PLL Reference Clock: LRCK or BICK pin)
EXT Slave Mode
0
0
x
Figure 22
EXT Master Mode
0
1
x
Figure 23
Note 54. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid
clocks are output from MCKO pin when MCKO bit is “1”.
Table 2. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
0
PLL Master Mode
1
0
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
1
MCKO pin
“L”
Selected by
PS1-0 bits
“L”
Selected by
PS1-0 bits
MCKI pin
Selected by
PLL3-0 bits
Selected by
PLL3-0 bits
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
0
“L”
GND
EXT Slave Mode
0
“L”
Selected by
FS1-0 bits
EXT Master Mode
0
“L”
Selected by
FS1-0 bits
BICK pin
Output
(Selected by
BCKO bit)
LRCK pin
Input
(≥ 32fs)
Input
(1fs)
Input
(Selected by
PLL3-0 bits)
Input
(≥ 32fs)
Output
(Selected by
BCKO bit)
Output
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
Table 3. Clock pins state in Clock Mode
■ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4648 is power-down mode (PDN pin = “L”) and exits reset state, the AK4648 is slave mode. After exiting reset state,
the AK4648 goes to master mode by changing M/S bit = “1”.
When the AK4648 is used by master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK
and BICK pins of the AK4648 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the
floating state.
M/S bit
Mode
0
Slave Mode
(default)
1
Master Mode
Table 4. Select Master/Slave Mode
MS0625-E-01
2007/06
- 31 -
[AK4648]
■ PLL Mode (AIN3 bit = “0”, PMPLL bit = “1”)
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 5, whenever the AK4648 is supplied to stable clocks after
PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes. When AIN3 bit = “1”, the PLL is not
available.
1) Setting of PLL Mode
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
PLL Reference
Clock Input Pin
Input
Frequency
0
1
0
0
0
0
0
0
0
1
LRCK pin
N/A
1fs
-
2
0
0
1
0
BICK pin
32fs
3
0
0
1
1
BICK pin
64fs
4
5
6
7
8
12
13
14
15
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
0
0
1
0
1
Others
Others
R and C of
VCOC pin
R[Ω] C[F]
6.8k
220n
10k
4.7n
10k
10n
10k
4.7n
10k
10n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
10n
10k
10n
10k
220n
10k
220n
MCKI pin
11.2896MHz
MCKI pin
12.288MHz
MCKI pin
12MHz
MCKI pin
24MHz
MCKI pin
19.2MHz
MCKI pin
13.5MHz
MCKI pin
27MHz
MCKI pin
13MHz
MCKI pin
26MHz
N/A
Table 5. Setting of PLL Mode (*fs: Sampling Frequency)
PLL Lock
Time
(max)
160ms
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
40ms
40ms
40ms
60ms
60ms
(default)
2) Setting of sampling frequency in PLL Mode
When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 6.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
0
0
8kHz
(default)
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
4
0
1
0
0
7.35kHz
5
0
1
0
1
11.025kHz
6
0
1
1
0
14.7kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
14
1
1
1
0
29.4kHz
15
1
1
1
1
44.1kHz
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = MCKI pin)
MS0625-E-01
2007/06
- 32 -
[AK4648]
When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3 and FS1-0 bits. (Table
7). FS2 bit is “don’t care”.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency Range
0
x
0
0
0
(default)
7.35kHz ≤ fs ≤ 8kHz
0
x
1
1
0
8kHz < fs ≤ 12kHz
0
x
0
2
1
12kHz < fs ≤ 16kHz
0
x
1
3
1
16kHz < fs ≤ 24kHz
1
x
0
6
1
24kHz < fs ≤ 32kHz
1
x
1
7
1
32kHz < fs ≤ 48kHz
Others
Others
N/A
(x: Don’t care)
Table 7. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin)
■ PLL Unlock State
1) PLL Master Mode (AIN3 bit = “0”; PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BICK pins go to “L” and irregular frequency clock is output from MCKO pins at MCKO bit is
“1” before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, MCKO pin goes to “L” (Table
8).
After the PLL is locked, the first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
MCKO pin
BICK pin
MCKO bit = “0”
MCKO bit = “1”
After that PMPLL bit “0” Æ “1”
“L” Output
Invalid
“L” Output
PLL Unlock (except case above)
“L” Output
Invalid
Invalid
PLL Lock
“L” Output
Table 10
Table 11
Table 8. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PLL State
LRCK pin
“L” Output
Invalid
1fs Output
2) PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = “0” Æ “1”.
Then, the clock selected by Table 10 is output from MCKO pin when PLL is locked. ADC and DAC output invalid data
when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL and DACH bits.
MCKO pin
MCKO bit = “0” MCKO bit = “1”
Just after PMPLL bit “0” Æ “1”
“L” Output
Invalid
PLL Unlock (except case above)
“L” Output
Invalid
PLL Lock
“L” Output
Output
Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PLL State
MS0625-E-01
2007/06
- 33 -
[AK4648]
■ PLL Master Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz)
is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output
frequency is selected by PS1-0 bits (Table 10) and the output is enabled by MCKO bit. The BICK output frequency is
selected between 32fs or 64fs, by BCKO bit (Table 11).
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
DSP or μP
AK4648
MCKI
256fs/128fs/64fs/32fs
MCKO
32fs, 64fs
BICK
1fs
LRCK
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 18. PLL Master Mode
Mode
PS1 bit
PS0 bit
MCKO pin
0
0
0
256fs
(default)
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 10. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)
BICK Output
Frequency
0
32fs
(default)
1
64fs
Table 11. BICK Output Frequency at Master Mode
BCKO bit
MS0625-E-01
2007/06
- 34 -
[AK4648]
■ PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the
AK4648 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 5).
a) PLL reference clock: MCKI pin
BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not
matter. MCKO pin outputs the frequency selected by PS1-0 bits (Table 10) and the output is enabled by MCKO bit.
Sampling frequency can be selected by FS3-0 bits (Table 6).
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
AK4648
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 19. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
MS0625-E-01
2007/06
- 35 -
[AK4648]
b) PLL reference clock: BICK or LRCK pin
Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits ((x: Don’t care)
Table 7).
AK4648
DSP or μP
MCKO
MCKI
BICK
LRCK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 20. PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
AK4648
DSP or μP
MCKO
MCKI
BICK
LRCK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 21. PLL Slave Mode 2 (PLL Reference Clock: LRCK pin)
The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation
(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4648 may draw
excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external
clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”).
MS0625-E-01
2007/06
- 36 -
[AK4648]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4648 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit
is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI
(256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with LRCK.
The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits ((x: Don’t care)
Table 12).
Sampling Frequency
Range
0
0
(default)
7.35kHz ∼ 48kHz
0
1
7.35kHz ∼ 13kHz
1
0
7.35kHz ∼ 48kHz
1
1
7.35kHz ∼ 26kHz
(x: Don’t care)
Table 12. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
Mode
FS3-2 bits
0
1
2
3
x
x
x
x
FS1 bit
MCKI Input
Frequency
256fs
1024fs
256fs
512fs
FS0 bit
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through LOUT/ROUT pins at fs=8kHz is shown in Table 13.
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
93dB
1024fs
93dB
Table 13. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI
The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation
(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4648 may draw
excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external
clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”).
AK4648
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BICK
LRCK
MCLK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 22. EXT Slave Mode
MS0625-E-01
2007/06
- 37 -
[AK4648]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The AK4648 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from
MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The
input frequency of MCKI is selected by FS1-0 bits ((x: Don’t care)
Table 14).
Mode
0
1
2
3
Sampling Frequency
Range
x
0
0
(default)
7.35kHz ∼ 48kHz
x
0
1
7.35kHz ∼ 13kHz
x
1
0
7.35kHz ∼ 48kHz
x
1
1
7.35kHz ∼ 26kHz
(x: Don’t care)
Table 14. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
FS3-2 bits
FS1 bit
MCKI Input
Frequency
256fs
1024fs
256fs
512fs
FS0 bit
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through LOUT/ROUT pins at fs=8kHz is shown in Table 15.
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
93dB
1024fs
93dB
Table 15. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI
MCKI should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or
PMDAC bit = “1”). If MCKI is not provided, the AK4648 may draw excess current and it is not possible to operate
properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC and DAC should be in the
power-down mode (PMADL=PMADR=PMDAC bits = “0”).
AK4648
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
MCLK
32fs or 64fs
BICK
1fs
LRCK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 23. EXT Master Mode
BICK Output
Frequency
0
32fs
(default)
1
64fs
Table 16. BICK Output Frequency at Master Mode
BCKO bit
MS0625-E-01
2007/06
- 38 -
[AK4648]
■ System Reset
Upon power-up, the AK4648 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial values.
The ADC enters an initialization cycle that starts when the PMADL or PMADR bit is changed from “0” to “1” at PMDAC
bits is “0”. The initialization cycle time is [email protected]=44.1kHz. During the initialization cycle, the ADC digital
data outputs of both channels are forced to a 2’s complement, “0”. The ADC output reflects the analog input signal after
the initialization cycle is complete. When PMDAC bit is “1”, the ADC does not require an initialization cycle.
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL and
PMADR bits are “0”. The initialization cycle time is [email protected]=44.1kHz. During the initialization cycle, the
DAC input digital data of both channels are internally forced to a 2’s complement, “0”. The DAC output reflects the
digital input data after the initialization cycle is complete. When PMADL or PMADR bit is “1”, the DAC does not require
an initialization cycle.
■ Audio Interface Format
Four types of data formats are available and are selected by setting the DIF1-0 bits (Table 17). In all modes, the serial data
is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK and
BICK are output from the AK4648 in master mode, but must be input to the AK4648 in slave mode.
Mode
0
1
2
3
DIF1 bit
0
0
1
1
DIF0 bit
0
1
0
1
SDTO (ADC) SDTI (DAC)
DSP Mode
DSP Mode
MSB justified LSB justified
MSB justified MSB justified
I2S compatible I2S compatible
Table 17. Audio Interface Format
BICK
≥ 32fs
≥ 32fs
≥ 32fs
≥ 32fs
Figure
Table 18
Figure 28
Figure 29
Figure 30
(default)
In modes 1, 2 and 3, the SDTO is clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge
(“↑”). In Modes 0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (Table 18).
DIF1
0
DIF0
MSBS
BCKP
0
0
0
1
1
0
1
1
0
Audio Interface Format
MSB of SDTO is output by the rising edge (“↑”) of the first
BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the falling edge (“↓”) of the BICK
just after the output timing of SDTO’s MSB.
MSB of SDTO is output by the falling edge (“↓”) of the first
BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the BICK
just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next rising edge (“↑”) of the falling
edge (“↓”) of the first BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the falling edge (“↓”) of the BICK
just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next falling edge (“↓”) of the rising
edge (“↑”) of the first BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the BICK
just after the output timing of SDTO’s MSB.
Table 18. Audio Interface Format in Mode 0
Figure
Figure 24
(default)
Figure 25
Figure 26
Figure 27
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
MS0625-E-01
2007/06
- 39 -
[AK4648]
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
15 14
Lch
15
1
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
8
14
2
15
16
17
18
30
31
15 14
32
33
46
34
47
48
49
50
62
63
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
2
1
0
15 14
1
0
2
1
0
Rch
Lch
SDTI(i)
2
15 14
15 14
1/fs
15:MSB, 0:LSB
Figure 24. Mode 0 Timing (BCKP bit = “0”, MSBS bit = “0”)
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
34
46
47
48
49
50
62
63
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
2
1
0
2
1
0
2
1
0
Rch
Lch
SDTI(i)
15 14
15 14
15 14
1/fs
15:MSB, 0:LSB
Figure 25. Mode 0 Timing (BCKP bit = “1”, MSBS bit = “0”)
MS0625-E-01
2007/06
- 40 -
[AK4648]
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
46
34
48
47
49
50
27
26
62
63
30
31
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
15 14
Lch
SDTI(i)
2
1
0
2
1
0
Rch
15 14
2
1
0
15 14
1/fs
15:MSB, 0:LSB
Figure 26. Mode 0 Timing (BCKP bit = “0”, MSBS bit = “1”)
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
29
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
34
46
47
48
49
50
62
63
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
Lch
SDTI(i)
15 14
2
1
0
2
1
0
Rch
15 14
2
1
0
15 14
1/fs
15:MSB, 0:LSB
Figure 27. Mode 0 Timing (BCKP bit = “1”, MSBS bit = “1”)
MS0625-E-01
2007/06
- 41 -
[AK4648]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
SDTI(i)
1 0
15 14 13
15 14 13
15 14
Don't Care
1 0
1 0
Don't Care
15
15 14
2 1 0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 28. Mode 1 Timing
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14 13
1 0
SDTI(i)
15 14 13
1 0
Don't Care
15 14 13
1 0
15 14 13
1 0
15
Don't Care
15
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 29. Mode 2 Timing
MS0625-E-01
2007/06
- 42 -
[AK4648]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
0 15 14
8 7 6 5 4 3 2 1 0 15 14
8 7 6 5 4 3 2 1 0
SDTI(i)
0 15 14
8 7 6 5 4 3 2 1 0 15 14
8 7 6 5 4 3 2 1 0
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14
2 1 0
SDTI(i)
15 14
2 1 0
Don't Care
15 14
2 1 0
15 14
2 1 0
Don't Care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 30. Mode 3 Timing
■ Mono/Stereo Mode
PMADL, PMADR and MIX bits set mono/stereo ADC operation. When MIX bit = “1”, EQ and FIL3 bits should be set to
“0”. ALC operation (ALC bit = “1”) or digital volume operation (ALC bit = “0”) is applied to the data in Table 19.
PMADL bit
0
0
1
1
PMADR bit
0
1
0
MIX bit
ADC Lch data
ADC Rch data
x
All “0”
All “0”
x
Rch Input Signal
Rch Input Signal
x
Lch Input Signal
Lch Input Signal
0
Lch Input Signal
Rch Input Signal
1
1
(L+R)/2
(L+R)/2
Table 19. Mono/Stereo ADC operation (x: Don’t care)
(default)
■ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 0.9Hz
(@fs=44.1kHz) and scales with sampling rate (fs). When PMADL bit = “1” or PMADR bit = “1”, the HPF of ADC is
enabled but the HPF of DAC is disabled. When PMADL=PMADR bits = “0”, PMDAC bit = “1”, the HPF of DAC is
enabled but the HPF of ADC is disabled.
MS0625-E-01
2007/06
- 43 -
[AK4648]
■ MIC/LINE Input Selector
The AK4648 has input selector for MIC-Amp. When MDIF1 and MDIF2 bits are “0”, INL1-0 and INR1-0 bits select
LIN1/LIN2/LIN3/LIN4 and RIN1/RIN2/RIN3/RIN4, respectively. When MDIF1 and MDIF2 bits are “1”, LIN1, RIN1,
LIN2 and RIN2 pins become IN1−, IN1+, IN2+ and IN2− pins respectively. In this case, full-differential input is
available (Figure 32).
MDIF1 bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Others
MDIF2 bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
INL1 bit
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
INL0 bit
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
INR1 bit
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
Lch
LIN1
LIN1
LIN1
LIN1
LIN2
LIN2
LIN2
LIN2
LIN3
LIN3
LIN3
LIN3
LIN4
LIN4
LIN4
LIN4
LIN1
LIN3
LIN4
IN1+/−
IN1+/−
IN1+/−
IN1+/−
N/A
Table 20. MIC/Line In Path Select (N/A: Not Available)
MS0625-E-01
INR0 bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
Rch
RIN1
RIN2
RIN3
RIN4
RIN1
RIN2
RIN3
RIN4
RIN1
RIN2
RIN3
RIN4
RIN1
RIN2
RIN3
RIN4
IN2+/−
IN2+/−
IN2+/−
RIN2
RIN3
RIN4
IN2+/−
N/A
(default)
2007/06
- 44 -
[AK4648]
AK4648
INL1-0 bits
LIN1/IN1− pin
ADC Lch
RIN1/IN1+ pin
MDIF1 bit
MIC-Amp
INR1-0 bits
RIN2/IN2− pin
ADC Rch
LIN2/IN2+ pin
MDIF2 bit
AIN3 bit
LIN3
AIN3 bit
RIN3
MIC-Amp
MIN/LIN3 pin
PMMIN
PMAINR2 bit
PMAINL2 bit
PMAINL4 bit
PMAINR4 bit
MICR3 bit
RIN4/IN4− pin
PMAINR3 bit
VCOC
LIN4/IN4+ pin
PMAINL3 bit
MICL3 bit
VCOC/RIN3 pin
Lineout, HP-Amp, SPK-Amp
Figure 31. Mic/Line Input Selector
AK4648
MPWR pin
1k
IN1− pin
MIC-Amp
IN1+ pin
A/D
SDTO pin
1k
Figure 32. Connection Example for Full-differential Mic Input (MDIF1/2 bits = “1”)
<Input Selector Setting Example>
In case that IN1+/− pins are used as full-differential mic input and LIN2/RIN2 pins are used as stereo line input, it is
recommended that the following two modes are set by register setting according to each case.
MDIF1 bit
1
0
MDIF2 bit
0
0
INL1 bit
INL0 bit
INR1 bit
INR0 bit
0
0
0
1
0
1
0
1
Table 21. MIC/Line In Path Select Example
MS0625-E-01
Lch
IN1+/−
LIN2
Rch
RIN2
RIN2
2007/06
- 45 -
[AK4648]
■ MIC Gain Amplifier
The AK4648 has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN1-0 bits (Table
22). The typical input impedance is 60kΩ(typ.) @ MGAIN1-0 bits = “00” or 30kΩ(typ )@ MGAIN1-0 bits = “01”, “10”
or “11”.
MGAIN1 bit
0
0
1
1
MGAIN0 bit
Input Gain
0
0dB
1
+20dB
0
+26dB
1
+32dB
Table 22. Mic Input Gain
(default)
■ MIC Power
When PMMP bit = “1”, the MPWR pin supplies power for the microphone. This output voltage is typically 0.75 x AVDD
and the load resistance is minimum 0.5kΩ. In case of using two sets of stereo mic, the load resistance is minimum 2kΩ for
each channel. Capacitor must not be connected directly to MPWR pin (Figure 33).
PMMP bit
0
1
MPWR pin
Hi-Z
Output
Table 23. MIC Power
(default)
MIC Power
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
MPWR pin
Microphone
LIN1 pin
Microphone
RIN1 pin
Microphone
LIN2 pin
Microphone
RIN2 pin
Figure 33. MIC Block Circuit
MS0625-E-01
2007/06
- 46 -
[AK4648]
■ Digital EQ/HPF/LPF
The AK4648 performs wind-noise reduction filter, stereo separation emphasis, gain compensation and ALC (Automatic
Level Control) by digital domain for A/D converted data (Figure 34). FIL1, FIL3 and EQ blocks are IIR filters of 1st
order. The filter coefficient of FIL3, EQ and FIL1 blocks can be set to any value. Refer to the section of “ALC operation”
about ALC.
When only DAC is powered-up, digital EQ/HPF/LPF circuit operates at playback path. When only ADC is powered-up
or both ADC and DAC are powered-up, digital EQ/HPF/LPF circuit operates at recording path. Even if the path is
switched from recording to playback, the register setting of filter coefficient at recording remains. Therefore, FIL3, EQ,
FIL1 and GN1-0 bits should be set to “0” if digital EQ/HPF/LPF is not used for playback path.
PMADL bit, PMADR bit
PMDAC bit
0
1
0
LOOP bit
Status
Digital EQ/HPF/LPF
x
Power-down
Power-down
00
x
Playback
Playback path
x
Recording
Recording path
01, 10 or 11
0
Recording & Playback
Recording path
1
1
Recording Monitor Playback
Recording path
Note 55. Stereo separation emphasis circuit is effective only at stereo operation.
Table 24. Digital EQ/HPF/LPF Circuit Setting (x: Don’t care)
(default)
FIL3 coefficient also sets the attenuation of the stereo separation emphasis.
The combination of GN1-0 bit (Table 25) and EQ coefficient set the compensation gain.
FIL1 and FIL3 blocks become HPF when F1AS and F3AS bits are “0” and become LPF when F1AS and F3AS bits are
“1”, respectively.
When EQ and FIL1 bits are “0”, EQ and FIL1 blocks become “through” (0dB). When FIL3 bit is “0”, FIL3 block become
“MUTE”. When each filter coefficient is changed, each filter should be set to “through” (“MUTE” in case of FIL3).
When MIX bit = “1”, only FIL1 is available. In this case, EQ and FIL3 bits should be set to “0”.
Wind-noise reduction
FIL1
An y coefficient
F1A13-0
F1B13-0
F1AS
Stereo separation emphasis
FIL3
Gain compensation
EQ
An y coefficient 0dB ∼ -10dB
F3A13-0
MUTE
F3B13-0
(set by
F3AS
FIL3 coefficient)
Gain
ALC
An y coefficient
GN1-0
EQA15-0
+24/+12/0dB
EQB13-0
EQC15-0
+12dB ∼ 0dB
Figure 34. Digital EQ/HPF/LPF
GN1
GN0
Gain
0
0
0dB
(default)
0
1
+12dB
1
x
+24dB
Table 25. Gain select of gain block (x: Don’t care)
MS0625-E-01
2007/06
- 47 -
[AK4648]
[Filter Coefficient Setting]
1) When FIL1 and FIL3 are set to “HPF”
fs: Sampling frequency
fc: Cut-off frequency
f: Input signal frequency
K: Filter gain [dB] (Filter gain of should be set to 0dB.)
Register setting
FIL1: F1AS bit = “0”, F1A[13:0] bits =A, F1B[13:0] bits =B
FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A = 10K/20 x
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
Transfer function
Amplitude
1 − z −1
H(z) = A
2 − 2cos (2πf/fs)
M(f) = A
1 + Bz −1
Phase
θ(f) = tan −1
1 + B2 + 2Bcos (2πf/fs)
(B+1)sin (2πf/fs)
1 - B + (B−1)cos (2πf/fs)
2) When FIL1 and FIL3 are set to “LPF”.
fs: Sampling frequency
fc: Cut-off frequency
f: Input signal frequency
K: Filter gain [dB] (Filter gain of FIL1 should be set to 0dB.)
Register setting
FIL1: F1AS bit = “1”, F1A[13:0] bits =A, F1B[13:0] bits =B
FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1
A = 10K/20 x
,
1 + 1 / tan (πfc/fs)
Transfer function
1 + Bz −1
1 + 1 / tan (πfc/fs)
Amplitude
1 + z −1
H(z) = A
B=
2 + 2cos (2πf/fs)
M(f) = A
1 + B2 + 2Bcos (2πf/fs)
MS0625-E-01
Phase
θ(f) = tan −1
(B−1)sin (2πf/fs)
1 + B + (B+1)cos (2πf/fs)
2007/06
- 48 -
[AK4648]
3) EQ
fs: Sampling frequency
fc1: Pole frequency
fc2: Zero-point frequency
f: Input signal frequency
K: Filter gain [dB] (Maximum +12dB)
Register setting
EQA[15:0] bits =A, EQB[13:0] bits =B, EQC[15:0] bits =C
(MSB=EQA15, EQB13, EQC15; LSB=EQA0, EQB0, EQC0)
A = 10K/20 x
1 − 1 / tan (πfc1/fs)
1 + 1 / tan (πfc2/fs)
,
B=
1 + 1 / tan (πfc1/fs)
A + Cz
Amplitude
−1
1 + Bz −1
C =10K/20 x
1 + 1 / tan (πfc1/fs)
Transfer function
H(z) =
,
2
1 − 1 / tan (πfc2/fs)
1 + 1 / tan (πfc1/fs)
Phase
2
A + C + 2ACcos (2πf/fs)
M(f) =
1 + B2 + 2Bcos (2πf/fs)
θ(f) = tan −1
(AB−C)sin (2πf/fs)
A + BC + (AB+C)cos (2πf/fs)
[Translation the filter coefficient calculated by the equations above from real number to binary code (2’s complement)]
X = (Real number of filter coefficient calculated by the equations above) x 213
X should be rounded to integer, and then should be translated to binary code (2’s complement).
MSB of each filter coefficient setting register is sine bit.
[Filter Coefficient Setting Example]
1) FIL1 Block
Example: HPF, fs=44.1kHz, fc=100Hz
F1AS bit = “0”
F1A[13:0] bits = 01 1111 1100 0110
F1B[13:0] bits = 10 0000 0111 0100
2) EQ block
Example: fs=44.1kHz, fc1=300Hz, fc2=3000Hz, Gain=+8dB
Gain[dB]
+8dB
fc1
fc2
Frequency
EQA[15:0] bits = 0000 1001 0110 1110
EQB[13:0] bits = 10 0001 0101 1001
EQC[15:0] bits = 1111 1001 1110 1111
MS0625-E-01
2007/06
- 49 -
[AK4648]
■ ALC Operation
The ALC (Automatic Level Control) is operated by ALC block when ALC bit is “1”. When only DAC is powered-up,
ALC circuit operates at playback path. When only ADC is powered-up or both ADC and DAC are powered-up, ALC
circuit operates at recording path.
PMADL bit, PMADR bit
PMDAC bit
0
1
0
00
01, 10 or 11
1.
1
LOOP bit
Status
x
Power-down
x
Playback
x
Recording
0
Recording & Playback
1
Recording Monitor Playback
Table 26. ALC Setting (x: Don’t care)
ALC
Power-down
Playback path
Recording path
Recording path
Recording path
(default)
ALC Limiter Operation
During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 27), the IVL
and IVR values (same value) are attenuated automatically to the amount defined by the ALC limiter ATT step (Table 28).
The IVL and IVR are then set to the same value for both channels.
When ZELMN bit = “0” (zero cross detection is enabled), the IVL and IVR values are changed by ALC limiter operation
at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing
timeout period of both ALC limiter and recovery operation (Table 29).
When ZELMN bit = “1” (zero cross detection is disabled), IVL and IVR values are immediately (period: 1/fs) changed by
ALC limiter operation. Attenuation step is fixed to 1 step regardless as the setting of LMAT1-0 bits.
The attenuate operation is done continuously until the input signal level becomes ALC limiter detection level (Table 27)
or less. After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the input
signal level exceeds LMTH1-0 bits.
LMTH1
0
0
1
1
LMTH0
0
1
0
1
ALC Limier Detection Level
ALC Recovery Waiting Counter Reset Level
−2.5dBFS > ALC Output ≥ −4.1dBFS
ALC Output ≥ −2.5dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
ALC Output ≥ −4.1dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
ALC Output ≥ −6.0dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
ALC Output ≥ −8.5dBFS
Table 27. ALC Limiter Detection Level / Recovery Counter Reset Level
ZELMN
0
1
ZTM1
ZTM0
0
0
1
1
0
1
0
1
LMAT1
LMAT0
ALC Limiter ATT Step
0
0
1 step
0.375dB
0
1
2 step
0.750dB
1
0
4 step
1.500dB
1
1
8 step
3.000dB
x
x
1step
0.375dB
Table 28. ALC Limiter ATT Step (x: Don’t care)
(default)
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 29. ALC Zero Crossing Timeout Period
MS0625-E-01
(default)
(default)
2007/06
- 50 -
[AK4648]
2.
ALC Recovery Operation
The ALC recovery operation waits for the WTM2-0 bits (Table 30) to be set after completing the ALC limiter operation.
If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 27) during the wait time, the ALC
recovery operation is done. The IVL and IVR values are automatically incremented by RGAIN1-0 bits (Table 31) up to
the set reference level (Table 32) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 29).
Then the IVL and IVR are set to the same value for both channels. The ALC recovery operation is done at a period set by
WTM2-0 bits. When zero cross is detected at both channels during the wait period set by WTM2-0 bits, the ALC recovery
operation waits until WTM2-0 period and the next recovery operation is done. If ZTM1-0 is longer than WTM2-0 and no
zero crossing occurs, the ALC recovery operation is done at a period set by ZTM1-0 bits.
For example, when the current IVOL value is 30H and RGAIN1-0 bits are set to “01”, IVOL is changed to 32H by the
auto limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the IVOL value exceeds
the reference level (REF7-0), the IVOL values are not increased.
When
“ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)”
during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When
“ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”,
the waiting timer of ALC recovery operation starts.
The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation
becomes faster than a normal recovery operation (Fast Recovery Operation). When large noise is input to microphone
instantaneously, the quality of small signal level in the large noise can be improved by this fast recovery operation. The
speed of fast recovery operation is set by RFST1-0 bits (Table 33).
WTM2
WTM1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
ALC Recovery Operation Waiting Period
8kHz
16kHz
44.1kHz
0
128/fs
16ms
8ms
2.9ms
1
256/fs
32ms
16ms
5.8ms
0
512/fs
64ms
32ms
11.6ms
1
1024/fs
128ms
64ms
23.2ms
0
2048/fs
256ms
128ms
46.4ms
1
4096/fs
512ms
256ms
92.9ms
0
8192/fs
1024ms
512ms
185.8ms
1
16384/fs
2048ms
1024ms
371.5ms
Table 30. ALC Recovery Operation Waiting Period
WTM0
RGAIN1
0
0
1
1
RGAIN0
GAIN STEP
0
1 step
0.375dB
1
2 step
0.750dB
0
3 step
1.125dB
1
4 step
1.500dB
Table 31. ALC Recovery GAIN Step
MS0625-E-01
(default)
(default)
2007/06
- 51 -
[AK4648]
REF7-0
GAIN(dB)
Step
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
E2H
+30.375
0.375dB
E1H
+30.0
(default)
E0H
+29.625
:
:
03H
−53.25
02H
−53.625
01H
−54.0
00H
MUTE
Table 32. Reference Level at ALC Recovery operation
RFST1 bit
0
0
1
1
RFST0 bit
Recovery Speed
0
4 times
1
8 times
0
16times
1
N/A
Table 33. Fast Recovery Speed Setting
MS0625-E-01
(default)
2007/06
- 52 -
[AK4648]
3.
Example of ALC Operation
Table 34 shows the examples of the ALC setting for MIC recording.
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same or
longer data as ZTM1-0 bits.
Maximum gain at recovery operation
WTM2-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
RFST1-0
ALC
Gain of IVOL
Limiter ATT step
Recovery GAIN step
Fast Recovery Speed
ALC enable
Data
01
0
01
fs=8kHz
Operation
−4.1dBFS
Enable
32ms
Data
01
0
11
fs=44.1kHz
Operation
−4.1dBFS
Enable
23.2ms
001
32ms
011
23.2ms
E1H
+30dB
E1H
+30dB
E1H
+30dB
E1H
+30dB
00
00
00
1
1 step
1 step
4 times
Enable
00
1 step
00
1 step
00
4 times
1
Enable
Table 34. Example of the ALC setting
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0” or PMADL=PMADR bits = “0”.
• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN and RFST1-0 bits
Example:
Limiter = Zero crossing Enable
Recovery Cycle = [email protected]
Zero Crossing Timeout Period = [email protected]
Limiter and Recovery Step = 1
Fast Recovery Speed = 4 step
Gain of IVOL = +30dB
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC bit = “1”
Manual Mode
WR (ZTM1-0, WTM2-0, RFST1-0)
(1) Addr=06H, Data=14H
WR (REF7-0)
(2) Addr=08H, Data=E1H
WR (IVL/R7-0)
* The value of IVOL should be
(3) Addr=09H&0CH, Data=E1H
the same or smaller than REF’s
WR (RGAIN1, LMTH1)
(4) Addr=0BH, Data=00H
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”)
(5) Addr=07H, Data=21H
ALC Operation
Note : WR : Write
Figure 35. Registers set-up sequence at ALC operation
MS0625-E-01
2007/06
- 53 -
[AK4648]
■ Input Digital Volume (Manual Mode)
The input digital volume becomes a manual mode when ALC bit is “0”. This mode is used in the case shown below.
1.
2.
3.
After exiting reset state, set-up the registers for the ALC operation (ZTM1-0, LMTH1-0 and etc)
When the registers for the ALC operation (Limiter period, Recovery period and etc) are changed.
For example; when the change of the sampling frequency.
When IVOL is used as a manual volume.
IVL7-0 and IVR7-0 bits set the gain of the volume control (Table 35). The IVOL value is changed at zero crossing or
timeout. Zero crossing timeout period is set by ZTM1-0 bits. If IVL7-0 or IVR7-0 bits are written during
PMADL=PMADR bits = “0”, IVOL operation starts with the written values at the end of the ADC initialization cycle
after PMADL or PMADR bit is changed to “1”.
Even if the path is switched from recording to playback, the register setting of IVOL remains. Therefore, IVL7-0 and
IVR7-0 bits should be set to “91H” (0dB).
IVL7-0
IVR7-0
F1H
F0H
EFH
:
E2H
E1H
E0H
:
03H
02H
01H
00H
GAIN (dB)
Step
+36.0
+35.625
+35.25
:
+30.375
0.375dB
+30.0
+29.625
:
−53.25
−53.625
−54
MUTE
Table 35. Input Digital Volume Setting
MS0625-E-01
(default)
2007/06
- 54 -
[AK4648]
When writing to the IVL7-0 and IVR7-0 bits continuously, the control register should be written with an interval more
than zero crossing timeout. If not, IVL and IVR are not changed since zero crossing counter is reset at every write
operation. If the same register value as the previous write operation is written to IVL and IVR, this write operation is
ignored and zero crossing counter is not reset. Therefore, IVL and IVR can be written with an interval less than zero
crossing timeout.
ALC bit
ALC Status
Disable
Enable
IVL7-0 bits
E1H(+30dB)
IVR7-0 bits
C6H(+20dB)
Internal IVL
E1H(+30dB)
Internal IVR
C6H(+20dB)
E1(+30dB) --> F1(+36dB)
(1)
Disable
E1(+30dB)
(2)
E1(+30dB) --> F1(+36dB)
C6H(+20dB)
Figure 36. IVOL value during ALC operation
(1) The IVL value becomes the start value if the IVL and IVR are different when the ALC starts.
(2) Writing to IVL and IVR registers (09H and 0CH) is ignored during ALC operation. After ALC is disabled, the IVOL
changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be set to “1”
by an interval more than zero crossing timeout period after ALC bit = “0”.
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[AK4648]
■ De-emphasis Filter
The AK4648 includes the digital de-emphasis filter (tc = 50/15μs) by IIR filter. Setting the DEM1-0 bits enables the
de-emphasis filter (Table 36).
DEM1
0
0
1
1
DEM0
Mode
0
44.1kHz
1
OFF
(default)
0
48kHz
1
32kHz
Table 36. De-emphasis Control
■ 5 Band Equalizer
The AK4648 has 5 Band Equalizer on DAC block. The center frequencies and cut/boost amount are selected by
FBEQx3-0 bits (Table 37).
• Center frequency: 100Hz, 250Hz, 1kHz, 3.5kHz, and 10kHz (Note 56, Note 57)
• Cut/Boost amount: Minimum –10.5dB, Maximum +12dB, Step 1.5dB
Note 56: These are the frequencies when the sampling frequency is 44.1kHz. These frequencies are proportional to the
sampling frequency.
Note 57: 100Hz is not center frequency but the frequency component lower than 100Hz is controlled.
Note 58: 10kHz is not center frequency but the frequency component higher than 10kHz is controlled.
FBEQ bit controls ON/OFF of this Equalizer.
FBEQA3-0:
FBEQB3-0:
FBEQC3-0:
FBEQD3-0:
FBEQE3-0:
Select the boost level of 100Hz
Select the boost level of 250Hz
Select the boost level of 1kHz
Select the boost level of 3.5kHz
Select the boost level of 10kHz
FBEQx3-0
Boost amount
0H
+12.0dB
1H
+10.5dB
2H
+9.0dB
3H
+7.5dB
:
:
8H
0dB
(default)
:
:
DH
−7.5dB
EH
−9.0dB
FH
−10.5dB
Table 37. Boost amount of 5 Band Equalizer
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[AK4648]
■ Digital Output Volume
The AK4648 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVL7-0 and
DVR7-0 bits. The volume is included in front of a DAC block. The input data of DAC is changed from +12 to –115dB or
MUTE. When the DVOLC bit = “1”, the DVL7-0 bits control both Lch and Rch attenuation levels. When the DVOLC bit
= “0”, the DVL7-0 bits control Lch level and DVR7-0 bits control Rch level. This volume has a soft transition function.
The DVTM bit sets the transition time between set values of DVL/R7-0 bits as either 1061/fs or 256/fs (Table 39). When
DVTM bit = “0”, a soft transition between the set values occurs (1062 levels). It takes 1061/fs ([email protected]=44.1kHz)
from 00H (+12dB) to FFH (MUTE).
DVL/R7-0
00H
01H
02H
:
18H
:
FDH
FEH
FFH
DVTM bit
0
1
Gain
Step
+12.0dB
+11.5dB
+11.0dB
:
0.5dB
0dB
:
−114.5dB
−115.0dB
MUTE (−∞)
Table 38. Digital Volume Code Table
(default)
Transition time between DVL/R7-0 bits = 00H and FFH
Setting
fs=8kHz
fs=44.1kHz
1061/fs
133ms
24ms
256/fs
32ms
6ms
Table 39. Transition Time Setting of Digital Output Volume
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(default)
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[AK4648]
■ Soft Mute
Soft mute operation is performed in the digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated
by −∞ (“0”) during the cycle set by the DVTM bit. When the SMUTE bit is returned to “0”, the mute is cancelled and the
output attenuation gradually changes to the value set by the DVL/R7-0 bits during the cycle set of the DVTM bit. If the
soft mute is cancelled within the cycle set by the DVTM bit after starting the operation, the attenuation is discontinued and
returned to the value set by the DVL/R7-0 bits. The soft mute is effective for changing the signal source without stopping
the signal transmission (Figure 37).
S M U T E bit
D VTM bit
D VL/R 7-0 bits
D VTM bit
(1)
(3)
A ttenuation
-∞
GD
(2)
GD
A nalog O utput
Figure 37. Soft Mute Function
(1) The output signal is attenuated until −∞ (“0”) by the cycle set by the DVTM bit.
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled within the cycle set by the DVTM bit, the attenuation is discounted and returned to the
value set by the DVL/R7-0 bits.
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[AK4648]
■ Analog Mixing: Stereo Input (LIN2/RIN2/LIN4/RIN4, AIN3 bit = “1”: LIN3/RIN3 pins)
When PMAINL2=PMAINR2 bits = “1”, LIN2 and RIN2 pins can be used as stereo line input for analog mixing. When
the LINS2 and RINS2 bits are set to “1”, the input signal from the LIN2/RIN2 pins is output from Speaker-Amp. When
the LINH2 and RINH2 bits are set to “1”, the input signal from the LIN2/RIN2 pins is output from Headphone-Amp.
When the LINL2/RINR2 bits are set to “1”, the input signal from the LIN2/RIN2 pins is output from the stereo line output
amplifier.
When PMAINL4=PMAINR4 bits = “1”, LIN4 and RIN4 pins can be used as stereo line input for analog mixing. When
the LINS4 and RINS4 bits are set to “1”, the input signal from the LIN4/RIN4 pins is output from Speaker-Amp. When
the LINH4 and RINH4 bits are set to “1”, the input signal from the LIN4/RIN4 pins is output from Headphone-Amp.
When the LINL4/RINR4 bits are set to “1”, the input signal from the LIN4/RIN4 pins is output from the stereo line output
amplifier.
When the analog mixing is used, A/D converter is also available if PMADL or PMADR bit is “1”. In this case, the input
resistance of LIN2/RIN2/LIN4/RIN4 pins becomes 30kΩ (typ.) at MGAIN1-0 bits = “00” and 20kΩ (typ.) at MGAIN1-0
bits = “01”, “10” or “11”, respectively.
Pin
LIN2
RIN2
LIN4
RIN4
PMAINL2 bit
PMAINR2 bit
PMAINL4 bit
PMAINR4 bit
0
1
bit
PMMICL or PMADL bit
PMMICR or PMADR bit
PMMICL or PMADL bit
PMMICR or PMADR bit
MGAIN1-0 bits
Input Impedance
(typ.)
00
01, 10 or 11
00
0
01, 10 or 11
00
1
01, 10 or 11
Table 40. Input Impedance of LIN2/RIN2/LIN4/RIN4 pins
1
60k
30k
60k
30k
30k
20k
When AIN3 bit = “1”, MIN and VCOC pins become LIN3 and RIN3 pins, respectively. In this case, PLL is not available.
When PMAINL3=PMAINR3 bits = “1”, LIN3 and RIN3 pins can be used as stereo line input for analog mixing. When
PMMICL=PMMICR=MICL3=MICR3 bits = “1”, analog mixing source is changed from LIN3/RIN3 input to MIC-Amp
output signal. When the LINS3 and RINS3 bits are set to “1”, the input signal from the LIN3/RIN3 pins is output from
Speaker-Amp. When the LINH3 and RINH3 bits are set to “1”, the input signal from the LIN3/RIN3 pins is output from
Headphone-Amp. When the LINL3/RINR3 bits are set to “1”, the input signal from the LIN3/RIN3 pins is output from
the stereo line output amplifier.
When the analog mixing is used, A/D converter is also available if PMADL or PMADR bit is “1”. When the analog
mixing is used at MICL3=MICR3 bits = “0”, the input resistance of LIN3/RIN3 pins becomes 30kΩ (typ.) at MGAIN1-0
bits = “00” and 20kΩ (typ.) at MGAIN1-0 bits = “01”, “10” or “11”, respectively. When the analog mixing is used at
MICL3=MICR3 bits = “1”, the input resistance of LIN3/RIN3 pins becomes 60kΩ (typ.) at MGAIN1-0 bits = “00” and
30kΩ (typ.) at MGAIN1-0 bits = “01”, “10” or “11”, respectively.
Pin
LIN3
RIN3
PMAINL3 bit
PMAINR3 bit
bit
PMMICL or PMADL bit
PMMICR or PMADR bit
MICL3 bit
MICR3 bit
MGAIN1-0 bits
Input Impedance
(typ.)
00
01, 10 or 11
00
1
0
0
01, 10 or 11
00
0
01, 10 or 11
1
1
00
1
01, 10 or 11
Table 41. Input Impedance of LIN3/RIN3 pins (AIN3 bit = “1”; x: Don’t care)
0
1
x
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60k
30k
60k
30k
30k
20k
60k
30k
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[AK4648]
Table 42, Table 43, Table 44, and Table 45 show the typical gain.
AK4648
INL1-0 bits
LIN1/IN1− pin
ADC Lch
RIN1/IN1+ pin
MDIF1 bit
MIC-Amp
INR1-0 bits
RIN2/IN2− pin
ADC Rch
LIN2/IN2+ pin
MDIF2 bit
MIC-Amp
MIN/LIN3 pin
MICR3 bit
PMAINR3 bit
PMAINR2 bit
PMAINL2 bit
PMAINR4 bit
PMAINL4 bit
RIN4/IN4− pin
MICL3 bit
LIN4/IN4+ pin
PMAINL3 bit
VCOC/RIN3 pin
Lineout, HP-Amp, SPK-Amp
Figure 38. Analog Mixing Circuit (Stereo Input)
PMAINL2 bit
PMAINR2 bit
LIN2 pin
RIN2 pin
LINL2 bit
RINR2 bit
LINH2 bit
RINH2 bit
LOUT/LOP pin,
ROUT/LON pin
HPL, HPR pin
LINS2 bit
RINS2 bit
SPLP/SPLN pin,
SPRP/SPRN pin
Figure 39. Analog Mixing Circuit (LIN2/RIN2)
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[AK4648]
PMAINL4 bit
PMAINR4 bit
LIN4 pin
RIN4 pin
LINL4 bit
RINR4 bit
LINH4 bit
RINH4 bit
LOUT/LOP pin,
ROUT/LON pin
HPL, HPR pin
LINS4 bit
RINS4 bit
SPLP/SPLN pin,
SPRP/SPRN pin
Figure 40. Analog Mixing Circuit (LIN4/RIN4)
PMAINL3 bit
PMAINR3 bit
LIN3 pin
RIN3 pin
LINL3 bit
RINR3 bit
LINH3 bit
RINH3 bit
LOUT/LOP pin,
ROUT/LON pin
HPL, HPR pin
LINS3 bit
RINS3 bit
SPLP/SPLN pin,
SPRP/SPRN pin
Figure 41. Analog Mixing Circuit (LIN3/RIN3: PLL is not available.)
LOVL bit
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4
Æ LOUT/ROUT
0
0dB
(default)
1
+2dB
Table 42. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ LOUT/ROUT Output Gain (typ.)
LOVL bit
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4
Æ LOP/LON
0
0dB
(default)
1
+2dB
Table 43. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ LOP/LON Output Gain (typ.)
HPG bit Setting
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4
Æ HPL/HPR
0dB
0dB
(default)
Table 44. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ Headphone-Amp Output Gain (typ.)
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[AK4648]
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Æ SPLP/SPLN or SPRP/SPRN
ALC bit = “0”
ALC bit = “1”
SPKMN bit = “1” SPKMN bit = “0” SPKMN bit = “1”
SPKMN bit = “0”
+4.41dB
+0.41dB
+6.41dB
(default)
000
−1.59dB
001
+0.41dB
+6.41dB
+2.41dB
+8.41dB
010
+4.63dB
+10.63dB
+6.63dB
+12.63dB
011
+6.63dB
+12.63dB
+8.63dB
+14.63dB
100
-6dB
0dB
-4dB
+2dB
101
-12dB
-6dB
-10dB
-4dB
110
N/A
N/A
N/A
N/A
111
N/A
N/A
N/A
N/A
Table 45. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ Speaker-Amp Output Gain (typ.), N/A: Not available
SPKG2-0
bits
■ Analog Mixing: Full-differential Mono Input (L4DIF bit = “1”: IN4+/IN4− pins)
When L4DIF bit = “1”, LIN4 and RIN4 pins become IN4+ and IN4− pins, respectively.
When PMAINL4 bit = “1”, IN4+ and IN4− pins can be used as full-differential mono line input for analog mixing. When
the LINS4 and RINS4 bits are set to “1”, the input signal from the IN4+/IN4− pins is output to Speaker-Amp. When the
LINH4 and RINH4 bits are set to “1”, the input signal from the IN4+/IN4− pins is output to Headphone-Amp. When the
LINL4/RINR4 bits are set to “1”, the input signal from the IN4+/IN4− pins is output to the stereo line output amplifier.
Table 46, Table 47, Table 48, and Table 49 show the typical gain. Input signal amplitude is defined as (IN4+) − (IN4−).
AK4648
MIC-Amp Lch
LIN4/IN4+ pin
L4DIF bit PMAINL4 bit
MIC-Amp Rch
RIN4/IN4− pin
PMAINR4 bit
Lineout, HP-Amp, Speaker-Amp
Figure 42. Full-differential Mono Analog Mixing Circuit
LOVL bit
IN4+/IN4− Æ LOUT/ROUT
(default)
0
−6dB
1
−4dB
Table 46. IN4+/IN4− Input Æ LOUT/ROUT Output Gain (typ.)
LOVL bit
IN4+/IN4− Æ LOP/LON
0
0dB
(default)
1
+2dB
Table 47. IN4+/IN4− Input Æ LOP/LON Output Gain (typ.)
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[AK4648]
HPG bit Setting
IN4+/IN4− Æ HPL/HPR
(default)
0dB
−6dB
Table 48. IN4+/IN4− Input Æ Headphone-Amp Output Gain (typ.)
IN4+/IN4- Æ SPLP/SPLN or SPRP/SPRN
ALC bit = “0”
ALC bit = “1”
+0.41dB
(default)
000
−1.59dB
001
+0.41dB
+2.41dB
010
+4.63dB
+6.63dB
011
+6.63dB
+8.63dB
100
-6dB
-4dB
101
-12dB
-10dB
110
N/A
N/A
111
N/A
N/A
Table 49. IN4+/IN4- Input Æ Speaker-Amp Output Gain (typ.), N/A: Not available
SPKG2-0 bits
■ Analog Mixing: Mono Input (AIN3 bit = “0”: MIN pin)
When AIN3 bit = “0”, MIN pin is used as mono input for analog mixing. When the PMMIN bit is set to “1”, the mono
input is powered-up. When the MINS bit is set to “1”, the input signal from the MIN pin is output to Speaker-Amp. When
the MINH bit is set to “1”, the input signal from the MIN pin is output from Headphone-Amp. When the MINL bit is set
to “1”, the input signal from the MIN pin is output from the stereo line output amplifier. The external resister Ri adjusts
the signal level of MIN input. Table 50, Table 51, Table 52, and Table 53 show the typical gain example at Ri = 20kΩ.
This gain is in inverse proportion to Ri .
Ri
MINL bit
Analog Input
LOUT/LOP pin,
ROUT/LON pin
MIN pin
MINH bit
HPL, HPR pin
MINS bit
SPLP/SPLN pin,
SPRP/SPRN pin
Figure 43. Block Diagram of MIN pin
LOVL bit
MIN Æ LOUT/ROUT
0
0dB
(default)
1
+2dB
Table 50. MIN Input Æ LOUT/ROUT Output Gain (typ.) at Ri = 20kΩ
LOVL bit
MIN Æ LOP/LON
0
+6dB
(default)
1
+8dB
Table 51. MIN Input Æ LON/LOP Output Gain (typ.) at Ri = 20kΩR
HPG bit Setting
MIN Æ HPL/HPR
0dB
−20dB
Table 52. MIN Input Æ Headphone-Amp Output Gain (typ.) at Ri = 20kΩ
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[AK4648]
MIN Æ SPLP/SPLN or SPRP/SPRN
ALC bit = “0”
ALC bit = “1”
000
+4.43dB
+6.43dB
(default)
001
+6.43dB
+8.43dB
010
+10.65dB
+12.65dB
011
+12.65dB
+14.65dB
100
0dB
+2dB
101
-6dB
-4dB
110
N/A
N/A
111
N/A
N/A
Table 53. MIN Input Æ Speaker-Amp Output Gain (typ.) at Ri = 20kΩ; N/A: Not available
SPKG2-0 bits
■ Stereo Line Output (LOUT/ROUT pins)
When the LODIF bit is set to “0”, the LOUT/ROUT pins become stereo line mode. When DACL bit is “1”, Lch/Rch
signal of DAC is output from the LOUT/ROUT pins which is single-ended. When DACL bit is “0”, output signal is
muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10kΩ (min.). When the PMLO=LOPS bits
= “0”, the stereo line output enters power-down mode and the output is pulled-down to VSS1 by 100kΩ(typ.). When the
LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at power-up/down can be reduced by changing
PMLO bit at LOPS bit = “1”. In this case, output signal line should be pulled-down to VSS1 by 20kΩ after AC coupled as
Figure 45. Rise/Fall time is 300ms(max.) at C=1μF and AVDD=3.3V. When PMLO bit = “1” and LOPS bits = “0”, stereo
line output is in normal operation.
LOVL bit set the gain of stereo line output.
When LOM bit = “1”, DAC output signal is output to LOUT and ROUT pins as (L+R)/2 mono signal.
When LOM3 bit = “1”, the signal selected by MICL3 and MICR3 bits (LIN3/RIN3 inputs or MIC-Amp outputs) to
LOUT and ROUT pins as (L+R)/2 mono signal.
DACL bit
LOVL bit
LOUT pin
DAC
ROUT pin
Figure 44. Stereo Line Output
LOPS
0
1
PMLO
0
1
0
1
Mode
LOUT/ROUT pin
Power-down
Pull-down to VSS1
Normal Operation
Normal Operation
Power-save
Fall down to VSS1
Power-save
Rise up to VCOM
Table 54. Stereo Line Output Mode Select
(default)
LOVL
Gain
Output Voltage (typ.)
0
0dB
0.6 x AVDD
(default)
1
+2dB
0.757 x AVDD
Table 55. Stereo Line Output Volume Setting
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[AK4648]
LOUT pin
ROUT pin
1μF
220Ω
20kΩ
Figure 45. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit)
<Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)>
(2 )
(5 )
P M L O b it
(1 )
(3 )
(4 )
(6 )
L O P S b it
L O U T , R O U T p in s
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
Figure 46. Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)
(1) Set LOPS bit = “1”. Stereo line output enters the power-save mode.
(2) Set PMLO bit = “1”. Stereo line output exits the power-down mode.
LOUT and ROUT pins rise up to VCOM voltage. Rise time is 200ms (max. 300ms) at C=1μF and
AVDD=3.3V.
(3) Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits the power-save mode.
Stereo line output is enabled.
(4) Set LOPS bit = “1”. Stereo line output enters power-save mode.
(5) Set PMLO bit = “0”. Stereo line output enters power-down mode.
LOUT and ROUT pins fall down to VSS1. Fall time is 200ms (max. 300ms) at C=1μF and AVDD=3.3V.
(6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode.
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[AK4648]
<Analog Mixing Circuit for Stereo Line Output>
DACL, MINL, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, MICL3, and MICR3 bits control each path switch. MIN
path mixing gain is 0dB(typ.)@LOVL bit = “0” when AIN3 bit is “0” and the external input resistance is 20kΩ. LIN2,
RIN2, LIN3, RIN3, LIN4, RIN4 and DAC paths mixing gain is 0dB(typ.)@LOVL bit = “0”.
LINL2 bit
LIN2 pin
0dB
LINL4 bit
LIN4 pin
0dB
MINL bit
MIN
AIN3 bit
LIN3/MIN pin
LIN3
M
0dB
MICL3 bit
I
LINL3 bit
LOUT pin
X
0dB
LIN1 pin
MIC-Amp Lch
DACL bit
DAC Lch
0dB
RINR2 bit
RIN2 pin
0dB
RINR4 bit
RIN4 pin
0dB
AIN3 bit
RIN3
MICR3 bit
RIN3/VCOM pin
RINR3 bit
I
ROUT pin
0dB
VCOC
RIN1 pin
M
MINL bit
X
0dB
MIC-Amp Rch
DACL bit
DAC Rch
0dB
Note: When MICL3 bit is set to “1”, MIN path is not available.
Figure 47. Stereo line output Mixing Circuit (LOVL bit = “0”)
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[AK4648]
■ Full-differential Mono Line Output (LOP/LON pins)
When LODIF bit = “1”, LOUT/ROUT pins become LOP/LON pins, respectively. Lch/Rch signal of DAC or
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 is output from the LOP/LON pins which is full-differential as (L+R)/2 signal. The
load impedance is 10kΩ (min.) for LOP and LON pins, respectively. When the PMLO bit = “0”, the mono line output
enters power-down mode and the output is Hi-Z. When the PMLO bit is “1” and LOPS bit is “1”, mono line output enters
power-save mode. Pop noise at power-up/down can be reduced by changing PMLO bit at LOPS bit = “0”. When PMLO
bit = “1” and LOPS bit = “0”, mono line output enters in normal operation. LOVL bit set the gain of mono line output.
When L4DIF=LODIF bits = “1”, full-differential output signal is as follows: (LOP) − (LON) = (IN4+) − (IN4−).
DACL bit
LOVL bit
LOP pin
DAC
LON pin
Figure 48. Mono Line Output
PMLO
0
1
LOPS
Mode
LOP
LON
x
Power-down
Hi-Z
Hi-Z
1
Power-save
Hi-Z
VCOM
0
Normal Operation
Normal Operation Normal Operation
Table 56. Mono Line Output Mode Setting (x: Don’t care)
LOVL
0
1
(default)
Gain
Output Voltage (typ.)
+6dB
1.2 x AVDD
(default)
+8dB
1.5 x AVDD
Table 57. Mono Line Output Volume Setting
PMLO bit
LOPS bit
LOP pin
LON pin
Hi-Z
Hi-Z
Hi-Z
VCOM
VCOM
Hi-Z
Figure 49. Power-up/Power-down Timing for Mono Line Output
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[AK4648]
<Analog Mixing Circuit for Mono Line Output>
DACL, MINL, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, MICL3, and MICR3 bits control each path switch.
MIN path mixing gain is +6dB(typ.)@LOVL bit = “0” when AIN3 bit is “0” and the external input resistance is 20kΩ.
LIN2, RIN2, LIN3, RIN3, LIN4, RIN4 and DAC paths mixing gain is 0dB(typ.)@LOVL bit = “0”.
LINL2 bit
LIN2 pin
0dB
LINL4 bit
LIN4 pin
0dB
MINL bit
MIN
AIN3 bit
LIN3/MIN pin
LIN3
+6dB
MICL3 bit
LINL3 bit
0dB
LIN1 pin
MIC-Amp Lch
RINR2 bit
RIN2 pin
0dB
RIN4 pin
0dB
M
RINR4 bit
AIN3 bit
RIN3
MICR3 bit
RIN3/VCOM pin
I
LOP/N pin
X
RINR3 bit
0dB
VCOC
RIN1 pin
MIC-Amp Rch
DACL bit
DAC Lch
0dB
DAC Rch
0dB
DACL bit
Note: When MICL3 bit is set to “1”, MIN path is not available.
Figure 50. Mono Line Output Mixing Circuit ( LOVL bit = “0”)
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[AK4648]
■ Headphone-Amp
Power supply voltage for the Headphone-Amp is supplied from the HVDD pin and centered on the HVDD/2 voltage at
VBAT bit = “0”. The load resistance is 16Ω (min.). HPG3-0 bits select the output voltage (Table 58).
When HPM bit = “1”, DAC output signal is output to HPL and HPR pins as (L+R)/2 mono signal.
When HPM3 bit = “1”, the signal selected by MICL3 and MICR3 bits (LIN3/RIN3 inputs or MIC-Amp outputs) to HPL
and HPR pins as (L+R)/2 mono signal.
HPG3-0 bits
Volume [dB]
FH-DH
N/A
CH
+3dB
BH
0dB
(default)
AH
-3dB
9H
-6dB
8H
-9dB
7H
-12dB
6H
-15dB
5H
-18dB
4H
-21dB
3H
-24dB
2H
-27dB
1H
-30dB
0H
-33dB
Table 58. Headphone-Amp volume setting (N/A: Not available)
<Connection with Headphone>
The AK4648 can be connected with the headphone as follows.
1. Single-ended Mode (In case of not using common buffer for Headphone-Amp)
HP-Amp
HPL pin
Headphone
C
R
0.22μF
10Ω
VCOM Amp for
HP-Amp
16Ω
HVCM pin
HP-Amp
16Ω
HPR pin
C
R
0.22μF
10Ω
Figure 51. External circuit example of HP-Amp (Single-ended Mode)
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[AK4648]
When an external resistor R is smaller than 12Ω, put an oscillation prevention circuit (0.22μF±20% capacitor and
10Ω±20% resistor) because it has the possibility that Headphone-Amp oscillates.
The cut-off frequency (fc) of Headphone-Amp depends on the external resistor and capacitor. This fc can be shifted to
lower frequency by using 5-band equalizer function. Table 59 shows the cut off frequency and the output power for
various resistor/capacitor combinations. The headphone impedance RL is 16Ω. The output voltage of headphone is typ.
(0.6 x AVDD) Vpp @HPG = 0dB.
R [Ω]
C [μF]
fc [Hz]
fc [Hz]
5-band EQ =
OFF
5-band EQ = ON
(+6dB/100Hz @
fs=44.1kHz)
220
45
100
100
100
70
6.8
47
149
100
50
16
47
106
10
137
Note 59. Output power at 16Ω load.
17
43
28
78
19
47
69
0
Output Power [mW]@0dBFS
HVDD=3.0V
AVDD=3.0V
HVDD=3.3V
AVDD=3.3V
HVDD=5V
AVDD=3.3V
25.3
30.6
30.6
12.5
15.1
15.1
6.3
7.7
7.7
Table 59. External Circuit Example
When the HPMTN bit is “0”, the common voltage of Headphone-Amp falls and the outputs (HPL and HPR pins) go to
“L” (VSS2). When the HPMTN bit is “1”, the common voltage rises to HVDD/2 at VBAT bit = “0”. A capacitor between
the MUTET pin and ground reduces pop noise at power-up. Rise/Fall time constant is in proportional to HVDD voltage
and the capacitor at MUTET pin.
HPMTN bit= “0” Æ “1”
HPMTN bit = “1” Æ “0”
(Note 60)
(Note 61)
typ.
max
typ.
max.
3.6V
120ms
210ms
140ms
260ms
1μF±30%
4.2V
230ms
270ms
5.0V
260ms
290ms
3.6V
260ms
460ms
310ms
560ms
2.2μF±30%
4.2V
500ms
570ms
550ms
590ms
5.0V
Note 60. Rising time of HP-Amp (0.8 x HVDD/2)
Note 61. Time until the common voltage goes to VSS2.
Table 60. Relationship between capacitor value of MUTET pin and MUTE ON/OFF time (VBAT bit = “0”)
HVDD
Capacitor value of
MUTET pin
MS0625-E-01
2007/06
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[AK4648]
When PMHPL and PMHPR bits are “0”, the Headphone-Amp is powered-down, and HPL and HPR pins go to “L”
(VSS2).
PMHPL bit,
PMHPR bit
HPMTN bit
HPL pin,
HPR pin
(1) (2)
(3)
(4)
Figure 52. Power-up/down sequence for Headphone-Amp (Single-ended Mode)
(1) Headphone-Amp power-up (PMHPL, PMHPR bit = “1”). The outputs are still VSS2.
(2) Headphone-Amp common voltage rises up (HPMTN bit = “1”). Common voltage of Headphone-Amp is rising.
(3) Headphone-Amp common voltage falls down (HPMTN bit = “0”). Common voltage of Headphone-Amp is falling.
(4) Headphone-Amp power-down (PMHPL, PMHPR bit = “0”). The outputs are VSS2. If the power supply is switched
off or Headphone-Amp is powered-down before the common voltage goes to VSS2, some POP noise occurs.
2. Pseudo Cap-less Mode (In case of using common buffer for Headphone-Amp)
HP-Amp
HPL pin
Headphone
R
0.22μF
10Ω
VCOM Amp for
HP-Amp
16Ω
HVCM pin
HP-Amp
16Ω
HPR pin
R
0.22μF
10Ω
Figure 53. External circuit example for Headphone-Amp (Pseudo Cap-less Mode)
When an external resistor R is smaller than 12Ω, put an oscillation prevention circuit (0.22μF±20% capacitor and
10Ω±20% resistor) because it has the possibility that Headphone-Amp oscillates.
MS0625-E-01
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[AK4648]
When the HPMTN bit is “0”, common voltages of Headphone-Amp and common buffer for Headphone-Amp fall and
HPL, HPR and HVCM pins go to “L” (VSS2). When the HPMTN bit is “1”, the common voltages rises to HVDD/2 at
VBAT bit = “0”. A capacitor between the MUTET pin and ground reduces pop noise at power-up. Rise/Fall time constant
is in proportional to HVDD voltage and the capacitor at MUTET pin.
HPMTN bit= “0” Æ “1”
HPMTN bit = “1” Æ “0”
(Note 62)
(Note 63)
typ.
max
typ.
max.
3.6V
120ms
210ms
140ms
260ms
1μF±30%
4.2V
230ms
270ms
5.0V
260ms
290ms
3.6V
260ms
460ms
310ms
560ms
2.2μF±30%
4.2V
500ms
570ms
5.0V
550ms
590ms
Note 62. Rising time of HP-Amp (0.8 x HVDD/2)
Note 63. Time until the common voltage goes to VSS2.
Table 61. Relationship between capacitor value of MUTET pin and MUTE ON/OFF time (VBAT bit = “0”)
HVDD
Capacitor value of
MUTET pin
When PMHPL, PMHPR, and PMHPC bits are “0”, the Headphone-Amp is powered-down, and HPL, HPR, HVCM pins
go to “L” (VSS2).
PMHPL bit,
PMHPR bit
PMHPC bit
HPMTN bit
HPL pin,
HPR pin,
HVCM pin
(1) (2)
(3)
(4)
Figure 54. Power-up/down sequence for Headphone-Amp (Pseudo Cap-less Mode)
(1)
(2)
(3)
(4)
Headphone-Amp power-up (PMHPL=PMHPR=PMHPC bits = “1”). Outputs are still VSS2.
Headphone-Amp common voltage rises up (HPMTN bit = “1”). Common voltage of Headphone-Amp is rising.
Headphone-Amp common voltage falls down (HPMTN bit = “0”). Common voltage of Headphone-Amp is falling.
Headphone-Amp power-down (PMHPL=PMHPR=PMHPC bits = “0”). Outputs become VSS2. If the power supply
is switched off or Headphone-Amp is powered-down before the common voltage goes to VSS2, some POP noise
occurs.
<Headphone-Amp PSRR>
When HVDD is directly supplied from the battery in the mobile phone system, RF noise may influences headphone
output performance. When VBAT bit is set to “1”, HP-Amp PSRR for the noise applied to HVDD is improved. In this
case, HP-Amp common voltage is 0.64 x AVDD (typ.). When AVDD is 3.3V, common voltage is 2.1V. Therefore, when
HVDD voltage becomes lower than 4.2V, the output signal will be clipped.
VBAT bit
Common Voltage [V]
0
0.5 x HVDD
Table 62. HP-Amp Common Voltage
MS0625-E-01
1
0.64 x AVDD
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[AK4648]
<Wired OR with External Headphone-Amp>
When PMVCM=PMHPL=PMHPR bits = “0” and HPZ bit = “1”, Headphone-Amp is powered-down and HPL/R pins are
pulled-down to VSS2 by 200kΩ (typ.). In this setting, it is available to connect Headphone-Amp of the AK4648 and
external single supply Headphone-Amp by “wired OR” and the output level of external HP-Amp should be from “ -0.3V”
to “HVDD+0.3V”. In this mode, power supply current is 20μA(typ.). This function is not supported in Pseudo Cap-less
Mode.
PMVCM
x
0
1
1
PMHPL/R
0
0
1
1
HPMTN
HPZ
Mode
x
0
Power-down & Mute
x
1
Power-down
0
x
Mute
1
x
Normal Operation
Table 63. HP-Amp Mode Setting (x: Don’t care)
HPL/R pins
VSS2
(default)
Pull-down by 200kΩ
VSS2
Normal Operation
HPL pin
AK4648
Headphone
HPR pin
Another
HP-Amp
Figure 55. Wired OR with External Headphone-Amp
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[AK4648]
<Connection with mono headphone>
The AK4648 can be connected with mono headphone by using Headphone-Amp power management bit and HPZ bit. As
right channel of mono headphone is usually connected to GND, the right channel of Headphone-Amp must be Hi-Z. Here
are the power up sequence in Single-ended Mode and Pseudo Cap-less Mode.
1.
Single-ended Mode
(1) Power-down Headphone-amp: PMHPL=PMHPR=HPZ bits = “0”
HPL/HPR pins output VSS2.
(2) Power-up left channel of Headphone-amp: PMHPL = “1”
Left channel of Headphone-amp is powered-up and HPL pin outputs VSS2.
(3) Change pull-down resistor of right channel of Headphone-amp: HPZ bit = “1”
HPR pin is pulled-down by 200kΩ(typ.) to VSS2.
(4) Release mute of Headphone-amp: HPMTN bit: “0” Æ 1
HPL pin outputs the signal and HPR pin is pulled-down by 200kΩ (typ.) to VSS2.
2.
Pseudo Cap-less Mode
(1) Power-down of Headphone-amp: PMHPL=PMHPR=PMHPC=HPZ bits = “0”
HPL/HPR/HVCM pins output VSS2.
(2) Power-up left channel and common buffer of Headphone-amp: PMHPL = PMHPC bits = “1”
Left channel and common buffer of Headphone-amp are powered-up and they output VSS2.
(3) Change pull-down resistor of right channel of Headphone-amp: HPZ bit = “1”
HPR pin is pulled-down by 200kΩ(typ.) to VSS2.
(4) Release mute of Headhone-amp: HPMTN bit: “0” Æ 1
HPL pin outputs the signal. HPR pin is pulled-down by 200kΩ (typ.) to VSS2 and outputs HVCM voltage.
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[AK4648]
<Analog Mixing Circuit for Headphone Output>
DACH, MINH, LINH2, RINH2, LINH3, RINH3, LINH4, RINH4, MICL3, and MICR3 bits control each path switch.
MIN path mixing gain is −20dB(typ.) @ HPG = 0dB when AIN3 bit is “0” and the external input resistance is 20kΩ.
DACH, LIN2, RIN2, LIN3, RIN3, LIN4, RIN4 and DAC paths mixing gain is 0dB(typ.) @ HPG =0dB.
LINH2 bit
LIN2 pin
0dB
LINH4 bit
LIN4 pin
0dB
MINH bit
MIN
AIN3 bit
LIN3/MIN pin
LIN3
M
-20dB
MICL3 bit
I
LINH3 bit
HPL pin
X
0dB
LIN1 pin
MIC-Amp Lch
DACH bit
DAC Lch
0dB
RINH2 bit
RIN2 pin
0dB
RINH4 bit
RIN4 pin
0dB
AIN3 bit
RIN3
MICR3 bit
RIN3/VCOM pin
RINH3 bit
I
HPR pin
0dB
VCOC
RIN1 pin
M
MINH bit
X
-20dB
MIC-Amp Rch
DACH bit
DAC Rch
0dB
Note: When MICL3 bit is set to “1”, MIN path is not available.
Figure 56. Headphone Output Mixing Circuit (HPG = 0dB)
MS0625-E-01
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[AK4648]
■ Speaker-Amp
Speaker output mode is selected by SPKMN bit and Power ON/OFF of Speaker-Amp is controlled by PMSPL and
PMSPR bits. In Stereo SPK Mode (SPKMN bit = “1”, PMSPL=PMSPR bits = “1”) and Mono SPK Mode (SPKMN bit =
“0”, PMSPL bit = “1” or PMSPR bit = “1”), the output power is 640mW/ch at HVDD=3.6V, 8Ω. In High Power Mono
SPK Mode (SPKMN bit = “0”, PMSPL=PMSPR bit = “1”), the output power is 820mW at HVDD=3.6V, 8Ω. When
using High Power Mono SPK mode, SPLP pin should be connected to SPRP pin and SPLN pin should be connected to
SPRN pin. When SPKMN bit is changed, PMSPL and PMSPR bits should be set to “0”. Power-Save mode is controlled
by SPPSN bit.
Mode
Mono SPK
SPKMN bit PMSPL bit PMSPR bit SPLP/SPLN pin SPRP/SPRN pin
0
0
0
PD
PD
0
1
0
PU (*1)
PD
0
0
1
PD
PU (*1)
High Power Mono SPK
0
1
1
PU (*2)
Stereo SPK
1
0
0
PD
PD
1
0
1
PD
PU: Rch
1
1
0
PU: Lch
PD
1
1
1
PU: Lch
PU: Rch
*1: The output signal is Mono Mixing [(L+R)/2]. The output power is 640mW at HVDD=3.6V, 8Ω.
*2: The output signal is Mono Mixing [(L+R)/2]. The output power is 820mW at HVDD=3.6V, 8Ω.
Table 64. Speaker Output Mode Setting (PD: Power-Down, PU: Power-Up)
Power supply for Speaker-Amp (HVDD) is 2.6V to 5.0V. The DAC or LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 signal is
input to the Speaker-amp as Mono: [(L+R)/2] or stereo signal. The input signal selects Mono or Stereo by using SPKMN
bit. The Speaker-amp is mono/stereo with BTL output. The gain is set by SPKG2-0 bits. Output level depends on AVDD
voltage and SPKG2-0 bits.
SPKG2-0 bits
Gain
ALC bit = “0”
ALC bit = “1”
000
+4.43dB
+6.43dB
(default)
001
+6.43dB
+8.43dB
010
+10.65dB
+12.65dB
011
+12.65dB
+14.65dB
100
0dB
+2dB
101
-6dB
-4dB
110
N/A
N/A
111
N/A
N/A
Table 65. SPK-Amp Internal gain (Gain of mono mixing is not included.), N/A: Not available
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[AK4648]
AVDD
HVDD
3.6V
3.3V
4.5V
SPKG2-0 bits
000
001
010
011
000
001
010
011
SPK-Amp Output (DAC Input = 0dBFS)
ALC bit = “0”
ALC bit = “1”
(LMTH1-0 bits = “00”; -2.5dBFS)
3.30Vpp
3.11Vpp
4.15Vpp
3.92Vpp
5.2Vpp (Note 64)
5.2Vpp (Note 64)
5.2Vpp (Note 64)
5.2Vpp (Note 64)
3.30Vpp
3.11Vpp
4.15Vpp
3.92Vpp
6.75Vpp
6.37Vpp
7.0Vpp (Note 64)
7.0Vpp (Note 64)
Note 64. The output level is calculated assuming that output signal is not clipped. In actual case, output signal may be
clipped when DAC outputs 0dBFS signal. DAC output level should be set to lower level by setting digital
volume so that Speaker-Amp output level is 5.2Vpp (HVDD=3.6V) or 7.0Vpp (HVDD=4.5V) or less and output
signal is not clipped.
Table 66. SPK-Amp Output Level
<ALC Operation Example of Speaker Playback>
fs=44.1kHz
Operation
−2.5dBFS
Enable
11.6ms
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same data
as ZTM1-0 bits
Maximum gain at recovery operation
011
23.2ms
C1H
+18dB
Gain of IVOL
91H
0dB
WTM2-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
ALC
Data
00
0
10
Limiter ATT step
00
Recovery GAIN step
00
ALC enable
1
Table 67. ALC Opeation Example of Speaker Playback
MS0625-E-01
1 step
1 step
Enable
2007/06
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[AK4648]
<Speaker-Amp Control Sequence>
Lch Speaker-Amp is powered-up/down by PMSPL bit and Rch Speaker-Amp is powered-up/down by PMSPR bit.
Power-save mode of both Lch and Rch Speaker-Amps are controlled by SPPSN bit.
When PMSPL (PMSPR) bit is “0”, both SPLP (SPRP) and SPLN (SPRN) pin are in Hi-Z state. When PMSPL (PMSPR)
bit is “1” and SPPSN bit is “0”, the Speaker-Amp enters power-save mode. In this mode, SPLP (SPRP) pin is placed in
Hi-Z state and SPLN (SPRN) pin goes to HVDD/2 voltage. Power-save mode can reduce the pop noise at power-up and
power-down.
When The PDN pin is changed from “L” to “H” after power-up and PMSPL (PMSPR) bit is set to “1”, SPLP (SPRP) and
SPLN (SPRN) pins are in power-save mode. When changing the output mode of Speaker-Amp, PMSPL and PMSPR bits
should be set to “0”.
PMSPL bit
PMSPR bit
0
SPLP pin
SPLN pin
SPRP pin
SPRN pin
x
Power-down
Hi-Z
Hi-Z
0
Power-Save
Hi-Z
HVDD/2
1
Normal Operation
Normal Operation Normal Operation
Table 68. Setting of Speaker-Amp Mode (x: Don’t care)
SPPSN bit
1
Mode
(default)
PMSPL bit
PMSPR bit
SPPSN bit
SPLP pin,
SPRP pin
SPLN pin,
SPRN pin
Hi-Z
Hi-Z
Hi-Z
HVDD/2
HVDD/2
Hi-Z
Figure 57. Power-up/Power-down Timing for Speaker-Amp
MS0625-E-01
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[AK4648]
<Analog Mixing Circuit for Speaker Output>
1. Stereo SPK Mode (SPKMN bit = “1”)
DACS, MINS, LINS2, RINS2, LINS3, RINS3, LINS4, RINS4, MICL3, and MICR3 bits control each path switch. MIN
path mixing gain is +4.43dB(typ.) @ SPKG2-0 bits = “000” & ALC bit = “0” when AIN3 bit is “0” and the external input
resistance is 20kΩ. DACS, LINS2, RINS2, LINS3, RINS3, LINS4, and RINS4 paths mixing gain is +4.43(typ.) @
SPKG2-0 bits = “000” & ALC bit = “0”.
LINS2 bit
LIN2 pin
+4.43dB
LINS4 bit
LIN4 pin
+4.43dB
MINS bit
MIN
+4.43dB
AIN3 bit
LIN3/MIN pin
LIN3
MICL3 bit
M
I
LINS3 bit
SPLP/N pin
X
+4.43dB
LIN1 pin
MIC-Amp Lch
DACS bit
DAC Lch
+4.43dB
RINS2 bit
+4.43dB
RIN2 pin
RINS4 bit
RIN4 pin
+4.43dB
AIN3 bit
RIN3
MICR3 bit
RINS3 bit
I
SPRP/N pin
+4.43dB
RIN3/VCOM pin
VCOC
RIN1 pin
M
MINS bit
X
+4.43dB
MIC-Amp Rch
DACS bit
DAC Rch
+4.43dB
Note: When MICL3 bit is set to “1”, MIN path is not available.
Figure 58. Speaker Mixing Circuit (SPKMN bit = “1”, SPKG2-0 bits = “000”, ALC bit = “0”)
MS0625-E-01
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[AK4648]
2. Mono SPK Mode & High Power Mono SPK Mode (SPKMN bit = “0”)
DACS, MINS, LINS2, RINS2, LINS3, RINS3, LINS4, RINS4, MICL3, and MICR3 bits control each path switch. MIN
path mixing gain is +4.43dB(typ.)@SPKG2-0 bits = “000” & ALC bit = “0” when AIN3 bit is “0” and the external input
resistance is 20kΩ. DACS, LINS2, RINS2, LINS3, RINS3, LINS4, RINS4, MICL3, and MICR3 paths mixing gain is
–1.59dB(typ.) @ SPKG2-0 bits = “000” & ALC bit = “0”.
LINS2 bit
LIN2 pin
-1.59dB
LINS4 bit
LIN4 pin
-1.59dB
MINS bit
MIN
+4.43dB
AIN3 bit
LIN3/MIN pin
LIN3
MICL3 bit
LINS3 bit
-1.59dB
LIN1 pin
MIC-Amp Lch
DACS bit
DAC Lch
-1.59dB
M
I
RINS2 bit
SPLP/N pin
or
SPRP/N pin
X
-1.59dB
RIN2 pin
RINS4 bit
-1.59dB
RIN4 pin
AIN3 bit
RIN3
MICR3 bit
RINS3 bit
-1.59dB
RIN3/VCOM pin
VCOC
RIN1 pin
MIC-Amp Rch
DACS bit
DAC Rch
-1.59dB
Note: When MICL3 bit is set to “1”, MIN path is not available.
Figure 59. Speaker Mixing Circuit (SPKMN bit = “0”, SPKG2-0 bits = “000”, ALC bit = “0”)
MS0625-E-01
2007/06
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[AK4648]
■ Serial Control Interface
The AK4648 supports the fast-mode I2C-bus (max.: 400kHz). Pull-up resistors at SDA and SCL pins should be connected
to (TVDD+0.3) V or less voltage.
1. WRITE Operations
Figure 60 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 66). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant six bits of the slave address are fixed as “001001”. The next bit is CAD0 (device address bit).
This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets these device address bits
(Figure 61). If the slave address matches that of the AK4648, the AK4648 generates an acknowledge and the operation is
executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the
acknowledge clock pulse (Figure 67). A R/W bit value of “1” indicates that the read operation is to be executed. A “0”
indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4648. The format is MSB first, and those most
significant 2-bits are fixed to zeros (Figure 62). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 63). The AK4648 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 66).
The AK4648 can perform more than one byte write operation per sequence. After receiving the third byte the AK4648
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 27H prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 68) except for the START and STOP
conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 60. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
1
CAD0
R/W
A2
A1
A0
D2
D1
D0
(The CAD0 should match with CAD0 pin)
Figure 61. The First Byte
0
0
A5
A4
A3
Figure 62. The Second Byte
D7
D6
D5
D4
D3
Figure 63. Byte Structure after the second byte
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[AK4648]
2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4648. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after receiving the first data word.
After receiving each data packet the internal 6-bit address counter is incremented, and the next data is automatically taken
into the next address. If the address exceeds 27H prior to generating a stop condition, the address counter will “roll over”
to 00H and the data of 00H will be read out.
The AK4648 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
2-1. CURRENT ADDRESS READ
The AK4648 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would
access data from the address n+1. After receiving the slave address with R/W bit set to “1”, the AK4648 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge but instead generates a stop condition, the AK4648
ceases transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
Data(n+1)
Data(n+2)
MA
AC
SK
T
E
R
A
C
K
MA
AC
SK
T
E
R
Data(n+x)
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
P
MN
AA
SC
T
EK
R
Figure 64. CURRENT ADDRESS READ
2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4648 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but instead generates a stop condition, the AK4648 ceases transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
MA
AC
S K
T
E
R
Data(n+x)
MA
AC
S
T K
E
R
MA
AC
S
T K
E
R
P
MN
A A
S
T C
E K
R
Figure 65. RANDOM ADDRESS READ
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[AK4648]
SDA
SCL
S
P
start condition
stop condition
Figure 66. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 67. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 68. Bit Transfer on the I2C-Bus
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[AK4648]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Lch Input Volume Control
Lch Digital Volume Control
ALC Mode Control 3
Rch Input Volume Control
Rch Digital Volume Control
Mode Control 3
Mode Control 4
Power Management 3
Digital Filter Select
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
Power Management 4
Mode Control 5
Lineout Mixing Select
HP Mixing Select
SPK Mixing Select
EQ Control 250Hz/100Hz
EQ Control 3.5kHz/1kHz
EQ Control 10kHz
D7
D6
PMSPR
PMVCM
HPZ
SPPSN
LOVL
PLL3
PS1
DVTM
0
REF7
IVL7
DVL7
RGAIN1
IVR7
DVR7
0
HPG3
INR1
GN1
F3A7
F3AS
F3B7
0
EQA7
EQA15
EQB7
0
EQC7
EQC15
F1A7
F1AS
F1B7
0
HPMTN
MINS
LOPS
PLL2
PS0
WTM2
0
REF6
IVL6
DVL6
LMTH1
IVR6
DVR6
LOOP
HPG2
INL1
GN0
F3A6
0
F3B6
0
EQA6
EQA14
EQB6
0
EQC6
EQC14
F1A6
0
F1B6
0
PMAINR4
0
LOM
0
0
FBEQB3
FBEQD3
0
D5
PMMIN
PMHPL
DACS
PLL1
FS3
ZTM1
ALC
REF5
IVL5
DVL5
0
IVR5
DVR5
SMUTE
HPG1
0
0
F3A5
F3A13
F3B5
F3B13
EQA5
EQA13
EQB5
EQB13
EQC5
EQC13
F1A5
F1A13
F1B5
F1B13
PMHPR
DACL
SPKG1
PLL0
MSBS
ZTM0
ZELMN
REF4
IVL4
DVL4
0
IVR4
DVR4
DVOLC
HPG0
MDIF2
FIL1
F3A4
F3A12
F3B4
F3B12
EQA4
EQA12
EQB4
EQB12
EQC4
EQC12
F1A4
F1A12
F1B4
F1B12
D3
PMLO
M/S
0
SPKG0
BCKO
BCKP
WTM1
LMAT1
REF3
IVL3
DVL3
0
IVR3
DVR3
0
IVOLC
MDIF1
EQ
F3A3
F3A11
F3B3
F3B11
EQA3
EQA11
EQB3
EQB11
EQC3
EQC11
F1A3
F1A11
F1B3
F1B11
D2
PMDAC
PMHPC
PMMP
MINL
0
FS2
WTM0
LMAT0
REF2
IVL2
DVL2
0
IVR2
DVR2
FBEQ
HPM
INR0
FIL3
F3A2
F3A10
F3B2
F3B10
EQA2
EQA10
EQB2
EQB10
EQC2
EQC10
F1A2
F1A10
F1B2
F1B10
D1
0
MCKO
0
SPKG2
DIF1
FS1
RFST1
RGAIN0
REF1
IVL1
DVL1
VBAT
IVR1
DVR1
DEM1
MINH
INL0
0
F3A1
F3A9
F3B1
F3B9
EQA1
EQA9
EQB1
EQB9
EQC1
EQC9
F1A1
F1A9
F1B1
F1B9
0
DIF0
FS0
RFST0
LMTH0
REF0
IVL0
DVL0
0
IVR0
DVR0
DEM0
DACH
PMADR
0
F3A0
F3A8
F3B0
F3B8
EQA0
EQA8
EQB0
EQB8
EQC0
EQC8
F1A0
F1A8
F1B0
F1B8
PMAINL4
PMAINR3
PMAINL3
PMAINR2
PMAINL2
PMMICR
PMMICL
SPKMN
LOM3
HPM3
0
FBEQB2
FBEQD2
0
MICR3
RINR4
RINH4
RINS4
FBEQB1
FBEQD1
0
MICL3
LINL4
LINH4
LINS4
FBEQB0
FBEQD0
0
L4DIF
RINR3
RINH3
RINS3
FBEQA3
FBEQC3
FBEQE3
MIX
LINL3
LINH3
LINS3
FBEQA2
FBEQC2
FBEQE2
AIN3
RINR2
RINH2
RINS2
FBEQA1
FBEQC1
FBEQE1
LODIF
LINL2
LINH2
LINS2
FBEQA0
FBEQC0
FBEQE0
MGAIN1
D4
PMSPL
D0
PMADL
PMPLL
MGAIN0
Note 65. PDN pin = “L” resets the registers to their default values.
Note 66. Unused bits must contain “0” value.
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[AK4648]
■ Register Definitions
Addr
00H
Register Name
Power Management 1
R/W
Default
D7
PMSPR
R/W
0
D6
PMVCM
R/W
0
D5
PMMIN
R/W
0
D4
PMSPL
R/W
0
D3
PMLO
R/W
0
D2
PMDAC
R/W
0
D1
0
RD
0
D0
PMADL
R/W
0
PMADL: MIC-Amp Lch and ADC Lch Power Management
0: Power down (default)
1: Power up
When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms
@44.1kHz) starts. After initializing, digital data of the ADC is output.
PMDAC: DAC Power Management
0: Power down (default)
1: Power up
PMLO: Stereo Line Out Power Management
0: Power down (default)
1: Power up
PMSPL: Speaker-Amp Lch Power Management
0: Power down (default)
1: Power up
PMMIN: MIN Input Power Management
0: Power down (default)
1: Power up
PMMIN or PMAINL3 bit should be set to “1” for playback.
PMVCM: VCOM Power Management
0: Power down (default)
1: Power up
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only
when all power management bits of 00H, 01H, 02H, 10H, 20H and MCKO bits are “0”.
PMSPR: Speaker-Amp Rch Power Management
0: Power down (default)
1: Power up
Each block can be powered-down respectively by writing “0” to each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value.
When all power management bits are “0” in the 00H, 01H, 02H, 10H and 20H addresses and MCKO bit is “0”, all
blocks are powered-down. The register values remain unchanged.
When neither ADC nor DAC are powered-up, external clocks may not be present. When ADC or DAC is powered-up,
external clocks must always be present.
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[AK4648]
Addr
01H
Register Name
Power Management 2
R/W
Default
D7
HPZ
R/W
0
D6
HPMTN
R/W
0
D5
PMHPL
R/W
0
D4
PMHPR
R/W
0
D3
M/S
R/W
0
D2
PMHPC
R/W
0
D1
MCKO
R/W
0
D0
PMPLL
R/W
0
PMPLL: PLL Power Management
0: EXT Mode and Power-Down (default)
1: PLL Mode and Power-up
MCKO: Master Clock Output Enable
0: Disable: MCKO pin = “L” (default)
1: Enable: Output frequency is selected by PS1-0 bits.
PMHPC: Headphone-Amp’s Common Buffer Power Management
0: Power-down (default)
1: Power-up
M/S: Master / Slave Mode Select
0: Slave Mode (default)
1: Master Mode
PMHPR: Headphone-Amp Rch Power Management
0: Power-down (default)
1: Power-up
PMHPL: Headphone-Amp Lch Power Management
0: Power-down (default)
1: Power-up
HPMTN: Headphone-Amp Mute Control
0: Mute (default)
1: Normal operation
HPZ: Headphone-Amp Pull-down Control
0: Shorted to GND (default)
1: Pulled-down by 200kΩ (typ.)
This bit is enabled when Lch or Rch of Headphone-amp is powered-down.
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[AK4648]
Addr
02H
Register Name
Signal Select 1
R/W
Default
D7
SPPSN
R/W
0
D6
MINS
R/W
0
D5
DACS
R/W
0
D4
DACL
R/W
0
D3
0
RD
0
D2
PMMP
R/W
0
D1
0
RD
0
D0
MGAIN0
R/W
1
MGAIN1-0: MIC-Amp Gain Control (Table 22)
MGAIN1 bit is D5 bit of 03H.
PMMP: MPWR pin Power Management
0: Power down: Hi-Z (default)
1: Power up
DACL: Switch Control from DAC to Line Output
0: OFF (default)
1: ON
When PMLO bit is “1”, DACL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to VSS1.
DACS: Switch Control from DAC to Speaker-Amp
0: OFF (default)
1: ON
When DACS bit is “1”, DAC output signal is input to Speaker-Amp.
MINS: Switch Control from MIN pin to Speaker-Amp
0: OFF (default)
1: ON
When MINS bit is “1”, mono singal is input to Speaker-Amp.
SPPSN: Speaker-Amp Power-Save Mode
0: Power Save Mode (default)
1: Normal Operation
When SPPSN bit is “0”, Speaker-Amp is in power-save mode. In this mode, SPLP/SPRP pins go to Hi-Z and
SPLN/SPRN pins output HVDD/2 voltage. When PMSPL or PMSPR bit is “1”, SPPSN bit is enabled.
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[AK4648]
Addr
03H
Register Name
Signal Select 2
R/W
Default
D7
LOVL
R/W
0
D6
LOPS
R/W
0
D5
MGAIN1
R/W
0
D4
SPKG1
R/W
0
D3
SPKG
R/W
0
D2
MINL
R/W
0
D1
SPKG2
R/W
0
D0
0
RD
0
MINL: Switch Control from MIN pin to Stereo Line Output
0: OFF (default)
1: ON
When PMLO bit is “1”, MINL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to VSS1.
SPKG2-0: Speaker-Amp Output Gain Select (Table 65)
MGAIN1: MIC-Amp Gain Control (Table 22)
LOPS: Stereo Line Output Power-Save Mode
0: Normal Operation (default)
1: Power Save Mode
LOVL: Stereo Line Output Gain Select (Table 55, Table 57)
0: 0dB/+6dB (default)
1: +2dB/+8dB
Addr
04H
Register Name
Mode Control 1
R/W
Default
D7
PLL3
R/W
0
D6
PLL2
R/W
0
D5
PLL1
R/W
0
D4
PLL0
R/W
0
D3
BCKO
R/W
0
D2
0
RD
0
D1
DIF1
R/W
1
D0
DIF0
R/W
0
DIF1-0: Audio Interface Format (Table 17)
Default: “10” (Left justified)
BCKO: BICK Output Frequency Select at Master Mode (Table 11)
PLL3-0: PLL Reference Clock Select (Table 5)
Default: “0000”(LRCK pin)
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[AK4648]
Addr
05H
Register Name
Mode Control 2
R/W
Default
D7
PS1
R/W
0
D6
PS0
R/W
0
D5
FS3
R/W
0
D4
MSBS
R/W
0
D3
BCKP
R/W
0
D2
FS2
R/W
0
D1
FS1
R/W
0
D0
FS0
R/W
0
FS3-0: Sampling Frequency Select (Table 6 and Table 7) and MCKI Frequency Select (Table 12)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
BCKP: BICK Polarity at DSP Mode (Table 18)
0: SDTO is output by the rising edge (“↑”) of BICK and SDTI is latched by the falling edge (“↓”). (Default)
1: SDTO is output by the falling edge (“↓”) of BICK and SDTI is latched by the rising edge (“↑”).
MSBS: LRCK Polarity at DSP Mode (Table 18)
0: The rising edge (“↑”) of LRCK is half clock of BICK before the channel change. (Default)
1: The rising edge (“↑”) of LRCK is one clock of BICK before the channel change.
PS1-0: MCKO Output Frequency Select (Table 10)
Default: “00” (256fs)
Addr
06H
Register Name
Timer Select
R/W
Default
D7
DVTM
R/W
0
D6
WTM2
R/W
0
D5
ZTM1
R/W
0
D4
ZTM0
R/W
0
D3
WTM1
R/W
0
D2
WTM0
R/W
0
D1
RFST1
R/W
0
D0
RFST0
R/W
0
RFST1-0: ALC First recovery Speed (Table 33)
Default: “00” (4 times)
WTM2-0: ALC Recovery Waiting Period (Table 30)
Default: “000” (128/fs)
ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (Table 29)
Default: “00” (128/fs)
DVTM: Digital Volume Transition Time Setting
0: 1061/fs (default)
1: 256/fs
This is the transition time between DVL/R7-0 bits = 00H and FFH.
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[AK4648]
Addr
07H
Register Name
ALC Mode Control 1
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
ALC
R/W
0
D4
ZELMN
R/W
0
D3
LMAT1
R/W
0
D2
LMAT0
R/W
0
D1
R/W
0
D0
LMTH0
R/W
0
D1
REF1
R/W
0
D0
REF0
R/W
1
RGAIN0
LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 27)
Default: “00”
LMTH1 bit is D6 bit of 0BH.
RGAIN1-0: ALC ALC Recovery GAIN Step (Table 31)
Default: “00”
RGAIN1 bit is D7 bit of 0BH.
LMAT1-0: ALC Limiter ATT Step (Table 28)
Default: “00”
ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation
0: Enable (default)
1: Disable
ALC: ALC Enable
0: ALC Disable (default)
1: ALC Enable
Addr
08H
Register Name
ALC Mode Control 2
R/W
Default
D7
REF7
R/W
1
D6
REF6
R/W
1
D5
REF5
R/W
1
D4
REF4
R/W
0
D3
REF3
R/W
0
D2
REF2
R/W
0
REF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (Table 32)
Default: “E1H” (+30.0dB)
Addr
09H
0CH
Register Name
Lch Input Volume Control
Rch Input Volume Control
R/W
Default
D7
IVL7
IVR7
R/W
1
D6
IVL6
IVR6
R/W
1
D5
IVL5
IVR5
R/W
1
D4
IVL4
IVR4
R/W
0
D3
IVL3
IVR3
R/W
0
D2
IVL2
IVR2
R/W
0
D1
IVL1
IVR1
R/W
0
D0
IVL0
IVR0
R/W
1
D3
DVL3
DVR3
R/W
1
D2
DVL2
DVR2
R/W
0
D1
DVL1
DVR1
R/W
0
D0
DVL0
DVR0
R/W
0
IVL7-0, IVR7-0: Input Volume; 0.375dB step, 242 Level (Table 35)
Default: “E1H” (+30.0dB)
Addr
0AH
0DH
Register Name
Lch Digital Volume Control
Rch Digital Volume Control
R/W
Default
D7
DVL7
DVR7
R/W
0
D6
DVL6
DVR6
R/W
0
D5
DVL5
DVR5
R/W
0
D4
DVL4
DVR4
R/W
1
DVL7-0, DVR7-0: Output Digital Volume (Table 38)
Default: “18H” (0dB)
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[AK4648]
Addr
0BH
Register Name
ALC Mode Control 3
R/W
Default
D7
RGAIN1
R/W
0
D6
LMTH1
R/W
0
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
0
RD
0
D1
VBAT
R/W
0
D0
0
RD
0
D2
FBEQ
R/W
0
D1
DEM1
R/W
0
D0
DEM0
R/W
1
VBAT: HP-Amp Common Voltage (Table 62)
0: 0.5 x HVDD (default)
1: 0.64 x AVDD
LMTH1: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 27)
RGAIN1: ALC Recovery GAIN Step (Table 31)
Addr
0EH
Register Name
Mode Control 3
R/W
Default
D7
0
RD
0
D6
LOOP
R/W
0
D5
SMUTE
R/W
0
D4
DVOLC
R/W
1
D3
0
RD
0
DEM1-0: De-emphasis Frequency Select (Table 36)
Default: “01” (OFF)
FBEQ: 5-Band Equalizer Enable
0: Disable (default)
1: Enable
DVOLC: Output Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When DVOLC bit = “1”, DVL7-0 bits control both Lch and Rch volume level, while register values of
DVL7-0 bits are not written to DVR7-0 bits. When DVOLC bit = “0”, DVL7-0 bits control Lch level and
DVR7-0 bits control Rch level, respectively.
SMUTE: Soft Mute Control
0: Normal Operation (default)
1: DAC outputs soft-muted
LOOP: Digital Loopback Mode
0: SDTI → DAC (default)
1: SDTO → DAC
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[AK4648]
Addr
0FH
Register Name
Mode Control 4
R/W
Default
D7
HPG3
R/W
1
D6
D5
D4
HPG2
HPG1
HPG0
R/W
0
R/W
1
R/W
1
D3
IVOLC
R/W
1
D2
HPM
R/W
0
D1
MINH
R/W
0
D0
DACH
R/W
0
DACH: Switch Control from DAC to Headphone-Amp
0: OFF (default)
1: ON
MINH: Switch Control from MIN pin to Headphone-Amp
0: OFF (default)
1: ON
HPM: Headphone-Amp Mono Output Select
0: Stereo (default)
1: Mono
When the HPM bit = “1”, DAC output signal is output to Lch and Rch of the Headphone-Amp as (L+R)/2.
IVOLC: Input Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0
bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits
control Rch level, respectively.
HPG3-0: Headphone-Amp Volume Control
Default: 0dB (Table 58)
Addr
10H
Register Name
Power Management 3
R/W
Default
D7
INR1
R/W
0
D6
INL1
R/W
0
D5
0
RD
0
D4
MDIF2
R/W
0
D3
MDIF1
R/W
0
D2
INR0
R/W
0
D1
INL0
R/W
0
D0
PMADR
R/W
0
PMADR: MIC-Amp Lch and ADC Rch Power Management
0: Power-down (default)
1: Power-up
INL1-0: ADC Lch Input Source Select (Table 20)
Default: 00 (LIN1 pin)
INR1-0: ADC Rch Input Source Select (Table 20)
Default: 00 (RIN1 pin)
MDIF1: Single-ended / Full-differential Input Select 1
0: Single-ended input (LIN1/RIN1 pins: Default)
1: Full-differential input (IN1+/IN1− pins)
MDIF1 bit selects the input type of pins D7 and F5.
MDIF2: Single-ended / Full-differential Input Select 2
0: Single-ended input (LIN2/RIN2 pins: Default)
1: Full-differential input (IN2+/IN2− pins)
MDIF2 bit selects the input type of pins C5 and B6.
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[AK4648]
Addr
11H
Register Name
Digital Filter Select
R/W
Default
D7
GN1
R/W
0
D6
GN0
R/W
0
D5
0
RD
0
D4
FIL1
R/W
0
D3
EQ
R/W
0
D2
FIL3
R/W
0
D1
0
RD
0
D0
0
RD
0
GN1-0: : Gain Select at GAIN block (Table 25)
Default: “00” (0dB)
FIL3: FIL3 (Stereo Separation Emphasis Filter) Coefficient Setting Enable
0: Disable (default)
1: Enable
When FIL3 bit is “1”, the settings of F3A13-0 and F3B13-0 bits are enabled. When FIL3 bit is “0”, FIL3 block
is OFF (MUTE).
EQ: EQ (Gain Compensation Filter) Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ bit is “1”, the settings of EQA15-0, EQB13-0 and EQC15-0 bits are enabled. When EQ bit is “0”,
EQ block is through (0dB).
FIL1: FIL1 (Wind-noise Reduction Filter) Coefficient Setting Enable
0: Disable (default)
1: Enable
When FIL1 bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When FIL1 bit is “0”, FIL1 block
is through (0dB).
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[AK4648]
Addr
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Register Name
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
R/W
Default
D7
F3A7
F3AS
F3B7
0
EQA7
EQA15
EQB7
0
EQC7
EQC15
F1A7
F1AS
F1B7
0
R/W
0
D6
F3A6
0
F3B6
0
EQA6
EQA14
EQB6
0
EQC6
EQC14
F1A6
0
F1B6
0
R/W
0
D5
F3A5
F3A13
F3B5
F3B13
EQA5
EQA13
EQB5
EQB13
EQC5
EQC13
F1A5
F1A13
F1B5
F1B13
R/W
0
D4
F3A4
F3A12
F3B4
F3B12
EQA4
EQA12
EQB4
EQB12
EQC4
EQC12
F1A4
F1A12
F1B4
F1B12
R/W
0
D3
F3A3
F3A11
F3B3
F3B11
EQA3
EQA11
EQB3
EQB11
EQC3
EQC11
F1A3
F1A11
F1B3
F1B11
R/W
0
D2
F3A2
F3A10
F3B2
F3B10
EQA2
EQA10
EQB2
EQB10
EQC2
EQC10
F1A2
F1A10
F1B2
F1B10
R/W
0
D1
F3A1
F3A9
F3B1
F3B9
EQA1
EQA9
EQB1
EQB9
EQC1
EQC9
F1A1
F1A9
F1B1
F1B9
R/W
0
D0
F3A0
F3A8
F3B0
F3B8
EQA0
EQA8
EQB0
EQB8
EQC0
EQC8
F1A0
F1A8
F1B0
F1B8
R/W
0
F3A13-0, F3B13-0: FIL3 (Stereo Separation Emphasis Filter) Coefficient (14bit x 2)
Default: “0000H”
F3AS: FIL3 (Stereo Separation Emphasis Filter) Select
0: HPF (default)
1: LPF
EQA15-0, EQB13-0, EQC15-C0: EQ (Gain Compensation Filter) Coefficient (14bit x 2 + 16bit x 1)
Default: “0000H”
F1A13-0, F1B13-B0: FIL1 (Wind-noise Reduction Filter) Coefficient (14bit x 2)
Default: “0000H”
F1AS: FIL1 (Wind-noise Reduction Filter) Select
0: HPF (default)
1: LPF
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[AK4648]
Addr
20H
Register Name
Power Management 4
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
PMAINR4
PMAINL4
PMAINR3
PMAINL3
PMAINR2
PMAINL2
PMMICR
PMMICL
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PMMICL: MIC-Amp Lch Power Management
0: Power down (default)
1: Power up
PMMICR: MIC-Amp Rch Power Management
0: Power down (default)
1: Power up
PMAINL2: LIN2 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINR2: RIN2 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINL3: LIN3 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMMIN or PMAINL3 bit should be set to “1” for playback.
PMAINR3: RIN3 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINL4: LIN4 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINR4: RIN4 Mixing Circuit Power Management
0: Power down (default)
1: Power up
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[AK4648]
Addr
21H
Register Name
Mode Control 5
R/W
Default
D7
0
RD
0
D6
D5
SPKMN MICR3
R/W
R/W
0
0
D4
D3
D2
D1
D0
MICL3
R/W
0
L4DIF
R/W
0
MIX
R/W
0
AIN3
R/W
0
LODIF
R/W
0
LODIF: Lineout Select
0: Single-ended Stereo Line Output (LOUT/ROUT pins) (default)
1: Full-differential Mono Line Output (LOP/LON pins)
AIN3: Analog Mixing Select
0: Mono Input (MIN pin) (default)
1: Stereo Input (LIN3/RIN3 pins): PLL is not available.
MIX: Mono Recording
0: Stereo (default)
1: Mono: (L+R)/2
L4DIF: Line Input Type Select
0: Stereo Single-ended Input: LIN4/RIN4 pins (default)
1: Mono Full-differential Input: IN4+/− pins
MICL3: Switch Control from MIC-Amp Lch to Analog Output
0: LIN3 input signal is selected. (default)
1: MIC-Amp Lch output signal is selected.
MICR3: Switch Control from MIC-Amp Rch to Analog Output
0: RIN3 input signal is selected. (default)
1: MIC-Amp Rch output signal is selected.
SPKMN: Speaker-Amp Output Mode Select (Table 68)
0: Mono SPK Mode or High Power Mono SPK Mode (default)
1: Stereo SPK Mode
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[AK4648]
Addr
22H
Register Name
Lineout Mixing Select
R/W
Default
D7
LOM
R/W
0
D6
LOM3
R/W
0
D5
RINR4
R/W
0
D4
LINL4
R/W
0
D3
RINR3
R/W
0
D2
LINL3
R/W
0
D1
RINR2
R/W
0
D0
LINL2
R/W
0
LINL2: Switch Control from LIN2 pin to Stereo Line Output (without MIC-Amp)
0: OFF (default)
1: ON
RINR2: Switch Control from RIN2 pin to Stereo Line Output (without MIC-Amp)
0: OFF (default)
1: ON
LINL3: Switch Control from LIN3 pin (or MIC-Amp Lch) to Stereo Line Output
0: OFF (default)
1: ON
RINR3: Switch Control from RIN3 pin (or MIC-Amp Rch) to Stereo Line Output
0: OFF (default)
1: ON
LINL4: Switch Control from LIN4 pin to Stereo Line Output (without MIC-Amp)
0: OFF (default)
1: ON
RINR4: Switch Control from RIN4 pin to Stereo Line Output (without MIC-Amp)
0: OFF (default)
1: ON
LOM3: Mono Mixing from MIC-Amp (or LIN3/RIN3) to Stereo Line Output
0: Stereo Mixing (default)
1: Mono Mixing
LOM: Mono Mixing from DAC to Stereo Line Output
0: Stereo Mixing (default)
1: Mono Mixing
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[AK4648]
Addr
23H
Register Name
HP Mixing Select
R/W
Default
D7
0
RD
0
D6
HPM3
R/W
0
D5
RINH4
R/W
0
D4
LINH4
R/W
0
D3
RINH3
R/W
0
D2
LINH3
R/W
0
D1
RINH2
R/W
0
D0
LINH2
R/W
0
LINH2: Switch Control from LIN2 pin to Headphone Output (without MIC-Amp)
0: OFF (default)
1: ON
RINH2: Switch Control from RIN2 pin to Headphone Output (without MIC-Amp)
0: OFF (default)
1: ON
LINH3: Switch Control from LIN3 pin (or MIC-Amp Lch) to Headphone Output
0: OFF (default)
1: ON
RINH3: Switch Control from RIN3 pin (or MIC-Amp Rch) to Headphone Output
0: OFF (default)
1: ON
LINH4: Switch Control from LIN4 pin to Headphone Output (without MIC-Amp)
0: OFF (default)
1: ON
RINH4: Switch Control from RIN4 pin to Headphone Output (without MIC-Amp)
0: OFF (default)
1: ON
HPM3: Mono Mixing from MIC-Amp (or LIN3/RIN3) to Headphone Output
0: Stereo Mixing (default)
1: Mono Mixing
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[AK4648]
Addr
24H
Register Name
SPK Mixing Select
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
RINS4
R/W
0
D4
LINS4
R/W
0
D3
RINS3
R/W
0
D2
LINS3
R/W
0
D1
RINS2
R/W
0
D0
LINS2
R/W
0
LINS2: Switch Control from LIN2 pin to Speaker Output
0: OFF (default)
1: ON
RINS2: Switch Control from RIN2 pin to Speaker Output
0: OFF (default)
1: ON
LINS3: Switch Control from LIN3 pin to Speaker Output
0: OFF (default)
1: ON
RINS3: Switch Control from RIN3 pin to Speaker Output
0: OFF (default)
1: ON
LINS4: Switch Control from LIN4 pin to Speaker Output
0: OFF (default)
1: ON
RINS4: Switch Control from RIN4 pin to Speaker Output
0: OFF (default)
1: ON
Addr
25H
26H
Register Name
D7
D6
D5
EQ Control of 250Hz/100Hz FBEQB3 FBEQB2 FBEQB1
EQ Control of 3.5kHz/1kHz FBEQD3 FBEQD2 FBEQD1
R/W
R/W
R/W
R/W
Default
1
0
0
Addr
27H
Register Name
EQ Control of 10kHz
R/W
Default
D7
0
RD
0
D4
FBEQB0
FBEQD0
R/W
0
D3
D2
D1
FBEQA3 FBEQA2 FBEQA1
FBEQC3 FBEQC2 FBEQC1
R/W
R/W
R/W
1
0
0
D0
FBEQA0
FBEQC0
R/W
0
D0
FBEQE0
R/W
D6
0
D5
0
D4
0
RD
RD
RD
D3
FBEQE3
R/W
0
0
0
1
D2
D1
FBEQE2 FBEQE1
R/W
R/W
0
0
0
Select boost amount of 5-Band Equalizer (Table 37). When FBEQ bit is set to “1”, the 5-Band Equalize function is
enabled.
FBEQA3-0:
FBEQB3-0:
FBEQC3-0:
FBEQD3-0:
FBEQE3-0:
Select the boost level of 100Hz (Default: 0dB)
Select the boost level of 250Hz (Default: 0dB)
Select the boost level of 1kHz (Default: 0dB)
Select the boost level of 3.5kHz (Default: 0dB)
Select the boost level of 10kHz (Default: 0dB)
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[AK4648]
SYSTEM DESIGN
Figure 69 and Figure 70 show the system connection diagram of the AK4648. The evaluation board [AKD4648]
demonstrates the optimum layout, power supply arrangements and measurement results.
Analog Supply
2.6 ∼ 3.6V
10u
Analog
Ground
Digital
Ground
2.2k
2.2k
2.2k
2.2k
10
C
Internal MIC
R
2.2u
External MIC
0.1u
0.1u
Line In
TEST
VCOM
AVDD
LIN1
MPWR
CAD0
NC
μP
Mono In
220
1u
LIN4
RIN2
MIN
VSS1
VCOC
SCL
SDTI
ROUT
LOUT
LIN2
NC
NC
RIN1
LRCK
SPRP
SPRN
RIN4
NC
NC
SDA
BICK
220
10u
1u
VSS2
0.1u
Analog Supply
2.6 ∼ 5.0V
20k
20k
Line out
HPL
DVDD
SDTO
MCKO
CPU
HVDD
SPLP
HVCM
HPR
PDN
TVDD
TVDD
NC
SPLN
VSS2
MUTET
VSS3
MCKI
NC
Stereo Speaker
1u
0.1u
0.1u
Digital
1.6 ∼ 3.6V
Top View
Headphone
(See Figure 51 and Figure 53)
Notes:
- VSS1, VSS2, andVSS3 of the AK4648 should be distributed separately from the ground of external controllers.
- All digital input pins should not be left floating.
- When the AK4648 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC/RIN3 pin is not needed.
- When the AK4648 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC/RIN3 pin is should be
connected as shown in Table 5.
- When the AK4648 is used in master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4648.
- When DVDD is supplied from AVDD via 10Ω resistor, a capacitor should be 0.1μF or less.
Figure 69. Typical Connection Diagram (AIN3 bit = “0”, CAD0 = “0”, MIC Input, Stereo SPK Mode)
MS0625-E-01
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[AK4648]
Analog Supply
2.6 ∼ 3.6V
10u
Analog
Ground
10
Digital
Ground
2.2u
Line In
0.1u
TEST
VCOM
0.1u
AVDD
LIN1
MPWR
CAD0
NC
μP
220
1u
LIN4
RIN2
LIN3
VSS1
RIN3
SCL
SDTI
ROUT
LOUT
LIN2
NC
NC
RIN1
LRCK
SPRP
SPRN
RIN4
NC
NC
SDA
BICK
220
10u
1u
VSS2
0.1u
Analog Supply
2.6 ∼ 5.0V
20k
20k
Line out
HPL
DVDD
SDTO
MCKO
CPU
HVDD
SPLP
HVCM
HPR
PDN
TVDD
TVDD
NC
SPLN
VSS2
MUTET
VSS3
MCKI
NC
0.1u
1u
Mono Speaker
0.1u
Digital
1.6 ∼ 3.6V
Top View
Headphone
(See Figure 51 and Figure 53)
Notes:
- VSS1, VSS2, and VSS3 of the AK4648 should be distributed separately from the ground of external
controllers.
- All digital input pins should not be left floating.
- When AIN3 bit = “1”, PLL is not available.
- When the AK4648 is used in master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4648.
- When DVDD is supplied from AVDD via 10Ω resistor, a capacitor should be 0.1μF or less.
Figure 70. Typical Connection Diagram
(AIN3 bit = “1”: PLL is not available, CAD0 = “0”, Line Input, High Power Mono SPK Mode)
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[AK4648]
1. Grounding and Power Supply Decoupling
The AK4648 requires careful attention to power supply and grounding arrangements. AVDD, DVDD, TVDD and HVDD
are usually supplied from the system’s analog supply. If AVDD, DVDD, TVDD and HVDD are supplied separately, the
power-up sequence is not critical.
PDN pin should be held to “L” upon power-up. PDN pin should be set to “H” after all power supplies are powered-up.
In case that the pop noise should be avoided at speaker output, line output, and headphone output, the AK4648 should be
operated by the following recommended power-up/down sequence.
1) Power-up
- PDN pin should be held to “L” upon power-up. The AK4648 should be reset by bringing PDN pin “L” for 150ns or
more.
- In case that the power supplies are separated in two or more groups, the power supply including TVDD should be
powered ON at first. Regarding the relationship between DVDD and HVDD, the power supply including DVDD
should be powered ON prior to the power supply including HVDD.
2) Power-down
- Each power supplies should be powered OFF after PDN pin is set to “L”.
- In case that the power supplies are separated in two or more groups, the power supply including TVDD should be
powered OFF at last. Regarding the relationship between DVDD and HVDD, the power supply including HVDD
should be powered OFF prior to the power supply including DVDD.
VSS1, VSS2, and VSS3 of the AK4648 should be connected to the analog ground plane. System analog ground and
digital ground should be connected together near to where the supplies are brought onto the printed circuit board.
Decoupling capacitors should be as near to the AK4648 as possible, with the small value ceramic capacitor being the
nearest.
2. Voltage Reference
VCOM is a signal ground of this chip. A 2.2μF electrolytic capacitor in parallel with a 0.1μF ceramic capacitor attached
to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All
signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the
AK4648.
3. Analog Inputs
The Mic, Line and MIN inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp(typ.)
@MGAIN1-0 bits = “01”, 0.03 x AVDD Vpp(typ.) @MGAIN1-0 bits = “10”, 0.015 x AVDD Vpp(typ.) @MGAIN1-0
bits = “11” or 0.6 x AVDD Vpp(typ.) @MGAIN1-0 bits = “00” for the Mic/Line input and 0.6 x AVDD Vpp (typ.) for the
MIN input, centered around the internal common voltage (0.45 x AVDD). Usually the input signal is AC coupled using a
capacitor. The cut-off frequency is fc =1/ (2πRC). The AK4648 can accept input voltages from VSS1 to AVDD.
4. Analog Outputs
The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and
a negative full scale for 8000H(@16bit). The ideal output is VCOM voltage for 0000H(@16bit). Stereo Line Output is
centered at 0.45 x AVDD. Headphone-Amp and Speaker-Amp outputs are centered at HVDD/2.
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[AK4648]
CONTROL SEQUENCE
■ Clock Set up
When ADC or DAC is powered-up, the clocks must be supplied.
1. PLL Master Mode.
Example:
Power Supply
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
(3)
PMVCM bit
(Addr:00H, D6)
(4)
(1) Power Supply & PDN pin = “L” Æ “H”
MCKO bit
(Addr:01H, D1)
PMPLL bit
(2)Addr:01H, Data:08H
Addr:04H, Data:4AH
Addr:05H, Data:27H
(Addr:01H, D0)
(5)
MCKI pin
Input
M/S bit
(3)Addr:00H, Data:40H
(Addr:01H, D3)
40msec(max)
(6)
BICK pin
LRCK pin
Output
(4)Addr:01H, Data:0BH
Output
MCKO, BICK and LRCK output
40msec(max)
(8)
MCKO pin
(7)
Figure 71. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4648.
The AK4648 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid the pop noise at the speaker output, lineout output, and
headphone output.
(2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period.
(3) Power UpVCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered-up before the other block operates.
(4) In case of using MCKO output: MCKO bit = “1”
In case of not using MCKO output: MCKO bit = “0”
(5) PLL lock time is 40ms(max.) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external
source.
(6) The AK4648 starts to output the LRCK and BICK clocks after the PLL becomes stable. Then normal operation
starts.
(7) The invalid frequency is output from MCKO pin during this period if MCKO bit = “1”.
(8) The normal clock is output from MCKO pin after the PLL is locked if MCKO bit = “1”.
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[AK4648]
2. PLL Slave Mode (LRCK or BICK pin)
Example:
Power Supply
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
(3)
PMVCM bit
(Addr:00H, D6)
PMPLL bit
(2) Addr:04H, Data:32H
Addr:05H, Data:27H
(Addr:01H, D0)
LRCK pin
BICK pin
Input
(3) Addr:00H, Data:40H
(4)
Internal Clock
(5)
(4) Addr:01H, Data:01H
Figure 72. Clock Set Up Sequence (2)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4648.
The AK4648 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid the pop noise at the speaker output, lineout output, and
headphone output.
(2) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (LRCK or BICK pin) is
supplied. PLL lock time is 160ms(max.) when LRCK is a PLL reference clock. And PLL lock time is
2ms(max.) when BICK is a PLL reference clock.
(5) Normal operation stats after that the PLL is locked.
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3. PLL Slave Mode (MCKI pin)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(3)
(2)Addr:04H, Data:4AH
Addr:05H, Data:27H
PMVCM bit
(Addr:00H, D6)
(4)
MCKO bit
(Addr:01H, D1)
(3)Addr:00H, Data:40H
PMPLL bit
(Addr:01H, D0)
(5)
MCKI pin
(4)Addr:01H, Data:03H
Input
40msec(max)
(6)
MCKO pin
MCKO output start
Output
(7)
(8)
BICK pin
LRCK pin
Input
BICK and LRCK input start
Figure 73. Clock Set Up Sequence (3)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4648.
The AK4648 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid the pop noise at the speaker output, lineout output, and
headphone output.
(2) DIF1-0, PLL3-0 and FS3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) Enable MCKO output: MCKO bit = “1”
(5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied.
PLL lock time is 40ms(max.).
(6) The normal clock is output from MCKO during this period.
(7) The invalid frequency is output from MCKO after PLL is locked.
(8) BICK and LRCK clocks should be synchronized with MCKO clock.
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[AK4648]
4. EXT Slave Mode
Example:
Audio I/F Format: MSB justified (ADC and DAC)
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(2) Addr:04H, Data:02H
Addr:05H, Data:00H
(3)
PMVCM bit
(Addr:00H, D6)
(4)
MCKI pin
Input
(3) Addr:00H, Data:40H
(4)
LRCK pin
BICK pin
Input
MCKI, BICK and LRCK input
Figure 74. Clock Set Up Sequence (4)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4648.
The AK4648 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid the pop noise at the speaker output, lineout output, and
headphone output.
(2) DIF1-0 and FS1-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) Normal operation starts after the MCKI, LRCK and BICK are supplied.
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5. EXT Master Mode
Example:
Audio I/F Format: MSB justified (ADC and DAC)
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
(1) Power Supply & PDN pin = “L” Æ “H”
Power Supply
(1)
PDN pin
(2) MCKI input
(4)
PMVCM bit
(Addr:00H, D6)
(3) Addr:04H, Data:02H
Addr:05H, Data:00H
Addr:01H, Data:08H
(2)
MCKI pin
Input
(3)
M/S bit
BICK and LRCK output
(Addr:01H, D3)
LRCK pin
BICK pin
Output
(4) Addr:00H, Data:40H
Figure 75. Clock Set Up Sequence (5)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4648.
The AK4648 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid the pop noise at the speaker output, lineout output, and
headphone output.
(2) MCKI should be input.
(3) After DIF1-0 and FS1-0 bits are set, M/S bit should be set to “1”. Then LRCK and BICK are output.
(4) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
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[AK4648]
■ MIC Input Recording (Stereo)
Example:
FS3-0 bits
(Addr:05H, D5&D2-0)
0,000
PLL Master Mode
Audio I/F Format:MSB justified (ADC & DAC)
Sampling Frequency:44.1kHz
Pre MIC AMP:+20dB
MIC Power On
ALC setting:Refer to Table 34
ALC bit=“1”
1,111
(1)
MIC Control
(Addr:02H, D2-0)
ALC Control 1
(Addr:06H)
ALC Control 2
(Addr:08H)
(1) Addr:05H, Data:27H
001
101
(2) Addr:02H, Data:05H
(2)
00H
3CH
(3) Addr:06H, Data:3CH
E1H
(4) Addr:08H, Data:E1H
(3)
E1H
(4)
(5) Addr:0BH, Data:00H
ALC Control 3
(Addr:0BH)
00H
00H
(6) Addr:07H, Data:21H
(5)
ALC Control 4
(Addr:07H)
07H
21H
01H
(6)
ALC State
(9)
ALC Disable
ALC Enable
ALC Disable
(7) Addr:00H, Data:41H
Addr:10H, Data:01H
Recording
PMADL/R bits
(Addr:00H&10H, D0)
1059 / fs
(8)
(7)
ADC Internal
State
Power Down
(8) Addr:00H, Data:40H
Addr:10H, Data:00H
Initialize Normal State Power Down
(9) Addr:07H, Data:01H
Figure 76. MIC Input Recording Sequence
<Example>
This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to
“Figure 35. ”.
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bit). When the AK4648 is PLL mode, MIC and ADC should be powered-up
in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up MIC input (Addr: 02H)
(3) Set up Timer Select for ALC (Addr: 06H)
(4) Set up REF value for ALC (Addr: 08H)
(5) Set up LMTH1 and RGAIN1 bits (Addr: 0BH)
(6) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H)
(7) Power Up MIC and ADC: PMADL = PMADR bits = “0” → “1”
The initialization cycle time of ADC is [email protected]=44.1kHz.
After the ALC bit is set to “1” and MIC&ADC block is powered-up, the ALC operation starts from IVOL
default value (+30dB).
The time of offset voltage going to “0” after the ADC initialization cycle depends on both the time of analog
input pin going to the common voltage and the time constant of the offset cancel digital HPF. This time can be
shorter by using the following sequence:
At first, PMVCM and PMMP bits should set to “1”. Then, the ADC should be powered-up. The wait time to
power-up the ADC should be longer than 4 times of the time constant that is determined by the AC coupling
capacitor at analog input pin and the internal input resistance 60k(typ.).
(8) Power Down MIC and ADC: PMADL = PMADR bits = “1” → “0”
When the registers for the ALC operation are not changed, ALC bit may be keeping “1”. The ALC operation is
disabled because the MIC&ADC block is powered-down. If the registers for the ALC operation are also changed
when the sampling frequency is changed, it should be done after the AK4648 goes to the manual mode (ALC bit
= “0”) or MIC&ADC block is powered-down (PMADL=PMADR bits = “0”). IVOL gain is not reset when
PMADL=PMADR bits = “0”, and then IVOL operation starts from the setting value when PMADL or PMADR
bit is changed to “1”. ALC Disable: ALC bit = “1” → “0”
(9) ALC Disable: ALC bit = “1” → “0”
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[AK4648]
■ Speaker-amp Output
FS3-0 bits
(Addr:05H, D5&D2-0)
X,XXX
1,111
(1)
(14)
DACS bit
(Addr:02H, D5)
(2)
SPKG2-0 bits
(Addr:03H, D4-3, D1)
ALC Control 1
(Addr:06H)
ALC Control 2
(Addr:08H)
ALC Control 3
(Addr:0BH)
000
Example:
001
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: 0dB
ALC: Enable, Stereo SPKMode
(3)
XXH
3CH
(4)
(1) Addr:05H, Data:27H
XXH
C1H
(2) Addr:02H, Data:20H
(5)
XXH
00H
(3) Addr:03H, Data:08H
(6)
ALC bit
(Addr:07H, D5)
0
(4) Addr:06H, Data:3CH
X
(7)
(5) Addr:08H, Data:E1H
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
E1H
91H
(6) Addr:0BH, Data:00H
(8)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
18H
XXH
(7) Addr:07H, Data:20H
(9)
SPKMN bit
(Addr:21H, D6)
0
X
(8) Addr:09H & 0CH, Data:91H
(10)
(15)
PMDAC bit
(9) Addr:0AH & 0DH, Data:28H
(Addr:00H, D2)
(10) Addr:21H, Data:40H
PMMIN bit
(Addr:00H, D5)
(11)
(11) Addr:00H, Data:F4H
PMSPL/R bits
(Addr:00H, D7,D4)
(12) Addr:02H, Data:A0H
(12)
SPPSN bit
(Addr:02H, D7)
Playback
(13)
SPLP pin
SPRP pin
SPLN pin
SPRN pin
Hi-Z
Hi-Z
Normal Output
Hi-Z
HVDD/2 Normal Output HVDD/2
(13) Addr:02H, Data:20H
Hi-Z
(14) Addr:02H, Data:00H
(15) Addr:00H, Data:40H
Figure 77. Speaker-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4648 is PLL mode, DAC and Speaker-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC Æ SPK-Amp”: DACS bit = “0” Æ “1”
(3) SPK-Amp gain setting: SPKG2-0 bits = “000” Æ “001”
(4) Set up Timer Select for ALC (Addr: 06H)
(5) Set up REF value for ALC (Addr: 08H)
(6) Set up LMTH1 and RGAIN1 bits (Addr: 0BH)
(7) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H)
When PMADL or PMADR bit is “1”, ALC for DAC path is disabled.
(8) Set up the input digital volume (Addr: 09H and 0CH)
When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).
(9) Set up the output digital volume (Addr: 0AH and 0DH).
When DVOLC bit is “1” (default), DVL7-0 bits (Addr=0AH) set the volume of both channels. After DAC is
powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft
transition.
(10) Set up Speaker Output Mode: SPKMN bit: “0” Æ “1” (Stereo SPK Mode)
SPKMN bit should be set to “0” in Mono SPK Mode or High Power Mono SPK Mode.
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(11) Power Up of DAC, MIN-Amp and Speaker-Amp:
a. Mono SPK Mode (When Lch Speaker-Amp, SPLP/SPLN pins are used.): PMDAC = PMMIN = PMSPL
bits = “0” → “1”
b. Stereo SPK Mode or High Power Mono SPK Mode: PMDAC = PMMIN = PMSPL = PMSPR bits = “0”
→ “1”
The DAC enters an initialization cycle when the PMDAC bit is changed from “0” to “1” at PMADL and
PMADR bits are “0”. The initialization cycle time is [email protected]=44.1kHz. During the initialization
cycle, the DAC input digital data of both channels are internally forced to a 2's complement, “0”. The DAC
output reflects the digital input data after the initialization cycle is complete. When PMADL or PMADR bit is
“1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable (ALC gain is set by
IVL/R7-0 bits) during an initialization cycle ([email protected]=44.1kHz). After the initialization cycle, ALC
operation starts from the gain set by IVL/R7-0 bits.
(12) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”
The powered-down channel is Hi-Z in Mono SPK Mode.
(13) Enter the power-save-mode of Speaker-Amp : SPPSN bit = “1” → “0”
(14) Disable the path of “DAC Æ SPK-Amp”: DACS bit = “1” Æ “0”
(15) Power Down DAC, MIN-Amp and Speaker-Amp: PMDAC = PMMIN = PMSPL = PMSPR bits = “1” → “0”
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[AK4648]
■ Mono signal output from Speaker-Amp
Example:
Clocks can be stopped.
CLOCK
Stereo SPK Mode
SPKMN bit
0
(Addr:21H, D6)
X
(1) Addr:21H, Data:40H
(1)
PMMIN bit
(Addr:00H, D5)
(2)
(2) Addr:00H, Data:E0H
(6)
PMSPL/R bits
(Addr:00H, D7&D4)
(3) Addr:02H, Data:60H
DACS bit
(Addr:02H, D5)
X
0
(3)
(7)
MINS bit
(Addr:02H, D6)
(4) Addr:02H, Data:E0H
(4)
Mono Signal Output
SPPSN bit
(Addr:02H, D7)
(5)
SPLP pin
SPRP pin
SPLN pin
SPRN pin
Hi-Z
Hi-Z
Normal Output
HVDD/2
Normal Output
(5) Addr:02H, Data:60H
Hi-Z
HVDD/2
Hi-Z
(6) Addr:00H, Data:40H
(7) Addr:02H, Data:00H
Figure 78. “MIN-Amp Æ Speaker-Amp” Output Sequence
<Example>
The clocks can be stopped when only MIN-Amp and Speaker-Amp are operating.
(1) Set up speaker output mode
a. Mono SPK Mode & High Power Mono SPK Mode: SPKMN bit = “0”
b. Stereo SPK Mode: SPKMN bit = “1”
(2) Power Up MIN-Amp and Speaker-Amp:
a. Mono SPK Mode (When Lch Speaker-Amp, SPLP/SPLN pins are used.): PMMIN = PMSPL bits = “0”
→ “1”
b. Stereo SPK Mode or High Power Mono SPK Mode: PMMIN = PMSPL = PMSPR bits = “0” → “1”
(3) Disable the path of “DAC Æ SPK-Amp”: DACS bit = “0”
Enable the path of “MIN Æ SPK-Amp”: MINS bit = “0” → “1”
(4) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”
(5) Enter the power-save-mode of Speaker-Amp: SPPSN bit = “1” → “0”
(6) Power Down MIN-Amp and Speaker-Amp: PMMIN = PMSPK bits = “1” → “0”
(7) Disable the path of “MIN Æ SPK-Amp”: MINS bit = “1” → “0”
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■ Headphone-amp Output
FS3-0 bits
(Addr:05H, D5&D2-0)
HPG3-0 bits
(Addr:0FH, D7-4)
0,000
1,111
(1)
E x a m p le :
1011
P L L M a s te r M o d e
S a m p lin g F r e q u e n c y : 4 4 .1 k H z
D V O L C b it = “ 1 ” ( d e fa u lt)
D ig ita l V o lu m e L e v e l: − 8 d B , H P V o lu m e L e v e l: - 3 d B
E Q : E n a b le
D e -e m p h a s e s re s p o n s e : O F F
S o f t M u te T im e : 2 5 6 /fs , P s e u d o C a p -le s s M o d e
1010
(2)
DACH bit
(13)
(Addr:0FH, D0)
FBEQ bit
(Addr: 0EH, D2)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
( 1 ) A d d r :0 5 H , D a t a :2 7 H
( 2 ) A d d r :0 F H , D a ta A 9 H
0
1
0
(3)
(12)
E1H
91H
( 3 ) A d d r :0 E H , D a t a 1 5 H
( 4 ) A d d r :0 9 H & 0 C H , D a ta 9 1 H
(4)
( 5 ) A d d r :0 A H & 0 D H , D a ta 2 8 H
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
18H
28H
( 6 ) A d d r :0 0 H , D a t a 6 4 H
(5)
PMDAC bit
( 7 ) A d d r :0 1 H , D a t a 3 D H
(Addr:00H, D2)
(6)
(11)
( 8 ) A d d r :0 1 H , D a t a 7 9 H
PMMIN bit
(Addr:00H, D5)
PMHPL/R/C bits
P la y b a c k
(7)
(10)
( 9 ) A d d r :0 1 H , D a t a 3 9 H
(Addr:01H, D5-4&D2)
( 1 0 ) A d d r :0 1 H , D a ta 0 9 H
HPMTN bit
(8)
(9)
(Addr:01H, D6)
HPL/R pins,
HVCM pin
( 1 1 ) A d d r :0 0 H , D a ta 4 0 H
( 1 2 ) A d d r :0 E H , D a ta 1 1 H
Normal Output
( 1 3 ) A d d r :0 F H , D a ta A 8 H
Figure 79. Headphone-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4648 is PLL mode, DAC and Speaker-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC Æ HP-Amp”: DACH bit = “0” → “1”
Set up analog volume for HP-Amp (Addr: 0F, HPG3-0 bits)
(3) Enable 5-band Equalizer. (Boost amount is selected by Addr=25H-27H.): FBEQ bit = “0” Æ “1”
(4) Set up input volume (Addr: 09H and 0CH)
When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).
(5) Set up the output digital volume (Addr: 0AH and 0DH)
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(6) Power up DAC and MIN-Amp: PMDAC = PMMIN bits = “0” → “1”
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL
and PMADR bits are “0”. The initialization cycle time is [email protected]=44.1kHz. During the
initialization cycle, the DAC input digital data of both channels are internally forced to a 2's complement, “0”.
The DAC output reflects the digital input data after the initialization cycle is complete. When PMADL or
PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable
(ALC gain is set by IVL/R7-0 bits) during an initialization cycle ([email protected]=44.1kHz). After the
initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits.
(7) Power up headphone-amp:
a. Pseudo Cap-less Mode: PMHPL = PMHPR = PMHPC bits = “0” → “1”
b. Single-ended Mode: PMHPL=PMHPR bits = “0” Æ “1”
Output voltages of headphone-amp are still VSS2.
(8) Rise up the common voltage of headphone-amp: HPMTN bit = “0” → “1”
The rise time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V
and the capacitor value is 1.0μF±30%, the time constant (0.8 x HVDD/2) is τr = 120ms(typ.), 210ms(max.).
In Single-ended Mode, HVCM pin still outputs VSS2.
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(9) Fall down the common voltage of headphone-amp: HPMTN bit = “1” → “0”
The fall time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V
and the capacitor value is 1.0μF±30%, the time constant is τ f = 260ms(max.).
If the power supply is powered-off or headphone-Amp is powered-down before the common voltage goes to
VSS2, the pop noise occurs. It takes twice of τf that the common voltage goes to VSS2.
(10) Power down headphone-amp: PMHPL = PMHPR bits = “1” → “0”
(11) Power down DAC and MIN-Amp: PMDAC = PMMIN bits = “1” → “0”
(12) Disable 5-band Equalizer: FBEQ bit = “1” Æ “0”
(13) Disable the path of “DAC → HP-Amp”: DACH bit = “1” → “0”
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[AK4648]
■ Stereo Line Output
Example:
FS3-0 bits
(Addr:05H, D5&D2-0)
0,000
PLL, Master Mode
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: −8dB
LOVL=MINL bits = “0”
1,111
(1)
(1) Addr:05H, Data:27H
(10)
DACL bit
(2)
(2) Addr:02H, Data:10H
(Addr:02H, D4)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
E1H
(3) Addr:09H&0CH, Data:91H
91H
(3)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
(4) Addr:0AH&0DH, Data:28H
18H
28H
(5) Addr:03H, Data:40H
(4)
LOPS bit
(6) Addr:00H, Data:6CH
(Addr:03H, D6)
(7)
(5)
(8)
(11)
PMDAC bit
(Addr:00H, D2)
Playback
PMMIN bit
(8) Addr:03H, Data:40H
(Addr:00H, D5)
(6)
(9)
(9) Addr:00H, Data:40H
PMLO bit
(Addr:00H, D3)
(7) Addr:03H, Data:00H
>300 ms
(10) Addr:02H, Data:00H
LOUT pin
ROUT pin
>300 ms
Normal Output
(11) Addr:03H, Data:00H
Figure 80. Stereo Lineout Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up the sampling frequency (FS3-0 bits). When the AK4648 is PLL mode, DAC and Stereo Line-Amp
should be powered-up in consideration of PLL lock time after the sampling frequency is changed.
(2) Set up the path of “DAC Æ Stereo Line Amp”: DACL bit = “0” Æ “1”
(3) Set up the input digital volume (Addr: 09H and 0CH)
When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).
(4) Set up the output digital volume (Addr: 0AH and 0DH)
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(5) Enter power-save mode of Stereo Line Amp: LOPS bit = “0” Æ “1”
(6) Power-up DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMMIN = PMLO bits = “0” → “1”
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL
and PMADR bits are “0”. The initialization cycle time is [email protected]=44.1kHz. During the
initialization cycle, the DAC input digital data of both channels are internally forced to a 2's complement, “0”.
The DAC output reflects the digital input data after the initialization cycle is complete. When PMADL or
PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable
(ALC gain is set by IVL/R7-0 bits) during an initialization cycle ([email protected]=44.1kHz). After the
initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits.
LOUT and ROUT pins rise up to VCOM voltage after PMLO bit is changed to “1”. Rise time is 300ms(max.)
at C=1μF and AVDD=3.3V.
(7) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0”
LOPS bit should be set to “0” after LOUT and ROUT pins rise up. Stereo Line-Amp goes to normal operation
by setting LOPS bit to “0”.
(8) Enter power-save mode of Stereo Line-Amp: LOPS bit: “0” Æ “1”
(9) Power-down DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMMIN = PMLO bits = “1” → “0”
LOUT and ROUT pins fall down to VSS1. Fall time is 300ms(max.) at C=1μF and AVDD=3.3V.
(10) Disable the path of “DAC Æ Stereo Line-Amp”: DACL bit = “1” Æ “0”
(11) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0”
LOPS bit should be set to “0” after LOUT and ROUT pins fall down.
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■ Stop of Clock
Master clock can be stopped when ADC and DAC are not used.
1. PLL Master Mode
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(Addr:01H, D0)
(2)
MCKO bit
"1" or "0"
(1) (2) Addr:01H, Data:08H
(Addr:01H, D1)
(3)
External MCKI
Input
(3) Stop an external MCKI
Figure 81. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop an external master clock.
2. PLL Slave Mode (LRCK or BICK pin)
Example
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(Addr:01H, D0)
(2)
External BICK
Input
(1) Addr:01H, Data:00H
(2)
External LRCK
Input
(2) Stop the external clocks
Figure 82. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and LRCK clocks
3. PLL Slave (MCKI pin)
Example
(1)
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: MCKI
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
PMPLL bit
(Addr:01H, D0)
(1)
MCKO bit
(1) Addr:01H, Data:00H
(Addr:01H, D1)
(2)
External MCKI
Input
(2) Stop the external clocks
Figure 83. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
Stop MCKO output: MCKO bit = “1” → “0”
(2) Stop the external master clock.
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4. EXT Slave Mode
(1)
External MCKI
Input
Example
(1)
External BICK
Input
External LRCK
Input
Audio I/F Format: MSB justified (ADC & DAC)
Input MCKI frequency: 1024fs
Sampling Frequency: 44.1kHz
(1)
(1) Stop the external clocks
Figure 84. Clock Stopping Sequence (4)
<Example>
(1) Stop the external MCKI, BICK and LRCK clocks.
5. EXT Master Mode
(1)
External MCKI
Input
Example
BICK
Output
"H" or "L"
LRCK
Output
"H" or "L"
Audio I/F Format: MSB justified (ADC & DAC)
Input MCKI frequency: 1024fs
Sampling Frequency: 44.1kHz
(1) Stop the external MCKI
Figure 85. Clock Stopping Sequence (5)
<Example>
(1) Stop MCKI clock. BICK and LRCK are fixed to “H” or “L”.
■ Power down
Power supply current can be shut down (typ. 1μA) by stopping clocks and setting PMVCM bit = “0” after all blocks
except for VCOM are powered-down. Power supply current can be also shut down (typ. 1μA) by stopping clocks and
setting PDN pin = “L”. When PDN pin = “L”, the registers are initialized.
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(0.38)
3.76 ± 0.05
0.50
7
6
6
0.50
7
XXXX
5
5
4
4
3
3
2
(0.33)
4648
3.66 ± 0.05
B
PACKAGE
2
1
B
C
Top View
D
E
F
G
G
F
E
D
C
B
φ 0.30 ± 0.05
0.25 ± 0.05
0.60 ± 0.02
1
A
A
A
φ 0.05 M S AB
Bottom View
S
0.08 S
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MARKING
4648
XXXX
1
A
XXXX: Date code (4 digits)
Pin #A1 indication
REVISION HISTORY
Date (YY/MM/DD)
07/05/25
07/06/07
Revision
00
01
Reason
First Edition
Error Correct
Page
Contents
1
Features:
Stereo Spekaer-Amp, Output Power
“1.3W @ 8Ω, HVDD=5V, Stereo SPK & Mono
SPK Mode”
Î “1.3W @ 8Ω, HVDD=5V, Mono SPK
Mode”
“1.0W @ 8Ω, HVDD=4.5V, Mono SPK Mode”
was added.
Speaker-Amp Characteristics:
S/(N+D), Po=1.3W:
“Stereo SPK Mode” was deleted.
15
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IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
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