ASAHI KASEI [AKD4665A-A] AKD4665A-A AK4665A Evaluation board Rev.1 GENERAL DESCRIPTION AKD4665A-A is an evaluation board for the AK4665A, 20bit CODEC with built-in Input PGA and Headphone Amplifier. The AKD4665A-A can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D → D/A). AKD4665A-A also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide AKD4665A-A --- Evaluation board for AK4665A (Cable for connecting with printer port of IBM-AT, compatible PC and control software are packed with this. This control software does not support Windows NT.) FUNCTION • DIT/DIR with optical input/output • RCA connector for an external clock input • 10pin Header for serial control mode HVDD AVDD DVDD TVDD LVC_IN GND 5V 3V Regulator up-I/F MIC-Jack AINL1/ MICIN 10pin Header AINR1 DSP LIN/RIN/MIN AK4665A 10pin Header LOUT ROUT HPL AK4114 HPR HP-Jack Opt In Opt Out Figure 1. AKD4665A-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM082201> 2006/05 -1- ASAHI KASEI [AKD4665A-A] Evaluation Board Manual Operation sequence 1) Set up the power supply lines. 1-1) When AVDD, DVDD, HVDD, TVDD and LVC are supplied from the regulator. (AVDD, DVDD, HVDD, TVDD and LVC_IN jack should be open.). See “Other jumper pins set up (page 5)”. <default> [REG] (red ) [HVDD] (orange) [AVDD] (orange) [DVDD] (orange) [TVDD] (blue) [LVC_IN] (blue) [VD_IN] (orenge) [AGND] (black) [DGND] (black) = 5V = open = open = open = open = open = 2.7 ∼ 3.6V = 0V = 0V : 3V is supplied to HVDD of AK4665A from regulator. : 3V is supplied to AVDD of AK4665A from regulator. : 3V is supplied to DVDD of AK4665A from regulator. : 3V is supplied to TVDD of AK4665A from regulator. : 3V is supplied to logic block of LVC from regulator. : for other logic (typ. 3V) : for analog ground : for logic ground 1-2) When AVDD, DVDD, HVDD, TVDD and LVC are not supplied from the regulator. (AVDD, DVDD, HVDD, TVDD and LVC jack should be junction.) See “Other jumper pins set up (page 5)”. [REG] (red) [HVDD] (orange) [AVDD] (orange) [DVDD] (orange) [TVDD] (blue) [LVC_IN] (blue) [VD_IN] (orenge) [AGND] (black) [DGND] (black) = “REG” jack and JP2 should be open. = 2.6 ∼ 3.6V : for HVDD of AK4665A (typ. 3V) = 2.6 ∼ 3.6V : for AVDD of AK4665A (typ. 3V) = 2.6 ∼ 3.6V : for DVDD of AK4665A (typ. 3V) = 1.6 ∼ 3.6V : for TVDD of AK4665A (typ. 3V) = 1.65 ∼ 5.5V : for logic block of LVC (typ. 3V) = 2.7 ∼ 3.6V : for other logic (typ. 3V) = 0V : for analog ground = 0V : for logic ground Each supply line should be distributed from the power supply unit. AVDD and DVDD each must be same voltage level, and TVDD and LVC_IN each too. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK4665A and AK4114 should be reset once bringing SW1, 2 “L” upon power-up. Evaluation mode In case of AK4665A evaluation using AK4114, same audio interface format should be set for both AK4665A and AK4114. About AK4665A’s audio interface format, refer to datasheet of AK4665A. About AK4114’s audio interface format, refer to Table 2 in this manual. Applicable Evaluation Mode (1) Evaluation of loop-back mode (Default) (2) Evaluation of using DIR of AK4114 (opt-connector) (3) Evaluation of using DIT of AK4114 (opt-connector) (4) All interface signals including master clock are fed externally. <KM082201> 2006/05 -2- ASAHI KASEI [AKD4665A-A] (1) Evaluation of loop-back mode (Default) Nothing should be connected to PORT3. PORT1(TORX141), or X’tal mode of the AK4114 is used. When an external clock through an RCA connector (J10: MCLK) is supplied, short JP12 (XTI). JP13 (EXT) and R28 should be properly selected in order to much the output impedance of the clock generator. Then X’tal(X1) and capacitance (C35,C36) should be removed. JP12 JP19 JP14 XTI DIR_MCLK DIR_BICK JP15 BICK_INV THR JP16 DIR_LRCK INV JP18 SDTI ADC JP17 SDTO DIR (2) Evaluation of using DIR of AK4114 (opt-connector) PORT1(TORX141), is used. DIR generates MCLK, BICK, LRCK and SDTI from the received data through optical connector (TORX141). Used for the evaluation using CD test disk. Nothing should be connected to PORT3. JP12 JP19 JP14 XTI DIR_MCLK DIR_BICK JP15 BICK_INV THR JP16 DIR_LRCK INV JP18 SDTI ADC JP17 SDTO DIR (3) Evaluation of using DIT of AK4114 (opt-connector) PORT1(TORX141) and PORT2(TOTX141), or X’tal mode of the AK4114 and PORT2(TOTX141) is used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX141). It is possible to connect AKM’s D/A converter evaluation boards on the digital-amplifier which equips DIR input. Nothing should be connected to PORT3. When an external clock through a RCA connector (J10: MCLK) is supplied, short JP12 (XTI). JP13 (EXT) and R28 should be properly selected in order to much the output impedance of the clock generator. Then X’tal(X1) and capacitance (C35,C36) should be removed. JP12 JP19 JP14 XTI DIR_MCLK DIR_BICK JP15 BICK_INV THR JP16 DIR_LRCK INV JP18 SDTI ADC JP17 SDTO DIR (4) All interface signals including master clock are fed externally. When all interface signals through PORT3 are supplied, the jumper pins should be set to the following. JP12 JP19 JP14 XTI DIR_MCLK DIR_BICK JP15 BICK_INV THR INV <KM082201> JP16 DIR_LRCK JP18 SDTI ADC JP17 SDTO DIR 2006/05 -3- ASAHI KASEI [AKD4665A-A] DIP Switch set up [SW2] (MODE) : Mode Setting of AK4114 ON is “H”, OFF is “L”. No. 1 2 3 Name DIF0 DIF1 DIF2 4 CM0 5 OCKS1 ON (“H”) DIF2 0 0 1 1 DIF1 0 1 0 0 DIF0 0 0 0 1 SW2-#4 (CM0) OFF ON OFF (“L”) AK4114 Audio Format Setting See Table 2 Clock Operation Mode select See Table 3 Master Clock Frequency Select OFF See Table 4 Table 1. Mode Setting for AK4114 OFF Setting for AK4114 Audio Interface Format Mode 0 2 4 5 Default OFF OFF ON Register setting for AK4665A Audio Interface Format DAUX SDTO DIF1 24bit, Left justified 16bit, Right justified 0 24bit, Left justified 20bit, Right justified 0 24bit, Left justified 24bit, Left justified 1 24bit, I2S 24bit, I2S 1 Table 2. Setting for AK4114 Audio Interface Format Clock Mode Clock source SDTO PLL Mode PORT1 (TORX141) RX (Optical) X’tal Mode X1 (X'tal) or J10 (RCA) DAUX (ADC) Table 3. Clock Operation Mode select SW2-#5 (OCKS1) OFF ON PLL Mode X’tal Mode 256fs 256fs 512fs 512fs Table 4. Master Clock Frequency Select <KM082201> DIF0 0 1 0 1 Default Default Default 2006/05 -4- ASAHI KASEI [AKD4665A-A] Other jumper pins set up 1. JP1 (GND) OPEN SHORT : Analog ground and Digital ground : Separated. : Common. (The connector “DGND” can be open.) <Default> 2. JP3 (REG) OPEN : HVDD of the AK4665A : HVDD is supplied from “HVDD ” jack. : HVDD is supplied from the regulator (“HVDD” jack should be open). < Default > SHORT 3. JP3 (AVDD_SEL) : AVDD of the AK4665A OPEN : AVDD is supplied from “AVDD ” jack. SHORT : AVDD is supplied from “HVDD” (“AVDD” jack should be open). < Default > 4. JP4 (DVDD_SEL) : DVDD of the AK4665A OPEN : DVDD is supplied from “DVDD ” jack. < Default > SHORT : DVDD is supplied from “HVDD” (“DVDD” jack should be open). 5. JP6 (TVDD_SEL), JP7 (LVC_SEL): JP6 JP7 TVDD is supplied from Logic block of LVC is supplied from Note OPEN OPEN “TVDD” jack “LVC_IN” jack - OPEN TVDD “TVDD” jack “TVDD” jack OPEN VD “TVDD” jack “VD_IN” jack SHORT OPEN “DVDD” “LVC_IN” jack SHORT TVDD SHORT VD “LVC_IN” jack should be open. “LVC_IN” jack should be open. “TVDD” jack should be open. “TVDD” and “LVC_IN” jack <Default> should be open. TVDD” and “LVC_IN” jack “DVDD” “VD” jack should be open. Table 5. JP6 (TVDD_SEL), JP7 (LVC_SEL) select “DVDD” “TVDD” 6. JP5 (MPWR) : Connection between MPWR pin and MICIN pin of the AK4665A OPEN : MPWR is not connected to MICIN. SHORT : MPWR is connected to MICIN. < Default > <KM082201> 2006/05 -5- ASAHI KASEI [AKD4665A-A] The function of the toggle SW [SW1] (DIR) : Power control of AK4114. Keep “H” during normal operation. Keep “L” when AK4114 is not used. [SW3] (PDN) : Power control of AK4665A. Keep “H” during normal operation. Indication for LED [LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114. Serial Control The AK4665A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4 (CTRL) with PC by 10 wire flat cable packed with the AKD4665A-A Connect PC 10 wire flat cable 10pin Connector CSN SCL/CCLK SDA/CDTI SDA/(ACK) 10pin Header AKD4665A-A Figure 2. Connect of 10 wire flat cable <KM082201> 2006/05 -6- ASAHI KASEI [AKD4665A-A] Analog Input / Output Circuits (1) Input Circuits a) MIC/AINL1/AINR1 Input Circuit J1 MIC-JACK 6 4 3 JACK JP8 MIC_SEL INT RCA J3 AINL1/MICIN MR-552LS J5 AINR1 MR-552LS C25 1u 1 AINL1 R16 (open) 2 C26 1u 1 AINR1 + 2 3 1 2 + 2 3 1 R17 (open) Figure 3. MIC/AINL1/AINR1 Input Circuit (a-1) Analog signal is input to MICIN pin via J1 (MIC-JACK) connector. JP8 MIC_SEL RCA JACK (a-2) Analog signal is input to MICIN pin via J3 (AINL1/MICIN) connector. JP12 MIC_SEL RCA JACK <KM082201> 2006/05 -7- ASAHI KASEI [AKD4665A-A] b) LIN/RIN/MIN Input Circuit J8 LIN/RIN/MIN 2 3 1 MR-552LS C27 0.047u R21 (open) LIN RIN MIN JP10 LIN LIN/RIN/MIN RIN MIN Figure 4. LIN/RIN/MIN Input Circuit (2) Output Circuits a) LOUT/ROUT Output Circuit LOUT 1 + C23 R12 220 2 4.7u R13 10k 1 + C24 ROUT 2 3 1 MR-552LS R14 220 2 4.7u J2 LOUT R15 10k 2 3 1 J4 ROUT MR-552LS Figure 5. LOUT/ROUT Output Circuit <KM082201> 2006/05 -8- ASAHI KASEI [AKD4665A-A] b) HPL/HPR Output Circuit 2 3 1 R18 16 R19 (short) J6 HPL MR-552LS JP9 HPL HPL J7 HP 6 R20 (short) 4 3 HPR JP11 HPR 2 3 1 R22 16 J9 HPR MR-552LS Figure 6. HPL/HPR Output Circuit (b-1) HPL and HPR pins are outputted from J7 (mini jack). JP11 HPR JP9 HPL (b-2) HPL and HPR pins are outputted from J6 and J9. JP11 HPR JP9 HPL ∗ AKM assumes no responsibility for the trouble when using the above circuit examples. <KM082201> 2006/05 -9- ASAHI KASEI [AKD4665A-A] 2. Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD4665A-A according to previous term. 2. Connect IBM-AT compatible PC with AKD4665A-A by 10-line type flat cable (packed with AKD4665A-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AKD4665A-A Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “akd4665a-a.exe” to set up the control program. 5. Then please evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. 3. Click “Write default” button Explanation of each buttons 1. [Port Reset] : 2. [Write default] : 3. [All Write] : 4. [Function1] : 5. [Function2] : 6. [Function3] : 7. [Function4] : 8. [Function5]: 9. [SAVE] : 10. [OPEN] : 11. [Write] : Set up the USB interface board (AKDUSBIF-A) when using the board. Initialize the register of the AK4665A. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM082201> 2006/05 - 10 - ASAHI KASEI [AKD4665A-A] Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. If you want to write the input data to the AK4665A, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. If you want to write the input data to the AK4665A, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate DATT There are dialogs corresponding to register of 05h, 0Ah, 0Bh and 0Ch. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to the AK4665A by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to the AK4665A, click [OK] button. If not, click [Cancel] button. <KM082201> 2006/05 - 11 - ASAHI KASEI [AKD4665A-A] 4. [SAVE] and [OPEN] 4-1. [SAVE] All of current register setting values displayed on the main window are saved to the file. The extension of file name is “akr”. <Operation flow> (1) Click [SAVE] Button. (2) Set the file name and click [SAVE] Button. The extension of file name is “akr”. 4-2. [OPEN] The register setting values saved by [SAVE] are written to the AK4665A. The file type is the same as [SAVE]. <Operation flow> (1) Click [OPEN] Button. (2) Select the file (*.akr) and Click [OPEN] Button. <KM082201> 2006/05 - 12 - ASAHI KASEI [AKD4665A-A] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [START] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file name is “aks”. Figure 7. Window of [F3] <KM082201> 2006/05 - 13 - ASAHI KASEI [AKD4665A-A] 6. [Function4 Dialog] The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed. When [F4] button is clicked, the window as shown in Figure 8 opens. Figure 8. [F4] window <KM082201> 2006/05 - 14 - ASAHI KASEI [AKD4665A-A] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3]. The sequence file name is displayed as shown in Figure 9. ( In case that the selected sequence file name is “DAC_Stereo_ON.aks”) Figure 9. [F4] window(2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name is “*.ak4”. [OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the change. <KM082201> 2006/05 - 15 - ASAHI KASEI [AKD4665A-A] 7. [Function5 Dialog] The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to buttons and then executed. When [F5] button is clicked, the window as shown in Figure 10 opens. Figure 10. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 11. (In case that the selected file name is “DAC_Output.akr”) (2) Click [WRITE] button, then the register setting is executed. <KM082201> 2006/05 - 16 - ASAHI KASEI [AKD4665A-A] Figure 11. [F5] windows(2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file name is “*.ak5”. [OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded. 7-3. Note (1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change. <KM082201> 2006/05 - 17 - ASAHI KASEI [AKD4665A-A] MEASUREMENT RESULTS [Measurement condition] • Measurement unit • MCLK • BICK • fs • Bit • Power Supply • Measurement Filter • Temperature : Audio Precession System Two Cascade : 11.2896MHz : 64fs : 44.1kHz : 20bit : AVDD = DVDD = HVDD = TVDD = 3.0V : 10Hz ∼ 20kHz : Room Parameter MIC-Amp: (MICIN pin Æ ADC) THD+N (-1dBFS Output) D-Range (-60dB Output, A-weighted) S/N (A-weighted) Result (Lch / Rch) Unit -90.6 / -90.4 93.4 / 93.4 93.4 / 93.4 dB dB dB Parameter Result (Lch / Rch) Analog Input Characteristics: (AINL1/AINR1 pins Æ ADC Æ IVOL), IVOL=0dB, ALC1= OFF THD+N (-1dBFS Output) -91.6 / -91.2 D-Range (-60dB Output, A-weighted) 94.5 / 94.5 S/N (A-weighted) 94.6 / 94.6 Unit Parameter Result (Lch / Rch) Headphone-Amp: (DAC Æ HPL/HPR pins), RL=16Ω, HPG bit = “0”, ATTL7-0=ATTR7-0 bits=0dB THD+N (0dBFS Output) -58.7 / -58.7 D-Range (-60dB Output, A-weighted) 88.4 / 88.2 S/N (A-weighted) 88.5 / 88.2 Unit Parameter Result (Lch / Rch) Stereo Line Output: (DAC Æ LOUT/ROUT pins), ATTL7-0 = ATTR7-0 = ATTS3-0 bits = 0dB THD+N (0dBFS Output) -84.5 / -84.1 D-Range (-60dB Output, A-weighted) 88.7 / 88.4 S/N (A-weighted) 88.8 / 88.5 Unit <KM082201> dB dB dB dB dB dB dB dB dB 2006/05 - 18 - ASAHI KASEI [AKD4665A-A] PLOT DATA 1.ADC (AINL1/AINR1 Æ ADC) PLOT DATA AKM AKD4665 ADC(mic) THD+N vs.Input Level (fs=44.1kHz, fin=1kHz) -60 -62 -64 -66 -68 -70 -72 -74 -76 -78 d B F S -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dBr Figure 12. THD+N vs. Input Level AKM AK4665 ADC(AIN) THD+N vs. Input Frequency (fs=44.1kHz, Input=-1dB) -60 -62.5 -65 -67.5 -70 -72.5 -75 d B F S -77.5 -80 -82.5 -85 -87.5 -90 -92.5 -95 -97.5 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 13. THD+N vs. Input Frequency (Input Level = -1dBFS) <KM082201> 2006/05 - 19 - ASAHI KASEI [AKD4665A-A] AKM AK4665 ADC(AIN) Linearity (fs=44.1kHz, fin=1kHz) +0 -10 -20 -30 -40 d B F S -50 -60 -70 -80 -90 -100 -110 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure 14. Linearity AKM AK4665 ADC(AIN) Frequency Response (fs=44.1kHz, Input=-1dB) +0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 d B F S -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 15. Frequency Response <KM082201> 2006/05 - 20 - ASAHI KASEI [AKD4665A-A] AKM AK4665 ADC(AINL1/AINR1) FFT (fs=44.1kHz, fin=1kHz, Input=-1dB) FFT point=16384, Avg=8 +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 16. FFT Plot (Input level=-1dBFS) AKM AK4665 ADC(AINL1/AINR1) FFT (fs=44.1kHz, fin=1kHz, Input=-60dB) FFT point=16384, Avg=8 +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k Hz Figure 17. FFT Plot (Input level=-60dBFS) <KM082201> 2006/05 - 21 - ASAHI KASEI [AKD4665A-A] AKM AK4665 ADC(AINL1/AINR1) FFT (fs=44.1kHz, Input=no signal) FFT point=16384, Avg=8 +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 18. FFT Plot (no signal input) Figure 19. Crosstalk <KM082201> 2006/05 - 22 - ASAHI KASEI [AKD4665A-A] 2. DAC (DAC Æ LOUT/ROUT) PLOT DATA AKM AK4665 DAC(LINEOUT) THD+N vs.Input Level (fs=44.1kHz, input=0dB) -70 -72 -74 -76 -78 d B r -80 A -82 -84 -86 -88 -90 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 20. THD+N vs. Input Level AKM AK4665 DAC(LINEOUT) THD+N vs.Input Frequency(fs=44.1kHz, input=0dB) -70 -72 -74 -76 -78 d B r -80 A -82 -84 -86 -88 -90 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 21. THD+N vs. Input Frequency (Input Level = 0dBFS) <KM082201> 2006/05 - 23 - ASAHI KASEI [AKD4665A-A] AKM AK4665 DAC(LINEOUT) Linearity (fs=44.1kHz, input=0dB) +0 -10 -20 -30 -40 d B r A -50 -60 -70 -80 -90 -100 -110 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 22. Linearity AKM AKD4665 DAC(LINEOUT) Frequency Response (fs=44.1kHz, Input=0dB) +0.5 +0.4 +0.3 +0.2 +0.1 +0 -0.1 d B r -0.2 -0.3 A -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Hz Figure 23. Frequency Response <KM082201> 2006/05 - 24 - ASAHI KASEI [AKD4665A-A] AKM AK4665 DAC(LINEOUT) FFT (fs=44.1kHz, fin=1kHz, Input=0dB) FFT point=16384, Avg=8 +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 24. FFT Plot (Input level=0dBFS) AKM AK4665 DAC(LINEOUT) FFT (fs=44.1kHz, fin=1kHz, Input=-60dB) FFT point=16384, Avg=8 +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k Hz Figure 25. FFT Plot (Input level=-60dBFS) <KM082201> 2006/05 - 25 - ASAHI KASEI [AKD4665A-A] AKM AK4665 DAC(LINEOUT) FFT (fs=44.1kHz, Input=no data) FFT point=16384, Avg=8 +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 26. FFT Plot (no data input) AKM AK4665 DAC(LINEOUT) Out band noise (fs=44.1kHz, Input=no data) FFT point = 16384, Avg = 8 +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k Hz Figure 27. Out band noise (no data input) <KM082201> 2006/05 - 26 - ASAHI KASEI [AKD4665A-A] Figure 28. Crosstalk <KM082201> 2006/05 - 27 - ASAHI KASEI [AKD4665A-A] 3. DAC (DAC Æ HPL/HPR) PLOT DATA AKM AKD4665 DAC(HP) THD+N vs.Input Level (fs=44.1kHz, fin=1kHz) -50 -52 -54 -56 -58 -60 -62 -64 -66 d B r A -68 -70 -72 -74 -76 -78 -80 -82 -84 -86 -88 -90 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 29. THD+N vs. Input Level AKM AK4665 DAC(HP) Input Frequency (fs=44.1kHz, Input=0dB) -30 -35 -40 -45 -50 -55 d B r -60 A -70 -65 -75 -80 -85 -90 -95 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 30. THD+N vs. Input Frequency (Input Level = 0dBFS) <KM082201> 2006/05 - 28 - ASAHI KASEI [AKD4665A-A] AKM AK4665 DAC(HP) FFT (fs=44.1kHz, fin=1kHz, Input=0dB) FFT point=16384, Avg=8 +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 31. FFT Plot (Input level=0dBFS) AKM AK4665 DAC(HP) FFT (fs=44.1kHz, fin=1kHz, Input=0dB) FFT point=16384, Avg=8 +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k Hz Figure 32. FFT Plot (Input level=-60.0dBFS) <KM082201> 2006/05 - 29 - ASAHI KASEI [AKD4665A-A] AKM AK4665 DAC(HP) FFT (fs=44.1kHz, Input=no data) FFT point=16384, Avg=8 +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 33. FFT Plot (no data input) Figure 34. Crosstalk <KM082201> 2006/05 - 30 - ASAHI KASEI [AKD4665A-A] Revision History Date (YY/MM/DD) 05/12/19 06/05/17 Manual Revision KM082200 KM082201 Board Revision 0 1 Reason First Edition Circuit change Contents A 2Ω resistor was inserted at HVDD line in series. IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <KM082201> 2006/05 - 31 - 1 C4 + T45_BK 1 AGND1 T45_B 1 TVDD1 T45_O 1 DVDD1 T45_O 1 4665_AVDD AVDD1 T45_O E 25 REG 26 27 28 29 PDN CSN/CAD0 CCLK/SCL HVDD1 T45_R HVDD AVDD DVDD LVC_IN1 VD_IN1 DGND1 T45_B T45_BK T45_O TVDD 4665_HVDD C5 4.7u (short) 1 1 2 1 R100 30 CDTI/SDA CN1 32pin_4 2 C6 2.2u + 2 47u 2 AGND E REG1 1 JP2 REG L1 DGND 31 HVDD C1 + 47u 32 C3 0.1u 2 1 OUT C2 0.1u 1 D JP1 GND GND IN C 1 T1 TA48M03F REG E B 1 A LVC_IN VD_IN 2 + 1 5 C L4 25 AVSS 26 3 BICK AINL1 22 4 SDTI AINR1 21 5 SDTO LIN 20 6 TVDD RIN 19 7 DVSS MIN 18 4665A 32pin_1 DVDD LOUT 10 9 CP 8 HVSS C16 0.1u INT 23 C15 0.1u 12 8 + HVDD C14 10u CN2 2.2k 51 1 7 JP5 MPWR 24 R9 6 2 (short) 2 47u + C11 0.22u R11 51 2 C13 1 1 AVDD 23 22 AINL1 21 AINR1 20 LIN 19 RIN 18 MIN 17 LOUT C 17 32pin_3 ROUT SDTO R7 JP6 TVDD_SEL 27 MPWR R10 51 (short) TVDD 28 MCLK 16 4 VREF 2 51 HPR SDTI 29 24 15 3 PDN MICIN HPL BICK CSN LRCK 14 2 D C9 0.1u 1 11 1 + MCLK 2 47u 2 30 51 R8 1 C8 0.1u NVSS L3 1 LRCK JP4 DVDD_SEL C7 0.1u 13 DVDD R5 51 VCOM R6 CN3 C12 31 U1 (short) R4 51 CN + 2 47u 2 R3 51 CDTI C10 1 1 R2 51 R1 10 CCLK JP3 AVDD_SEL 4665_AVDD L2 32 AVDD D B B JP7 TVDD LVC_SEL L5 C21 + 2 (short) 1 2 C20 10u LVC VD 14 15 16 HPL HPR ROUT 13 12 11 10 CN4 9 2 47u 1 1 C18 C19 0.1u 2.2u + LVC_IN C17 2.2u 32pin_2 VD_IN 47u 1 + 2 VD (short) 2 C22 4665_HVDD L6 1 A A Title Size A3 Date: A B C D AKD4665A-A Document Number Rev AK4665A Wednesday, May 17, 2006 Sheet E 1 1 of 4 A B C D E J1 MIC-JACK 6 4 3 JACK JP8 MIC_SEL C23 INT LOUT 1 RCA + E R12 220 R13 10k J3 AINL1/MICIN C25 1u 2 MR-552LS R14 220 J4 ROUT 2 2 3 1 4.7u 1 R15 10k AINL1 + 2 3 1 + C24 1 E 2 3 1 4.7u ROUT J2 LOUT 2 MR-552LS R16 (open) MR-552LS D J5 AINR1 D C26 1u 2 1 J6 HPL AINR1 + 2 3 1 2 3 1 R17 (open) MR-552LS R18 16 R19 (short) MR-552LS JP9 HPL HPL J7 HP 6 R20 (short) C 4 3 HPR J8 LIN/RIN/MIN JP10 2 3 1 R21 (open) MR-552LS C27 0.047u LIN 2 RIN 4 MIN 6 1 3 5 JP11 HPR LIN LIN/RIN/MIN C RIN J9 HPR 2 3 1 MIN R22 16 MR-552LS B B A A Title Size A3 Date: A B C D AKD4665A-A Document Number Rev ANALOG Wednesday, May 17, 2006 Sheet E 1 2 of 4 A B C D E C28 C29 0.1u 0.1u VD 0.1u C31 10u R24 470 2 2 1 VD + TORX141 1 4 A E 3 L C32 0.1u H SW1 DIR 2 C33 0.1u 1 VCC GND OUT D1 HSU119 7 3 2 1 R23 10k VD 14 C30 7 PORT1 74HC14_1 U2B VD 74HC14_1 3 U2A 2 E 14 L7 (short) K 1 VD 1 D R26 1k 14 38 37 VD INT1 R AVDD 40 39 R25 18k VCOM 41 RX0 AVSS 42 43 NC 44 RX1 45 TEST1 46 RX2 10 9 8 7 6 NC 48 U4 SW2 1 2 3 4 5 RX3 DIF0 DIF1 DIF2 CM0 OCKS1 D 47 C34 0.47u U3A IPS0 INT0 36 1 2 LED1 ERF K A VD 74HC04 7 MODE 2 NC OCKS0 35 3 DIF0 OCKS1 34 4 TEST2 CM1 33 5 DIF1 CM0 32 6 NC PDN 31 7 DIF2 XTI 30 8 IPS1 XTO 29 9 P/SN DAUX 28 10 XTL0 MCKO2 27 11 XTL1 BICK 26 DIR_BICK 12 VIN SDTO 25 DIR_SDTI RP1 6 5 4 3 2 1 CM0 OCKS1 OCKS1 47k AK4114 CM0 C C35 5p 1 C X1 11.2896MHz C36 5p JP12 XTI MCLK J10 R27 51 2 2 3 1 DAUX JP13 EXT MR-552LS R28 51 1 + 2 1 C39 10u VD LRCK 24 MCKO1 23 22 DVSS DVDD 21 C37 0.1u C38 0.1u DIR_LRCK + 20 VOUT UOUT 19 COUT 18 BOUT 17 TX1 16 15 14 TVDD 13 TX0 B DVSS B DIR_MCLK 2 C40 10u VD PORT2 A IN VCC GND 3 2 1 A VD C41 0.1u TOTX141 Title Size A3 Date: A B C D AKD4665A-A Document Number Rev DIR/DIT Wednesday, May 17, 2006 Sheet E 1 3 of 4 A B C D E LVC 8 14 1 PDN1 U6A 74LVC07 1 14 VD SDTI1 U6B 7 C42 0.1u E VD 2 SDTI SDTO 74LVC07 2 SW3 PDN 74LVC07 14 14 9 1 3 H U5A 2 DAUX C46 0.1u 7 6 7 5 L RP2 R-PACK8R U2D 74HC14_1 LVC 7 U2C 74HC14_1 VD VD 14 K A D2 HSU119 R30 10k VD 7 VD E R29 1k 1 2 3 4 5 6 7 8 9 4 BICK 3 U6D 74LVC07 U6E 74LVC07 U6F 74LVC07 8 LRCK BICK1 3 7 DIR_BICK 14 2 7 1 14 INV JP15 10 7 VD D 9 THR BICK_INV 10 CCLK/SCL MCLK1 14 11 5 7 14 JP14 DIR_BICK 14 U2E 74HC14_1 VD 74LVC07 6 MCLK D U6C 7 VD BICK1 LRCK1 11 CCLK1/SCL JP16 LRCK1 DIR_LRCK 12 CSN/CAD0 14 VD JP17 C44 14 DIR 3 DIR_SDTI 74HC04 U2F 13 7 14 11 10 7 74LVC07 U8F 12 13 74LVC07 12 74LVC07 3 A A Title Size A3 Date: A U8E 10 13 74HC04 8 7 7 U5F 12 7 74LVC07 4 7 14 U5B 13 9 74LVC07 U3F 12 74HC14_1 7 VD 11 74HC04 U8D 74LVC07 8 7 1k 0.1u 10 7 R39 U5E U3E 14 51 B 74LVC07 7 VD 11 R38 9 74HC04 C43 LVC uP-I/F 8 14 74LVC07 CSN SCL/CCLK SDA/CDTI SDA(ACK) CDTI/SDA 14 10 9 8 7 6 4 6 7 14 PORT4 A1-10PA-2.54DSA 1 2 3 4 5 U3D 9 3 U5D 14 VD U8B 470 470 470 7 R36 R35 R37 5 74LVC07 6 74HC04 CCLK1/SCL 10k 10k 10k U8C 6 7 5 CSN1/CAD0 5 14 B R32 R33 R34 0.1u 14 U3C VD 0.1u U5C 74LVC07 14 SDTI VD C47 4 7 3 LVC C45 U3B DAUX 2 SDTI1 VD 0.1u JP18 1 ADC PDN1 74LVC07 14 VD R31 10k C 1 7 SDTO CSN1/CAD0 U8A 2 PDN DSP MCLK1 13 14 GND GND NC NC SDTO 14 DIR_MCLK 10 9 8 7 6 7 DIR_MCLK PORT3 1 2 3 4 5 14 C MCLK BICK LRCK SDTI VD 7 JP19 14 DIR_LRCK B C D AKD4665A-A Document Number Rev Interface Wednesday, May 17, 2006 Sheet E 1 4 of 4