AKM AKD4682-A

ASAHI KASEI
[AKD4682-A]
AKD4682-A
AK4682 Evaluation Board Rev.0
FEATURE
AKD4682-A is an evaluation board for AK4682, a single chip 24bit CODEC that has two channels of ADC
and four channels of DAC. This board has interfaces with AKM’s evaluation boards for A/D converter and
D/A converter and makes easy to evaluate AK4682. Also this board has the digital audio interface and
then achieves the interface with digital audio systems via RCA connector.
„ Ordering guide
AKD4682-A --- AK4682 Evaluation Board
10 wire flat cable for connection with printer port of PC (IBM-AT compatible machine),
control software for AK4682, driver for control software on Windows 2000/XP are
packed with this.
Control software does not work on Windows NT
Windows 2000/XP needs an installation of driver.
Windows 95/98/ME does not need an installation of driver.
FUNCTION
† On-board clock generators (AK4114 x2)
† Compatible with 2 types of digital audio interface
- RCA (S/PDIF) input/output
- 10pin headers for interfacing with external data source (x2)
† RCA connectors for clock input with external clock source
† 10pin headers for register control
GND +9V
+5V
+3.3V
Regulator
Regulator
EXA
AK4114
(DIR)
LOUT1/ROUT1
RCA IN
PORT A
10pin Header
LOUT2/ROUT2
AK4682
LOUT3/ROUT3
Control Data
10pin Header
PORT B
10pin Header
AK4114
(DIT)
LINA/RINA
RCA OUT
EXB
(Note) Each AK4114 integrates DIR, DIT and X’tal oscillator.
Figure 1. AKD4682-A Block Diagram
(* Circuit diagram and PCB layout are attached at the end of this manual.)
<KM086400>
2007/02
-1-
ASAHI KASEI
[AKD4682-A]
EVALUATION BOARD MANUAL
„ Operating sequence
1. Set up power supply lines.
Name of
Jack
Color
of Jack
Voltage
Used for
Comment and attention
AVDD1
Orange
+4.5∼+5.5V
AVDD1 and DVDD1
of AK4682
AVDD2
Orange
+4.5∼+5.5V
AVDD2 and DVDD2
of AK4682
D3.3V
Orange
+3.0∼+3.6V
Power supply of logic
TVDD
(4682)
Orange
+2.7∼+5.5V
TVDD of AK4682
TVDD of AK4114
PVDD
Red
+9∼+12V
AVSS1
AVSS2
DGND
Black
Black
Black
0V
0V
0V
PVDD of AK4682
Regulator
Analog Ground
Analog Ground
Digital Ground
Should be always connected when JP25
(AVDD1_SEL) is set to AVDD1 side.
Can be open when JP25 (AVDD1_SEL)
is set to REG side.
Should be always connected when JP26
(AVDD2_SEL) is set to AVDD2 side.
Can be open when JP26 (AVDD2_SEL)
is set to AVDD1 side.
Should be always connected when JP45
(D3.3V_SEL) is set to D3.3V side.
Can be open when JP45 (D3.3V_SEL) is
set to REG side.
Should be always connected when JP32
(TVDD_SEL) is set to TVDD side.
Can be open when JP32 (TVDD_SEL) is
set to REG side.
Default
Open
Open
Open
Open
Should be always connected
+9V
Should be always connected
Should be always connected
Should be always connected
Table 1. Power supply lines
0V
0V
0V
Each supply line should be distributed from the power supply unit.
2. Set up evaluation mode and jumper pins. (Refer to the following item.)
3. Connect cables. (Refer to the following item.)
4. Power on.
The AK4682 should be reset once bringing PDN (SW1) “L” upon power-up.
5. Set up control software registers. (Refer to the following item.)
<KM086400>
2007/02
-2-
ASAHI KASEI
[AKD4682-A]
„ Evaluation modes
(1) DAC with external DIR
1. Connection of connector
For digital (S/PDIF) input, RCA connector J22 (PORTA_RX0) is available.
For analog output, RCA connector J15 (LOUT1) and JP28 (ROUT1) are available.
2. Setting of jumper pin
Setting of interface signal of PORTA: AK4114 (U7) is as follows.
(Default input of PORTA is SDTIA1.)
Jumper
Default
JP10
JP13
JP14
JP16
JP17
JP18
XTIA
SDTIA1_SEL
SDTIA2_SEL
MCLKA_SEL
BICKA
LRCKA
Open
DIR
GND
MCKO1
Short
Short
Table 2. Setting of interface signal of PORTA: AK4114 (U7) (1/3)
3. Setting of toggle switch
Switch
SW3
Default
H
Table 3. Setting of interface signal of PORTA: AK4114 (U7) (2/3)
4. Setting of DIP switch
Switch
SW2
DIF0
DIF1
DIF2
CM0
OCKS0
OCKS1
H
L
H
L
L
L
Default
Table 4. Setting of interface signal of PORTA: AK4114 (U7) (3/3)
(2) ADC with external DIT
1. Connection of connector
For analog input, RCA connector J3 (LINA)/J6 (RINA), J7 (LINB)/J9 (RINB) are available.
Setting of jumpers without inputs are open.
For digital (S/PDIF) output, RCA connector J26 (PORTB_TX1) is available.
2. Setting of jumper pin
Setting of analog inputs.
JP39 (LIN1)/
JP33 (RIN1)
JP40 (LIN2)/
JP34 (RIN2)
JP41 (LIN3)/
JP35 (RIN3)
JP42 (LIN4)/
JP36 (RIN4)
JP43 (LIN5)/
JP37 (RIN5)
JP44 (LIN6)/
JP38 (RIN6)
LIN2/ RIN2
LINA/RINA
Open
Open
LINA/RINA
Open
Open
Open
Open
Open
Open
Open
Open
LIN3/ RIN3
Open
Open
LINA/RINA
Open
Open
Open
LIN4/ RIN4
Open
Open
Open
LINA/RINA
Open
Open
LIN5/ RIN5
Open
Open
Open
Open
LINA/RINA
Open
LIN6/ RIN6
Open
Open
Open
Open
Open
LINA/RINA
Inputs
LIN1/ RIN1
(Default)
Table 5. Setting of inputs through LINA/RINA
<KM086400>
2007/02
-3-
ASAHI KASEI
[AKD4682-A]
JP39 (LIN1)/
JP33 (RIN1)
JP40 (LIN2)/
JP34 (RIN2)
JP41 (LIN3)/
JP35 (RIN3)
JP42 (LIN4)/
JP36 (RIN4)
JP43 (LIN5)/
JP37 (RIN5)
JP44 (LIN6)/
JP38 (RIN6)
LIN2/ RIN2
LINB/RINB
Open
Open
LINB/RINB
Open
Open
Open
Open
Open
Open
Open
Open
LIN3/ RIN3
Open
Open
LINB/RINB
Open
Open
Open
LIN4/ RIN4
Open
Open
Open
LINB/RINB
Open
Open
LIN5/ RIN5
Open
Open
Open
Open
LINB/RINB
Open
LIN6/ RIN6
Open
Open
Open
Open
Open
LINB/RINB
Inputs
LIN1/ RIN1
Table 6. Setting of inputs through LINB/RINB
Setting of interface signal of PORTB: AK4114 (U10) is as follows.
X3 (12.288MHz) is used as Clock (256fs) .
Jumper
Default
JP20
JP27
JP28
JP29
JP46
EXA50
MCLKB_SEL1
BICKB_SEL
LRCKB_SEL
MCLKB_SEL2
Open
Open
BICK
LRCK
MCKO1
Table 7. Setting of interface signal of PORTB: AK4114 (U10) (1/3)
3. Setting of toggle switch
Switch
SW5
Default
H
Table 8. Setting of PORTB: AK4114 (U10) (2/3)
4. Setting of DIP switch
Switch
SW4
DIF0
DIF1
CM0
OCKS0
OCKS1
MSB
H
L
H
L
L
L
Default
Table 9. Setting of interface signal of PORTB: AK4114 (U7) (3/3)
(3) Analog input to analog output (Through: Analog input → Analog output)
1. Connection of connector
For analog input, RCA connector J3 (LINA)/J6 (RINA), J7 (LINB)/J9 (RINB) are available.
Setting of jumpers without inputs are open.
For analog output, RCA connector J15 (LOUT1)/J28 (ROUT1), J16 (LOUT2)/J18 (ROUT2), J17
(LOUT3)/J27 (ROUT3) are available.
2. Setting of jumper pin
Setting of analog inputs.
JP39 (LIN1)/
JP33 (RIN1)
JP40 (LIN2)/
JP34 (RIN2)
JP41 (LIN3)/
JP35 (RIN3)
JP42 (LIN4)/
JP36 (RIN4)
JP43 (LIN5)/
JP37 (RIN5)
JP44 (LIN6)/
JP38 (RIN6)
LIN2/ RIN2
LINA/RINA
Open
Open
LINA/RINA
Open
Open
Open
Open
Open
Open
Open
Open
LIN3/ RIN3
Open
Open
LINA/RINA
Open
Open
Open
LIN4/ RIN4
Open
Open
Open
LINA/RINA
Open
Open
LIN5/ RIN5
Open
Open
Open
Open
LINA/RINA
Open
LIN6/ RIN6
Open
Open
Open
Open
Open
LINA/RINA
Inputs
LIN1/ RIN1
(Default)
Table 10. Setting of inputs through LINA/RINA
<KM086400>
2007/02
-4-
ASAHI KASEI
[AKD4682-A]
JP39 (LIN1)/
JP33 (RIN1)
JP40 (LIN2)/
JP34 (RIN2)
JP41 (LIN3)/
JP35 (RIN3)
JP42 (LIN4)/
JP36 (RIN4)
JP43 (LIN5)/
JP37 (RIN5)
JP44 (LIN6)/
JP38 (RIN6)
LIN2/ RIN2
LINB/RINB
Open
Open
LINB/RINB
Open
Open
Open
Open
Open
Open
Open
Open
LIN3/ RIN3
Open
Open
LINB/RINB
Open
Open
Open
LIN4/ RIN4
Open
Open
Open
LINB/RINB
Open
Open
LIN5/ RIN5
Open
Open
Open
Open
LINB/RINB
Open
LIN6/ RIN6
Open
Open
Open
Open
Open
LINB/RINB
Inputs
LIN1/ RIN1
Table 11. Setting of inputs through LINB/RINB
3. Setting of toggle switch
Switch
SW3
SW5
Default
L
H
Table 12. Setting of interface signal of PORTB: AK4114 (U7, U10)
(4) Analog input to analog output with external DIR (Analog input → ADC → DAC → Analog output)
1. Connection of connector
For analog input, RCA connector J3 (LINA)/J6 (RINA), J7 (LINB)/J9 (RINB) are available.
Setting of jumpers for unused inputs are open.
For analog output, RCA connector J15 (LOUT1)/J28 (ROUT1), J16 (LOUT2)/J18 (ROUT2), J17
(LOUT3)/J27 (ROUT3) are available.
* X2 is available for clock. X2 is the X’tal for 11.2896MHz on the evaluation board. Change the X’tal depends
on Fs.
2. Setting of jumper pin
Setting of analog inputs.
JP39 (LIN1)/
JP33 (RIN1)
JP40 (LIN2)/
JP34 (RIN2)
JP41 (LIN3)/
JP35 (RIN3)
JP42 (LIN4)/
JP36 (RIN4)
JP43 (LIN5)/
JP37 (RIN5)
JP44 (LIN6)/
JP38 (RIN6)
LIN2/ RIN2
LINA/RINA
Open
Open
LINA/RINA
Open
Open
Open
Open
Open
Open
Open
Open
LIN3/ RIN3
Open
Open
LINA/RINA
Open
Open
Open
LIN4/ RIN4
Open
Open
Open
LINA/RINA
Open
Open
LIN5/ RIN5
Open
Open
Open
Open
LINA/RINA
Open
LIN6/ RIN6
Open
Open
Open
Open
Open
LINA/RINA
Inputs
LIN1/ RIN1
(Default)
Table 13. Setting of inputs through LINA/RINA
JP39 (LIN1)/
JP33 (RIN1)
JP40 (LIN2)/
JP34 (RIN2)
JP41 (LIN3)/
JP35 (RIN3)
JP42 (LIN4)/
JP36 (RIN4)
JP43 (LIN5)/
JP37 (RIN5)
JP44 (LIN6)/
JP38 (RIN6)
LIN2/ RIN2
LINB/RINB
Open
Open
LINB/RINB
Open
Open
Open
Open
Open
Open
Open
Open
LIN3/ RIN3
Open
Open
LINB/RINB
Open
Open
Open
LIN4/ RIN4
Open
Open
Open
LINB/RINB
Open
Open
LIN5/ RIN5
Open
Open
Open
Open
LINB/RINB
Open
LIN6/ RIN6
Open
Open
Open
Open
Open
LINB/RINB
Inputs
LIN1/ RIN1
Table 14. Setting of inputs through LINB/RINB
<KM086400>
2007/02
-5-
ASAHI KASEI
[AKD4682-A]
Setting of interface signal of PORTA: AK4114 (U7) is as follows.
(Default input of PORTA is SDTIA1.)
JP10
JP13
JP14
JP16
Jumper
Default
JP17
JP18
XTIA
SDTIA1_SEL
SDTIA2_SEL
MCLKA_SEL
BICKA
LRCKA
Open
DIR
GND
MCKO1
Short
Short
Table 15. Setting of interface signal of PORTA: AK4114 (U7) (1/5)
Setting of interface signal of PORTB: AK4114 (U10) is as follows.
JP20
JP27
JP28
JP29
Jumper
Default
JP46
EXA50
MCLKB_SEL1
BICKB_SEL
LRCKB_SEL
MCLKB_SEL2
Open
Open
BICKA
LRCKA
MCLKA
Table 16. Setting of interface signal of PORTB: AK4114 (U10) (2/5)
3. Setting of toggle switch
Switch
SW3
SW5
Default
H
H
Table 17. Setting of interface signal of PORTB: AK4114 (U7, U10) (3/5)
4. Setting of DIP switch
Switch
Default
SW2
DIF0
DIF1
DIF2
CM0
OCKS0
OCKS1
H
L
H
H
L
L
Table 18. Setting of interface signal of PORTA: AK4114 (U7) (4/5)
Switch
Default
SW4
DIF0
DIF1
CM0
OCKS0
OCKS1
MSB
H
L
H
L
L
L
Table 19. Setting of interface signal of PORTB: AK4114 (U7) (5/5)
<KM086400>
2007/02
-6-
ASAHI KASEI
[AKD4682-A]
„ Register control
AKD4682-A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2
(uP-I/F) to PC by 10-line flat cable packed with this. Take care of the direction of connector. There is a mark at
connector. Connect the mark of 10-pin connector to pin#6 of PORT2. (Figure 2.)
PORT2
1 UP-I/F 10
SCL
Connect
PC
SDA
SDA (ACK)
RED
10-wire flat cable
10-pin connector
5
6
10-pin header
AKD4682-A
Figure 2. PORT2 pin layout
Control software is packed with this evaluation board. Software operation procedure is included in evaluation board
manual.
„ Set-up DIP switch (SW2)
No.
1
2
3
Name
DIF0
DIF1
DIF2
Content
Default
ON
OFF
ON
Setting of AK4114 Audio Interface Format
(Refer Table 20.)
Selection of AK4114 Clock Mode (Clock Source)
(Refer Table 21.)
OCKS0 Selection of AK4114 Master Clock Output frequency
(Refer Table 22.)
OCKS1
Table 20. Set up modes of AK4114 (U7) and AK4682 (U1)
4
CM0
6
7
Mode
DIF2
DIF1
DIF0
DAUX
SDTO
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
24bit, Left justified 16bit, Right justified
24bit, Left justified 18bit, Right justified
24bit, Left justified 20bit, Right justified
24bit, Left justified 24bit, Right justified
24bit, Left justified 24bit, Left justified
24bit, I2S
24bit, I2S
24bit, Left justified 24bit, Left justified
24bit, I2S
24bit, I2S
Table 21. AK4114 Audio Interface Format
Mode
0
1
CM0
0
1
PLL
X'tal
Clock source
SDTO
ON ON(Note)
PLL
RX
OFF
ON
X'tal
DAUX
Table 22. AK4114 Clock Mode (Clock Source)
<KM086400>
OFF
OFF
OFF
LRCK
I/O
H/L
O
H/L
O
H/L
O
H/L
O
H/L
O
L/H
O
H/L
I
L/H
I
BICK
64fs
64fs
64fs
64fs
64fs
64fs
64-128fs
64-128fs
I/O
O
O
O
O
O
O
I
I
<Default>
<Default>
2007/02
-7-
ASAHI KASEI
[AKD4682-A]
No.
0
1
2
3
OCKS1
0
0
1
1
OCKS0 MCKO1 MCKO2 X’tal fs (max)
0
256fs
256fs
256fs 96 kHz
1
256fs
128fs
256fs 96 kHz
0
512fs
256fs
512fs 48 kHz
1
128fs
64fs
128fs 192 kHz
Table 23. AK4114 Master Clock Output Frequency
<Default>
„ Toggle switch
[SW1] PDN:
Switch for power down reset of AK4682 (U1). Keep “H” during operation of AK4682 (U1).
Power down reset of AK4682 will be done by setting SW1 to “L” once, after power on.
[SW3] AK4114 (U7)-PDN:
Switch for power down reset of AK4114 (U7). Keep “H” during operation of AK4114 (U7).
Power down reset of AK4114 (U7) will be done by setting SW1 to “L” once, after power on.
[SW5] AK4114 (U10)-PDN:
Switch for power down reset of AK4114 (U10). Keep “H” during operation of AK4114 (U10).
Power down reset of AK4114 (U10) will be done by setting SW1 to “L” once, after power on.
„ LED indication
[LED1] ERF:
LED for output of AK4114 (U7): INT0. It turns on when output of AK4114 (U7): INT0 is “H”.
[LED2] ERF:
LED for output of AK4114 (U10): INT0. It turns on when output of AK4114 (U10): INT0 is “H”.
<KM086400>
2007/02
-8-
ASAHI KASEI
[AKD4682-A]
„ Set up Jumper pins
Jumper
Evaluation Mode
1
2
3
4
JP39 (LIN1)
Open
LINA
LINA
Open
JP40 (LIN2)
Open
Open
Open
Open
JP41 (LIN3)
Open
Open
Open
Open
JP42 (LIN4)
Open
Open
Open
Open
JP43 (LIN5)
Open
Open
Open
Open
JP44 (LIN6)
Open
Open
Open
Open
JP33 (RIN1)
Open
RINA
RINA
Open
JP34 (RIN2)
JP35 (RIN3)
Open
Open
Open
Open
Open
Open
Open
Open
JP36 (RIN4)
Open
Open
Open
Open
JP37 (RIN5)
Open
Open
Open
Open
JP38 (RIN6)
Open
Open
Open
Open
JP10 (XTIA)
Open
Open
Open
Open
JP13 (SDTIA1_SEL)
GND
GND
DIR
JP14 (SDTIA2_SEL)
DIR
GND
GND
GND
GND
JP16 (MCLKA_SEL)
MCKO1
Open
Open
MCKO1
JP17 (BICKA)
Short
Open
Open
Short
JP18 (LRCKA)
Short
Open
Open
Short
JP27 (MCLKB_SEL1)
Open
Open
Open
MCLKA
JP28 (BICKB_SEL)
Open
BICK
Open
BICK
JP29 (LRCKB_SEL)
Open
LRCK
Open
LRCK
JP46 (MCLKB_SEL2)
Open
MCKO1
Open
MCKO1
JP25 (AVDD1_SEL)
JP45 (D3.3V_SEL)
REG
REG
REG
REG
REG
REG
REG
REG
REG
REG
REG
REG
REG
REG
REG
REG
JP19 (EXA50)
Open
Open
Open
Open
JP20 (EXB50)
Open
Open
Open
Open
JP26 (AVDD2_SEL)
JP32 (TVDD_SEL)
(Default)
„ Set up control software registers
After the reset, setting example files are available as follows in CD-ROM to set registers in each evaluation modes.
Evaluation Mode 1
ADC/DAC: ak4682_dac_mode1.akr
Evaluation Mode 2
ADC/DAC: ak4682_adc_mode2.akr
Evaluation Mode 3
ADC/DAC: ak4682_analog_through _mode3.akr
Evaluation Mode 4
ADC/DAC: ak4682_loopback_mode4.akr
<KM086400>
2007/02
-9-
ASAHI KASEI
[AKD4682-A]
„ Analog Input Circuit
LIN1
LINB
2.2u
LIN1
JP40
LIN2
LINA
+
C20
JP39
2
3
1
J3
LINA
MR-552LS
LINA
AVSS1
LIN2
LINB
LINA
C109
+
JP41
LIN3
LIN3
2
3
1
LINB
2.2u
JP42
LIN4
LINB
MR-552LS
LINA
LIN4
LINB
JP43
LIN5
J7
AVSS1
LINA
LIN5
LINB
JP44
LIN6
LINA
LIN6
LINB
RIN1
RINB
2.2u
RIN1
JP34
RIN2
RINA
+
C25
JP33
2
3
1
J6
RINA
MR-552LS
RINA
AVSS1
RIN2
RINB
RINA
C108
+
JP35
RIN3
RIN3
2
3
1
RINB
2.2u
JP36
RIN4
RIN4
JP37
RIN5
JP38
RIN6
RINB
MR-552LS
RINA
AVSS1
RINB
RIN5
J9
RINA
RINB
RINA
RIN6
RINB
Figure 3. Analog Input Circuit
For analog input, RCA connector: J3 (LINA), J6 (RINA), J7 (LINB), J9 (RINB) are available to use.
Analog inputs are single-ended and input ranges of each channel are nominally 5.6 [email protected]
<KM086400>
2007/02
- 10 -
ASAHI KASEI
[AKD4682-A]
„ Analog Output Circuit
C112
220
+
R54
10k
LOUT2
+
22u
+
2
3
1
C38
4.7n
J16
22u
LOUT2
ROUT2
10k
C40
4.7n
PVSS
J17
22u
LOUT3
ROUT3
R62
10k
MR-552LS
PVSS
PVSS
ROUT1
MR-552LS
R61
220
+
10k
C110
2
3
1
J28
PVSS
C42
2
3
1
4.7n
PVSS
220
C113
2
3
1
4.7n
R60
MR-552LS
R59
R58
+
10k
PVSS
+
220
R64
C41
+
R65
PVSS
220
PVSS
LOUT3
ROUT1
MR-552LS
R57
10k
22u
22u
LOUT1
PVSS
R56
C39
C37
4.7n
PVSS
C36
2
3
1
J15
+
R55
+
LOUT1
+
22u
+
C35
J18
ROUT2
MR-552LS
PVSS
R63
220
+
C111
4.7n
2
3
1
J27
ROUT3
MR-552LS
PVSS
Figure 4. Analog Output Circuit
For analog output, RCA connector: J15 (LOUT1), J28 (ROUT1), J16 (LOUT2), J18 (ROUT2), J17(LOUT3),
J27(ROUT3) are available to use.
Analog outputs are single-ended and output ranges of each channel are nominally [email protected]
Output range: AOUT is proportional to AVDD2 (AOUT=2 x AVDD2/5 x 1.4 x 2 = 2 x 5/5 x 1.4 x 2 =5.6Vpp).
„ Digital Input Circuit (External DIR : PORTA)
J22
C46
PORTA_RX0
2
3
1
R74
75
MR-552LS
0.1u
DGND
DGND
Figure 5. Digital Input Circuit (External DIR)
For digital input, RCA connector: J22 (PORTA-RX0) is available.
„ Digital Output Circuit (External DIT : PORTB)
J26
PORTB_TX1
MR-552LS
2
3
1
4
DGND1
1
T3
DA02
R85
8
5
R84
240
150
DGND1
Figure 6. Digital Output Circuit (External DIT)
For digital output, RCA connector: J26 (PORTB-TX1) is available.
<KM086400>
2007/02
- 11 -
ASAHI KASEI
[AKD4682-A]
Control Software Manual
„ Set-up of evaluation board and control software
1. Set up the AKD4682-A according to previous term.
2. Connect IBM-AT compatible PC with AKD4682-A by 10-line type flat cable (packed with AKD4682-A). Take care
of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on
Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”.
In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows
NT.)
3. Insert the CD-ROM labeled “AKD4682-A Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive, and double-click the icon of “akd4682-a.exe”, and set up the control program.
akd4682-a.exe: AK4682-A control program
5. Then evaluate according to the follows.
„ Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click “Port Reset” button.
„ Explanation of each buttons
1. [Port Reset]:
2. [Write default]:
3. [All Write]:
4. [Function1]:
5. [Function2]:
6. [Function3]:
7. [Function4]:
8. [Function5]:
9. [SAVE]:
10. [OPEN]:
11. [Write]:
Set up the USB interface board (AKDUSBIF-A).
Initialize the registers.
Write all registers data that is currently displayed.
Dialog to write data by keyboard operation.
Dialog to write data by keyboard operation.
The sequence of register setting can be set and executed.
The sequence that is created on [Function3] can be assigned to buttons and
executed.
The register setting that is created by [SAVE] function on main window can
be assigned to buttons and executed.
Save the current register setting.
Write the saved values to all register.
Dialog to write data by mouse operation.
„ Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the
part that is not defined in the datasheet.
<KM086400>
2007/02
- 12 -
ASAHI KASEI
[AKD4682-A]
„ Explanation of each dialog
1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data
becomes “H” or “1”. If not, “L” or “0”.
When writing the input data to register, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog]: Dialog to write data by keyboard operation
Address Box: Input registers address in 2 figures of hexadecimal.
Data Box:
Input registers data in 2 figures of hexadecimal.
When writing the input data to register, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog]: Dialog to evaluate ATT
This is a dialog corresponding to address: 08H, 09H, 0AH, 0BH, 0CH, and 0DH of AK4682.
Address Box:
Input registers address in 2 figures of hexadecimal.
Start Data Box:
Input starts data in 2 figures of hexadecimal.
End Data Box:
Input end data in 2 figures of hexadecimal.
Interval Box:
Data is written to register by this interval.
Step Box:
Data changes by this step.
Mode Select Box:
With checking this check box, data reaches end data, and returns to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
Without checking this check box, data reaches end data, but does not return to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
When writing the input data to register, click [OK] button. If not, click [Cancel] button.
<KM086400>
2007/02
- 13 -
ASAHI KASEI
[AKD4682-A]
4. [Save] and [Open]
4-1. [Save]
Save the current register setting data to the file. The extension of file name is “akr”.
(Operation flow)
(1) Click [Save] Button.
(2) Set the file name and push [Save] Button. The extension of file name is “akr”.
4-2. [Open]
The register setting data saved to the file by [Save] is written to register. The file type is the same as [Save].
(Operation flow)
(1) Click [Open] Button.
(2) Select the file (*.akr) and Click [Open] Button.
<KM086400>
2007/02
- 14 -
ASAHI KASEI
[AKD4682-A]
5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button.
Set the control sequence.
Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused.
(3) Click [Start] button. Then this sequence is executed.
The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step.
This sequence can be saved and opened by [Save] and [Open] button on the [Function3] window. The extension of file
name is “aks”.
Figure 7. Window of [F3]
<KM086400>
2007/02
- 15 -
ASAHI KASEI
[AKD4682-A]
6. [Function4 Dialog]
The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the
window as shown in Figure 8 opens.
Figure 8. [F4] window
<KM086400>
2007/02
- 16 -
ASAHI KASEI
[AKD4682-A]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks).
The sequence file name is displayed as shown in Figure 9.
Figure 9. [F4] window(2)
(2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side
[SAVE]: The sequence file names can assign be saved. The file name is *.ak4.
[OPEN]: The sequence file names assign that are saved in *.ak4 are loaded.
6-3. Note
(1) [Function4] doesn't support the pause function of sequence function.
(2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side.
(3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change.
<KM086400>
2007/02
- 17 -
ASAHI KASEI
[AKD4682-A]
7. [Function5 Dialog]
The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When
[F5] button is clicked, the following window as shown in Figure 10 opens.
Figure 10. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
(2) Click [WRITE] button, then the register setting is executed.
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE]: The register setting file names assign can be saved. The file name is *.ak5.
[OPEN]: The register setting file names assign that are saved in *.ak5 are loaded.
7-3. Note
(1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side.
(2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to
reflect the change.
<KM086400>
2007/02
- 18 -
ASAHI KASEI
[AKD4682-A]
Measure Result
1) ADC part
[Measurement condition]
• Measurement unit : Audio Precision
• MCLK
: 256fs (fs=48kHz)
• BICK
: 64fs
• fs
: 48kHz
• BW
: 20Hz∼20kHz (fs=48kHz)
• Bit
: 24bit
• Power Supply
: AVDD1=AVDD2=DVDD1=DVDD2=5V, TVDD=3V, PVDD =9V
• Interface
: External DIT (fs=48kHz,)
• Temperature
: Room Temp
fs=48kHz (ADC)
Parameter
S/(N+D)
DR
DR
S/N
S/N
Input signal
Measurement filter
1kHz, -0.5dB
1kHz, -60dB
1kHz, -60dB
No signal
No signal
20kLPF
20kLPF
20kLPF, A-weighted
20kLPF
20kLPF, A-weighted
<KM086400>
Results
Lch
90.7
93.5
96.1
93.5
96.1
[dB]
Rch
90.9
93.6
96.1
93.6
96.1
2007/02
- 19 -
ASAHI KASEI
[AKD4682-A]
2) DAC part
[Measurement condition]
• Measurement unit : Audio Precision
• MCLK
: 256fs (fs=48kHz, 96kHz), 128fs (fs=192kHz)
• BICK
: 64fs
• fs
: 48kHz, 96kHz, 192kHz
• BW
: 20Hz∼20kHz (fs=48kHz), 20Hz∼40kHz (fs=96kHz), 20Hz∼40kHz (fs=192kHz)
• Resolution
: 24bit
• Power Supply
: AVDD1=AVDD2=DVDD1=DVDD2=5V, TVDD=3V, PVDD =9V
• Interface
: External DIR (48kHz, 96kHz, 192kHz)
• Temperature
: Room Temp
fs=48kHz
20kLPF
20kLPF
22kLPF, A-weighted
Results
Lch
87.9
98.7
101.4
[dB]
Rch
87.4
98.4
101.2
“0” data
“0” data
20kLPF
22kLPF, A-weighted
98.7
101.4
98.4
101.2
Parameter
Input signal
Measurement filter
S/(N+D)
DR
DR
S/N
S/N
1kHz, 0dB
1kHz, -60dB
1kHz, -60dB
“0” data
“0” data
40kLPF
40kLPF
22kLPF, A-weighted
40kLPF
22kLPF, A-weighted
Parameter
Input signal
Measurement filter
S/(N+D)
DR
DR
S/N
S/N
1kHz, 0dB
1kHz, -60dB
1kHz, -60dB
“0” data
“0” data
40kLPF
40kLPF
22kLPF, A-weighted
40kLPF
22kLPF, A-weighted
Parameter
Input signal
Measurement filter
S/(N+D)
DR
DR
1kHz, 0dB
1kHz, -60dB
1kHz, -60dB
S/N
S/N
fs=96kHz
Results [dB]
Lch
Rch
87.2
96.6
101.4
96.6
101.4
86.8
96.3
101.2
96.3
101.2
fs=192kHz
<KM086400>
Results [dB]
Lch
Rch
87.1
96.4
101.4
96.5
101.4
86.7
96.2
101.2
96.3
101.2
2007/02
- 20 -
ASAHI KASEI
[AKD4682-A]
1. ADC part
(ADC fs=48kHz)
AK4682 FFT fs=48kHz -1.0dB input
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 11. FFT(Input Frequency =1kHz,Input Level=-1.0dBFS)
AK4682 FFT fs=48kHz -60dB input
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
Hz
Figure 12. FFT(Input Frequency =1kHz,Input Level=-60dBFS)
<KM086400>
2007/02
- 21 -
ASAHI KASEI
[AKD4682-A]
(ADC fs=48kHz)
AK4682 FFT fs=48kHz No signal input
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 13. FFT(noise floor)
AK4682 THD+N vs Input Level fs=48kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-45
-50
-55
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-105
-110
-115
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 14. THD + N vs Input Level (Input Frequency =1kHz)
<KM086400>
2007/02
- 22 -
ASAHI KASEI
[AKD4682-A]
(ADC fs=48kHz)
AK4682 THD+N vs Input Frequency fs=48kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-80
-82.5
-85
-87.5
-90
-92.5
-95
d
B
F
S
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
Figure 15. THD + N vs Input Frequency (Input Level=-1.0dBFS)
AK4682 Linearity fs=48kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
T
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 16. Linearity (Input Frequency =1kHz)
<KM086400>
2007/02
- 23 -
ASAHI KASEI
[AKD4682-A]
(ADC fs=48kHz)
AK4682 Frequency Respons fs=48kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
d
B
F
S
-0.9
-1
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 17. Frequency Response (Input Level=-1.0dBFS)
AK4682 Crosstalk fs=48kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-70
T
-75
-80
-85
-90
-95
-100
-105
d
B
-110
-115
-120
-125
-130
-135
-140
-145
-150
20
50
100
200
500
1k
2k
Hz
Figure 18. Crosstalk (Input Level=-1.0dBFS)
<KM086400>
2007/02
- 24 -
ASAHI KASEI
[AKD4682-A]
2. DAC part
(DAC fs=48kHz)
AK4682 FFT fs=48kHz 0dBFS input
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 19. FFT(Input Frequency =1kHz, Input Level=0dBFS)
AK4682 FFT(Out of Band Noise) fs=48kHz No signal input
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 20. FFT(Input Frequency =1kHz, Input Level=0dBFS,Notch=on)
<KM086400>
2007/02
- 25 -
ASAHI KASEI
[AKD4682-A]
(DAC fs=48kHz)
AK4682 FFT fs=48kHz -60dBFS input
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 21. FFT(Input Frequency =1kHz, Input Level=-60dBFS)
AK4682 FFT fs=48kHz No signal input
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
A
-90
-80
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
Hz
Figure 22. FFT(noise floor)
<KM086400>
2007/02
- 26 -
ASAHI KASEI
[AKD4682-A]
(DAC fs=48kHz)
AK4682 FFT(Out of Band Noise) fs=48kHz No signal input
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
-80
-90
A
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 23. FFT(out-of-band noise)
AKM
AK4682 THD+N vs Input Level fs=48kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-80
-82.5
-85
-87.5
-90
-92.5
-95
d
B
r
-97.5
A
-102.5
-100
-105
-107.5
-110
-112.5
-115
-117.5
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 24. THD+N vs Input Level (Input Frequency =1kHz)
<KM086400>
2007/02
- 27 -
ASAHI KASEI
[AKD4682-A]
(DAC fs=48kHz)
AK4682 THD+N vs Input Frequency fs=48kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-70
-72.5
-75
-77.5
-80
-82.5
-85
d
B
r
-87.5
A
-92.5
-90
-95
-97.5
-100
-102.5
-105
-107.5
-110
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 25. THD+N vs Input Frequency (Input Level=0dBFS)
AKM
AK4682 Linearity fs=48kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 26. Linearity (Input Frequency =1kHz)
<KM086400>
2007/02
- 28 -
ASAHI KASEI
[AKD4682-A]
(DAC fs=48kHz)
AKM
AK4682 Frequency Response fs=48kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
+1
+0.8
+0.6
+0.4
+0.2
d
B
r
+0
A
-0.2
-0.4
-0.6
-0.8
-1
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 27. Frequency Response (Input Level=0dBFS)
AKM
AK4682 Crosstalk fs=48kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
d
B
-110
-112.5
-115
-117.5
-120
-122.5
-125
-127.5
-130
20
50
100
200
500
1k
2k
5k
Hz
Figure 28. Cross-talk (Input Level=0dBFS)
<KM086400>
2007/02
- 29 -
ASAHI KASEI
[AKD4682-A]
(DAC fs=96kHz)
AK4682 FFT fs=96kHz 0dBFS input
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
40
50
100
200
500
1k
2k
5k
10k
20k
40k
10k
20k
40k
Hz
Figure 29. FFT(Input Frequency =1kHz, Input Level=0dBFS)
AK4682 FFT(Notch) fs=96kHz 0dBFS input
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
A
-90
-80
-100
-110
-120
-130
-140
-150
-160
40
50
100
200
500
1k
2k
5k
Hz
Figure 30. FFT(Input Frequency =1kHz, Input Level=0dBFS,Notch=on)
<KM086400>
2007/02
- 30 -
ASAHI KASEI
[AKD4682-A]
(DAC fs=96kHz)
AK4682 FFT fs=96kHz -60dBFS input
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
40
50
100
200
500
1k
2k
5k
10k
20k
40k
10k
20k
40k
Hz
Figure 31. FFT(Input Frequency =1kHz, Input Level=-60dBFS)
AK4682 FFT fs=96kHz No signal input
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
A
-90
-80
-100
-110
-120
-130
-140
-150
-160
40
50
100
200
500
1k
2k
5k
Hz
Figure 32. FFT(noise floor)
<KM086400>
2007/02
- 31 -
ASAHI KASEI
[AKD4682-A]
(DAC fs=96kHz)
AK4682 THD+N vs Input Level fs=96kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-80
-82.5
-85
-87.5
-90
-92.5
-95
d
B
r
-97.5
A
-102.5
-100
-105
-107.5
-110
-112.5
-115
-117.5
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
FigureFigure 33. THD+N vs Input Level (Input Frequency =1kHz)
AK4682 THD+N vs Input Frequency fs=96kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-70
-72.5
-75
-77.5
-80
-82.5
-85
d
B
r
-87.5
A
-92.5
-90
-95
-97.5
-100
-102.5
-105
-107.5
-110
40
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 34. THD+N vs fin (Input Level=0dBFS)
<KM086400>
2007/02
- 32 -
ASAHI KASEI
[AKD4682-A]
(DAC fs=96kHz)
AK4682 Linearity fs=96kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 35. Linearity (Input Frequency =1kHz)
AK4682 Frequency Response fs=96kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
+1
+0.8
+0.6
+0.4
+0.2
d
B
r
A
+0
-0.2
-0.4
-0.6
-0.8
-1
40
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 36. Frequency Response (Input Level=0dBFS)
<KM086400>
2007/02
- 33 -
ASAHI KASEI
[AKD4682-A]
(DAC fs=96kHz)
AK4682 Crosstalk fs=96kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
d
B
-110
-112.5
-115
-117.5
-120
-122.5
-125
-127.5
-130
40
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 37. Cross-talk (Input Level=0dBFS)
<KM086400>
2007/02
- 34 -
ASAHI KASEI
[AKD4682-A]
(DAC fs=192kHz)
AK4682 FFT fs=192kHz 0dBFS input
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
90
200
500
1k
2k
5k
10k
20k
50k
80k
20k
50k
80k
Hz
Figure 38. FFT(Input Frequency =1kHz, Input Level=0dBFS)
AK4682 FFT(Notch) fs=192kHz 0dBFS input
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
A
-90
-80
-100
-110
-120
-130
-140
-150
-160
90
200
500
1k
2k
5k
10k
Hz
Figure 39. FFT(Input Frequency =1kHz, Input Level=0dBFS,Notch=on,40kHzLPF)
<KM086400>
2007/02
- 35 -
ASAHI KASEI
[AKD4682-A]
(DAC fs=192kHz)
AK4682 FFT fs=192kHz -60dBFS input
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
90
200
500
1k
2k
5k
10k
20k
50k
80k
20k
50k
80k
Hz
Figure 40. FFT(Input Frequency =1kHz, Input Level=-60dBFS)
AK4682 FFT fs=192kHz No signal input
AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
A
-90
-80
-100
-110
-120
-130
-140
-150
-160
90
200
500
1k
2k
5k
10k
Hz
Figure 41. FFT(noise floor)
<KM086400>
2007/02
- 36 -
ASAHI KASEI
[AKD4682-A]
(DAC fs=192kHz)
AK4682 THD+N vs Input Level fs=192kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-80
-82.5
-85
-87.5
-90
-92.5
-95
d
B
r
-97.5
A
-102.5
-100
-105
-107.5
-110
-112.5
-115
-117.5
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 42. THD+N vs Input Level (Input Frequency =1kHz)
AK4682 THD+N vs Input Frequency fs=192kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-70
-72.5
-75
-77.5
-80
-82.5
-85
d
B
r
-87.5
A
-92.5
-90
-95
-97.5
-100
-102.5
-105
-107.5
-110
90
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 43. THD+N vs Input Frequency (Input Level=0dBFS)
<KM086400>
2007/02
- 37 -
ASAHI KASEI
[AKD4682-A]
(DAC fs=192kHz)
AK4682 Linearity fs=192kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
50k
80k
dBFS
Figure 44. Linearity (f Input Frequency =1kHz)
AK4682 Frequency Response fs=192kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
+1
+0.75
+0.5
+0.25
-0
-0.25
-0.5
d
B
r
-0.75
A
-1.25
-1
-1.5
-1.75
-2
-2.25
-2.5
-2.75
90
200
500
1k
2k
5k
10k
20k
Hz
Figure 45. Frequency Response (Input Level=0dBFS)
<KM086400>
2007/02
- 38 -
ASAHI KASEI
[AKD4682-A]
(DAC fs=192kHz)
AK4682 Crosstalk fs=192kHz
AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-80
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
d
B
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 46. Cross-talk (Input Level=0dBFS
<KM086400>
2007/02
- 39 -
ASAHI KASEI
[AKD4682-A]
Revision History
Date
Manual
Board
(YY/MM/DD) Revision Revision
07/02/19
KM086400
0
Reason
Contents
First Edition
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
<KM086400>
2007/02
- 40 -
1
RIN3
LIN3
2
LIN4
RIN4
RIN5
RIN6
LIN5
3
LIN6
4
DVDD1
5
CN4
48pin_4
R12
R11
R10
(short)
(short)
(short)
R9
R8
(short)
(short)
R7
37
38
39
40
41
42
43
44
45
46
47
D
48
D
R6
(short)
(short)
R5
(short)
MCLKB
R13
37
38
39
40
41
42
43
44
45
46
47
LIN3
RIN3
NC
LIN4
NC
RIN4
LIN5
RIN5
NC
1
DVSS1
RIN2
36
R4
2
MCLKB
LIN2
35
R3
NC
34
RIN1
33
DVSS1
36
RIN2
35
LIN2
(short)
2
(short)
+
4682_TVDD
LIN6
0.1u
RIN6
C17
10u
1
DVSS1
48pin_3
C16
DVDD1
+
CN1
48
AVSS1
U1
10u
0.1u
C98
C99
(short)
3
3
TVDD
4
4
LRCKB
34
C
C
R2
(short)
BICKB
R15
5
5
BICKB
LIN1
32
6
6
SDTOB
AVDD1
31
7
7
AVSS1
30
PDN
8
8
LRCKA
VCOM3
29
9
9
BICKA
VCOM36
28
10
10
MCLKA
AVSS2
27
R1
(short)
SDTOB
R16
PDN
R18
AK4682
R19
C97
+10u
C96
C92
C93
0.1u
10u
0.1u
(short)
BICKA
RIN1
32
LIN1
31
AVDD1
(short)
(short)
LRCKA
33
(short)
30
AVSS1
AVSS1
29
C94
C95
0.1u
10u
+
R14
+
LRCKB
AVSS1
28
(short)
R20
(short)
SDTIA1
R21
27
C87
C91
0.1u
10u
+
MCLKA
AVSS2
AVSS2
11
11
SDTIA1
AVDD2
26
26
12
12
SDTIA2
ROUT3
25
25
AVDD2
ROUT3
LOUT3
PVSS
PVDD
ROUT2
LOUT2
MSB
DVDD2
SCL
SDA
(short)
ROUT1
R22
DVSS2
SDTIA2
LOUT1
(short)
48pin_1
10u
10u
24
23
22
21
20
19
18
PVSS
17
16
15
14
B
C15
DVSS2
13
24
23
C13
0.1u
C14
+
22
21
20
19
18
17
16
C12
0.1u
+
15
14
13
CN3
B
CN2
48pin_2
DVSS2
PVSS
R25
(short)
PVDD1
R24
(short)
DVDD2
R23
(short)
LOUT3
ROUT2
MSB
LOUT2
ROUT1
LOUT1
SCL
A
SDA
A
Title
Size
A2
Date:
5
4
3
2
AKD4682-A
Document Number
Rev
0
AK4682
Monday, November 20, 2006
1
Sheet
1
of
1
5
4
3
2
1
D
D
LIN1
LINB
2.2u
LIN1
JP40
LIN2
LINA
+
C20
JP39
J3
LINA
2
3
1
MR-552LS
LINA
AVSS1
LIN2
LINB
LINA
C109
J7
+
JP41
LIN3
LIN3
2.2u
JP42
LIN4
MR-552LS
LINA
LIN4
LINB
JP43
C
LIN5
LINB
2
3
1
LINB
AVSS1
LINA
C
LIN5
LINB
JP44
LIN6
LINA
LIN6
LINB
RIN1
RINB
2.2u
RIN1
JP34
RIN2
RINA
+
C25
JP33
J6
RINA
2
3
1
MR-552LS
RINA
AVSS1
RIN2
RINB
RIN3
RINA
C108
J9
+
JP35
B
RIN3
2.2u
JP36
RIN4
MR-552LS
RINA
RIN4
RINB
JP37
RIN5
B
RINB
2
3
1
RINB
AVSS1
RINA
RIN5
RINB
JP38
RIN6
RINA
RIN6
RINB
A
A
Title
Size
A3
Date:
5
4
3
2
AKD4682-A
Document Number
LIN/RIN
Monday, September 11, 2006
Sheet
1
Rev
0
1
of
1
5
4
3
2
1
D
D
14
D3.3V
R35
R38
10k
470
3
U3B
4
74LS07
R40
R36
470
1
7
10k
C
R39
100
R41
100
SCL
D3.3V
14
7
D3.3V
U3A
2
SDA
74LS07
C
PORT2
A1-10PA-2.54DSA
1
2
3
4
5
DGND
10
9
8
7
6
SCL
SDA
SDA(ACK)
R44
(short)
uP-I/F
R66
10k
R48
10k
D3.3V
K
D3.3V
1
A
L
7
H
SW1
C33
ATE1D-2M3
0.1u
U4A
2
74HC14
D3.3V
14
D3.3V
3
7
10k
14
R49
D1
1S1588
B
U4B
4
R51
74HC14
100
B
PDN
PDN
DGND
A
A
Title
Size
A3
Date:
5
4
3
2
AKD4682-A
Document Number
INPUT/OUTPUT
Monday, November 20, 2006
Sheet
1
1
Rev
0
of
1
5
4
3
2
1
D
D
+
22u
C112
R55
J15
220
LOUT1
+
R54
10k
C37
2
3
1
4.7n
PVSS
22u
LOUT1
+
C35
R65
J28
220
ROUT1
+
R64
10k
MR-552LS
4.7n
PVSS
PVSS
C113
ROUT1
2
3
1
MR-552LS
PVSS
C
C
C41
R57
J16
220
LOUT2
+
R56
10k
+
22u
10k
C110
J17
10k
C40
4.7n
PVSS
+
22u
LOUT3
2
3
1
C42
10k
MR-552LS
PVSS
PVSS
MR-552LS
PVSS
R63
J27
220
ROUT3
R62
ROUT2
2
3
1
4.7n
PVSS
220
+
J18
220
R60
MR-552LS
R59
R58
R61
ROUT2
PVSS
LOUT3
B
2
3
1
4.7n
PVSS
C39
C38
22u
LOUT2
+
+
22u
+
C36
+
C111
4.7n
ROUT3
2
3
1
MR-552LS
B
PVSS
A
A
Title
Size
A3
Date:
5
4
3
2
AKD4682-A
Document Number
LOUT/ROUT
Monday, September 11, 2006
Sheet
1
Rev
0
1
of
1
5
4
3
2
DGND
PORTA_RX0
0.1u
C47
0.1u
D3.3V
1
D3.3V
C48
0.47u
U14B
4
74HC14
R76
18k
U14A
2
74HC14
3
D
1
H
C49
1
D3.3V
7
38
37
INT1
R
AVDD
39
40
VCOM
41
AVSS
42
NC
RX0
43
44
RX1
45
TEST1
46
47
NC
RX2
16
15
14
13
12
11
10
9
RX3
1
2
3
4
5
6
7
8
D3.3V
IPS0
INT0
36
1
14
OCKS0
OCKS1
U7
SW2
48
PORT A_DIR/4682
DIF0
DIF1
DIF2
CM0
2
NC
OCKS0
35
3
DIF0
OCKS1
34
4
TEST2
CM1
33
5
DIF1
CM0
32
6
NC
PDN
31
7
DIF2
XTI
30
R77
1k
U8A
2
D3.3V
SW3
0.1u
ATE1D-2M3
DIR PORTA
LED1
ERF
K
A
D3.3V
74HC04
DGND
PORTA_OCKS0
RP1
D3.3V
9
8
7
6
5
4
3
2
1
C
D2
HSU119
14
7
D3.3V
10k
D3.3V
A
DGND
DGND
K
R75
D3.3V
7
DGND
D
R74
75
MR-552LS
2
+
2
3
1
C45
10u
C46
14
J22
1
PORTA_CM0
PORTA_OCKS1
PORTA_OCKS0
PORTA_OCKS1
DGND
C
PORTA_CM0
47k
AK4114
C50
5p
EXA
IPS1
XTO
29
9
P/SN
DAUX
28
10
XTL0
MCKO2
27
11
XTL1
BICK
26
12
VIN
SDTO
25
C51
5p
2
X2
11.2896MHz
8
JP10 XTIA
1
DGND
DGND
DGND
SDTOB
MCLKA
BICKA
C52
0.1u
B
LRCK
JP13
SDTIA1_SEL
DIR
SDTIA1
GND
24
MCKO1
23
22
DVSS
DVDD
21
VOUT
20
UOUT
19
COUT
18
BOUT
17
16
TX0
15
14
13
DGND
DVSS
TVDD
B
TX1
LRCKA
C53
0.1u
DIR
SDTIA2
JP14
SDTIA2_SEL
2
1
C54
10u
4114_TVDD
+
1
+
GND
2
C55
10u
DGND
JP16
MCLKA_SEL
DGND
MCKO2
D3.3V
MCKO1
DGND
D3.3V
1
1
BNC
JP19
EXA50
7
2
3
4
5
A
14
EXA J29
JP17 BICKA
MCLKA
BICKA
LRCKA
SDTOB
1
2
3
4
5
PORT A
JP18 LRCKA
U9A
2
10 GND
9
8 SDTIA1
7 SDTIA2
6
PORT4
DGND
A1-10PA-2.54DSA
EXA
A
74VHC04
DGND
Title
R87
50
Size
A3
DGND
Date:
5
4
3
2
AKD4682-A
Document Number
PORT A
Monday, November 20, 2006
Sheet
1
1
Rev
0
of
1
5
4
3
2
1
DGND1
PORTB_RX0
2
0.1u
C58
0.1u
D3.3V
1
D3.3V
DGND1
D3.3V
U14C
5
D
C59
0.47u
DGND1
DVDD2
R82
18k
6
7
D3.3V
L
1
37
7
38
ATE1D-2M3
3
IPS0
DIT PORTB
D3.3V
INT1
R
AVDD
39
40
VCOM
41
AVSS
42
NC
RX0
43
44
RX1
45
TEST1
46
NC
RX2
47
48
U10
16
15
14
13
12
11
10
9
INT0
36
14
OCKS0
OCKS1
MSB
SW5
0.1u
RX3
CM0
H
C60
SW4
1
2
3
4
5
6
7
8
D
74HC14
PORT B_DIT
DIF0
DIF1
D3
HSU119
U14D
9
8
74HC14
10k
A
DGND1
R81
D3.3V
14
75
7
R80
MR-552LS
K
+
2
3
1
C57
10u
C56
14
J25
2
NC
OCKS0
35
3
DIF0
OCKS1
34
4
TEST2
CM1
33
5
DIF1
CM0
32
6
NC
PDN
31
7
DIF2
XTI
30
R83
1k
U8B
4
LED2
ERF
K
A
D3.3V
74HC04
DGND
PORTB_OCKS0
RP2
9
8
7
6
5
4
3
2
1
PORTB_CM0
PORTB_OCKS0
PORTB_OCKS1
MSB
DGND1
47k
DGND1
AK4114
C
PORTB_CM0
C61
5p
JP27
MCLKA
1
C
PORTB_OCKS1
C62
5p
EXB
MCLKB_SEL1
2
X3
12.288MHz
8
IPS1
XTO
29
9
P/SN
DAUX
28
10
XTL0
MCKO2
27
11
XTL1
BICK
26
12
VIN
SDTO
25
DGND1
DGND1
SDTOB
MCLKB
BICKB
2
LRCK
2
C66
10u
PORT5
JP46
DGND1
4114_TVDD
T3
DA02
2
3
1
MR-552LS
4
MCLKA
MCLKB_SEL2
8
R84
DGND1
1
DGND1
R85
5
MCLK
BICKB
LRCKB
SDTOB
150
JP28
240
D3.3V
EXB J30
DGND1
DGND1
1
BNC
3
JP20
EXA50
BICKA
4
EXB
BICKB_SEL
A
74VHC04
7
2
3
4
5
JP29
LRCKA
R86
LRCKB_SEL
50
Title
Size
A3
DGND1
Date:
5
4
10 GND
9
8
7
6
PORT B
U9B
A
1
2
3
4
5
14
PORTB_TX1
DGND1
A1-10PA-2.54DSA
MCKO2
MCKO1
D3.3V
J26
B
24
MCKO1
23
22
DVSS
DVDD
21
1
C65
10u
C64
0.1u
+
20
VOUT
UOUT
19
COUT
18
BOUT
17
16
15
14
TX0
DVSS
TVDD
13
1
C63
0.1u
+
DGND1
TX1
LRCKB
B
3
2
AKD4682-A
Document Number
PORT B
Monday, November 20, 2006
Sheet
1
1
Rev
0
of
1
5
4
3
2
1
TM_AVDD1
L2
T4
NJM78M05FA
+
C68
C69
47u
AVSS1
AVSS2
PVDD1
C71
AVSS2
AVSS2
AVDD2
T-45(O)
TVDD
T-45(O)
D3.3V
T-45(O)
D
47u
0.1u
AVSS2
AVDD1
T-45(O)
(short)
+
C70
0.1u
AVDD1
R94
1
1
(short)
IN
1
DVSS1
OUT
1
3
AVDD1_SEL
D
PVDD
T-45(R)
L4
REG
47u
1
C67
1
AVDD1
GND
R98
TM_PVDD
JP25
(short)
2
+
TM_PVDD
TM_AVDD2
TM_D3.3V
TM_AVDD1
TM_TVDD
AVSS2
DVDD1
AVSS2
T-45(B)
1
1
TM_AVDD2
AVSS1
T-45(B)
1
DGND
T-45(B)
(short)
L3
+
R95
JP26
(short)
47u
AVDD2_SEL
DVSS2
(short)
DGND AVSS1
AVDD2
R91
REG
C74
AVSS2
(short)
AVSS2
R97
AVDD2
T5
TA48M033F
DVDD2
(short)
C
IN
TM_TVDD
(open)
C
GND
R90
OUT
DGND
C79
C80
0.1u
0.1u
+
DVSS2
C81
47u
R96
L8
+
JP32
(short)
(open)
TVDD
C82
DVSS1
REG
47u
DVSS1
DGND1
TVDD_SEL
DVSS1
4682_TVDD
R93
4114_TVDD
(short)
TM_D3.3V
PVSS
AVSS2
L9
B
+
B
JP45
(short)
D3.3V
R92
REG
C114
47u
DGND
D3.3V_SEL
(short)
D3.3V
DGND
DGND
74HC04
U8F
12
13
74HC04
DGND
U9E
10
9
74VHC04
U9F
12
5
74VHC04
DGND
for 74HC14(U4), 74LS07(U3)
U4E
10
D3.3V
D3.3V
74HC04(U8), 74VHC04(U9), 74HC14(U14)
74HC14
14
14
7
14
7
74VHC04
74HC14
U4D
8
13
74HC14
7
11
11
U4F
12
14
U8E
10
U9D
8
14
7
74HC04
74VHC04
7
9
13
14
14
7
14
U8D
8
U9C
6
U4C
6
11
74HC14
7
13
74HC04
D3.3V
7
14
14
U3F
12
74LS07
7
13
7
14
7
11
7
14
11
A
U3E
10
74LS07
5
14
9
U8C
6
7
7
14
U3D
8
74LS07
7
9
7
14
7
5
14
U3C
6
74LS07
5
D3.3V
7
14
D3.3V
14
D3.3V
U14F
12
C88
C89
C90
C100
C101
0.1u
0.1u
0.1u
0.1u
0.1u
A
74HC14
DGND
U14E
10
Title
74HC14
Size
A3
DGND
Date:
5
4
3
2
AKD4682-A
Document Number
Power Supply
Monday, November 20, 2006
Sheet
1
Rev
0
1
of
1