AKM AKD4683

ASAHI KASEI
[AK4683]
AK4683
Asynchronous Multi-Channel Audio CODEC with DIR/T
GENERAL DESCRIPTION
The AK4683 is a single chip CODEC that includes two channels of ADC and four channels of DAC. The ADC
outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit
architecture with wide dynamic range. The DAC introduces the new developed Advanced Multi-Bit
architecture, and achieves wider dynamic range and lower outband noise. The also has digital audio receiver
(DIR) and transmitter (DIT) compatible with 192kHz, 24bits. The DIR can automatically detect a Non-PCM bit
stream such as Dolby Digital (AC-3)*.
The AK4683 has a dynamic range of 100dB for ADC, 106dB for DAC and is well suited for digital TV and
home theater system.
* Dolby Digital (AC-3) is a trademark of Dolby Laboratories.
FEATURES
† ADC/DAC part
† Asynchronous ADC/DAC Operation
† 6:1 Input Selector with Pre-amp
† 2ch 24bit ADC
- 64x Oversampling
- Sampling Rate up to 96kHz
- Linear Phase Digital Anti-Alias Filter
- Single-Ended Input
- S/(N+D): 90dB
- Dynamic Range, S/N: 100dB
- Digital HPF for Offset Cancellation
- Channel Independent Digital Volume (+24/-103dB, 0.5dB/step)
- Soft Mute
- Overflow Flag
† 4ch 24bit DAC
- 128x Oversampling
- Sampling Rate up to 192kHz
- 24bit 8 times Digital Filter
- Single-Ended Outputs
- S/(N+D): 90dB
- Dynamic Range, S/N: 106dB
- Channel Independent Digital Volume (+12/-115dB, 0.5dB/step)
- Soft Mute
- De-emphasis Filter (32kHz, 44.1kHz, 48kHz)
- Zero Detect Function
† Stereo Headphone Amp with Volume
- 50mW at 16ohm
- Click-noise free at Power on/off
† High Jitter Tolerance
MS0427-E-01
2005/11
-1-
ASAHI KASEI
[AK4683]
† DIR/DIT Part
- AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible
- Low jitter Analog PLL
- PLL Lock Range : 32kHz to 192kHz
- Clock Source: PLL or X'tal
- 4-channel Receiver input
- 1-channel Transmission output (Through output or DIT)
- Auxiliary digital input
- De-emphasis for 32kHz, 44.1kHz, 48kHz and 96kHz
- Detection Functions
• Non-PCM Bit Stream Detection
• DTS-CD Bit Stream Detection
• Sampling Frequency Detection
(32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz)
• Unlock & Parity Error Detection
• Validity Flag Detection
- Up to 24bit Audio Data Format
- 40-bit Channel Status Buffer
- Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream
- Q-subcode Buffer for CD bit stream
† TTL Level Digital I/F
† External Master Clock Input:
- 256fs, 384fs, 512fs (fs=32kHz ∼ 48kHz)
- 128fs, 192fs, 256fs (fs=64kHz ∼ 96kHz)
- 128fs (fs=120kHz ∼ 192kHz)
† Master Clock Output: 128fs/256fs/384fs/512fs
† 2 Audio Serial I/F (PORTA, PORTB)
- Master/Slave mode
- I/F format
PORTA: Left/Right(20/24 bit) justified, I2S, TDM
2
PORTB: Left/Right(20/24 bit) justified, I S
2
† 4-wire Serial and I C Bus µP I/F for mode setting
† Operating Voltage: 4.5 to 5.5V
† Power Supply for output buffer: 2.7 to 5.5V
† 64pin LQFP Package (0.5mm pitch)
MS0427-E-01
2005/11
-2-
ASAHI KASEI
[AK4683]
„ Block Diagram
RMCLK
RX0
RX1
RX2
RX3
Clock
Recovery
4:2
Input
Selector
XTO
DAIF
Decoder
X’tal
Oscillator
XTI
LISEL
LOPIN
LIN1
LIN2
LIN3
LIN4
LIN5
LIN6
IPS0/1, OPS0/1 bit
MCLK2
HPF,
DVOL
ADC
LIN0/1/2, RIN0/1/2 bit
RIN1
RIN2
RIN3
RIN4
RIN5
RIN6
MCKO
ADC
Audio
I/F
PORTB
BICKB
LRCKB
DIR
HPF,
DVOL
ADC
ADC
SDOUT
SDTIA1
off
SDTOB0/1 bit
ROPIN
RISEL
SDTIB
DIR
Through
ADC
TX
DIT
DIT
DIT0/1 bit
ROUT1
LPF
DAC
DVOL
LPF
DAC
DVOL
LOUT2
LPF
ROUT2
LPF
I2C
SDTIB
SDTIA1
DIT bit
LOUT1
SDTOB
DAC
DAC
DVOL
DVOL
µP
DIR
I/F
ADC
SDTIB
DAC1
Audio
I/F
CSN
CCLK
CDTI
CDTO
SDTIA1
SDTIA2
SDTIA3
DAC2
Audio
I/F
DIR
DIR
ADC
ADC
SDTIB
SDTIB
SDTIA1
off
SDTIA2
SDTIA3
SDTOA0/1 bit
PORTA
SDTOA
OLRCKA
BICKA
ILRCKA
DAC10/11/12,
HPL
DAC20/21/22 bit
HPR
MS0427-E-01
SDTIA1
SDTIA2
SDTIA3
2005/11
-3-
ASAHI KASEI
[AK4683]
„ Ordering Guide
-20 ∼ +85°C
64pin LQFP (0.5mm pitch)
Evaluation Board for AK4683
AK4683EQ
AKD4683
AVSS1
AVDD1
LIN1
RIN1
LIN2
RIN2
LIN3
RIN3
LIN4
RIN4
LIN5
RIN5
LIN6
RIN6
PVSS
R
„ Pin Layout
PVDD
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
RISEL
RX0
2
47
ROPIN
I2C
3
46
LOPIN
RX1
4
45
LISEL
RX2
5
44
AVSS2
RX3
6
43
AVDD2
INT
7
42
VCOM
VOUT
8
41
ROUT2
40
LOUT2
AK4683EQ
Top View
13
36
HPL
ILRCKA
14
35
HPR
BICKA
15
34
HVSS
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
HVDD
MCKO
SDTOA
SDTIB
OLRCKA
SDTIA3
MUTET
SDTIA2
37
SDTIA1
12
CSN
SDTOB
CCLK
LOUT2
CDTI
38
PDN
11
MCLK2
BICKB
TX
ROUT2
XTO
39
XTI
10
DVDD
LRCKB
DVSS
9
TVDD
CDTO
„ Compatibility with AK4588
Functions
DAC, ADC Asynchronous operation
DAC ch#
HP-Amp
ADC Input selector
AK4588
NOT Available
8ch
-
MS0427-E-01
AK4683
Available
4ch
2ch
6:1
2005/11
-4-
ASAHI KASEI
[AK4683]
PIN/FUNCTION
No.
1
2
Pin Name
PVDD
RX0
I/O
I
3
I2C
I
4
5
6
7
RX1
RX2
RX3
INT
VOUT
I
I
I
O
O
8
DZF
O
OVF
O
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CDTO
LRCKB
BICKB
SDTOB
OLRCKA
ILRCKA
BICKA
SDTOA
MCKO
TVDD
DVSS
DVDD
XTI
XTO
O
I/O
I/O
O
I/O
I/O
I/O
O
O
I
O
23
TX
O
24
MCLK2
I
25
PDN
I
29
30
31
32
33
34
35
36
CDTI
SDA
CCLK
SCL
CSN
TEST
SDTIA1
SDTIA2
SDTIA3
SDTIB
HVDD
HVSS
HPR
HPL
I
I/O
I
I
I
I
I
I
I
I
O
O
37
MUTET
-
26
27
28
Function
PLL Power supply Pin, 4.5V∼5.5V
Receiver Channel 0 Pin (Internal biased pin. Internally biased at PVDD/2)
Control Mode Select Pin.
“L”: 4-wire Serial, “H”: I2C Bus
Receiver Channel 1 Pin
Receiver Channel 2 Pin
Receiver Channel 3 Pin
Interrupt Pin
V-bit Output Pin for Receiver Input
Zero Input Detect Pin
When the input data of DAC follow total 8192 LRCK cycles with “0” input data, this
pin goes to “H”. And when RSTN1 bit is “0”, PWDA bit is “0”, this pin goes to “H”.
Analog Input Overflow Detect Pin
This pin goes to “H” if the analog input of Lch or Rch overflows.
Control Data Output Pin in Serial Mode and I2C pin = “L”.
Channel Clock B Pin
Audio Serial Data Clock B Pin
Audio Serial Data Output B Pin
Output Channel Clock A Pin
Input Channel Clock A Pin
Audio Serial Data Clock A Pin
Audio Serial Data Output A Pin
Master Clock Output Pin
Output Buffer Power Supply Pin, 2.7V∼5.5V
Digital Ground Pin, 0V
Digital Power Supply Pin, 4.5V∼5.5V
X'tal Input Pin
X'tal Output Pin
Transmit Channel Output pin
When DIT bit = “0”, RX0~3 Through.
When DIT bit = “1”, Internal DIT Output.
Master Clock Input Pin
Power-Down Mode & Reset Pin
When “L”, the AK4683 is powered-down, all registers are reset. And then all digital
output pins go “L”. The AK4683 must be reset once upon power-up.
Control Data Input Pin in Serial Mode and I2C pin = “L”.
Control Data Pin in Serial Mode and I2C pin = “H”.
Control Data Clock Pin in Serial Mode and I2C pin = “L”
Control Data Clock Pin in Serial Mode and I2C pin = “H”
Chip Select Pin in Serial Mode and I2C pin = “L”.
This pin should be connected to DVSS in Serial Mode and I2C pin = “H”.
Audio Serial Data Input A1 Pin
Audio Serial Data Input A2 Pin
Audio Serial Data Input A3 Pin
Audio Serial Data Input B Pin
HP Power Supply Pin, 4.5V∼5.5V
HP Ground Pin, 0V
HP Rch Output Pin
HP Lch Output Pin
HP Common Voltage Output Pin
1µF capacitor should be connected to HVSS externally.
MS0427-E-01
2005/11
-5-
ASAHI KASEI
[AK4683]
No.
38
39
40
41
Pin Name
LOUT2
ROUT2
LOUT1
ROUT1
I/O
O
O
O
O
42
VCOM
-
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
AVDD2
AVSS2
LISEL
LOPIN
ROPIN
RISEL
AVSS1
AVDD1
LIN1
RIN1
LIN2
RIN2
LIN3
RIN3
LIN4
RIN4
LIN5
RIN5
LIN6
RIN6
PVSS
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
-
64
R
-
Function
DAC2 Lch Positive Analog Output Pin
DAC2 Rch Positive Analog Output Pin
DAC1 Lch Positive Analog Output Pin
DAC1 Rch Positive Analog Output Pin
DAC/ADC Common Voltage Output Pin
2.2µF capacitor should be connected to AVSS2 externally.
DAC Power Supply Pin, 4.5V∼5.5V
DAC Ground Pin, 0V
Lch Feedback Resistor Output Pin
Lch Feedback Resistor Input Pin. 0.5 x AVDD1.
Rch Feedback Resistor Input Pin. 0.5 x AVDD1.
Rch Feedback Resistor Output Pin
ADC Ground Pin, 0V
ADC Power Supply Pin, 4.5V∼5.5V
Lch Input 1 Pin
Rch Input 1 Pin
Lch Input 2 Pin
Rch Input 2 Pin
Lch Input 3 Pin
Rch Input 3 Pin
Lch Input 4 Pin
Rch Input 4 Pin
Lch Input 5 Pin
Rch Input 5 Pin
Lch Input 6 Pin
Rch Input 6 Pin
PLL Ground pin
External Resistor Pin
12kΩ +/-1% resistor should be connected to PVSS externally.
Note: All input pins except internal biased pin (RX0) and analog input pins (LIN1-6, RIN1-6) should not be left
floating.
„ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
RX0, LOUT1-2, ROUT1-2, LIN1-6, RIN1-6
INT, XTO, MCKO, VOUT/DZF/OVF, SDTOA-B,
CDTO, TX
RX1-3, CSN, CCLK, CDTI, XTI, MCLK2,
OLRCKA, ILRCKA, BICKA, SDTIA1-3,
LRCKB, BICKB, SDTIB
MS0427-E-01
Setting
These pins should be open.
These pins should be open.
These pins should be connected to DVSS.
2005/11
-6-
ASAHI KASEI
[AK4683]
ABSOLUTE MAXIMUM RATINGS
(AVSS1, AVSS2, DVSS, PVSS, HVSS=0V; Note 1)
Parameter
Symbol
min
-0.3
Power Supplies
ADC Analog
AVDD1
-0.3
DAC Analog
AVDD2
-0.3
Headphone Analog
HVDD
-0.3
Digital
DVDD
-0.3
PLL
PVDD
-0.3
Output buffer
TVDD
|AVSS2-AVSS1| (Note 2)
∆GND1
|AVSS2-DVSS|
(Note 2)
∆GND2
|AVSS2-PVSS|
(Note 2)
∆GND3
|AVSS2-HVSS|
(Note 2)
∆GND4
Input Current (any pins except for supplies)
Analog Input Voltage
(LIN, RIN pins)
Digital Input Voltage
Except for ILRCKA, OLRCKA, LRCKB,
BICKA-B, RX0, I2C pins
ILRCKA, OLRCKA, LRCKB, BICKA-B pins
RX0, I2Cpins
Ambient Temperature (power applied)
Storage Temperature
max
6.0
6.0
6.0
6.0
6.0
6.0
0.3
0.3
0.3
0.3
Units
V
V
V
V
V
V
V
V
V
V
IIN
-
±10
mA
VINA
-0.3
AVDD1+0.3
V
VIND1
-0.3
DVDD+0.3
V
VIND2
VIND3
Ta
Tstg
-0.3
-0.3
-20
-65
TVDD+0.3
PVDD+0.3
85
150
V
V
°C
°C
Notes:
1. All voltages with respect to ground.
2.AVSS, DVSS and PVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS, PVSS=0V; Note 3)
Parameter
Symbol
min
typ
5.0
4.5
AVDD1
Power Supplies
ADC Analog
5.0
4.5
AVDD2
(Note 4)
DAC Analog
5.0
AVDD2
HVDD
Headphone Analog
5.0
4.5
DVDD
Digital
5.0
4.5
PVDD
PLL
5.0
2.7
TVDD
Output buffer
0
-0.3
|DVDD - AVDD1|
∆VDD1
0
-0.3
|DVDD - AVDD2|
∆VDD2
0
-0.3
|DVDD - HVDD|
∆VDD3
0
-0.3
|DVDD - PVDD|
∆VDD4
0
-0.1
|AVDD1 – AVDD2|
∆VDD5
max
5.5
5.5
5.5
5.5
5.5
DVDD
+0.3
+0.3
+0.3
+0.3
+0.1
Units
V
V
V
V
V
V
V
V
V
V
V
Notes:
3. All voltages with respect to ground.
4. The power up sequences among AVDD1, AVDD2, DVDD, PVDD, HVDD and TVDD are not critical.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0427-E-01
2005/11
-7-
ASAHI KASEI
[AK4683]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD1, AVDD2, HVDD, DVDD, PVDD, TVDD=5V; AVSS1, AVSS2, HVSS, DVSS, PVSS=0V;
fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at fs=48kHz,
20Hz~40kHz at fs=96kHz; 20Hz~40kHz at fs=192kHz, all blocks are synchronized, unless otherwise specified)
Parameter
min
typ
max
Units
Pre-Amp Characteristics:
Feedback Resistance
10
50
kΩ
S/(N+D)
(Note 5)
100
dB
S/N
(A-weighted) (Note 5)
108
dB
Load Capacitance
20
pF
ADC Analog Input Characteristics (note 6)
Resolution
24
Bits
S/(N+D)
(-0.5dBFS) fs=48kHz
84
92
dB
fs=96kHz
86
dB
DR
(-60dBFS) fs=48kHz, A-weighted
92
100
dB
fs=96kHz
96
dB
fs=96kHz, A-weighted
100
dB
dB
100
92
S/N
(Note 7)
fs=48kHz, A-weighted
dB
96
fs=96kHz
dB
100
fs=96kHz, A-weighted
Interchannel Isolation
(Note 8)
90
105
dB
Interchannel Gain Mismatch
0.2
0.5
dB
Gain Drift
50
ppm/°C
Input Voltage (note 6)
AIN=1.22xAVDD1
5.7
6.1
6.5
Vpp
Power Supply Rejection
(Note 9)
50
dB
DAC Analog Output Characteristics
Resolution
24
Bits
dB
90
80
S/(N+D)
fs=48kHz
dB
88
fs=96kHz
dB
88
fs=192kHz
DR
(-60dBFS)
fs=48kHz, A-weighted
95
106
dB
fs=96kHz
100
dB
fs=96kHz, A-weighted
106
dB
fs=192kHz
100
dB
fs=192kHz, A-weighted
106
dB
S/N
(Note 10)
fs=48kHz, A-weighted
95
106
dB
fs=96kHz
100
dB
fs=96kHz, A-weighted
106
dB
fs=192kHz
100
dB
fs=192kHz, A-weighted
106
dB
Interchannel Isolation
90
110
dB
Interchannel Gain Mismatch
0.2
0.5
dB
Gain Drift
50
ppm/°C
Output Voltage
AOUT=0.6xAVDD2
2.75
3.0
3.25
Vpp
Load Resistance
(AC Load)
5
kΩ
Load Capacitance
30
pF
Power Supply Rejection
(Note 9)
50
dB
MS0427-E-01
2005/11
-8-
ASAHI KASEI
[AK4683]
Analog Volume Characteristics (OPGA):
+0dB ∼ -16dB
0.1
-16dB ∼ -38dB
0.1
-38dB ∼ -50dB
Headphone-Amp Characteristics: DAC → HPL/HPR pins, RL=16Ω
Output Voltage
(0.506xHVDD)
1.94
S/(N+D)
(−3dBFS)
S/N
(A-weighted)
Interchannel Isolation
Interchannel Gain Mismatch
Load Resistance
16
C1 in Figure 1
Load Capacitance
C2 in Figure 1
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
(Note 11)
AVDD1+ AVDD2
fs=48kHz, fs=96kHz
fs=192kHz
HVDD
PVDD
DVDD+TVDD
fs=48kHz
(Note 12)
fs=96kHz
fs=192kHz
Power-down mode (PDN pin = “L”)
(Note 13)
Step Size:
HP-Amp
1
2
4
-
dB
dB
dB
2.43
70
90
80
0.1
-
2.92
0.5
30
300
Vpp
dBFS
dB
dB
dB
Ω
pF
pF
37
19
7
8
35
45
55
80
52
27
10
11
49
63
77
200
mA
mA
mA
mA
mA
mA
mA
µA
HPL, HPR
-
+
+
C1
C2
16Ω
Figure 1. Headphone Amplifier output circuit
Notes:
5. Measured at LISEL/RISEL pins when the input resistor=47kohm, the feedback resistor=24kohm and input level
=2Vrms.
6. Measured through Pre-Amp -> ADC. Input resistor=47kohm, feedback resistor=24kohm.
7. S/N measured by CCIR-ARM is 96dB(@fs=48kHz).
8. This value is the interchannel isolation between all the channels of the LIN1-6 and RIN1-6.
9. PSR is applied to AVDD, DVDD, PVDD and TVDD with 1kHz, 50mVpp.
10. S/N measured by CCIR-ARM is 102dB(@fs=48kHz).
11. CL=20pF, X'tal=24.576MHz, CM1-0=“10”, CM1-0=“10”, OCKS1-0="10"@48kHz,"00"@96kHz,
"11"@192kHz. Headphone = No output. The resister network is attached to TX pin.
12. TVDD=6mA([email protected]=48kHz), 7mA([email protected]=96kHz), 10mA([email protected]=192kHz).
13. In the power-down mode. RX0 input is open and all digital input pins including clock pins (MCLK2, BICKA,
BICKB, ILRCKA, OLRCKA, BICKB pins) and RX1-3 pins are held DVSS.
MS0427-E-01
2005/11
-9-
ASAHI KASEI
[AK4683]
FILTER CHARACTERISTICS
(Ta=25°C; AVDD1, AVDD2, DVDD, PVDD, HVDD=4.5∼5.5V; TVDD=2.7∼5.5V; fs=48kHz)
Parameter
Symbol
min
typ
max
ADC Digital Filter (Decimation LPF):
18.9
PB
0
Passband
±0.1dB
20.0
(Note 14)
-0.2dB
23.0
-3.0dB
Stopband
SB
28.0
Passband Ripple
PR
±0.04
Stopband Attenuation
SA
68
Group Delay
(Note 15)
GD
19
Group Delay Distortion
0
∆GD
ADC Digital Filter (HPF):
Frequency Response (Note 14)
-3dB
FR
1.0
-0.1dB
6.5
DAC Digital Filter:
Passband
(Note 14)
-0.1dB
PB
0
21.8
-6.0dB
24.0
Stopband
SB
26.2
Passband Ripple
PR
±0.02
Stopband Attenuation
SA
54
Group Delay
(Note 15)
GD
21
DAC Digital Filter + Analog Filter:
FR
±0.2
Frequency Response:
0 ∼ 20.0kHz
FR
40.0kHz (Note 16)
±0.3
FR
80.0kHz (Note 16)
±1.0
Units
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
Hz
Hz
kHz
kHz
kHz
dB
dB
1/fs
dB
dB
dB
Notes:
14. The passband and stopband frequencies scale with fs.
For example, 21.8kHz at –0.1dB is 0.454 x fs (DAC). The reference frequency of these responses is 1kHz.
15. The calculating delay time which occurred by digital filtering. This time is from setting the input of analog signal
to setting the 24bit data of both channels to the output register of PORTA or PORTB.
For DAC, this time is from setting the 20/24bit data of both channels on input register of PORTA or PORTB to
the output of analog signal.
16. [email protected]=96kHz, [email protected]=192kHz
MS0427-E-01
2005/11
- 10 -
ASAHI KASEI
[AK4683]
DC CHARACTERISTICS
(Ta=25°C; AVDD1, AVDD2, DVDD, PVDD, HVDD=4.5∼5.5V; TVDD=2.7∼5.5V)
Parameter
Symbol
min
typ
High-Level Input Voltage
(Except XTI pin)
VIH
2.2
(XTI pin)
VIH
70%DVDD
Low-Level Input Voltage
(Except XTI pin)
VIL
(XTI pin)
VIL
Input Voltage at AC Coupling (XTI pin) (Note 17)
VAC
40%DVDD
High-Level Output Voltage
(Except TX pins: Iout=-400µA)
VOH
TVDD-0.4
(TX pin: Iout=-400µA)
VOH
DVDD-0.4
Low-Level Output Voltage
(Iout=400µA)
VOL
Iin
Input Leakage Current (Except RX0 pin)
Notes:
17. In case of connecting capacitance to XTI pin.
S/PDIF RECEIVER CHARACTERISTICS (RX0)
(Ta=25°C; AVDD1, AVDD2, DVDD, PVDD, HVDD=4.5∼5.5V; TVDD=2.7∼5.5V)
Parameter
Symbol
min
typ
Input Resistance
Zin
10
Input Voltage (internally biased at PVDD/2)
VTH
200
Input Hysteresis
VHY
50
Input Sample Frequency
fs
32
-
max
0.8
30%DVDD
-
Units
V
V
V
V
Vpp
0.4
±10
V
V
V
µA
max
Units
kΩ
mVpp
mV
kHz
192
PVDD
RX0 pin
20k(typ)
20k(typ)
PVSS
VCOM
Internal biased pin Circuit
S/PDIF RECEIVER CHARACTERISTICS (RX1-3)
(Ta=25°C; AVDD1, AVDD2, DVDD, PVDD, HVDD=4.5~5.5V;TVDD=2.7~5.5V)
Parameter
Symbol
min
typ
High-Level Input Voltage
VIH
2.2
Low-Level Input Voltage
VIL
Input Sample Frequency
fs
32
Iin
Input Leakage Current
-
MS0427-E-01
max
0.8
192
±10
Units
V
V
kHz
µA
2005/11
- 11 -
ASAHI KASEI
[AK4683]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD1, AVDD2, DVDD, PVDD, HVDD=4.5∼5.5V; TVDD=2.7∼5.5V; CL=20pF; Note 18)
Parameter
Symbol
min
typ
max
Master Clock Timing
Crystal Resonator Frequency
fXTAL
11.2896
24.576
External Clock
Frequency
fECLK
4.096
24.576
Duty
dECLK
40
50
60
24.576
4.096
fMCK
MCKO Output
Frequency
60
40
50
dMCLK
Duty
(Note 19)
33
dMCK
(Note 20)
PLL Clock Recover Frequency (RX0-3)
fpll
32
192
Master Clock
12.288
8.192
fCLK
256fsn, 128fsd:
27
tCLKL
Pulse Width Low
27
tCLKH
Pulse Width High
18.432
12.288
fCLK
384fsn, 192fsd:
20
tCLKL
Pulse Width Low
20
tCLKH
Pulse Width High
24.576
16.384
fCLK
512fsn, 256fsd, 128fsq:
15
tCLKL
Pulse Width Low
15
tCLKH
Pulse Width High
LRCKA (LRCKB) Timing (Slave Mode)
Normal mode
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
TDM 256 mode
LRCKA frequency
“H” time
“L” time
TDM 128 mode
LRCKA frequency
“H” time
“L” time
LRCKA (LRCKB) Timing (Master Mode)
Normal mode
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
TDM 256 mode
LRCKA frequency
“H” time
(Note 21)
TDM 128 mode
LRCKA frequency
“H” time
(Note 21)
Power-down & Reset Timing
PDN Pulse Width
(Note 22)
PDN “↑” to SDTO valid
(Note 23)
Units
MHz
MHz
%
MHz
%
%
kHz
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
fsn
fsd
fsq
Duty
32
64
120
45
48
96
192
55
kHz
kHz
kHz
%
fsd
tLRH
tLRL
32
1/256fs
1/256fs
48
kHz
ns
ns
fsd
tLRH
tLRL
64
1/128fs
1/128fs
96
kHz
ns
ns
fsn
fsd
fsq
Duty
32
64
120
48
96
192
kHz
kHz
kHz
%
fsn
tLRH
32
48
kHz
ns
fsd
tLRH
64
96
1/4fs
kHz
ns
tPD
tPDV
150
522
ns
1/fs
50
1/8fs
Notes:
18. SDTOA is specified against OLRCKA, SDTIA1-3 are measured against ILRCKA.
19. When MCKO1-0 bits = “01”, “10” or MCKO1-0 bits = “00” and CKSDT bit = “0”.
20. When MCKO1-0 bits = “00” and CKSDT bit = “1” and the EXTCLK is selected by CM1-0 bits.
Duty = (“H” width) / (clock cycle) x 100
21. “L” time at I2S format
22. The AK4683 can be reset by bringing PDN “L” to “H” upon power-up.
23. These cycles are the number of LRCKA (LRCKB) rising from PDN rising.
MS0427-E-01
2005/11
- 12 -
ASAHI KASEI
[AK4683]
Parameter
Audio Interface Timing (Slave Mode)
Normal mode
BICKA (BICKB) Period
BICKA (BICKB) Pulse Width Low
Pulse Width High
LRCKA (LRCKB) Edge to BICKA (BICKB) “↑” (Note 24)
BICKA (BICKB) “↑” to LRCKA (LRCKB) Edge (Note 24)
LRCKA (LRCKB) to SDTOA, SDTOB (MSB)
BICKA (BICKB) “↓” to SDTOA, SDTOB
SDTIA1-3, SDTIB Hold Time
SDTIA1-3, SDTIB Setup Time
TDM 256 mode
BICKA Period
BICKA Pulse Width Low
Pulse Width High
LRCKA Edge to BICKA “↑”
(Note 24)
BICKA “↑” to LRCKA Edge
(Note 24)
BICKA “↓” to SDTOA
SDTIA1 Hold Time
SDTIA1 Setup Time
TDM 128 mode
BICKA Period
BICKA Pulse Width Low
Pulse Width High
LRCKA Edge to BICKA “↑”
(Note 24)
BICKA “↑” to LRCKA Edge
(Note 24)
BICKA “↓” to SDTOA
SDTIA1-2 Hold Time
SDTIA1-2 Setup Time
Audio Interface Timing (Master Mode)
Normal mode
BICKA (BICKB) Frequency
BICKA (BICKB) Duty
BICKA (BICKB) “↓” to LRCKA (LRCKB) Edge
BICKA (BICKB)“↓” to SDTO
SDTIA1-3, B Hold Time
SDTIA1-3, B Setup Time
TDM 256 mode
BICKA Frequency
BICKA Duty
(Note 25)
BICKA “↓” to LRCKA Edge
BICKA “↓” to SDTOA
SDTIA1 Hold Time
SDTIA1 Setup Time
TDM 128 mode
BICKA Frequency
BICKA Duty
(Note 26)
BICKA “↓” to LRCKA Edge
BICKA “↓” to SDTOA
SDTIA1-2 Hold Time
SDTIA1-2 Setup Time
Symbol
min
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
81
32
32
20
20
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
typ
max
20
20
20
20
20
10
10
20
10
10
64fs
50
-20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
12
20
Hz
%
ns
ns
ns
ns
12
20
Hz
%
ns
ns
ns
ns
256fs
50
10
10
128fs
50
-12
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
ns
ns
20
20
-12
Units
10
10
Notes:
24. BICK rising edge must not occur at the same time as LRCK edge.
25. When MCLK2/XTI is 512fs, dBCK is guaranteed. When 384fs and 256fs, dBCK can not be guaranteed.
26. When MCLK2/XTI is 256fs, dBCK is guaranteed. When 128fs, dBCK can not be guaranteed.
MS0427-E-01
2005/11
- 13 -
ASAHI KASEI
[AK4683]
Parameter
Control Interface Timing (4-wire serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
Control Interface Timing (I2C Bus mode)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 27 )
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
Symbol
min
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
50
50
150
50
50
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
tSP
4.7
4.0
4.7
4.0
4.7
0
0.25
4.0
0
typ
max
Units
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
1.0
0.3
50
400
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
pF
Notes:
27. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
28. I2C is a registered trademark of Philips Semiconductors.
MS0427-E-01
2005/11
- 14 -
ASAHI KASEI
[AK4683]
„ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fsn, 1/fsd, 1/fsq
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing (Normal mode)
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fsn, 1/fsd
VIH
LRCK
VIL
tLRH
tLRL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing (TDM 256 mode, TDM 128 mode)
LRCK= LRCKB, ILRCKA, OLRCKA,
BICK= BICKA, BICKB,
SDTI= SDTIA, SDTIB,
SDTO= SDTOA, SDTOB.
MS0427-E-01
2005/11
- 15 -
ASAHI KASEI
[AK4683]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tLRS
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
Audio Interface Timing (Normal mode)
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
Audio Interface Timing (TDM 256 mode, TDM 128 mode)
MS0427-E-01
2005/11
- 16 -
ASAHI KASEI
[AK4683]
LRCK
50%TVDD
tMBLR
50%TVDD
BICK
tBSD
50%TVDD
SDTO
tDXS
tDXH
VIH
SDTI
VIL
Audio Interface timing (Master Mode)
tPD
PDN
VIL
Power Down & Reset Timing
MS0427-E-01
2005/11
- 17 -
ASAHI KASEI
[AK4683]
VIH
CSN
VIL
tCSS
tCCK
tCCKL tCCKH
VIH
CCLK
VIL
tCDH
tCDS
C1
CDTI
C0
A4
R/W
VIH
VIL
Hi-Z
CDTO
WRITE/READ Command Input Timing in 4-wire serial mode
The ADC/DAC part doesn’t support READ command.
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
VIH
D0
VIL
Hi-Z
CDTO
WRITE Data Input Timing in 4-wire serial mode
VIH
CSN
VIL
VIH
CCLK
VIL
CDTI
A1
VIH
A0
VIL
tDCD
CDTO
Hi-Z
D7
D6
D5
50%TVDD
READ Data Output Timing 1 in 4-wire serial mode
The ADC/DAC part doesn’t support READ command..
MS0427-E-01
2005/11
- 18 -
ASAHI KASEI
[AK4683]
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
VIL
tCCZ
CDTO
D3
D2
D1
D0
Hi-Z
50%TVDD
READ Data Input Timing 2 in 4-wire serial mode
The ADC/DAC part doesn’t support READ command.
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
I2C Bus mode Timing
The ADC/DAC part doesn’t support READ command.
tPD
VIH
PDN
VIL
tPDV
SDTO
50%TVDD
Power-down & Reset Timing
MS0427-E-01
2005/11
- 19 -
ASAHI KASEI
[AK4683]
OPERATION OVERVIEW (General)
„ Device Configuration and System Clocks
The AK4683 integrates the stereo ADC with input selector, 4ch DAC with stereo HP amp, DIT and DIT. The AK4683
has two serial audio interfaces (PORTA, B) for two input/output dataset (Figure 2). Each block can independently select
the operation clock from the three clock sources (recovered clock from DIR (RMCLK), X’tal clock (XTI) and external
clock (MCLK2)) and also input data source/output data destination. By using the Clock Gen C, the loop-back such as
AD-DA can operate even if the PORTA/B are powered down.
DIR
XTI
MCKO
MCLK2
MCKO0/1 bit
DIR
DIR
XTI
PORTA
DIR
XTI
MCLK2
X’tal
Oscillator
(XTI)
CLKB0/1 bit
DIR
XTI
MCLK2
MCLK2
CLKA0/1 bit
Clock
Gen A
MCLK2
DIR
XTI
PORTB
MCLK2
DAC
Clock
Gen B
DIR
XTI
DIR
XTI
MCLK2
ADC
MCLK2
Clock
DIT
Gen C
CLKL0/1 bit
Note
Figure 2 System Clock
Note: Each block must select the same clock source each other when connected. The operation will not be normal when
the clock sources are not same among a connection. The ADC and DAC are synchronized to the clock source that
the connected block uses. Even if the RMCLK is selected, the X’tal/MCLK2 may be chosen by the setting of
CM1-0bits. DIR and DIT must be synchronized when these two blocks operates.
MS0427-E-01
2005/11
- 20 -
ASAHI KASEI
[AK4683]
„ X’tal Oscillator
The following circuits are available to feed the clock to XTI pin of the AK4683.
1) X’tal
XTI
C
25kΩ(typ)
C
XTO
AK4683
Note: External capacitance depends on the crystal oscillator (Typ. 10-40pF)
Figure 3. X’tal mode
2) External clock
- Note: Input clock must not exceed DVDD.
XTI
C
External
Clock
XTI
External
Clock
25kΩ(typ)
25kΩ(typ)
XTO
XTO
AK4683
AK4683
(Input: ≥40%DVDD, C=0.1µF)
(Input: CMOS Level)
Figure 4 (5V). (a). External clock mode
Figure 5 (3.3V). (b). External clock mode
3) XTI/XTO are not used
XTI
25kΩ(typ)
XTO
AK4683
Figure 6. OFF mode
MS0427-E-01
2005/11
- 21 -
ASAHI KASEI
[AK4683]
„ Master Clock Output
The AK4683 has one master clock output pin. The clock source can be selected from the three clocks (recovered clock
from DIR (RMCLK), X’tal clock (XTI) and external clock (MCLK2)). When the DIR is powered-down or unlocked
state at CM1/0 bit = “10”, the CLKDT bit selects the clock source. The OCKS1/0 bits select the clock speed. The 512fs
at fs=96kHz, 256fs/512fs at fs=192kHz are not available.
CM1 bit
0
0
CM0 bit
0
1
1
0
1
1
UNLOCK
0
1
-
Clock Source
RMCLK
EXTCLK
RMCLK
EXTCLK
EXTCLK
Table 1. Clock Mode Control
CLKDT bit
0
1
Clock Source
XTI
MCLK2
Default
Table 2. EXTCLK Control
OCKS1 bit
0
0
1
1
OCKS0 bit
0
1
0
1
MCLKO(RMCLK)
256fs
256fs
512fs
128fs
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
Table 3. MCLKO Speed
MCKO1 bit
0
0
1
1
MCKO0 bit
0
1
0
1
MCKO Clock Source
DIR
X’tal(XTI)
MCLK2
Reserved
default
Table 4. MCKO Clock Source Control
OCKS1/0 bit
RMCLK
PLL
EXTCLK
CM0/1 bit
x2/3
CKSDT bit
CLKDT bit
DIR
X’tal
Oscillator
(XTI)
XTI
MCLK2
MCKO
MCKO0/1 bit
MCLK2
Figure 7. MCKO Clock
MS0427-E-01
2005/11
- 22 -
ASAHI KASEI
[AK4683]
„ Master/Slave Mode Change
MSA and MSB bits control the master/slave mode of PORTA and PORTB respectively. The “1” is for master mode,
“0” is for slave mode. The AK4683 is slave mode at power-down (PDN pin = “L”). To change to the master mode,
write “1” to MSA/MSB bit. The ACKSAI, ACKSAO and ACKSB bits are ignored in master mode. Until when writing
“1” to MSA/MSB bit, the ILRCKA, OLRCKA, BICKA, LRCKB and BICKB pin are input pins. Pull-up(or down)
resistor with around 100kohm is required to prevent the floating of these input pins.
MSA, MSB bit
Mode
0
Slave Mode
(default)
1
Master Mode
Table 5. Select Master/Salve Mode
„ Other Detection Function
The FUNC1-0 bit selects the function of VOUT pin.
Mode
0
1
2
3
FUNC1
0
0
1
1
FUNC0
Mode
0
OFF (“L”)
1
ADC Overflow Detection
0
DAC Zero Detection
1
V bit output
Table 6. Detection Function Control
Default
1. Overflow Detection
The AK4683 has overflow detect function for analog input. Overflow detect function is enable if OVFE bit is set to “1”.
OVF pin goes to “H” if analog input of Lch or Rch overflows (more than -0.3dBFS). OVF output for overflowed analog
input has the same group delay as ADC (GD = 19/fs = 396µs @fs=48kHz). OVF pin is “L” for 522/fs (=10.9ms
@fs=48kHz) after PDN = “↑”, and then overflow detection is enabled. The overflow detection is applied to the data
between the digital HPF and the DATT.
2. Zero Detection
The AK4683 has one pin for zero detect flag output. The DZFM1-0 bits select the channel grouping (Table 7). The DZF
pin goes “H” when all of the enabled channels are continuously zeros for 8192 LRCK cycles. DZF pin immediately
goes to “L” if input data of any enabled channel is not zero after going DZF “H”.
Mode
DZFM1
bit
DZFM0
bit
0
1
2
3
0
0
1
1
0
1
0
1
L1
Enable
Enable
-
AOUT
R1
L2
Enable Enable
Enable
Enable
-
R2
Enable
Enable
-
(default)
Table 7. Zero Detection Control
3. Validity Detection
The AK4683 has Validity Detection function. DIR decodes the V bit and output “H” via pin. When unlocked, “L” is
output.
MS0427-E-01
2005/11
- 23 -
ASAHI KASEI
[AK4683]
OPERATION OVERVIEW (ADC/DAC/PORTA, B part)
„ System Clock
The AK4683 has two audio serial interface (PORTA, B), can operate these PORTs with asynchronous. At each PORT,
the external clocks, which are required to operate the AK4683, are MCLK, LRCK and BICK. The MCLK should be
synchronized with LRCK but the phase is not critical.
The CLKA1-0, CLKB1-0bits select the clock sources for each PORT (Table 8, Table 9). The MSA and MSB bits select
the master/slave mode (Table 16, Table 17).
The block that is connected to PORTA/B and the block that is connected to the PORT indirectly operate at the same
clock as the PORTA/B selects. e. g. When the DAC selects the ADC data while the PORTB selects the ADC data also,
the DAC operates same clock as the PORTB selects. The block that isn’t connected to PORTA/B is automatically
connected to the Clock Gen C and operates the same clock as the Clock Gen C selects with the CLKL1-0 bits (Table
10).
In master mode, the CKSIA2-0, OLRA1-0, BICKAF, CKSB2-0 bits select the clock frequency (Table 11, Table 12 ,
Table 13, Table 14). In master mode, external clock (MCLK) should always be supplied except in the power-down
mode. The AK4683 is in power-down mode until MCLK will be supplied, when reset was canceled by Power-ON and
so on. At PORTA, the input/output data has independent LRCK (ILRCKA/OLRCKA) and common BICK (BICKA).
The ILRCK and OLRCK can operate at different sample rate but synchronized each other (Table 12).
In slave mode, external clocks (MCLK, BICK, LRCK) should always be present whenever the AK4683 is in normal
operation mode (PDN pin = “H”). The master clock (MCLK) should be synchronized with LRCK but the phase is not
critical. If these clocks are not provided, the AK4683 may draw excess current because the device utilizes dynamic
refreshed logic internally. If the external clocks are not present, the AK4683 should be in the power-down mode (PDN
pin = “L”) or in the reset mode (RSTN1 bit = “0”). After exiting reset at power-up etc., the AK4683 is in the
power-down mode until MCLK and LRCK are input.
When the block selects RMCLK as clock source, the sample rate of the PORT in the master mode or ADC/DAC
connecting to the Clock Gen C is forced to the same rate as DIR. The DFSAD, DFSDA1-0 bits should be controlled
properly.
MS0427-E-01
2005/11
- 24 -
ASAHI KASEI
[AK4683]
CLKA1 bit
0
0
1
1
CLKA0 bit
0
1
0
1
PORTA Clock Source
DIR
X’tal(XTI)
MCLK2
Reserved
default)
Table 8. PORTA Clock Source Control
CLKB1 bit
0
0
1
1
CLKB0 bit
0
1
0
1
PORTB Clock Source
DIR
X’tal(XTI)
MCLK2
Reserved
default)
Table 9. PORTB Clock Source Control
CLKL1 bit
0
0
1
1
CLKL0 bit
0
1
0
1
Clock Gen C Clock Source
DIR
X’tal (XTI)
MCLK2
Reserved
(default)
Table 10. Clock Gen C Clock Source Control
CKSAI2
0
0
0
0
CKSAI1
0
0
1
1
CKSAI0
0
1
0
1
Clock Speed
128fs
192fs
256fs
384fs
1
1
1
1
0
0
1
1
0
1
0
1
512fs
Reserved
Reserved
Reserved
(default)
Table 11. PORTA Input Data Clock Control (Master Mode)
OLRA1 bit
OLRA0 bit
OLRCKA Clock Freq
0
0
ILRCKA x 1
0
1
ILRCKA x 1/2
1
0
ILRCKA x 2
1
1
Reserved
Note: Select OLRA1-0 bits = “00” in TDM mode.
(default)
Table 12. OLRCKA Clock Mode Control
MS0427-E-01
2005/11
- 25 -
ASAHI KASEI
[AK4683]
BCAF bit
PORTA BICK Frequency Mode
0
ILRCK x 64
(default)
1
ILRCK x128
Note: ILRCK x 128 is available when the MCLK=ILRCK x 256 or higher.
BCAF bit is ignored in TDM mode.
Table 13. PORTA BICK Control (Master Mode)
CKSB2
0
0
0
0
CKSB1
0
0
1
1
CKSB0
0
1
0
1
Clock Speed
128fs
192fs
256fs
384fs
1
1
1
1
0
0
1
1
0
1
0
1
512fs
Reserved
Reserved
Reserved
(default)
Table 14. PORTB Data Clock Control (Master Mode)
CKSL2
0
0
0
0
CKSL1
0
0
1
1
CKSL0
0
1
0
1
Clock Speed
128fs
192fs
256fs
384fs
1
1
1
1
0
0
1
1
0
1
0
1
512fs
Reserved
Reserved
Reserved
(default)
Table 15. Clock Gen C Clock Control
In master mode, LRCKA (LRCKB) pin, BICKA (BICKB) pin are output pins. In slave mode, these are input pins
(Table 18).
MSA bit
0
1
PORTA Master/Slave Mode
Slave
Master
(default)
Table 16. PORTA Master/Slave Control
MSB bit
0
1
PORTB Master/Slave Mode
Slave
Master
(default)
Table 17. PORTB Master/Slave Control
MS0427-E-01
2005/11
- 26 -
ASAHI KASEI
[AK4683]
PDN pin
L
H
H
PWPOA(PWPOB) bit
Master/Slave
LRCKA
BICKA
(LRCKB) pin
(BICKB) pin
Slave
Input
Input
Slave
Input (*)
Input (*)
“0”
Master
“L” output
L” output
Slave
Input
Input
“1”
Master
Output
Output
(*): These are input pins, but input signals are ignored internally.
Table 18. LRCKA (LRCKB) pin, BICKA (BICKB) pin
The SDTOB1-0, SDTOA1-0 bits select the output data source of each PORT.
SDTOB1 bit
0
SDTOB0 bit
0
SDTOB Source
DIR
0
1
ADC
1
1
0
1
off
SDTIA1
(default)
Table 19. SDTOB Source Control
SDTOA1 bit
0
SDTOA0 bit
0
SDTOA Source
DIR
0
1
ADC
1
1
0
1
SDTIB
off
(default)
Table 20. SDTOA Source Control
MS0427-E-01
2005/11
- 27 -
ASAHI KASEI
[AK4683]
„ ADC, DAC Control
There are two modes for controlling the sampling speed for ADC and DAC. One is the Manual Setting Mode using the
DFSAD1-0, DFSDA1-0 bits, and the other is Auto Setting Mode. When the block connects to both PORTA and
PORTB, the PORTA setting is used.
1. Manual Setting Mode
When the ADC and DAC are connected to each PORT placed in Manual Setting Mode, the sampling speed are selected
by DFSAD, DFSDA1-0 bits (Table 21, Table 22). The frequencies and the duties of the clocks (ILRCKA, OLRCKA,
LRCKB, BICKA, BICKB) may be unstable for the moment when changing the sampling speed mode.
DFSAD0
0
1
Sampling Speed (fs)
Normal Speed Mode
32kHz~48kHz
Double Speed Mode
64kHz~96kHz
Default
Table 21.ADC sampling speed (Manual Setting Mode)
DFSDA1
0
0
1
1
DFSDA0
0
1
0
1
Sampling Speed (fs)
Normal Speed Mode
32kHz~48kHz
Double Speed Mode
64kHz~96kHz
Quad Speed Mode
120kHz~192kHz
Not Available
-
Default
Table 22.DAC sampling speed (Manual Setting Mode)
LRCKA
(LRCKB)
fs
32.0kHz
44.1kHz
48.0kHz
MCLK (MHz)
256fs
384fs
512fs
8.1920
12.2880
16.3840
11.2896
16.9344
22.5792
12.2880
18.4320
24.5760
(Normal Speed Mode @Manual Setting Mode)
BICKA (BICKB)
(MHz)
64fs
2.0480
2.8224
3.0720
Table 23. system clock example
LRCKA
(LRCKB)
fs
88.2kHz
96.0kHz
MCLK (MHz)
BICKA (BICKB)
(MHz)
64fs
5.6448
6.1440
128fs
192fs
256fs
11.2896
16.9344
22.5792
12.2880
18.4320
24.5760
(Double Speed Mode @Manual Setting Mode)
(Note: ADC is not available for 128fs and 192fs at Double Speed Mode (DFSAD=“1”))
Table 24. system clock example
MS0427-E-01
2005/11
- 28 -
ASAHI KASEI
[AK4683]
LRCKA
(LRCKB)
Fs
176.4kHz
192.0kHz
MCLK (MHz)
BICKA (BICKB)
(MHz)
64fs
11.2896
12.2880
128fs
192fs
256fs
22.5792
24.5760
(Quad Speed Mode @Manual Setting Mode)
(Note: ADC is not available at the Quad Speed Mode)
Table 25. system clock example
2. Auto Setting Mode (ACSKAD/ACSKDA bit = “1”)
When the ADC and DACs are connected to each PORT placed in Auto Setting Mode, MCLK frequency is detected
automatically (Table 26) and the internal master clock is set to the appropriate frequency (Table 27). In this mode, the
setting of DFSAD, DFSDA1-0 bits are ignored.
MCLK
512fs
256fs
128fs
Sampling Speed
Normal
Double
Quad
Table 26. Sampling Speed (Auto Setting Mode)
LRCKA
(LRCKB)
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
MCLK (MHz)
128fs
22.5792
24.5760
256fs
22.5792
24.5760
-
512fs
16.3840
22.5792
24.5760
-
Sampling
Speed
Normal
Double
Quad
Table 27. System clock example (Auto Setting Mode)
MS0427-E-01
2005/11
- 29 -
ASAHI KASEI
[AK4683]
The DAC12-10, DAC22-20 bits select the output data for each DAC. DAC1 and DAC2 must be connected to the same
PORT.
DAC12 bit
0
0
0
DAC11 bit
0
0
1
DAC10 bit
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
DAC1 Source
DIR
ADC
SDTIB
SDTIA1
(default)
SDTIA2
SDTIA3
Reserved
Reserved
Table 28. DAC1 Source Control
DAC22 bit
0
0
0
0
DAC21 bit
0
0
1
1
DAC20 bit
0
1
0
1
1
0
0
1
1
1
0
1
1
1
0
1
DAC2 Source
DIR
ADC
SDTIB
SDTIA1
SDTIA2
(default)
SDTIA3
Reserved
Reserved
Table 29. DAC2 Source Control
MS0427-E-01
2005/11
- 30 -
ASAHI KASEI
[AK4683]
„ De-emphasis Filter
The AK4683 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. De-emphasis filter is not available in
Double Speed Mode and Quad Speed Mode. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz,
48kHz). De-emphasis of each DAC can be set individually by register.
Mode
0
1
2
3
Sampling Speed
Normal Speed
Normal Speed
Normal Speed
Normal Speed
DEM1
0
0
1
1
DEM0
0
1
0
1
DEM
44.1kHz
OFF
48kHz
32kHz
Default
Table 30. De-emphasis control
„ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz and
scales with sampling rate (fs).
„ Audio Serial Interface Format
Each PORTA/B can select independent audio interface format. The TDMA1-0, DIFA1-0 bits control the audio format
for PORTA and support normal mode, TDM256 mode and TDM128 mode. The DIFB1-0 bits control the audio format
for PORTB and support only normal mode. The default is mode 2. In all modes the serial data is MSB-first, 2’s
complement format. The SDTO pins are clocked out on the falling edge of BICK pins and the SDTI pins are latched on
the rising edge of BICK pins.
1. Setting for the PORTA
1-1. Normal mode: TDMA1-0 bit = “00”
The TDMA1-0 bits = “00” set the AK4683 audio serial interface format to the normal mode. The DIFB1-0 bits
select following eight serial data format (Table 31).
Mode
0
1
2
3
4
5
6
7
LRCKA
BICKA
I/O
I/O
Slave
0
0
24bit, L J
20bit, R J
H/L
I
I
≥ 48fs
Slave
0
1
24bit, L J
24bit, R J
H/L
I
I
≥ 48fs
Slave
1
0
24bit, L J
24bit, L J
H/L
I
I
≥ 48fs
Slave
1
1
24bit, I2S
24bit, I2S
L/H
I
I
≥ 48fs
Master
0
0
24bit, L J
20bit, R J
H/L
O
64fs
O
Master
0
1
24bit, L J
24bit, R J
H/L
O
64fs
O
Master
1
0
24bit, L J
24bit, L J
H/L
O
64fs
O
Master
1
1
24bit, I2S
24bit, I2S
L/H
O
64fs
O
Table 31 Audio Interface Format (Normal mode, L J: Left justified, R J: Right justified.)
Master
/slave
DIFA1
DIFA0
SDTOA
MS0427-E-01
SDTIA1-3
default
2005/11
- 31 -
ASAHI KASEI
[AK4683]
1-2. TDM 256 mode: TDMA1-0 bit = “01”
The TDMA1-0 bits = “01” set the AK4683 audio serial interface format to the TDM 256 mode. The serial data of
all SDTIA (1,2,3) is input to the SDTIA1 pin. The input data to SDTIA2-3 pins is ignored. BICKA should be fixed
to 256fs. “H” time and “L” time of I/OLRCKA pin should be 1/256fs at least. The DIFA1-0 bits select eight
modes.
Mode
8
9
10
11
12
13
14
15
LRCKA
BICKA
Master
DIFA1
DIFA0
SDTOA
SDTIA1-3
/slave
I/O
I/O
Slave
0
0
24bit, L J
20bit, R J
I
256fs
I
↑
Slave
0
1
24bit, L J
24bit, R J
I
256fs
I
↑
Slave
1
0
24bit, L J
24bit, L J
I
256fs
I
↑
Slave
1
1
24bit, I2S
24bit, I2S
I
256fs
I
↓
Master
0
0
24bit, L J
20bit, R J
O
256fs
O
↑
O
256fs
O
Master
0
1
24bit, L J
24bit, R J
↑
Master
1
0
24bit, L J
24bit, L J
O
256fs
O
↑
Master
1
1
24bit, I2S
24bit, I2S
O
256fs
O
↓
Table 32. Audio Interface Format (TDM 256 mode, L J: Left justified, R J: Right justified.)
default
1-3. TDM 128 mode: TDMA1-0 bit = “11”
The TDMA1-0 bits = “11” set the AK4683 audio serial interface format to the TDM 1286 mode. The four channel
serial data (SDTIA1, 2) is input to the SDTIA1 pin. Other two channel data (SDTIA3) is input to the SDTIA2 pin.
Mode
16
17
18
19
20
21
22
23
LRCKA
BICKA
Master
DIFA1
DIFA0
SDTOA
SDTIA1-3
/slave
I/O
I/O
Slave
0
0
24bit, L J
20bit, R J
I
128fs
I
↑
Slave
0
1
24bit, L J
24bit, R J
I
128fs
I
↑
Slave
1
0
24bit, L J
24bit, L J
I
128fs
I
↑
Slave
1
1
24bit, I2S
24bit, I2S
I
128fs
I
↓
Master
0
0
24bit, L J
20bit, R J
O
128fs
O
↑
Master
0
1
24bit, L J
24bit, R J
O
128fs
O
↑
Master
1
0
24bit, L J
24bit, L J
O
128fs
O
↑
Master
1
1
24bit, I2S
24bit, I2S
O
128fs
O
↓
Table 33. Audio Interface Format (TDM 128 mode, L J: Left justified, R J: Right justified.)
default
2. Setting for the PORTB
2-1: Normal mode:
The PORTB supports only the normal mode. The DIFB1-0 bits select following eight serial data format (Table 34).
Mode
0
1
2
3
4
5
6
7
LRCKB
BICKB
I/O
I/O
Slave
0
0
24bit, L J
20bit, R J
H/L
I
I
≥ 48fs
Slave
0
1
24bit, L J
24bit, R J
H/L
I
I
≥ 48fs
Slave
1
0
24bit, L J
24bit, L J
H/L
I
I
≥ 48fs
Slave
1
1
24bit, I2S
24bit, I2S
L/H
I
I
≥ 48fs
Master
0
0
24bit, L J
20bit, R J
H/L
O
64fs
O
Master
0
1
24bit, L J
24bit, R J
H/L
O
64fs
O
Master
1
0
24bit, L J
24bit, L J
H/L
O
64fs
O
Master
1
1
24bit, I2S
24bit, I2S
L/H
O
64fs
O
Table 34. Audio Interface Format (Normal mode, L J: Left justified, R J: Right justified.)
Master
/slave
DIFB1
DIFB0
SDTOB
MS0427-E-01
SDTIB
default
2005/11
- 32 -
ASAHI KASEI
[AK4683]
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
12 11 10
Don’t Care
SDTI(i)
0
19 18
23 22
8
7
1
12 11 10
Don’t Care
0
0
19 18
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
23
8
7
1
0
Rch Data
Figure 8. Mode 0,4 Timing
LRCK
0
1
2
8
9
10
24
25
31
0
1
2
8
9
10
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
16 15 14
Don’t Care
SDTI(i)
0
23 22
23:MSB, 0:LSB
23 22
8
7
1
16 15 14
Don’t Care
0
0
23 22
Lch Data
23
8
7
1
0
Rch Data
Figure 9. Mode 1 ,5 Timing
LRCK
0
1
2
21
22
23
24
28
29
30
31
0
1
2
22
23
24
28
29
30
31
0
1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
2
1
0
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
23
Don’t Care
23
Rch Data
Figure 10.Mode 2,6 Timing
LRCK
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
2
1
0
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
Don’t Care
Rch Data
Figure 11. Mode 3 ,7 Timing
MS0427-E-01
2005/11
- 33 -
ASAHI KASEI
[AK4683]
256 B ICK
LRCKA
(m ode 8)
LRCKA
(m ode 12)
BICKA(256fs)
SDTOA(o)
SDTIA1(i)
23 22
0
23 22
0
23 22
Lch
Rch
32 B ICK
32 B ICK
19 18
0
19 18
0
L1
R1
32 B ICK
32 B ICK
19 18
0
19 18
0
19 18
0
19 18
0
L2
R2
L3
R3
32 BICK
32 B ICK
32 B ICK
32 BICK
19
32 BICK
32 B ICK
Figure 12. Mode 8 ,12 Timing
256 B ICK
LRCKA
(m ode 9)
LRCKA
(m ode 13)
BICKA(256fs)
SDTOA(o)
23 22
0
23 22
Lch
32 B ICK
SDTIA1(i)
0
23 22
Rch
23 22
32 B ICK
0
23 22
0
L1
R1
32 B ICK
32 B ICK
23 22
0
23 22
0
23 22
0
23 22
0
L2
R2
L3
R3
32 BICK
32 B ICK
32 B ICK
32 BICK
23
32 BICK
32 B ICK
Figure 13. Mode 9 ,13 Timing
256 B ICK
LRCKA
(m ode 10)
LRCKA
(m ode 14)
BICKA(256fs)
SDTOA(o)
23 22
0
Lch
SDTIA1(i)
0
23 22
Rch
32 B ICK
23 22
23 22
0
32 B ICK
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
L3
R3
32 B ICK
32 B ICK
32 BICK
32 B ICK
32 B ICK
32 BICK
23 22
32 BICK
32 B ICK
Figure 14. Mode 10 ,14 Timinig
256 B ICK
LRCKA
(m ode 11)
LRCKA
(m ode 15)
BICKA(256fs)
SDTOA(o)
23
0
Lch
SDTIA1(i)
0
23
Rch
32 B ICK
23
23
0
32 B ICK
23
0
23
0
23
0
23
0
23
0
L1
R1
L2
R2
L3
R3
32 B ICK
32 B ICK
32 BICK
32 B ICK
32 B ICK
32 BICK
23
32 BICK
32 B ICK
Figure 15. Mode 11 ,15 Timing
MS0427-E-01
2005/11
- 34 -
ASAHI KASEI
[AK4683]
128 B ICK
LRCKA
(m ode 16)
LRCKA
(m ode 20)
BICKA(128fs)
SDTOA(o)
23 22
0
SDTIA2(i)
23 22
Rch
32 BICK
SDTIA1(i)
0
23 22
Lch
32 B ICK
19 18
0
19 18
0
19 18
0
0
19 18
L1
R1
L2
R2
32 BICK
32 B ICK
32 BICK
32 BICK
19 18
0
19 18
0
L3
R3
32 BICK
32 B ICK
19
19
32 B ICK
32 BICK
Figure 16. Mode 16 ,20 Timing
128 B ICK
LRCKA
(m ode 17)
LRCKA
(m ode 21)
BICKA(128fs)
23 22
0
SDTIA2(i)
23 22
Rch
32 BICK
SDTIA1(i)
0
23 22
Lch
32 B ICK
23 22
0
23 22
0
23 22
0
0
23 22
L1
R1
L2
R2
32 BICK
32 B ICK
32 BICK
32 BICK
23 22
0
23 22
0
L3
R3
32 BICK
32 B ICK
19
19
32 B ICK
32 BICK
Figure 17. Mode 17 ,21 TIming
128 B ICK
LRCKA
(m ode 18)
LRCKA
(m ode 22)
BICKA(128fs)
SDTOA(o)
23 22
0
SDTIA2(i)
23 22
23 22
Rch
32 BICK
SDTIA1(i)
0
23 22
Lch
32 B ICK
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
32 BICK
32 B ICK
32 BICK
32 BICK
23 22
0
L3
32 BICK
23 22
0
23 22
23 22
R3
32 B ICK
32 BICK
32 BICK
Figure 18. Mode 18 ,22 Timing
MS0427-E-01
2005/11
- 35 -
ASAHI KASEI
[AK4683]
128 B ICK
LRCKA
(m ode 19)
LRCKA
(m ode 23)
BICKA(128fs)
SDTOA(o)
23 22
0
SDTIA1(i)
SDTIA2(i)
23
Rch
32 BICK
23 22
0
23 22
Lch
32 B ICK
0
23 22
0
0
23 22
23 22
0
L1
R1
L2
R2
32 BICK
32 B ICK
32 BICK
32 BICK
23 22
0
L3
32 BICK
23 22
0
23
23
R3
32 B ICK
32 B ICK
32 BICK
Figure 19. Mode 19 ,23 Timing
MS0427-E-01
2005/11
- 36 -
ASAHI KASEI
[AK4683]
„ Digital Volume Control
The AK4683 has channel-independent digital volume control (256 levels, 0.5dB step). The ATTAD7-0 bit set the
volume level of each ADC channel (Table 35), ATTDA7-0 set each DAC channel (Table 36).
ATTAD7-0
00H
01H
02H
:
2FH
30H
31H
FEH
FFH
Attenuation Level
+24dB
+23.5dB
+22.0dB
:
+0.5dB
0dB
-0.5dB
:
-103dB
MUTE (-∞)
(default)
Table 35.ADC Digital Volume
ATTDA7-0
00H
01H
02H
:
17H
18H
19H
FEH
FFH
Attenuation Level
+12dB
+11.5dB
+11.0dB
:
+0.5dB
0dB
-0.5dB
:
-115dB
MUTE (-∞)
(default)
Table 36.DAC Digital Volume
Transition time between set values of ATTAD7-0 (ATTDA7-0) bits can be selected by ATSAD (ATSDA) bits (Table
37, Table 38). Transition between set values is the soft transition. Therefore, the switching noise does not occur in the
transition.
Mode
0
1
ATSAD
0
1
ATT speed
1061/fs
256/fs
(default)
Table 37. Transition time between set values of ATTAD7-0 bits (ADC)
Mode
0
1
ATSDA
0
1
ATT speed
1061/fs
256/fs
(default)
Table 38. Transition time between set values of ATTDA7-0 bits (DAC)
The transition between set values is soft transition of 1061 levels in mode 0. It takes 1061/fs ([email protected]=48kHz) from
00H to FFH(MUTE) in mode 0. If PDN pin goes to “L”, the ATTAD7-0(ATTDA7-0) bits are initialized to 30H(18H).
The ATTs goes to their default value when RSTN bit = “0”. When RSTN1 bit return to “1”, the ATTs fade to their
current value.
MS0427-E-01
2005/11
- 37 -
ASAHI KASEI
[AK4683]
„ Soft mute operation
The ADC and DAC have the soft mute function. The soft mute operation is performed at digital domain. When the
SMAD/SMDA bits go to “1”, the output signal is attenuated by -∞ during ATT_DATA×ATT transition time (Table 37,
Table 38) from the current ATT level. When the SMAD/SMDA bits are returned to “0”, the mute is cancelled and the
output attenuation gradually changes to the ATT level during ATT_DATA×ATT transition time. If the soft mute is
cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to ATT level
by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMAD/SMDA bits
ATT Level
(1)
(1)
(3)
Attenuation
-∞
GD
(2)
GD
AOUT
DZF
(for SMDA)
(4)
8192/fs
Notes:
(1) ATT_DATA×ATT transition time (Table 37, Table 38). For example, in Normal Speed Mode, this time is
1061/fs cycles (1792/fs) at ATT_DATA=00H. ATT transition of the soft-mute is from 00H to FFH
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
(4) When the input data at all the channels of the group are continuously zeros for 8192 cycles, DZF pin of each
channel goes to “H”. DZF pin immediately goes to “L” if the input data of either channel of the group are not
zero after going DZF “H”.
Figure 20. Soft mute and zero detection
MS0427-E-01
2005/11
- 38 -
ASAHI KASEI
[AK4683]
„ Input Selector, Input Attenuator
The AK4683 includes 6ch stereo input selectors (Figure 21). The input selector is 6 to 1 selector. The AIN2-0 bits set
the input channel (Table 39).
AIN2 bit
0
0
0
0
1
1
1
1
AIN1 bit
0
0
1
1
0
0
1
1
AIN0 bit
0
1
0
1
0
1
0
1
Input Selector
LIN1 / RIN1
LIN2 / RIN2
LIN3 / RIN3
LIN4 / RIN4
LIN5 / RIN5
LIN5 / RIN5
None
None
Default
Table 39. Input Selector
The input ATTs are constructed by adding the input resistor (Ri) for LIN1-6/RIN1-6 pins and the feedback resistor (Rf)
between LOPIN (ROPIN) pin and LOUT (ROUT) pin (Figure 21). The voltage range of the LISEL(RISEL) pin should
be less than typ. 0.62 x AVDD1 (Vpp). If the input voltage of the input selector exceeds typ. 0.62 x AVDD, the input
voltage of the LISEL(RISEL) pins must be attenuated to typ. 0.62 x AVDD1 (Vpp) by the input ATTs. The Table 40
shows the example of Ri and Rf.
Rf
L O P IN
Ri
L IN 1
Ri
L IN 2
Ri
L IN 3
Ri
L IN 4
Ri
L IN 5
Ri
L IN 6
Ri
R IN 1
Ri
R IN 2
Ri
R IN 3
Ri
R IN 4
L IS E L
To ADC
P re -A m p
P re -A m p
Ri
R IN 5
Ri
R IN 6
To ADC
R O P IN
R IS E L
Rf
Figure 21. Input ATT
Input Range
LISEL/R pin
1.02Vrms
4Vrms
47
12
−11.86
(2.88Vpp)
1.02Vrms
2Vrms
47
24
−5.84
(2.88Vpp)
1Vrms
1Vrms
47
47
0
(2.82Vpp)
Note: Input range of internal ADC is 0.62 x AVDD1 (5V) = 3.1Vpp typ.
Ri [kΩ]
Rf [kΩ]
ATT Gain [dB]
Table 40. Input ATT example
MS0427-E-01
2005/11
- 39 -
ASAHI KASEI
[AK4683]
[Input selector switching sequence]
The input selector should be changed after soft mute to avoid the switching noise of the input selector (Figure 22).
1. Enable the soft mute before changing channel.
2. Change channel.
3. Disable the soft mute.
SM U T E
D AT T Level
(1)
(1)
Attenuation
(2)
-∞
C hannel
LIN 1/R IN 1
LIN 2/R IN 2
Figure 22. Input channel switching sequence example
The period of (1) varies in the setting value of DATT. It takes 1028/fs to mute when DATT value is +24dB.
When changing channels, the input channel should be changed during (2). The period of (2) should be around 200ms
because there is some DC difference between the channels.
MS0427-E-01
2005/11
- 40 -
ASAHI KASEI
[AK4683]
„ Power ON/OFF Sequence
The each block of the AK4683 are placed in the power-down mode by bringing PDN pin “L” and both digital filters are
reset at the same time. PDN pin “L” also reset the control registers to their default values. In the power-down mode, the
analog outputs go to VCOM voltage and SDTOA,B, DZF/OVF pin go to “L”. This reset should always be done after
power-up.
In slave mode, after exiting reset at power-up etc., the AK4683 starts to operate from the rising edge of LRCK after
MLCK, then the device is in the power-down mode until MCLK and LRCK are input. In slave mode or Internal Loop
Mode, the AK4683 starts to operate by the input of MLCK after exiting reset.
The analog initialization cycle of ADC starts after exiting the power-down mode. Therefore, the output data, SDTO
becomes available after 522/fs cycles of LRCK clock. In case of the DAC, an analog initialization cycle starts after
exiting the power-down mode. The analog outputs are VCOM voltage during the initialization. Figure 23 hows the
sequences of the power-down and the power-up.
The ADC and all DACs can be powered-down individually by PWAD bit and PWDA1-2 bits. These bits don’t initialize
the internal register values. When PWAD bit = “0” and selecting ADC, the SDTOA(SDTOB) pin goes to “L”. When
PWDA1-2 bits = “0”, the analog outputs go to VCOM voltage and DZF/OVF pin go to “H”. Since some click noise
may occur, the analog output should muted externally if the click noise influences system application.
Power
PDN
522/fs
ADC Internal
State
(1)
Init Cycle
516/fs
DAC Internal
State
Normal Operation
Power-down
(2)
Init Cycle
Normal Operation
GD (3)
Power-down
GD
ADC In
(Analog)
ADC Out
(Digital)
“0”data (4)
DAC In
(Digital)
“0”data
(5)
“0”data
“0”data
GD
(3)
GD
(6)
DAC Out
(Analog)
(6)
(7)
Clock In
Don’t care
Don’t care
MCLK,LRCK,SCLK
10∼11/fs (10)
(8)
DZF1/DZF2
External
Mute
(9)
Mute ON
Mute ON
Notes:
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) The analog part of DAC is initialized after exiting the power-down state.
(3) Digital output corresponding to analog input and analog output corresponding to digital input have the group
delay (GD).
(4) ADC output is “0” data at the power-down state.
(5) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the
click noise influences system application.
(6) Click noise occurs at the falling edge of PDN and at 512/fs(DAC1) and 512/fs +96ms(DAC2) after the rising
edge of PDN.
(7) When the external clocks (MCLK, BICKA (BICKB), LRCKA (LRCKB)) are stopped, the AK4683 should be in the
power-down mode.
(8) DZF/OVF pin is “L” in the power-down mode (PDN pin = “L”).
(9) Please mute the analog output externally if the click noise (6) influences system application.
(10) DZF pin = “L” for 10∼11/fs after PDN= “↑”.
Figure 23. Power-down/up sequence example
MS0427-E-01
2005/11
- 41 -
ASAHI KASEI
[AK4683]
„ Status of analog output pins during power-down (PDN pin =”L”)
The status of analog output pins is as follows.
Pin Name
HPL/HPR
LOUT1/ROUT1/LOUT2/ROUT2
LISEL/RISEL
HVSS
VCOM
Hi-Z
„ Reset Function
When RSTN1 bit = “0”, ADC and DACs are powered-down but the internal register are not initialized. The analog
outputs go to VCOM voltage, DZF/OVF pin goes to “H” and SDTOA/B pins go to “L”. Because some click noise
occurs, the analog output should muted externally if the click noise influences system application. The Figure 24 shows
the power-up sequence.
RSTN bit
4~5/fs (9)
1~2/fs (9)
Internal
RSTN bit
516/fs (1)
ADC Internal
State
Normal Operation
Digital Block Power-down
DAC Internal
State
Normal Operation
Digital Block Power-down
Normal Operation
Init Cycle
Normal Operation
GD (2)
GD
ADC In
(Analog)
(3)
ADC Out
(Digital)
DAC In
(Digital)
(4)
“0”data
“0”data
(2)
GD
DAC Out
(Analog)
GD
(5)
(6)
(6)
(7)
Clock In
MCLK,LRCK,SCLK
Don’t care
4∼5/fs (8)
DZF1/DZF2
Notes:
(1) The analog part of ADC is initialized after exiting the reset state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group
delay (GD).
(3) ADC output is “0” data at the power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Please mute the digital output externally if the click
noise influences system application.
(5) When RSTN1 bit = “0”, the analog outputs go to VCOM voltage.
(6) Click noise occurs at 4∼5/fs after RSTN1 bit becomes “0”, and occurs at 1∼2/fs after RSTN1 bit becomes “1”.
This noise is output even if “0” data is input.
(7) The external clocks (MCLK, BICKA (BICKB), LRCKA (LRCKB)) can be stopped in the reset mode. When
exiting the reset mode, “1” should be written to RSTN1 bit after the external clocks (MCLK, BICKA (BICKB),
LRCKA (LRCKB)) are fed.
(8) DZF pins go to “H” when the RSTN1 bit becomes “0”, and go to “L” at 6~7/fs after RSTN1 bit becomes “1”.
(9) There is a delay, 4~5/fs from RSTN1 bit “0” to the internal RSTN bit “0”.
Figure 24. Reset sequence example
MS0427-E-01
2005/11
- 42 -
ASAHI KASEI
[AK4683]
„ Headphone Output
Power supply voltage for the Headphone-Amp is supplied from the HVDD pin and centered on the HVDD/2 voltage.
When the MUTEN bit is “0”, the common voltage of Headphone-Amp falls and the outputs (HPL and HPR pins) go to
“L” (HVSS). When the MUTEN bit is “1”, the common voltage rises to HVDD/2. A capacitor between the MUTET pin
and ground reduces click noise at power-up. Rise/Fall time constant is proportional to HVDD voltage and the capacitor
at MUTET pin.
[Example]: A capacitor between the MUTET pin and ground = 1.0µF, HVDD=5V:
Rise/fall time constant: τ = 120ms(typ)
When PWPD bit is “0”, the Headphone-Amp is powered-down, and the outputs (HPL and HPR pins) go to “L”
(HVSS).
PWHP bit
MUTEN bit
HPL pin,
HPR pin
(1) (2)
(3)
(4)
(5)
Figure 25. Power-up/Power-down Timing for Headphone-Amp
(1) Headphone-Amp power-up (PWHP bit = “1”). The outputs are still HVSS.
(2) Headphone-Amp common voltage rises up (MUTEN bit = “1”). Common voltage of Headphone-Amp is rising.
(3) Start the audio output after finishing the setup pf common voltage to prevent the clipping.
(4) Headphone-Amp common voltage falls down (MUTEN bit = “0”). Common voltage of Headphone-Amp is falling.
(5) Headphone-Amp power-down (PWHP bit = “0”). The outputs are HVSS. If the power supply is switched off or
Headphone-Amp is powered-down before the common voltage goes to HVSS, some CLICK noise occurs.
The cut-off frequency (fc) of Headphone-Amp depends on the external resistor and capacitor. Table 41 shows the cut
off frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is 16Ω.
Output powers are shown at HVDD = 5V.
HP-AMP
R
C
Headphone
16Ω
AK4683
Figure 26. External Circuit Example of Headphone
R [Ω]
0
6.8
16
C [µF]
fc [Hz]
220
100
100
47
100
47
45
100
70
149
50
106
Output Power [mW]@0dBFS
50
25
12.5
Table 41. External Circuit Example
MS0427-E-01
2005/11
- 43 -
ASAHI KASEI
[AK4683]
„ Output Analog Volume (OPGA)
Volume range of the output analog volume is 0dB to -50dB and MUTE with by zero crossing detection. The OPGA
operates with the clock for DAC. The zero crossing detection of Lch and Rch is worked independently. If there are no
zero-crossings, the level will then change after a timeout period; the timeout period scales with fs. When ZCE is “0”, it
is changed immediately without zero crossing detection.
When writing to OPGA4-0 bits continually, it should take an interval of zero crossing timeout period or more. If the
OPGA4-0 bits are changed before zero crossing.
OPGA4-0
1FH
1EH
1DH
:
10H
0FH
0EH
0DH
:
05H
04H
03H
02H
01H
00H
GAIN(dB)
+0
-1
-2
:
-15
-16
-18
-20
:
-36
-38
-42
-46
-50
MUTE
STEP
LEVEL
1dB
17
2dB
11
4dB
3
1
(default)
Table 42. Output Analog Volume Setting
When ZCE bit is “1”, the Lch/Rch volume level are changed independently by zero crossing detection or zero crossing
timeout operation. The count of timer is doubled when DAC double speed mode, four times when DAC quad speed
mode.
DAC2 Sampling Speed
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Zero crossing timeout
768/fs (16ms @fs=48kHz)
1536/fs (16ms @fs=96kHz)
3072/fs (16ms @fs=192kHz)
Table 43. Zero crossing timeout
The OPGA is enable at PWDA bit = PWDA2 bit = “1”. The initializing of OPGA starts when DAC is powered up. This
initializing cycle is 96ms(@fs=48kHz). Writing to the OPGA4-0 during the initialization is ignored. The default volume
value is mute after power up. Initialization time is 512/fs+96ms(@fs=48kHz) after PDN pin = ”H”.
DAC2 Sampling Speed
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
OPGA Initialization Time
4608/fs (96ms @fs=48kHz)
9216/fs (96ms @fs=96kHz)
18432/fs (96ms @fs=192kHz)
Table 44. OPGA Initialization Time
MS0427-E-01
2005/11
- 44 -
ASAHI KASEI
[AK4683]
OPERATION OVERVIEW (DIR/DIT part)
„ 192kHz Clock Recovery
On chip low jitter PLL has a wide lock range with 32kHz to 192kHz and the lock time is less than 20ms. The AK4683
has the sampling frequency detect function. By either the clock comparison against X’tal oscillator or using the channel
status, the AK4683 detects the sampling frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz).
The PLL loses lock when the received sync interval is incorrect.
„ Clock Operation Mode
When DIR is selected. the CM0/CM1 bits select the clock source and the data source of SDTO. In Mode 2, the clock
source is automatically switched from PLL to XTI/MCLK2 when PLL goes unlock state. In Mode 3, the clock source is
fixed to XTI/MCLK2, but PLL is also operating and the recovered data such as C bits can be monitored. For Mode 2
and 3, it is recommended that the frequency of XTI/MCLK2 is different from the recovered frequency from PLL.
Mode
0
1
CM1
0
0
2
1
3
1
CM0
0
1
UNLOCK
PLL
Clock source SDTO
ON
PLL
RX
OFF
EXTCLK
DIT source
0
ON
PLL
RX
0
1
ON
EXTCLK
DIT source
1
ON
EXTCLK
DIT source
ON: Oscillation (Power-up), OFF: STOP (Power-down)
(default)
Table 45. Clock Operation Mode select
When 384fs of XTI/MCLK2 is supplied to DIR/DIT, CKSDT bit should be set to “1”.
CKSDT bit
0
1
Clock Speed
x1
x 2/3
(default)
Table 46. XTI/MCLK2 speed
MS0427-E-01
2005/11
- 45 -
ASAHI KASEI
[AK4683]
„ Sampling Frequency and Pre-emphasis Detection
The AK4683 has two methods for detecting the sampling frequency as follows.
1. Clock comparison between recovered clock and XTI/MCLK2
2. Sampling frequency information on channel status
Those could be selected by XTL1, 0 bits. And the detected frequency is reported on FS3-0 bits.
XTL1
0
0
1
1
XTL0
0
1
0
1
XTI/MCLK2 Frequency
11.2896MHz
12.288MHz
24.576MHz
(Use channel status)
default
Table 47. Reference XTI/MCLK2 frequency
Except XTL1,0= “1,1”
XTL1,0= “1,1”
Consumer
Register output
fs
mode
Professional mode
Clock comparison
(Note 2)
(Note 1)
Byte3
Byte0
Byte4
FS3
FS2
FS1
FS0
Bit3,2,1,0
Bit7,6
Bit6,5,4,3
0
0
0
0
44.1kHz
44.1kHz
0000
01
0000
0
0
0
1
Reserved
Reserved
0001
(Others)
0
0
1
0
48kHz
48kHz
0010
10
0000
0
0
1
1
32kHz
32kHz
0011
11
0000
1
0
0
0
88.2kHz
88.2kHz
(1000)
00
1010
1
0
1
0
96kHz
96kHz
(1010)
00
0010
1
1
0
0
176.4kHz
176.4kHz
(1100)
00
1011
1
1
1
0
192kHz
192kHz
(1110)
00
0011
Note1: At least ±3% range is identified as the value in the Table 48. In case of intermediate frequency of those two,
FS3-0 bits indicate nearer value. When the frequency is much bigger than 192kHz or much smaller than
32kHz, FS3-0 bits may indicate “0001”.
Note2: When consumer mode, Byte3 Bit3-0 are copied to FS3-0 bits.
Table 48. fs Information
The pre-emphasis information is detected and reported on PEM bit. This information is extracted from channel 1 at
default. It can be switched to channel 2 by CS12 bit in control register.
PEM
Pre-emphasis
0
1
OFF
ON
Byte 0
Bits 3-5
≠ 0X100
0X100
Table 49. PEM in Consumer Mode
PEM
Pre-emphasis
0
1
OFF
ON
Byte 0
Bits 2-4
≠110
110
Table 50. PEM in Professional Mode
MS0427-E-01
2005/11
- 46 -
ASAHI KASEI
[AK4683]
„ De-emphasis Filter Control
The AK4683 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter corresponding to four sampling
frequencies (32kHz, 44.1kHz, 48kHz and 96kHz). When DEAU bit=“1”, the de-emphasis filter is enabled automatically
by sampling frequency and pre-emphasis information in the channel status. The AK4683 goes this mode at default.
Therefore, in Parallel Mode, the AK4683 is always placed in this mode and the status bits in channel 1 control the
de-emphasis filter. In Serial Mode, DEM0/1 and DFS bits can control the de-emphasis filter when DEAU bit is “0”. The
internal de-emphasis filter is bypassed and the recovered data is output without any change if either pre-emphasis or
de-emphasis Mode is OFF.
PEM
1
1
1
1
1
0
FS3
0
0
0
1
FS2
0
0
0
0
x
x
FS1
0
1
1
1
FS0
0
0
1
0
x
x
(Others)
Mode
44.1kHz
48kHz
32kHz
96kHz
OFF
OFF
Table 51. De-emphasis Auto Control at DEAU bit = “1” (default)
PEM
1
1
1
1
1
1
1
1
0
DFS
0
0
0
0
1
1
1
1
x
DEM1
0
0
1
1
0
0
1
1
x
DEM0
0
1
0
1
0
1
0
1
x
Mode
44.1kHz
OFF
48kHz
32kHz
OFF
OFF
96kHz
OFF
OFF
(default)
Table 52. De-emphasis Manual Control at DEAU bit = “0”
„ System Reset and Power-Down
The AK4683 has a power-down mode for all circuits by PDN pin can be partially powerd-down by PWN bit. The
RSTN2 bit initializes the register and resets the internal timing. The AK4683 should be reset once by bringing PDN pin
= “L” upon power-up.
PDN pin: All analog and digital circuit are placed in the power-down and reset mode by bringing PDN pin = “L”. All
the registers are initialized, and clocks are stopped. Reading/Witting to the register are disabled.
RSTN2 bit (Address 00H; D0):
All the registers except PWN and RSTN2 bits are initialized by bringing RSTN2 bit = “0”. The internal
timings are also initialized. When RSTN2 bit = “0”, the clock are output but SDTO pin is hold to “L”.
Witting to the register is not available except PWN and RSTN2 bits. Reading to the register is disabled.
PWN bit (Address 00H; D1):
The clock recovery part is initialized by bringing PWN bit = “0”. In this case, clocks from PLL are stopped.
The registers are not initialized and the mode settings are kept. Writing and Reading to the registers are
enabled.
MS0427-E-01
2005/11
- 47 -
ASAHI KASEI
[AK4683]
„ Biphase Input and Through Output
Eight receiver inputs (RX0-3) are available in Serial Control Mode. Only the RX0 input includes amplifier
corresponding to unbalance mode and can accept the signal of 200mV or more. IPS1-0 bits select the receiver channel.
The V bit can be output via pin.
IPS1 bit
0
0
1
1
IPS0 bit
0
1
0
1
DIR Source
RX0
RX1
RX2
RX3
(default)
Table 53. Recovery Data Select
(B)
1/4fs
VOUT
SDTO
C(R191)
V(L0)
R190
V(R0)
L191
V(L1)
R191
L0
V(L39)
L38
V(R39) V(L40)
R38
L39
LRCK
(except I2S)
LRCK
(I2S)
Figure 27. V output timings
MS0427-E-01
2005/11
- 48 -
ASAHI KASEI
[AK4683]
„ Biphase Output
The AK4683 can output either the through output (from RX) or transmitter output (DIT) via TX pin. Those could be
selected by DIT bit. The source of the through output from TX0 could be selected among RX0-3 by OPS0, 1 bits. When
output DIT data, V bit could be controlled by VIN bit and first 5 bytes of C bit could be controlled by CT39-CT0 bits in
control registers. When bit0= “0”(consumer mode), bit20-23 (Audio channel) could not be controlled directly but be
controlled by CT20 bit. When the CT20 bit is “1”, the AK4683 outputs “1000” as C20-23 for left channel and outputs
“0100” at C20-23 for right channel automatically. When CT20 bit is “0”, the AK4683 outputs “0000” set as “1000” for
sub frame 1, and “0100” for sub frame 2. U bits are fixed to “0”.
DIT bit
0
0
0
0
1
OPS1 bit
0
0
1
1
*
OPS0 bit
0
1
0
1
*
TX Source
RX0
RX1
RX2
RX3
DIT
(default)
Table 54. TX Source Control
The CLKDT bit selects the clock source of DIT. This clock must be the same clock as the clock sources of PORT
connecting to DIT.
CM1
CM0 UNLOCK Clock Source
(default)
0
0
PLL
0
1
EXTCLK
0
PLL
1
0
1
EXTCLK
1
1
EXTCLK
Table 55. Clock Mode Control
CLKDT bit
0
1
Clock Source
XTI
MCLK2
Table 56. EXTCLK Control
CKSDT
0
0
0
0
1
1
1
1
OCKS1
0
0
1
1
0
0
1
1
OCKS0
0
1
0
1
0
1
0
1
EXTCLK
256fs
256fs
512fs
128fs
384fs
384fs
768fs
192fs
fs(max)
96kHz
96kHz
48kHz
192kHz
48kHz
48kHz
32kHz
96kHz
Table 57. MCLKO Speed
MS0427-E-01
2005/11
- 49 -
ASAHI KASEI
[AK4683]
The DITD1-0 bits control the data source of DIT.
DITD1 bit
0
0
1
1
DITD0 bit
0
1
0
1
DIT Source
DIR
ADC
SDTIB
SDTIA1(default)
Table 58. DIT Source Control
„ Biphase signal input/output circuit (RX0, TX)
0.1uF
RX0
75Ω
Coax
75Ω
AK4683
Figure 28. Consumer Input Circuit (Coaxial Input)
Note: In case of coaxial input, if a coupling level to this input from the next RX input line
pattern exceeds 50mV, there is a possibility to occur an incorrect operation. In this case, it is
possible to lower the coupling level by adding this decoupling capacitor.
Optical Receiver
Optical
Fiber
470
RX0-3
O/E
AK4683
Figure 29. Consumer Input Circuit (Optical Input)
In case of coaxial input, as the input level of RX0 line is small, be careful not to crosstalk among RX input lines. For
example, by inserting the shield pattern among them.
The AK4683 includes the TX output buffer. The output level meets combination 0.5V+/-20% using the external resistor
network. The T1 in Figure 30 is a transformer of 1:1.
330±2%
TX
75Ω cable
100±2%
DVSS
T1
Figure 30. TX External Resistor Network
MS0427-E-01
2005/11
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ASAHI KASEI
[AK4683]
„ Q-subcode buffers
The AK4683 has Q-subcode buffer for CD application. The AK4683 takes Q-subcode into registers by following
conditions.
1. The sync word (S0,S1) is constructed at least 16 “0”s.
2. The start bit is “1”.
3. Those 7bits Q-W follows to the start bit.
4. The distance between two start bits are 8-16 bits.
The QINT bit in the control register goes “1” when the new Q-subcode differs from old one, and goes “0” when QINT
bit is read.
S0
S1
S2
S3
:
S97
S0
S1
S2
S3
:
1
0
0
1
1
:
1
0
0
1
1
:
2
3
4
5
6
7
8
*
0
0
0
0
0
0
0
0…
0
0
0
0
0
0
0
0…
Q2 R2 S2
T2
U2 V2 W2 0…
Q3 R3 S3
T3
U3 V3 W3 0…
:
:
:
:
:
:
:
:
Q97 R97 S97 T97 U97 V97 W97 0…
0
0
0
0
0
0
0
0…
0
0
0
0
0
0
0
0…
Q2 R2 S2
T2
U2 V2 W2 0…
Q3 R3 S3
T3
U3 V3 W3 0…
:
:
:
:
:
:
:
:
↑
Q
Q2
Q3 Q4
CTRL
Q5
Q6
Q7 Q8
ADRS
(*) number of "0" : min=0; max=8.
Figure 31. Configuration of U-bit(CD)
Q9
Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25
TRACK NUMBER
INDEX
Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49
MINUTE
SECOND
FRAME
Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73
ZERO
ABSOLUTE MINUTE
ABSOLUTE SECOND
Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97
ABSOLUTE FRAME
CRC
G(x)=x16+x12+x5+1
Figure 32. Q-subcode
Addr
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Register Name
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
D7
Q9
Q17
···
···
···
···
···
···
···
Q81
D6
Q8
Q16
···
···
···
···
···
···
···
Q80
D5
···
···
···
···
···
···
···
···
···
···
D4
···
···
···
···
···
···
···
···
···
···
D3
···
···
···
···
···
···
···
···
···
···
D2
···
···
···
···
···
···
···
···
···
···
D1
Q3
Q11
···
···
···
···
···
···
···
Q75
D0
Q2
Q10
···
···
···
···
···
···
···
Q74
Figure 33. Q-subcode register
MS0427-E-01
2005/11
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ASAHI KASEI
[AK4683]
„ Error Handling
There are the following eight events that make INT pin “H”. INT pin show the status of following conditions.
1. UNLOCK:
“1” when the PLL loses lock.
The AK4683 loses lock when the distance between two preambles is not correct or when those
preambles are not correct.
2. PAR:
“1” when parity error or biphase coding error is detected, and keeps “1” until this register is read.
Updated every sub-frame cycle. Reading this register resets itself.
3. AUTO:
“1” when Non-PCM bitstream is detected.
Updated every 4096 frames cycle.
4. DTSCD:
“1” when DTS-CD bitstream is detected.
Updated every DTS-CD sync cycle.
5. AUDION:
“1” when the “AUDIO” bit in recovered channel status indicates “1”.
Updated every block cycle.
6. PEM:
“1” when “PEM” in recovered channel status indicates “1”.
Updated every block cycle.
7. QINT:
“1” when Q-subcode differ from old one, and keeps “1” until this register is read.
Updated every sync code cycle for Q-subcode. Reading this register resets itself.
8. CINT:
“1” when received C bits differ from old one, and keeps “1” until this register is read.
Updated every block cycle. Reading this register resets itself.
INT pin is fixed to “L” when the PLL is off (CM1,0= “01”). Once the INT pin goes to “H”, this pin holds “H” for
1024/fs cycles (this value can be changed by EFH0/1 bits) after those events are removed. INT pin can mask those eight
events individually. Once PAR, QINT and CINT bit goes to “1”, those registers are held to “1” until those registers are
read. While the AK4683 loses lock, registers regarding C-bit or U-bits are not initialized and keep previous value.
INT pin outputs the ORed signal among those eight events. However, each mask bits can mask each event. When each
bit masks those events, the event does not affect INT pin operation (those mask do not affect those registers (UNLOCK,
PAR, etc.) themselves. Once INT pin goes “H”, it maintains “H” for 1024/fs cycles (this value can be changed by
EFH0-1 bits) after the all events are removed. Once those PAR, QINT or CINT bit goes “1”, it holds “1” until reading
those registers. While the AK4683 loses lock, the channel status Q-subcode bits are not updated and hold the previous
data. At initial state, INT outputs the ORed signal between UNLOCK and PAR.
UNLOCK
1
0
0
0
0
0
0
0
PAR
x
1
0
0
0
0
0
0
AUTO
x
x
1
x
x
x
x
x
Event
DTSCD AUDION
x
x
x
x
x
x
1
x
x
1
x
x
x
x
x
x
PEM
x
x
x
x
x
1
x
x
QINT
x
x
x
x
x
x
1
x
CINT
x
x
x
x
x
x
x
1
Pin
SDTO*
V*
TX*
“L”
“L”
Output
Previous Data Output Output
Output
Output Output
Output
Output Output
Output
Output Output
Output
Output Output
Output
Output Output
Output
Output Output
Note: when selected.
Table 59. Error Handling
MS0427-E-01
2005/11
- 52 -
ASAHI KASEI
Error
(UNLOCK, PAR,..)
[AK4683]
(Error)
INT pin
Hold Time (max: 4096/fs)
Register
(PAR,CINT,QINT)
Hold ”1”
Reset
Register
(others)
Command
MCKO, BICK, LRCK
(UNLOCK) note
MCKO, BICK, LRCK
(except UNLOCK)
note
SDTO (UNLOCK)
note
SDTO
(PAR error) note
READ 06H
Free Run
(fs: around 20kHz)
Previous Data
SDTO
(others) note
Vpin
(UNLOCK) note
Vpin
(except UNLOCK)
note
Normal Operation
note: When DIR is selected as source.
Figure 34. INT0/1 pin timing
MS0427-E-01
2005/11
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ASAHI KASEI
[AK4683]
PDN pin ="L" to "H"
Initialize
Read 06H
INT pin ="H"
No
Yes
Release
Muting
Mute DAC output
Read 06H
(Each Error Handling)
Read 06H
(Resets registers)
No
INT pin ="H"
Yes
Figure 35. Error Handling Sequence Example 1
MS0427-E-01
2005/11
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ASAHI KASEI
[AK4683]
PDN pin ="L" to "H"
Initialize
Read 06H
No
INT pin ="H"
Yes
Read 06H
and
Detect QSUB= “1”
(Read Q-buffer)
QCRC = “0”
No
New data
is invalid
Yes
INT pin ="L"
No
Yes
New data
is valid
Figure 36. Error Handling Sequence Example 2 (for Q/CINT)
MS0427-E-01
2005/11
- 55 -
ASAHI KASEI
[AK4683]
„ Non-PCM (AC-3, MPEG, etc.) and DTS-CD Bitstream Detection
The AK4683 has a Non-PCM steam auto-detection function. When the 32bit mode Non-PCM preamble based on Dolby
“AC-3 Data Stream in IEC60958 Interface” is detected, the AUTO bit goes “1”. The 96bit sync code consists of 0x0000,
0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the AUTO bit “1”. Once the AUTO bit
is set “1”, it will remain “1” until 4096 frames pass through the chip without additional sync pattern being detected.
When those preambles are detected, the burst preambles Pc and Pd that follow those sync codes are stored to registers.
The AK4683 also has the DTS-CD bitstream auto-detection function. When The AK4683 detects DTS-CD bitstreams,
DTSCD bit goes to “1”. When the next sync code does not come within 4096 flames, DTSCD bit goes to “0” until
when the AK4683 detects the stream again.
„ Burst Preambles in non-PCM Bitstreams
sub-frame of IEC958
0
3 4
preamble
7 8
11 12
Aux.
27 28 29 30 31
LSB
MSB V U C P
16 bits of bitstream
0
Pa Pb Pc Pd
15
Burst_payload
stuffing
repetition time of the burst
Figure 37. Data structure in IEC60958
Preamble word
Pa
Pb
Pc
Pd
Length of field
16 bits
16 bits
16 bits
16 bits
Contents
sync word 1
sync word 2
Burst info
Length code
Value
0xF872
0x4E1F
see Table 61
Numbers of bits
Table 60. Burst preamble words
MS0427-E-01
2005/11
- 56 -
ASAHI KASEI
Bits of Pc
Value
0-4
5, 6
7
8-12
13-15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-31
0
0
1
0
[AK4683]
Contents
Repetition time of burst
in IEC60958 frames
data type
NULL data
Dolby AC-3 data
reserved
PAUSE
MPEG-1 Layer1 data
MPEG-1 Layer2 or 3 data or MPEG-2 without extension
MPEG-2 data with extension
MPEG-2 AAC ADTS
MPEG-2, Layer1 Low sample rate
MPEG-2, Layer2 or 3 Low sample rate
reserved
DTS type I
DTS type II
DTS type III
ATRAC
ATRAC2/3
reserved
reserved, shall be set to “0”
error-flag indicating a valid burst_payload
error-flag indicating that the burst_payload may contain
errors
data type dependent info
bit stream number, shall be set to “0”
≤4096
1536
384
1152
1152
1024
384
1152
512
1024
2048
512
1024
(Refer the IEC standards.)
Table 61. Fields of burst info Pc
MS0427-E-01
2005/11
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ASAHI KASEI
[AK4683]
„ Non-PCM Bitstream timing
1) When Non-PCM preamble is not coming within 4096 frames,
PDN pin
Bit stream
Pa Pb Pc1 Pd1
Pa Pb Pc2 Pd2
Repetition time
Pa Pb Pc3 Pd3
>4096 frames
AUTO bit
Pc Register
“0”
Pd Register
“0”
Pc1
Pc2
Pd1
Pc3
Pd2
Pd3
Figure 38. Timing example 1
2) When Non-PCM bitstream stops (when MULK0=0),
INT0 hold time
INT0 pin
<20mS (Lock time)
Bit stream
Pa Pb Pc1 Pd1
Stop
Pa Pb Pcn Pdn
2~3 Syncs (B,M or W)
<Repetition time
AUTO bit
Pc Register
Pd Register
Pc0
Pc1
Pd0
Pcn
Pd1
Pdn
Figure 39. Timing example 2
MS0427-E-01
2005/11
- 58 -
ASAHI KASEI
[AK4683]
OPERATION OVERVIEW (ADC/DAC part, DIR/DIT part)
„ Serial Control Interface
The AK4683 has two registers, which are ADC/DAC part and DIR/DIT part. Each register is set by chip address pin.
(1). 4-wire serial control mode (I2C pin = “L”)
The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The
data on this interface consists of Chip address (2bits, C1-C0=”10” for ADC/DAC part, “00” for DIR/DIT part),
Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked
in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after the
16th rising edge of CCLK, after a high-to-low transition of CSN. For read operations, the CDTO output goes high
impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN pin = “L” resets the
registers to their default values. When the state of P/S pin is changed, the AK4683 should be reset by PDN pin = “L”.
Register of ADC/DAC part can not read.
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13
14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
WRITE
Hi-Z
CDTO
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
READ
CDTO
C1-C0:
R/W:
A4-A0:
D7-D0:
Hi-Z
D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
Chip Address: (Fixed to “10” for ADC/DAC part, “00” for DIR/DIT part)
READ/WRITE (0:READ, 1:WRITE)
Register Address
Control Data
Figure 40. 4-wire Serial Control I/F Timing
MS0427-E-01
2005/11
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ASAHI KASEI
[AK4683]
(2). I2C bus control mode (I2C pin = “H”)
AK4683 supports the standard-mode I2C-bus (max: 100kHz). Then AK4683 does not support a fast-mode I2C-bus
system (max: 400kHz).
(2)-1. Data transfer
All commands are preceded by a START condition. After the START condition, a slave address is sent. After the
AK4683 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted
over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave
device pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition
generated by the master device.
(2)-1-1. Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 41. Data transfer
(2)-1-2. START and STOP condition
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from
the START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the
STOP condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 42. START and STOP conditions
MS0427-E-01
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ASAHI KASEI
[AK4683]
(2)-1-3. ACKNOWLEDGE
ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will
release the SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the
acknowledge clock pulse so that that it remains stable “L” during “H” period of this clock pulse. The AK4683 will
generates an acknowledge after each byte has been received.
In the read mode, the slave, the AK4683 will transmit eight bits of data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue
to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the
STOP condition.
The register of ADC/DAC part can not generate acknowledge for READ operations.
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
START
CONDITION
acknowledge
Figure 43. Acknowledge on the I2C-bus
(2)-1-4. FIRST BYTE
The first byte, which includes seven bits of slave address and one bit of R/W bit, is sent after the START condition. If
the transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down
the SDA line.
The most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and CAD0 (device
address bits). These two bits identify the specific device on the bus. The eighth bit (LSB) of the first byte (R/W bit)
defines whether a write or read condition is requested by the master. A “1” indicates that the read operation is to be
executed. A “0” indicates that the write operation is to be executed.
0
0
1
0
0
CAD1
CAD0
R/W
(CAD1-CAD0 = fixed to “10” for ADC/DAC part, “00” for DIR/DIT part)
Figure 44. The First Byte
MS0427-E-01
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ASAHI KASEI
[AK4683]
(2)-2. WRITE Operations
Set R/W bit = “0” for the WRITE operation of the AK4683.
After receipt the start condition and the first byte, the AK4683 generates an acknowledge, and awaits the second byte
(register address). The second byte consists of the address for control registers of AK4683. The format is MSB first, and
those most significant 3-bits are “Don’t care”.
*
*
*
A4
A3
A2
A1
A0
(*: Don’t care)
Figure 45. The Second Byte
After receipt the second byte, the AK4683 generates an acknowledge, and awaits the third byte. Those data after the
second byte contain control data. The format is MSB first, 8bits.
D7
D6
D5
D4
D3
D2
D1
D0
Figure 46. Byte structure after the second byte
The AK4683 is capable of more than one byte write operation by one sequence.
After receipt of the third byte, the AK4683 generates an acknowledge, and awaits the next data again. The master can
transmit more than one words instead of terminating the write cycle after the first data word is transferred. After the
receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next
address automatically. If the address exceed 1FH prior to generating the stop condition, the address counter will “roll
over” to 00H and the previous data will be overwritten.
S
T
A
R
T
SDA
Register
Address(n)
Slave
Address
S
T
Data(n+x) O
P
Data(n+1)
Data(n)
S
P
A
C
K
A
C
K
A
C
K
A
C
K
Figure 47. WRITE Operation
MS0427-E-01
2005/11
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ASAHI KASEI
[AK4683]
(2)-3. READ Operations
Set R/W bit = “1” for the READ operation of the AK4683.
After transmission of a data, the master can read next address’s data by generating the acknowledge instead of
terminating the write cycle after the receipt the first data word. After the receipt of each data, the internal 5bits address
counter is incremented by one, and the next data is taken into next address automatically. If the address exceed 1FH
prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be
overwritten.
The AK4683 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
ADC/DAC part register can not read.
(2)-3-1. CURRENT ADDRESS READ
The AK4683 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would
access data from the address n+1.
After receipt of the slave address with R/W bit set to “1”, the AK4683 generates an acknowledge, transmits 1byte data
which address is set by the internal address counter and increments the internal address counter by 1. If the master does
not generate an acknowledge to the data but generate the stop condition, the AK4683 discontinues transmission
S
T
A
R
T
SDA
Slave
Address
Data(n)
Data(n+1)
S
Data(n+x) T
O
P
Data(n+2)
S
P
A
C
K
A
C
K
A
C
K
A
C
K
Figure 48. CURRENT ADDRESS READ
(2)-3-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation.
The master issues the start condition, slave address(R/W=“0”) and then the register address to read. After the register
address’s acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to
“1”. Then the AK4683 generates an acknowledge, 1byte data and increments the internal address counter by 1. If the
master does not generate an acknowledge to the data but generate the stop condition, the AK4683 discontinues
transmission.
S
T
A
R
T
SDA
Slave
Address
S
T
A
R
T
Word
Address(n)
S
Slave
Address
Data(n)
S
Data(n+x) T
O
P
Data(n+1)
S
A
C
K
P
A
C
K
A
C
K
A
C
K
A
C
K
Figure 49. RANDOM READ
MS0427-E-01
2005/11
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ASAHI KASEI
[AK4683]
„ Register Map (ADC/DAC part)
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
Register Name
Powerdown 1
Powerdown 2
Clock Select 1
Clock Select 2
Clock Select 3
Clock Select 4
Sampling Speed
Data Source Select 1
Data Source Select 2
Analog Input Control
Audio Data Format
De-emphasis/ ATT speed
LIN Volume Control
RIN Volume Control
LOUT1 Volume Control
ROUT1 Volume Control
LOUT2 Volume Control
ROUT2 Volume Control
HPL Volume Control
OVF/DZF/V Control
D7
PWXTL
PWPOB
0
CKSL2
CKSAI2
0
0
0
0
0
0
DEM21
D6
MUTEN
PWPOA
0
CKSL1
CKSAI1
XTL1
D5
PWVR
PWDA
0
CKSL0
CKSAI0
XTL0
DITD1
DAC21
0
DIFB1
DEM11
D4
PWHP
PWAD
0
CLKL1
0
CKSDT
ACKSB
DITD0
DAC20
0
DIFB0
DEM10
ACKSAI
ACKSAO
0
DAC22
0
0
DEM20
ATTAD7
ATTAD7
ATTDA7
ATTDA7
ATTDA7
ATTDA7
ATTAD6
ATTAD6
ATTDA6
ATTDA6
ATTDA6
ATTDA6
ATTAD5
ATTAD5
ATTDA5
ATTDA5
ATTDA5
ATTDA5
0
0
0
0
0
ZCE
D3
0
0
CLKB1
CLKL0
OLRA1
CKSB2
0
D2
SMAD
0
CLKB0
MCKO1
OLRA0
CKSB1
DFSAD
D1
SMDA
PWDA2
CLKA1
MCKO0
BCAF
CKSB0
D0
RSTN1
PWDA1
CLKA0
CLKDT
MSA
MSB
SDTOB1
SDTOB0
DFSDA1
SDTOA1
DFSDA0
SDTOA0
0
0
TDMA1
0
DAC12
AIN2
TDMA0
ATSAD
DAC11
AIN1
DIFA1
0
DAC10
AIN0
DIFA0
ATSDA
ATTAD4
ATTAD4
ATTDA4
ATTDA4
ATTDA4
ATTDA4
ATTAD3
ATTAD3
ATTDA3
ATTDA3
ATTDA3
ATTDA3
ATTAD2
ATTAD2
ATTDA2
ATTDA2
ATTDA2
ATTDA2
ATTAD1
ATTAD1
ATTDA1
ATTDA1
ATTDA1
ATTDA1
ATTAD0
ATTAD0
ATTDA0
ATTDA0
ATTDA0
ATTDA0
OPGA4
VIN
OPGA3
FUNC1
OPGA2
FUNC0
OPGA1
DZFM1
OPGA0
DZFM0
Note: For addresses from14H to 1FH, data must not be written.
When PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN1 bit goes to “0”, the internal timing is reset and DZF pin goes to “H”, but registers are not initialized
to their default values.
MS0427-E-01
2005/11
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ASAHI KASEI
[AK4683]
„ Register Definitions
Addr
00H
Register Name
Powerdown 1
Default
D7
PWXTL
1
D6
MUTEN
0
D5
PWVR
1
D4
PWHP
0
D3
0
0
D2
SMAD
0
D1
SMDA
0
D0
RSTN1
1
RSTN1: Internal timing reset
0: Reset. DZF pin go to “H”, but registers are not initialized.
1: Normal operation (default)
SMAD: ADC Soft Mute Enable
0: Normal operation (default)
1: ADC outputs soft-muted
SMDA: DAC Soft Mute Enable
0: Normal operation (default)
1: All DAC outputs soft-muted
PWHP: Power management for headphone amplifier
0: Power OFF (default)
1: Power ON
PWVR: Power management for reference voltage
0: Power OFF
1: Power ON (default)
MUTEN: Bias voltage control for headphone amp
0: bias = 0V (default).
1: Normal operation. Bias = 0.45xHVDD(typ).
PWXTL: Power management for X’tal oscillator
0: Power OFF
1: Power ON (default)
MS0427-E-01
2005/11
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ASAHI KASEI
Addr
01H
Register Name
Powerdown 2
Default
[AK4683]
D7
PWPOB
1
D6
PWPOA
1
D5
PWDA
1
D4
PWAD
1
D3
0
0
D2
0
0
D1
PWDA2
1
D0
PWDA1
1
D4
0
0
D3
CLKB1
0
D2
CLKB0
1
D1
CLKA1
0
D0
CLKA0
1
PWDA1: Power-down control of DAC1 Analog
0: Power-down
1: Normal operation (default)
PWDA2: Power-down control of DAC2 Analog
0: Power-down
1: Normal operation (default)
PWAD: Power-down control of ADC
0: Power-down
1: Normal operation (default)
PWDA: Full-Power-down control of DAC1-2
0: Power-down
1: Normal operation (default)
PWPOA: Power-down control of PORTA
0: Power-down
1: Normal operation (default)
PWPOB: Power-down control of PORTB
0: Power-down
1: Normal operation (default)
Addr
02H
Register Name
Clock Select 1
Default
D7
0
0
D6
0
0
D5
0
0
CLKA1-0: Clock source control for PORTA
00: DIR
01: X’tal(XTI) (default)
10: MCLK2
11: (Reserved)
CLKB1-0: Clock source control for PORTB
00: DIR
01: X’tal(XTI) (default)
10: MCLK2
11: (Reserved)
MS0427-E-01
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ASAHI KASEI
Addr
03H
Register Name
Clock Select 2
Default
[AK4683]
D7
D6
D5
D4
D3
D2
D1
D0
CKSL2
0
CKSL1
1
CKSL0
0
CLKL1
0
CLKL0
1
MCKO1
0
MCKO0
1
CLKDT
0
CLKDT: Clock source control for DIT
Refer Table 56.
MCLKO1-0: Clock source control for MCLKO
Refer Table 4.
CLKL1-0: Clock source control for Clock Gen C
00: DIR
01: X’tal(XTI) (default)
10: MCLK2
11: (Reserved)
CLSL2-0: Clock control for Clock Gen C
Refer Table 15
Addr
04H
Register Name
Clock Select 3
Default
D7
D6
D5
D4
D3
D2
D1
D0
CKSAI2
0
CKSAI1
1
CKSAI0
0
SELAO
0
OLRA1
0
OLRA0
0
BCAF
0
MSA
0
MSA: Master/Slave control for input data of PORTA.
Refer Table 16.
BCAF: Bit clock control for PORTA
Refer Table 13.
OLRA1-0: Clock control for PORTA OLRCKA.
Refer Table 12.
SELAO: Clock control for DIR/DIT
0: Except for the case at “1”. (default)
1: Selects when the frequency of ILRCKA and OLRCKA are different, DITD[1:0]= “00” or “01”
and both SDTOA[1:0] and DITD[1:0] select same data source.
CKSAI2-0: Clock control for PORTA Input Data.
Refer Table 11.
Addr
05H
Register Name
Clock Select 4
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
XTL1
0
XTL0
0
CKSDT
0
CKSB2
0
CKSB1
1
CKSB0
0
MSB
0
MSB: Master/Slave control for input data of PORTB.
Refer Table 17.
CKSB2-0: Clock control for PORTB.
Refer Table 14.
CKSDT: Clock control for DIT.
Refer Table 57.
XTL1-0: X’tal Frequency control
00: 11.2896MHz (default)
01: 12.288MHz
10: 24.576MHz
11: (channel status)
MS0427-E-01
2005/11
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ASAHI KASEI
Addr
06H
Register Name
Sampling Speed
Default
[AK4683]
D7
D6
D5
D4
D3
D2
D1
D0
0
0
ACKSAI
0
ACKSAO
0
ACKSB
0
0
0
DFSAD
0
DFSDA1
0
DFSDA0
0
DFSDA1-0: DAC sampling speed control
These settings are ignored in Auto Setting Mode. Refer Table 22.
DFSAD: ADC sampling speed control
This setting is ignored in Auto Setting Mode. Refer Table 21.
ACSKB: Auto Setting Mode of PORTB
0: Disable, Manual Setting Mode (default)
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKSB bit “1”. In this case, the setting of
DFSAD, DFSDA1-0 bits of the block connecting this PORT is ignored. When this bit is “0”,
DFSAD, DFSDA1-0 bits set the sampling speed mode.
ACSKAO: Auto Setting Mode of PORTA Output
0: Disable, Manual Setting Mode (default)
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKSAO bit “1”. In this case, the setting of
DFSAD, DFSDA1-0 bits of the block connecting this PORT is ignored. When this bit is “0”,
DFSAD, DFSDA1-0 bits set the sampling speed mode.
ACSKAI: Auto Setting Mode of PORTA Input
0: Disable, Manual Setting Mode (default)
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKSAI bit “1”. In this case, the setting of
DFSAD, DFSDA1-0 bits of the block connecting this PORT is ignored. When this bit is “0”,
DFSAD, DFSDA1-0 bits set the sampling speed mode.
Addr
07H
Register Name
Data Source Select 1
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
DITD1
1
DITD0
1
SDTOB1
0
SDTOB0
1
SDTOA1
0
SDTOA0
1
SDTOA1-0: Data source control for PORTA
00: DIR
01: ADC (default)
10: SDTIB
11: off (“L” output)
SDTOB1-0: Data source control for PORTB
00: DIR
01: ADC (default)
10: off (“L” output)
11: SDTIA1
DITD1-0: Data source control for DIT
00: DIR
01: ADC
10: SDTIB
11: SDTIA1 (default)
MS0427-E-01
2005/11
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ASAHI KASEI
Addr
08H
Register Name
Data Source Select 2
Default
[AK4683]
D7
D6
D5
D4
D3
D2
D1
D0
0
0
DAC22
1
DAC21
0
DAC20
0
0
0
DAC12
0
DAC11
1
DAC10
1
DAC12-10: Data source control for DAC1
000: DIR
001: ADC
010: SDTIB
011: SDTIA1 (default)
100: SDTIA2
101: SDTIA3
DAC22-20: Data source control for DAC2
000: DIR
001: ADC
010: SDTIB
011: SDTIA1
100: SDTIA2 (default)
101: SDTIA3
Addr
09H
Register Name
Analog Input Control
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
AIN2
0
AIN1
0
AIN0
0
AIN2-0: ADC input selector control
000: LIN1/RIN1 (default)
001: LIN2/RIN2
010: LIN3/RIN3
011: LIN4/RIN4
100: LIN5/RIN5
101: LIN6/RIN6
Addr
0AH
Register Name
Audio Data Format
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
DIFB1
1
DIFB0
0
TDMA1
0
TDMA0
0
DIFA1
1
DIFA0
0
DIFA1-0, TDMA1-0: Audio format control for PORTA
Refer Table 31, Table 32, Table 33.
DIFB1-0: Audio format control for PORTB
Refer Table 34.
Addr
0BH
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
De-emphasis/ ATT speed
DEM21
0
DEM20
1
DEM11
0
DEM10
1
0
0
ATSAD
0
0
0
ATSDA
0
Default
ATSDA: DAC digital Attenuator transition time control
ATSAD: ADC digital Attenuator transition time control
Refer Table 37, Table 38.
DEM11-10: DAC1 De-emphasis filter control
DEM21-20: DAC2 De-emphasis filter control
Refer Table 30.
MS0427-E-01
2005/11
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ASAHI KASEI
Addr
0CH
0DH
Register Name
LIN Volume Control
RIN Volume Control
Default
[AK4683]
D7
D6
D5
D4
D3
D2
D1
D0
ATTAD7
ATTAD6
ATTAD5
ATTAD4
ATTAD3
ATTAD2
ATTAD1
ATTAD0
ATTAD7
ATTAD6
ATTAD5
ATTAD4
ATTAD3
ATTAD2
ATTAD1
ATTAD0
0
0
1
1
0
0
0
0
ATTAD7-0: ADC Attenuation level control
Refer Table 35.
Addr
0EH
0FH
10H
11H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
LOUT1 Volume Control
ROUT1 Volume Control
LOUT2 Volume Control
ROUT2 Volume Control
ATTDA7
ATTDA7
ATTDA6
ATTDA6
ATTDA5
ATTDA5
ATTDA4
ATTDA4
ATTDA3
ATTDA3
ATTDA2
ATTDA2
ATTDA1
ATTDA1
ATTDA0
ATTDA0
ATTDA7
ATTDA6
ATTDA5
ATTDA4
ATTDA3
ATTDA2
ATTDA1
ATTDA0
ATTDA7
ATTDA6
ATTDA5
ATTDA4
ATTDA3
ATTDA2
ATTDA1
ATTDA0
0
0
0
1
1
0
0
0
D5
0
D4
D3
D2
D1
D0
OPGA4
OPGA3
OPGA2
OPGA1
OPGA0
0
0
0
0
0
0
Default
ATTDA7-0: DAC Attenuation level control
Refer Table 36.
Addr
12H
Register Name
HP Volume Control
Default
D7
D6
0
0
0
0
OPGA5-0: HP OPGA Attenuation level control
Refer Table 42.
Addr
13H
Register Name
OVF/DZF/V Control
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
ZCE
1
VIN
0
FUNC1
0
FUNC0
0
DZFM1
0
DZFM0
0
DZFM1-0: DZF mode setting
Refer Table 7.
FUNC1-0: OVF/DZF/V mode control
00: off (“L” output. default)
01: ADC Overflow detection
10: DAC Zero data detection
11: V output
VIN: DIT V bit control
0: V bit =”0” (default)
1: V bit =”1”
ZCE: OPGA Zero-cross enable
0: Disable
1: Enable (default)
MS0427-E-01
2005/11
- 70 -
ASAHI KASEI
[AK4683]
„ Register Map (DIR/DIT part)
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
CLK & Power Down Control
CS12
1
CM1
CM0
OCKS1
OCKS0
PWN
RSTN2
01H
Format & De-em Control
0
1
1
0
DEAU
DEM1
DEM0
DFS
02H
Input/ Output Control 0
TXE
0
OPS1
OPS0
0
0
0
0
03H
Input/ Output Control 1
EFH1
EFH0
0
DIT
04H
INT MASK
05H
TEST
06H
07H
MQIT0 MAUT0
0
MCIT0
MULK0 MDTS0
1
0
0
IPS1
IPS0
MPE0
MAUD0
MPAR0
1
0
1
1
0
1
Receiver status 0
QINT
AUTO
CINT
PEM
AUDION
PAR
Receiver status 1
FS3
FS2
FS1
FS0
0
V
QCRC
CCRC
08H
RX Channel Status Byte 0
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
UNLCK DTSCD
09H
RX Channel Status Byte 1
CR15
CR14
CR13
CR12
CR11
CR10
CR9
CR8
0AH
RX Channel Status Byte 2
CR23
CR22
CR21
CR20
CR19
CR18
CR17
CR16
0BH
RX Channel Status Byte 3
CR31
CR30
CR29
CR28
CR27
CR26
CR25
CR24
0CH
RX Channel Status Byte 4
CR39
CR38
CR37
CR36
CR35
CR34
CR33
CR32
0DH
TX Channel Status Byte 0
CT7
CT6
CT5
CT4
CT3
CT2
CT1
CT0
0EH
TX Channel Status Byte 1
CT15
CT14
CT13
CT12
CT11
CT10
CT9
CT8
0FH
TX Channel Status Byte 2
CT23
CT22
CT21
CT20
CT19
CT18
CT17
CT16
10H
TX Channel Status Byte 3
CT31
CT30
CT29
CT28
CT27
CT26
CT25
CT24
11H
TX Channel Status Byte 4
CT39
CT39
CT39
CT39
CT39
CT39
CT39
CT32
12H
Burst Preamble Pc Byte 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
13H
Burst Preamble Pc Byte 1
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
14H
Burst Preamble Pd Byte 0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
15H
Burst Preamble Pd Byte 1
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
16H
Q-subcode Address / Control
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
17H
Q-subcode Track
Q17
Q16
Q15
Q14
Q13
Q12
Q11
Q10
18H
Q-subcode Index
Q25
Q24
Q23
Q22
Q21
Q20
Q19
Q18
19H
Q-subcode Minute
Q33
Q32
Q31
Q30
Q29
Q28
Q27
Q26
1AH
Q-subcode Second
Q41
Q40
Q39
Q38
Q37
Q36
Q35
Q34
1BH
Q-subcode Frame
Q49
Q48
Q47
Q46
Q45
Q44
Q43
Q42
1CH
Q-subcode Zero
Q57
Q56
Q55
Q54
Q53
Q52
Q51
Q50
1DH
Q-subcode ABS Minute
Q65
Q64
Q63
Q62
Q61
Q60
Q59
Q58
1EH
Q-subcode ABS Second
Q73
Q72
Q71
Q70
Q69
Q68
Q67
Q66
1FH Q-subcode ABS Frame
Q81
Q80
Q79
Q78
Q77
Q76
Q75
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the internal timing is reset and the registers are initialized to their default values.
All data can be written to the register even if PWN bit is “0”.
The “0” register should be written “0”, the “1” register should be written “1” data.
Q74
MS0427-E-01
2005/11
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ASAHI KASEI
[AK4683]
„ Register Definitions
Reset & Initialize
Addr
Register Name
00H CLK & Power Down Control
R/W
Default
D7
CS12
R/W
0
D6
1
R/W
1
D5
CM1
R/W
0
D4
CM0
R/W
0
D3
D2
OCKS1 OCKS0
R/W
R/W
0
0
D1
PWN
R/W
1
D0
RSTN2
R/W
1
RSTN2: Timing Reset & Register Initialize
0: Reset & Initialize
1: Normal Operation (default)
PWN: Power Down
0: Power Down
1: Normal Operation (default)
OCKS1-0: Master Clock Frequency Select
Refer Table 3, Table 57.
CM1-0: Master Clock Operation Mode Select
Refer Table 1, Table 45, Table 55.
CS12: Channel Status Select
0: Channel 1 (default)
1: Channel 2
Selects which channel status is used to derive C-bit buffers, AUDION, PEM, FS3, FS2, FS1, FS0,
Pc and Pd. The de-emphasis filter is controlled by channel 1 in the Parallel Mode.
Format & De-emphasis Control
Addr
Register Name
01H Format & De-em Control
R/W
Default
D7
0
R/W
0
D6
1
R/W
1
D5
1
R/W
1
D4
0
R/W
0
D3
DEAU
R/W
1
D2
DEM1
R/W
0
D1
DEM0
R/W
1
D0
DFS
R/W
0
DFS: 96kHz De-emphasis Control
Refer Table 52.
DEM1-0: 32, 44.1, 48kHz De-emphasis Control
Refer Table 52.
DEAU: De-emphasis Auto Detect Enable
0: Disable
1: Enable (default)
MS0427-E-01
2005/11
- 72 -
ASAHI KASEI
[AK4683]
Input/Output Control
Addr
Register Name
02H Input/ Output Control 0
R/W
Default
D7
TXE
R/W
1
D6
0
R/W
0
D5
OPS1
R/W
0
D4
OPS0
R/W
0
D3
0
R/W
0
D2
0
R/W
0
D1
0
R/W
0
D0
0
R/W
0
D5
0
R/W
0
D4
0
R/W
0
D3
DIT
R/W
1
D2
0
R/W
0
D1
IPS1
R/W
0
D0
IPS0
R/W
0
OPS1-0: Output Through Data Select for TX pin
Refer Table 54.
TXE: TX Output Enable
0: Disable. TX0 pin outputs “L”.
1: Enable (default)
Addr
Register Name
03H Input/ Output Control 1
R/W
Default
D7
EFH1
R/W
0
D6
EFH0
R/W
1
IPS1-0: Input Recovery Data Select
Refer Table 53.
DIT: Through data/Transmit data select for TX1 pin
0: Through data (RX data).
1: Transmit data (DAUX2 data. default.).
(U bit for DIT is fixed to “0”)
EFH1-0: Interrupt 0 Pin Hold Count Select
00: 512 LRCK2
01: 1024 LRCK (default)
10: 2048 LRCK
11: 4096 LRCK
MS0427-E-01
2005/11
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ASAHI KASEI
[AK4683]
Mask Control for INT
Addr
Register Name
04H INT MASK
R/W
Default
MPR0:
MAN0:
MPE0:
MDTS0:
MUL0:
MCI0:
MAT0:
MQI0:
D7
MQI0
R/W
1
D6
MAT0
R/W
1
D5
MCI0
R/W
1
D4
MUL0
R/W
0
D3
MDTS0
R/W
1
D2
MPE0
R/W
1
D1
MAN0
R/W
1
D0
MPR0
R/W
0
Mask Enable for PAR bit
Mask Enable for AUDN bit
Mask Enable for PEM bit
Mask Enable for DTSCD bit
Mask Enable for UNLOCK bit
Mask Enable for CINT bit
Mask Enable for AUTO bit
Mask Enable for QINT bit
0: Mask disable
1: Mask enable
MS0427-E-01
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ASAHI KASEI
[AK4683]
Receiver Status 0
Addr
Register Name
06H Receiver status 0
R/W
Default
D7
QINT
RD
0
D6
AUTO
RD
0
D5
CINT
RD
0
D4
D3
UNLCK DTSCD
RD
RD
0
0
D2
PEM
RD
0
D1
AUDION
RD
0
D0
PAR
RD
0
D1
QCRC
RD
0
D0
CCRC
RD
0
PAR: Parity Error or Biphase Error Status
0: No Error
1: Error
It is “1” if Parity Error or Biphase Error is detected in the sub-frame.
AUDION: Audio Bit Output
0: Audio
1: Non Audio
This bit is made by encoding channel status bits.
PEM: Pre-emphasis Detect.
0: OFF
1: ON
This bit is made by encoding channel status bits.
DTSCD: DTS-CD Auto Detect
0: No detect
1: Detect
UNLCK: PLL Lock Status
0: Locked
1: Out of Lock
CINT: Channel Status Buffer Interrupt
0: No change
1: Changed
AUTO: Non-PCM Auto Detect
0: No detect
1: Detect
QINT: Q-subcode Buffer Interrupt
0: No change
1: Changed
QINT, CINT and PAR bits are initialized when 06H is read.
Receiver Status 1
Addr
Register Name
07H Receiver status 1
R/W
Default
D7
FS3
RD
0
D6
FS2
RD
0
D5
FS1
RD
0
D4
FS0
RD
1
D3
0
RD
0
D2
V
RD
0
CCRC: Cyclic Redundancy Check for Channel Status
0:No Error
1:Error
QCRC: Cyclic Redundancy Check for Q-subcode
0:No Error
1:Error
V: Validity of channel status
0:Valid
1:Invalid
FS3-0: Sampling Frequency detection (refer Table 48.)
MS0427-E-01
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ASAHI KASEI
[AK4683]
Receiver Channel Status
Addr
08H
09H
0AH
0BH
0CH
Register Name
RX Channel Status Byte 0
RX Channel Status Byte 1
RX Channel Status Byte 2
RX Channel Status Byte 3
RX Channel Status Byte 4
R/W
Default
D7
CR7
CR15
CR23
CR31
CR39
D6
CR6
CR14
CR22
CR30
CR38
D5
CR5
CR13
CR21
CR29
CR37
D4
CR4
CR12
CR20
CR28
CR36
D3
CR3
CR11
CR19
CR27
CR35
D2
CR2
CR10
CR18
CR26
CR34
D1
CR1
CR9
CR17
CR25
CR33
D0
CR0
CR8
CR16
CR24
CR32
D2
CT2
CT10
CT18
CT26
CT34
D1
CT1
CT9
CT17
CT25
CT335
D0
CT0
CT8
CT16
CT24
CT32
D2
PC2
PC10
PD2
PD10
D1
PC1
PC9
PD1
PD9
D0
PC0
PC8
PD0
PD8
RD
Not initialized
CR39-0: Receiver Channel Status Byte 4-0
Transmitter Channel Status
Addr
0DH
0EH
0FH
10H
11H
Register Name
TX Channel Status Byte 0
TX Channel Status Byte 1
TX Channel Status Byte 2
TX Channel Status Byte 3
TX Channel Status Byte 3
R/W
Default
D7
CT7
CT15
CT23
CT31
CT39
D6
CT6
CT14
CT22
CT30
CT38
D5
CT5
CT13
CT21
CT29
CT37
D4
D3
CT4
CT3
CT12
CT11
CT20 CT19
CT28 CT27
CT36 CT35
R/W
0
CT39-0: Transmitter Channel Status Byte 4-0
Burst Preamble Pc/Pd in non-PCM encoded Audio Bitstreams
Addr
12H
13H
14H
15H
Register Name
Burst Preamble Pc Byte 0
Burst Preamble Pc Byte 1
Burst Preamble Pd Byte 0
Burst Preamble Pd Byte 1
R/W
Default
D7
PC7
PC15
PD7
PD15
D6
PC6
PC14
PD6
PD14
D5
PC5
PC13
PD5
PD13
D4
PC4
PC12
PD4
PD12
D3
PC3
PC11
PD3
PD11
RD
Not initialized
PC15-0: Burst Preamble Pc Byte 0 and 1
PD15-0: Burst Preamble Pd Byte 0 and 1
MS0427-E-01
2005/11
- 76 -
ASAHI KASEI
[AK4683]
Q-subcode Buffer
Addr
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Register Name
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
R/W
Default
D7
Q9
Q17
Q25
Q33
Q41
Q49
Q57
Q65
Q73
Q81
D6
Q8
Q16
Q24
Q32
Q40
Q48
Q56
Q64
Q72
Q80
D5
Q7
Q15
Q23
Q31
Q39
Q47
Q55
Q63
Q71
Q79
D4
Q6
Q14
Q22
Q30
Q38
Q46
Q54
Q62
Q70
Q78
D3
Q5
Q13
Q21
Q29
Q37
Q45
Q53
Q61
Q69
Q77
D2
Q4
Q12
Q20
Q28
Q36
Q44
Q52
Q60
Q68
Q76
D1
Q3
Q11
Q19
Q27
Q35
Q43
Q51
Q59
Q67
Q75
D0
Q2
Q10
Q18
Q26
Q34
Q42
Q50
Q58
Q66
Q74
RD
Not initialized
MS0427-E-01
2005/11
- 77 -
ASAHI KASEI
[AK4683]
SYSTEM DESIGN
Figure 50 shows the system connection diagram. An evaluation board is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
5
Analog in
+ 10u
12k
+
10u
0.1u
S/PDIF sources
AVSS1 49
LIN1 51
AVDD1 50
LIN2 53
RIN1 52
LIN3 55
RIN2 54
LIN4 57
RIN3 56
LIN5 59
1 PVDD
RISEL 48
2 RX0
ROPIN 47
3 I2C
LOPIN 46
4 RX1
LISEL 45
5 RX2
AVSS2 44
6 RX3
AVDD2 43
7 INT
0.1u 10u
+
0.1u
VCOM 42
8 DZF
+
2.2u
ROUT2 41
MUTE
LOUT2 40
MUTE
10 LRCKB
ROUT2 39
MUTE
11 BICKB
LOUT2 38
MUTE
12 SDTOB
MUTET 37
AK4683
9 CDTO/TEST
1u
13 OLRCKA
HPL 36
14 ILRCKA
HPR 35
32 SDTIB
31 SDTIA3
30 SDTIA
29 SDTIA
27 SCL
26 SDA
HVDD 33
47u
6.8
47u
Analog out
Headphone
0.1u 10u
+
Analog 5V
X’tal
0.1u
C
C
3.3V to 5V
Digital
Audio DSP1
25 PDN
23 TX
22 XTO
21 XTI
20 DVDD
18 TVDD
19 DVSS
+
HVSS 34
6.8
Analog 5V
10u
+
0.1u
10u
17 MCKO
16 SDTOA
24 MCLK2
15 BICKA
28 CSN/TEST
Audio DSP2
RIN4 58
LIN6 61
RIN5 60
RIN6 62
PVSS 63
R 64
0.1u
Micro
Controller
5V Digital
S/PDIF out
Digital Ground
Analog Ground
Figure 50. Typical Connection Diagram( I2C serial control mode)
Notes:
- “C” depends on the crystal.
- AVSS, DVSS and PVSS must be connected the same analog ground plane.
- Digital signals, especially clocks, should be kept away from the R pin in order to avoid an effect to the clock jitter
performance.
- In case of coaxial input, ground of RCA connector and terminator should be connected to PVSS of the AK4683
with low impedance on PC board.
MS0427-E-01
2005/11
- 78 -
ASAHI KASEI
[AK4683]
1. Grounding and Power Supply Decoupling
The AK4683 requires careful attention to power supply and grounding arrangements. AVDD1, AVDD2, DVDD, PVDD
and HVDD are usually supplied from analog supply in system. If AVDD1, AVDD2, DVDD, PVDD and HVDD are
supplied separately, the power up sequence is not critical. AVSS1, AVSS2, DVSS PVSS and HVSS of the AK4683
must be connected to analog ground plane. System analog ground and digital ground should be connected together
near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the
AK4683 as possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference Inputs
The voltage of AVDD1, AVDD2 sets the analog input/output range. VCOM is a signal ground of this chip. An
electrolytic capacitor 2.2µF parallel with a 0.1µF ceramic capacitor attached between VCOM pin and AVSS1 pin
eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially
clocks, should be kept away from the AVDD1, AVDD2 and VCOM pins in order to avoid unwanted coupling into the
AK4683.
3. Analog Inputs
The AK4683 receives the analog input through the single-ended Pre-amp using external resistors. Adjust the input
level/gain at Pre-amp to match the input range 1.22 x AVDD1 Vpp (typ. fs=48kHz, Ri =47kohm, Rf = 24kohm). Each
input pins are biased internally. The ADC output data format is 2’s complement. The internal digital HPF removes the
DC offset.
The AK4683 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples
of 64fs. The AK4683 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
4. Analog Outputs
The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales with
the supply voltage and nominally 0.6 x AVDD2 Vpp. The DAC input data format is 2’s complement. The output voltage
is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is VCOM
voltage for 000000H(@24bit). The internal analog filters remove most of the noise generated by the delta-sigma
modulator of DAC beyond the audio passband.
DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV.
5. Attention to the PCB Wiring
LIN1-6 and RIN1-6 pins are the summing nodes of the Pre-Amp. Attention should be given to avoid coupling with
other signals on those nodes. This can be accomplished by making the wire length of the input resistors as short as
possible. The same theory also applies to the LOPIN/ROPIN pins and feedback resistors; keep the wire length to a
minimum. Unused input pins among LIN1-6 and RIN1-6 pins should be left open.
MS0427-E-01
2005/11
- 79 -
ASAHI KASEI
[AK4683]
PACKAGE
64pin LQFP(Unit:mm)
12.0±0.3
1.70max
0.10±0.10
10.0
1.40
33
48
32
64
17
0.5
12.0 ±0.3
49
0.17±0.05
1
16
0.21±0.05
0.10 M
1.0
0° ~10°
0.45±0.2
0.10
„ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0427-E-01
2005/11
- 80 -
ASAHI KASEI
[AK4683]
MARKING
AKM
AK4683EQ
XXXXXXX
1
1)
2)
3)
4)
Pin #1 indication
Asahi Kasei Logo
Marking Code: AK4683EQ
Date Code: XXXXXXX(7 digits)
Revision History
Date (YY/MM/DD)
05/09/30
05/11/15
Revision
00
01
Reason
First Edition
Error Correction
Page
Contents
30
38
67
Table 28, 29: “off” -> “SDTIB”
“(Table 16)” -> “(Table 37, Table 38)”
CLKDT: “Table 58” -> “Table 56”
SELAO: “DIT[1:0]” -> “DITD[1:0]”
MS0427-E-01
2005/11
- 81 -
ASAHI KASEI
[AK4683]
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to
customs and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
MS0427-E-01
2005/11
- 82 -