AKM AKD4708

[AK4708]
AK4708
AV SCART Switch with Two RGB Outputs
GENERAL DESCRIPTION
The AK4708 is an IIC controlled audio and video switch matrix designed for digital TV and set-top-box
applications. The AK4708 offers the ideal features for digital set-top-box systems. The AK4708 includes
the audio switches, video switches, video filters. The AK4708 provides high performance audio and video
routings to meet dual SCART connections. The AK4708 is supplied in a small 48-pin LQFP package to
contribute space saving in PCB.
FEATURES
†Analog Switches for SCART
Audio section
THD+N: −86dB (@2Vrms)
Dynamic Range: 96dB (@2Vrms)
Analog Inputs
Two Full Differential Stereo Inputs or Single-ended input for Decoder DAC
Two Stereo Inputs (TV & VCR SCART)
Analog Outputs
Two Stereo Outputs (TV & VCR SCART)
Stereo Analog Volume with Pop-noise Free Circuit (+6dB to –60dB & Mute)
Pop Noise Free Circuit for Power on/off
Video section
VCR SCART supports RGB mode
Integrated LPF: [email protected]
75Ω driver
6dB Gain for Outputs
Four CVBS/Y inputs (ENCx2, TV, VCR), Two CVBS/Y outputs (TV, VCR)
Three R/C inputs (ENCx2, VCR), Two R/C outputs (TV, VCR)
Two G and B inputs (ENC, VCR), Two G and B outputs (TV, VCR)
TV/VCR input monitor
Loop-through Mode for standby
Auto-Startup Mode for power saving
SCART pin#16 (Fast Blanking), pin#8 (Slow Blanking) Control
†Power supply
5V+/−5% and 12V+/−10%
Small current consumption in Standby Mode
(VD=10μA typ., VVD1+VVD2=10μA typ., VP=10μA typ.)
†Package
48-pin LQFP
MS0618-E-00
2007/04
-1-
[AK4708]
■ Block Diagram
DVCOM
-6dB to +12dB
+6 to -60dB
(3dB/step)
(2dB/step)
AINL+
TVOUTL
AINLAMP
AINR-
TVOUTR
AINR+
MONO
Volume #1
Volume #0
TV1-0
PVCOM
VD
VCRINL
VP
VCRINR
TVINL
VCROUTL
VCROUTR
TVINR
VMONO
SCL
Register
SDA
Control
Bias
VCR1-0
VSS
PDN
Audio Block
MS0618-E-00
2007/04
-2-
[AK4708]
( Typical connection )
VVD1
VVD2
( Typical connection )
Monitor
VVSS
ENC CVBS/Y
ENC Y
VCR CVBS/Y
TV CVBS
ENC R/C/Pr
ENC C
VCR R/C/Pr
ENCV
ENCY
6dB
TVVOUT
6dB
TVRC
VCRVIN
TVVIN
ENCRC
ENCC
TV SCART
VCRRC
ENC G/CVBS
ENCG
VCR G
VCRG
ENC B/Pb
ENCB
VCR B/Pb
VCRB
6dB
TVG
6dB
TVB
6dB
VCRVOUT
VCR SCART
6dB
VCRC
6dB
VCRGO
6dB
VCRBO
Video Block
MS0618-E-00
2007/04
-3-
[AK4708]
( Typical connection )
VCR FB
( Typical connection )
VCRFB
2V
6dB
TVFB
0V
TV SCART
0/ 6/ 12V
TVSB
VCRSB
VCR SCART
0/ 6/ 12V
Monitor
2V
6dB
INT
VCRFBO
0V
Video Blanking Block
MS0618-E-00
2007/04
-4-
[AK4708]
■ Ordering Guide
AK4708EQ
AKD4708
-10 ∼ +70°C
48pin LQFP (0.5mm pitch)
Evaluation board for AK4708
VD
VSS
PVCOM
DVCOM
VP
TVOUTL
TVOUTR
VCROUTL
VCROUTR
TVINL
TVINR
VCRINL
36
35
34
33
32
31
30
29
28
27
26
25
■ Pin Layout
AINR-
37
24
VCRINR
AINR+
38
23
TVSB
AINL-
39
22
VCRSB
AINL+
40
21
INT
SCL
41
20
VCRB
SDA
42
19
VCRG
PDN
43
18
VCRRC
VCRBO
44
17
VCRFB
VCRGO
45
16
VCRVIN
VCRFBO
46
15
TVVIN
VCRVOUT
47
14
ENCY
TVFB
48
13
ENCV
AK4708
8
9
10
11
12
VVD1
ENCB
ENCG
ENCRC
ENCC
5
TVRC
7
4
VVD2
TVB
3
TVVOUT
6
2
VVSS
TVG
1
VCRC
Top View
MS0618-E-00
2007/04
-5-
[AK4708]
PIN/FUNCTION
No.
1
2
3
Pin Name
VCRC
VVSS
TVVOUT
I/O
O
O
4
VVD2
-
5
6
7
TVRC
TVG
TVB
O
O
O
8
VVD1
-
9
10
11
12
13
14
15
16
17
18
19
20
ENCB
ENCG
ENCRC
ENCC
ENCV
ENCY
TVVIN
VCRVIN
VCRFB
VCRRC
VCRG
VCRB
I
I
I
I
I
I
I
I
I
I
I
I
21
INT
O
22
23
24
25
26
27
28
29
30
31
VCRSB
TVSB
VCRINR
VCRINL
TVINR
TVINL
VCROUTR
VCROUTL
TVOUTR
TVOUTL
32
VP
-
33
DVCOM
O
34
PVCOM
O
35
VSS
-
I/O
O
I
I
I
I
O
O
O
O
Function
Chrominance Output Pin for VCR
Video Ground Pin #1, 0V
Composite/Luminance Output Pin for TV
Video Power Supply Pin #2, 5V
Normally connected to VVSS with a 0.1μF ceramic capacitor in parallel
with a 10μF electrolytic cap.
Red/Chrominance Output Pin for TV
Green Output Pin for TV
Blue Output Pin for TV
Video Power Supply Pin #1, 5V
Normally connected to VVSS with a 0.1μF ceramic capacitor in parallel
with a 10μF electrolytic cap.
Blue Input Pin for Encoder
Green Input Pin for Encoder
Red/Chrominance Input Pin #1 for Encoder
Chrominance Input Pin #2 for Encoder
Composite/Luminance Input Pin #1 for Encoder
Composite/Luminance Input Pin #2 for Encoder
Composite/Luminance Input Pin for TV
Composite/Luminance Input Pin for VCR
Fast Blanking Input Pin for VCR
Red/Chrominance Input Pin for VCR
Green Input Pin for VCR
Blue Input Pin for VCR
Interrupt Pin for Video Blanking
Normally connected to VD(5V) through 10kΩ resistor externally.
Slow Blanking Input/Output Pin for VCR
Slow Blanking Output Pin for TV
Rch VCR Audio Input Pin
Lch VCR Audio Input Pin
Rch TV Audio Input Pin
Lch TV Audio Input Pin
Rch Analog Output Pin #1
Lch Analog Output Pin #1
Rch Analog Output Pin #2
Lch Analog Output Pin #2
Power Supply Pin, 12V
Normally connected to VSS with a 0.1μF ceramic capacitor in parallel
with a 10μF electrolytic cap.
Audio Common Voltage Pin #1
Normally connected to VSS with a 0.1μF ceramic capacitor in parallel
with a 10μF electrolytic cap.
Audio Common Voltage Pin #2
Normally connected to VSS with a 0.1μF ceramic capacitor in parallel
with a 10μF electrolytic cap. The caps affect the settling time of audio bias
level.
Ground Pin , 0V
MS0618-E-00
2007/04
-6-
[AK4708]
PIN/FUNCTION (Continued)
No.
Pin Name
I/O
36
VD
37
38
39
40
41
42
AINR−
AINR+
AINL−
AINL+
SCL
SDA
43
PDN
I
44
45
46
47
48
VCRBO
VCRGO
VCRFBO
VCRVOUT
TVFB
O
O
O
O
O
I
I
I
I
I
I/O
Function
Power Supply Pin, 5V
Normally connected to VSS with a 0.1μF ceramic capacitor in parallel
with a 10μF electrolytic cap.
Rch Negative Analog Input Pin
Rch Positive Analog Input Pin
Lch Negative Analog Input Pin
Lch Positive Analog Input Pin
Control Data Clock Pin
Control Data Pin
Power-Down Mode Pin
When at “L”, the AK4708 is in the power-down mode and is held in reset.
The AK4708 should always be reset upon power-up.
Blue Output Pin for VCR
Green Output Pin for VCR
Fast Blanking Output Pin for VCR
Composite/Luminance Output Pin for VCR
Fast Blanking Output Pin for TV
Note: All digital input pins should not be left floating.
MS0618-E-00
2007/04
-7-
[AK4708]
INTERNAL EQUIVALENT CIRCUIT
Pin No.
Pin Name
Type
41
43
SCL
PDN
Digital IN
Equivalent Circuit
VD
Description
200
VSS
VD
AINR+
AINR−
AINL−
AINL+
38
37
39
40
150K
Audio IN
VSS
VD
200
42
SDA
Digital I/O
I2C Bus voltage must not exceed
VD.
VSS
VVD1
21
INT
Normally connected to VD(5V)
through 10kΩ resister externally.
Digital OUT
VSS
47
48
3
5
6
7
1
44
45
46
VCRVOUT
TVFB
TVVOUT
TVRC
TVG
TVB
VCRC
VCRGO
VCRBO
VCRFBO
VVD2
VVD2
Video OUT
VVSS1
MS0618-E-00
VVSS2
2007/04
-8-
[AK4708]
Pin No.
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
ENCB
ENCG
ENCRC
ENCC
ENCV
ENCY
TVVIN
VCRVIN
VCRFB
VCRRC
VCRG
VCRB
Type
Equivalent Circuit
VVD1
200
VCRSB
TVSB
The 60kΩ is attached for
Chrominance input.
Video IN
(60K)
VVSS
VP
22
23
Description
VP
200
The 120kΩ is not attached for
TVSB.
Video SB
(120k)
VVSS
VVSS
VVSS
VP
24
25
26
27
VCRINR
VCRINL
TVINR
TVINL
150k
Audio IN
VSS
VP
28
29
30
31
VCROUTR
VCROUTL
TVOUTR
TVOUTL
VP
100
Audio OUT
VSS
VD
33
34
DVCOM
PVCOM
VSS
VD
VD
100
VCOM OUT
VSS
VSS
MS0618-E-00
VSS
2007/04
-9-
[AK4708]
ABSOLUTE MAXIMUM RATINGS
(VSS =VVSS = 0V;Note 1)
Parameter
Power Supply
(Note 2)
Input Current (any pins except for supplies)
Input Voltage
Video Input Voltage
Audio Input Voltage
(except AINL+/−, AINR+/− pins)
Audio Input Voltage
(AINL+/−, AINR+/− pins)
Ambient Operating Temperature
Storage Temperature
Symbol
VD
VVD1
VVD2
VP
IIN
VIND
VINV
min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
max
6.0
6.0
6.0
15
±10
VD+0.3
VVD1+0.3
Units
V
V
V
V
mA
V
V
VINA1
−0.3
VP+0.3
V
VINA2
−0.3
VD+0.3
V
Ta
Tstg
−10
−65
70
150
°C
°C
Note 1.All voltages with respect to ground.
Note 2.VSS and VVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
MS0618-E-00
2007/04
- 10 -
[AK4708]
RECOMMENDED OPERATING CONDITIONS
(VSS = VVSS = 0V; Note 1)
Parameter
Power Supply
(Note 2)
Symbol
VD
VVD1
VVD2
VP
min
4.75
4.75
4.75
10.8
typ
5.0
5.0
5.0
12
max
5.25
5.25
VVD1
13.2
Units
V
V
V
V
Note 1. All voltages with respect to ground.
Note 2. VVD1 and VVD2 must be connected to the same voltage.
*AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
ELECTRICAL CHARACTERISTICS
(Ta = 25°C; VP = 12V, VD = 5V; VVD1 = VVD2 = 5V)
Power Supplies
min
Power Supply Current
Normal Operation (PDN = “H”)
(Note 3)
VD+VVD1+VVD2
VP
Power-Down Mode (PDN = “L”)
(Note 4)
VD
VVD1+VVD2
VP
typ
max
Units
5
120
10
mA
mA
10
10
10
100
100
100
μA
μA
μA
typ
-
max
0.8
Units
V
V
-
0.4
V
-
±10
µA
Note 3. STBY bit = “0”, All video outputs active. No signal, no load for A/V switches.
Note 4. All digital inputs are held at VD or VSS.
DIGITAL CHARACTERISTICS
(Ta = 25°C; VD = 4.75 ∼ 5.25V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
2.0
Low-Level Input Voltage
VIL
Low-Level Output Voltage
VOL
(SDA pin: Iout= 3mA, INT pin: Iout= 1mA)
Input Leakage Current (Except VCRSB pin)
Iin
-
MS0618-E-00
2007/04
- 11 -
[AK4708]
ANALOG CHARACTERISTICS (AUDIO)
(Ta = 25°C; VP = 12V, VD = 5V; VVD1 = VVD2 = 5V; Signal Frequency = 1kHz;
Measurement frequency = 20Hz ∼ 20kHz; RL ≥4.5kΩ; 0dB=2Vrms output; unless otherwise specified)
Parameter
min
typ
max
Analog Input: (TVINL/TVINR/VCRINL/VCRINR pins)
Analog Input Characteristics
Input Voltage
2.0
Input Resistance
100
150
Analog Input: (AINL+/AINL-/AINR-/AINR+ pins)
Analog Input Characteristics
2.0
Input Voltage
(AIN+) − (AIN−) (Note 6)
Input Resistance
(AINL+, AINR+ pins) (Note 7)
140
210
Input Resistance
(AINL-, AINR- pins) (Note 7)
75
115
Stereo/Mono Output: (TVOUTL/TVOUTR/VCROUTL/VCROUTR pins)
(Note 5)
Analog Output Characteristics
Volume#0 Step Width
(Note 8)
2.3
3.0
3.7
Volume#1 Step Width (+6dB to –12dB)
1.6
2
2.4
(-12dB to –40dB)
0.5
2
3.5
(-40dB to –60dB)
0.1
2
3.9
-80
THD+N
(at 2Vrms output, Note 9)
−86
(at 3Vrms output, Note 9, Note 10)
-60
92
96
Dynamic Range (−60dB Output, A-weighted, Note 9)
S/N
(A-weighted, Note 9)
92
96
Interchannel Isolation
(Note 9, Note 11)
80
90
Interchannel Gain Mismatch
(Note 9, Note 11)
0.3
Gain Drift
200
Load Resistance
(AC-Lord)
TVOUTL/R, VCROUTL/R
4.5
Load Capacitance
TVOUTL/R, VCROUTL/R
20
1.85
2
2.15
Output Voltage
( Note 13)
Power Supply Rejection (PSR)
(Note 12)
50
Units
Vrms
kΩ
Vrms
kΩ
kΩ
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
ppm/°C
kΩ
pF
Vrms
dB
Note 5. Measured by Audio Precision System Two Cascade.
Note 6. If input is single ended, maximum input voltage is 1Vrms.
Note 7. Differential signal is input to AIN- and AIN+. volume #0 = 0dB.
Note 8. The output level of the internal AMP with volume #0 should be less than 2Vrms..
The output level must be adjusted by the volume #1 when output level of the AK4708 exceeds 2Vrms.
Note 9. Analog In to TVOUT. Path : AINL+/− → TVOUTL, AINR+/− → TVOUTR
Note 10. Except VCROUTL/VCROUTR pins.
Note 11. Between TVOUTL and TVOUTR with analog inputs AINL+/−, AINL/R+/−, 1kHz/0dB.
Note 12. The PSR is applied to VD with 1kHz, 100mV.
Note 13. The audio output must not exceed 3Vrms at VP±5%. The audio output must not exceed 2.15Vrms at VP±10%.
MS0618-E-00
2007/04
- 12 -
[AK4708]
ANALOG CHARACTERISTICS (VIDEO)
(Ta = 25°C; VP = 12V, VD= 5V; VVD1 = VVD2 = 5V; unless otherwise specified.)
Parameter
Conditions
Sync Tip Clamp Voltage
at output pin.
R/G/B Clamp Voltage
at output pin.
Pb/Pr Clamp Voltage
at output pin.
Chrominance Bias Voltage
at output pin.
Gain
Input = 0.3Vp-p, 100kHz
Interchannel Gain Mismatch1 TVRC, TVG, TVB. Input = 0.3Vp-p, 100kHz.
VCRC, VCRGO, VCRBO.
Interchannel Gain Mismatch2
Input = 0.3Vp-p, 100kHz.
Frequency Response
Input=0.3Vp-p, C1=C2=0pF. 100kHz to 6MHz.
at 10MHz.
at 27MHz.
Group Delay Distortion
At 4.43MHz with respect to 1MHz.
Input Impedance
Chrominance input (internally biased)
Input Signal
f = 100kHz, maximum with distortion < 1.0%,
gain = 6dB.
Load Resistance
(Figure 1)
Load Capacitance
C1 (Figure 1)
C2 (Figure 1)
Dynamic Output Signal
f = 100kHz, maximum with distortion < 1.0%
Y/C Crosstalk
f = 4.43MHz, 1Vp-p input. Among TVVOUT,
TVRC and VCRVOUT outputs.
S/N
Reference Level = 0.7Vp-p, CCIR 567 weighting.
BW = 15kHz to 5MHz.
Differential Gain
0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz.
Differential Phase
0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz.
min
max
5.5
-0.5
typ
0.7
0.7
2.2
2.2
6
-
6.5
0.5
Units
V
V
V
V
dB
dB
-0.5
-
0.5
dB
0.5
dB
dB
dB
ns
kΩ
-1.0
-3
-40
40
60
-25
15
-
-
-
1.5
Vpp
150
-
-
-
400
15
3
Ω
pF
pF
Vpp
-
−50
-
dB
-
74
-
dB
-
0.6
-
%
-
0.8
-
Degree
R1
75 ohm
Video Signal Output
R2
75 ohm
C1
C2
max: 15pF
max: 400pF
Figure 1. Load Resistance R1+R2 and Load Capacitance C1/C2.
MS0618-E-00
2007/04
- 13 -
[AK4708]
SWITCHING CHARACTERISTICS
(Ta = 25°C; VP = 10.8 ∼ 13.2V, VD = 4.75 ∼ 5.25V, VVD1 = VVD2 = 4.75 ∼ 5.25V)
Parameter
Symbol
min
typ
Control Interface Timing (I2C Bus):
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time
tHD:STA
0.6
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 14) tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise
tSP
0
Suppressed by Input Filter
Capacitive load on bus
Cb
Reset Timing
tPD
150
PDN Pulse Width
(Note 15)
max
Units
400
-
kHz
μs
μs
0.3
0.3
50
μs
μs
μs
μs
μs
μs
μs
μs
ns
400
pF
ns
Note 14. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 15. The AK4708 should be reset by PDN pin = “L” upon power up.
Note 16. I2C is a registered trademark of Philips Semiconductors.
MS0618-E-00
2007/04
- 14 -
[AK4708]
■ Timing Diagram
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
Figure 2. I2C Bus mode Timing
tPD
PDN
VIL
Figure 3. Power-down Timing
MS0618-E-00
2007/04
- 15 -
[AK4708]
OPERATION OVERVIEW
1. System Reset and Power-down options
The AK4708 should be reset once by bringing PDN pin = “L” upon power-up. The AK4708 has several operation modes.
The PDN pin, AUTO bit, BIAS bit, STBY bit and AMP bit control operation modes as shown in Table 1 and Table 2.
Mode
0
PDN pin
“L”
1
“H”
2
3
“H”
“H”
4
“H”
5
“H”
AUTO bit
x
Mode
Full Power-down
Auto Startup mode
1
x
x
(Power-on default)
0
1
1
Standby & Mute
0
1
0
Standby
Mute
0
0
1
(AMP power down)
Normal operation
0
0
0
(AMP operation)
Table 1. Operation Mode Settings (x: Don’t Care)
Register
Control
Mode
0
1
2
Standby & mute
3
Standby
Mute
(AMP power down)
Normal operation
(AMP operation)
4
5
Video
Output
TVFB
TVSB
VCRFBO
VCRSB
Power
down
Hi-Z
Hi-Z
Pull
-down
(Note 17)
Active
Active
(Note 25)
Power
down
Active
Power
down
Active
(Note 19)
Hi-Z/
Active
Active
Active
No video
input
Video input
(Note 18)
Available
BIAS bit
x
Audio Bias
Level
NOT
available
Full Power-down
Auto Startup mode
(Power-on default)
STBY bit
x
Note 17. Internally pulled down by 120kΩ (typ) resistor.
Note 18. Video input to TVVIN or VCRVIN.
Note 19. TVOUTL/R are muted by Mute bit in the default state.
Note 20. VCRC, VCRGO, VCRBO output 0V for termination.
Table 2. Status of each operation modes
MS0618-E-00
2007/04
- 16 -
[AK4708]
■ System Reset and Full Power-down Mode
The AK4708 should be reset once by bringing PDN pin = “L” upon power-up.
PDN pin: Power down pin
L: Device power down & reset
H: Normal operation.
■ Auto Startup Mode
After when the PDN pin is set to “H”, the AK4708 is in the auto startup mode. In this mode, all blocks except for the video
detection circuit are powered down. Once the video detection circuit detects video signal from TVVIN pin or VCRVIN
pin, the AK4708 goes to the stand-by mode automatically and sends “H” pulse via INT pin. The sources of TVOUTL/R
are fixed to VCRINL/R, the sources of VCROUTL/R are fixed to TVINL/R respectively. The source of DC- restore
circuit is VCRVIN pin. To exit the auto startup mode, set the AUTO bit to “0”.
AUTO bit (00H D3): Auto startup bit
0: Auto startup disable. (Manual startup)
1: Auto startup enable. (default)
■ Bias Mode
When the BIAS bit = “1”, the bias voltage on the audio output goes to GND level. Bringing BIAS bit to “0” changes this
bias voltage smoothly from GND to VP/2 by 2sec (typ.). This removes the huge click noise related the sudden change of
bias voltage at power-on. The change of BIAS bit from “1” to “0” also makes smooth transient from VP/2 to GND by 2sec
(typ). This removes the huge click noise related the sudden change of bias voltage at power-off.
BIAS bit (00H D1): Bias-off bit
0: Normal operation.
1: Set the audio bias to GND. (default)
■ Standby Mode
When the AUTO bit = BIAS bit = “0” and the STBY bit = “1”, the AK4708 is forced into TV-VCR loop through mode.
In this mode, the sources of TVOUTL/R pins are fixed to VCRINL/R pins; the sources of VCROUTL/R are fixed to
TVINL/R pins respectively. All register values themselves are NOT changed by STBY bit = “1”.
STBY bit (00H D0): Standby bit
0: Normal operation.
1: Standby mode. (default)
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[AK4708]
■ Normal Operation Mode
To change analog switches, set the AUTO bit, BIAS bit and STBY bit to “0”. The AK4708 is in power-down mode until
PDN pin = “H”. The Figure 4 shows an example of the system timing at the power-down and power-up by PDN pin.
■ Typical Operation Sequence (auto setup mode)
The Figure 4 shows an example of the system timing at auto startup mode.
Auto startup enable
PDN pin
Low Power Mode
Low Power Mode
AUTO bit
Low Power Mode
“1”(defaoult)
TVVIN
don’t care
VCRVIN
don’t care
TVVOUT,
VCRVOUT
No Signal
Signal in
Signal in
No Signal
Hi-Z
Audio out (DC)
No Signal
Signal in
Active (loop-through)
Hi-Z
don’t care
No Signal
Active (loop-through)
Active (loop-through)
(GND)
No Signal
don’t care
Hi-Z
Active (loop-through)
Figure 4.Auto startup mode sequence
■ Typical Operation Sequence (except auto setup mode)
Figure 5 shows an example of the system timing at normal operation mode.
PDN pin
AUTO bit
BIAS bit
STBY bit
TV-Source
select
“Stand-by“
“Mute”
“1” (default)
“Stand-by“
“0”
“1” (default)
“0”
“1”
“1” (default)
“1”
“0”
“1”
“0”
fixed to VCR in(Loop-through)
VCR in
VCR in
AMP
fixed to VCR in(Loop-through)
(default)
TV out
VCR in
(Note 21)
AMP
AMP
VCR in
(Note 22)
Note 21. Set the STBY bit = “0” to pass for 20.2ms after set the VMUTE bit = “0”, to prevent the click noise.
Note 22. Mute the analog outputs externally if click noise affects the system.
Figure 5. Typical operating sequence
MS0618-E-00
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- 18 -
[AK4708]
2. Audio Block
■ Switch Control
The AK4708 has switch matrixes designed primarily for SCART routing. Those are controlled via the control register as
shown in, Table 3 and Table 4 (Please refer to the Block Diagram).
(01H: D1-D0)
TV1
TV0
Source of TVOUTL/R
0
0
AMP
0
1
VCRIN
(default)
1
0
Mute
1
1
(Reserved)
Table 3. TVOUT Switch Configuration
(01H: D5-D4)
VCR1
VCR0
Source of VCROUTL/R
0
0
AMP
0
1
TVIN
(default)
1
0
Mute
1
1
Volume#1 output
Table 4. VCROUT Switch Configuration
■ Volume Control #0 (7-Level Volume)
The AK4708 has a 7-level volume control (Volume #0) as shown in Table 5. The volume reflects the change of register
value immediately.
1Vrms
2Vrms differential
input
AINL/R+
2Vrms
Volume Gain 0dB
0.47μ
TVOUTL/R
0.47μ
1Vrms
AINL/R-
Volume #0
(VCROUTL/R)
Figure 6. Volume #0(Volume Gain=0dB:default), Full Differential Stereo Input
(0DH: D5-D3)
VOL
Volume #0 Gain
Output Level (Typ)
0
1
1
1
+12dB
2Vrms (with 0.5Vrms differential input)
1
1
0
+9dB
1
0
1
+6dB
2Vrms (with 1Vrms differential input)
1
0
0
+3dB
0
1
1
0dB
2Vrms (with 2Vrms differential input) (default)
0
1
0
-3dB
0
0
1
-6dB
1Vrms (with 2Vrms differential input)
0
0
0
Mute
Note: Volume #1=0dB
Table 5. Volume #0, Full Differential Stereo Input
VOL2
VOL1
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- 19 -
[AK4708]
1Vrms
1Vrms
AINL/R+
0.47μ
Volume Gain 0dB
TVOUTL/R
AINL/R0.47μ
(VCROUTL/R)
Volume #0
Figure 7. Volume #0(Volume Gain=0dB:default), Single-ended Input
(0DH: D5-D3)
VOL VOL
VOL2
1
0
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
Note: Volume #1=0dB
Volume #0 Gain
Output Level (Typ)
+12dB
+9dB
+6dB
+3dB
0dB
-3dB
-6dB
Mute
2Vrms (with 0.5Vrms input)
2Vrms (with 1Vrms input)
1Vrms (with 1Vrms input)
0.5Vrms (with 1Vrms input)
-
(default)
Table 6. Volume #0, Single-ended Input
■ Volume Control #1 (Main Volume)
The AK4708 has main volume control (Volume #1) as shown in Table 7.
(02H: D5-D0)
L5
L4
L3
L2
L1
L0
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
…
…
…
…
…
…
0
0
0
0
0
1
0
0
0
0
0
0
Note: The output must not exceed 3Vrms.
Table 7. Volume #1
Gain
+6dB
+4dB
+2dB
0dB
…
-60dB
Mute
(default)
When the MOD bit = “1”(default), changing levels don’t have pop noise. MDT1-0 bits select the transition time (Table 8).
When the new gain value 1EH(-2dB) is written to gain resistor while the actual (stable) gain is 1FH(0dB), the gain
changes to 1EH(-2dB) within the transition time selected by MDT1-0 bits. The AK4708 compares the actual gain to the
value of gain register after finishing the transition time, and re-changes the actual gain to new resister value within the
transition time if the register value is different from the actual gain when compared. When the MOD bit = “0” then there
is no transition time and the gain changes immediately. This change may cause a click noise.
MS0618-E-00
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- 20 -
[AK4708]
WR
[Gain=1EH]
Gain Register
1FH
WR
[Gain=1DH]
WR
[Gain=1CH]
1DH
1EH
compare
Actual Gain
1FH (to 1EH)
1CH
compare
1EH
(to 1DH)
compare
(to 1CH)
1CH
1DH
Transition Time (5.3ms to 42.7ms pop free.)
Figure 8. Volume Change Operation (MOD bit = “1”)
MDT1
0
0
1
1
MDT0
Transition Time
0
5.3ms
1
10.7ms
0
21.3ms
1
42.7ms
Table 8. Volume Transition Time (typ.)
MS0618-E-00
(default)
2007/04
- 21 -
[AK4708]
3. Video Block
■ Video Switch Control
The AK4708 has switches for TV and VCR. Each switch can be controlled via registers independently. When AUTO bit
= “1” or STBY bit = “1”, these switches setting is ignored and set to fixed configuration (loop-through mode). Please refer
the auto startup mode and standby mode.
(04H: D2-D0)
Mode
VTV2-0 bit
Shutdown
Encoder
CVBS+RGB
or Encoder YPbPr
000
Encoder Y/C 1
010
Encoder Y/C 2
011
VCR (default)
100
TV CVBS
101
(Reserved)
(Reserved)
110
111
001
Source of
Source of
TVVOUT pin
TVRC pin
(Hi-Z)
(Hi-Z)
ENCV pin
ENCRC pin
(Encoder CVBS
(Encoder Red,C
or Y)
or Pb)
ENCV pin
ENCRC pin
(Encoder Y)
(Encoder C)
ENCY pin
ENCC pin
(Encoder Y)
(Encoder C)
VCRVIN pin
VCRRC pin
(VCR CVBS
(VCR Red,C
or Y)
or Pb)
TVVIN pin
(Hi-Z)
(TV CVBS)
Table 9. TV video output (Note 23)
Source of
TVG pin
(Hi-Z)
ENCG pin
(Encoder Green
or Y)
Source of
TVB pin
(Hi-Z)
ENCB pin
(Encoder Blue
or Pr)
(Hi-Z)
(Hi-Z)
(Hi-Z)
(Hi-Z)
VCRG pin
(VCR Green
or Y)
VCRB pin
(VCR Blue
or Pr)
(Hi-Z)
(Hi-Z)
-
-
(04H: D5-D3)
Source of
Source of
Source of
VCRVOUT pin
VCRC pin
VCRGO pin
(Hi-Z)
(Hi-Z)
(Hi-Z)
ENCV pin
ENCRC pin
(Encoder CVBS
(Hi-Z)
(Encoder C)
or Y)
ENCY pin
ENCC pin
(Encoder CVBS
(Hi-Z)
(Encoder C)
or Y)
TVVIN pin
(Hi-Z)
(Hi-Z)
(TV CVBS)
VCRVIN pin
VCRRC pin
VCRG pin
(VCR CVBS)
(VCR Red, C)
(VCR Green)
ENCV pin
ENCRC pin
ENCG pin
(Encoder CVBS
(Encoder Red,C
(Encoder Green
or Y)
or Pb)
or Y)
Table 10. VCR video output (Refer Note 23)
Mode
VVCR2-0 bit
Shutdown
000
Encoder CVBS or Y/C 1
001
Encoder CVBS or Y/C 2
010
TV CVBS (default)
011
VCR
100
Encoder CVBS /RGB
101
(Reserved)
(Reserved)
110
111
Source of
VCRBO pin
(Hi-Z)
(Hi-Z)
(Hi-Z)
(Hi-Z)
VCRB pin
(VCR Blue)
ENCB pin
(Encoder Blue
or Pr)
-
Note 23. When input the video signal via ENCRC pin or VCRRC pin, set CLAMP1-0 bits respectively.
MS0618-E-00
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- 22 -
[AK4708]
■ Video Output Control (05H: D6-D0, 0CH:D2-D0)
Each video output can be set to Hi-Z individually via control registers. These settings are ignored when the AUTO bit =
“1”.
TVV: TVVOUT output control
TVR: TVRCOUT output control
TVG: TVGOUT output control
TVB: TVBOUT output control
VCRV: VCRVOUT output control
VCRC: VCRC output control
VCRG: VCRGO output control
VCRB: VCRBO output control
TVFB: TVFB output control
VCRFB: VCRFBO output control
0: Hi-Z. (default)
1: Active.
■ RGB/Chroma Bi-directional Control for VCR SCART (05H: D7, D5)
The AK4708 supports the bi-directional RGB/Chroma signal on the VCR SCART.
(CIO bit &
VCRC bit)
#15 pin
75
VCRC
pin
VCRRC
pin
VCR SCART
0.1u
(AK4708)
Figure 9. VCR Red/Chroma Bi-directional Control
CIO
VCRC
State of VCRC pin
0
0
Hi-z
0
1
1
(default
)
1
Active
0
Connected to GND
1
Connected to GND
Table 11 VCR Red/Chroma Bi-directional Control
MS0618-E-00
2007/04
- 23 -
[AK4708]
(CIO bit &
VCRG bit)
#11 pin
75
VCRGO
pin
VCRG
pin
VCR SCART
0.1u
(AK4708)
Figure 10. VCR Green Bi-directional Control
CIO
0
0
1
1
VCRG
State of VCRGO pin
0
Hi-z
1
Active
0
Connected to GND
1
Connected to GND
Table 12 VCR Green Bi-directional Control
(CIO bit &
VCRB bit)
(default)
#7 pin
75
VCRBO
pin
VCRB
pin
VCR SCART
0.1u
(AK4708)
Figure 11. VCR Blue Bi-directional Control
CIO
0
0
1
1
VCRB
State of VCRC pin
0
Hi-z
1
Active
0
Connected to GND
1
Connected to GND
Table 13 VCR Blue Bi-directional Control
MS0618-E-00
(default)
2007/04
- 24 -
[AK4708]
■ Clamp and DC-restore circuit control (06H: D7-D2)
Each CVBS and Y input has the sync tip clamp circuit. The DC-restore circuit has two clamp voltages 0.7V(typ) and
2.2V(typ) to support both RGB and YPbPr signal. They correspond to 0.35V(typ) and 1.1V(typ) at the SCART connector
when matched by 75Ω resistors. The CLAMP1, CLAMP0 and CLAMPB bits select the input circuit for ENCRC pin
(Encoder Red/Chroma), ENCB pin (Encoder Blue), VCRRC pin (VCR Red/Chroma) and VCRB pin (VCR Blue)
respectively. VCLP2-0 bits select the sync source of DC- restore circuit.
CLAMPB
CLAMP0
0
0
0
1
1
0
1
1
CLAMPB
CLAMP1
0
0
0
1
1
0
1
1
VCRRC Input Circuit
VCRB Input Circuit
DC restore clamp active
DC restore clamp active
(0.7V at sync timing/output pin)
(0.7V at sync timing/output pin)
Biased
(DC restore clamp active)
(2.2V at sync timing/output pin)
(0.7V at sync timing output pin)
DC restore clamp active
DC restore clamp active
(2.2V at sync timing/output pin)
(2.2V at sync timing/output pin)
(reserved)
(reserved)
Table 14. DC-restore control for VCR Input
ENCRC Input Circuit
ENCB Input Circuit
DC restore clamp active
DC restore clamp active
(0.7V at sync timing/output pin)
(0.7V at sync timing/output pin)
Biased
DC restore clamp active
(2.2V at sync timing/output pin)
(0.7V at sync timing output pin)
DC restore clamp active
DC restore clamp active
(2.2V at sync timing/output pin)
(2.2V at sync timing/output pin)
(reserved)
(reserved)
Table 15. DC-restore control for Encoder Input
CLAMP2
0
1
ENCG Input Circuit
DC restore clamp active
(0.7V at sync timing/output pin)
Sync tip clamp active
(0.7V at sync timing/output pin)
note
for RGB
for Y/C
(default)
for Y/Pb/Pr
note
for RGB
(default)
for Y/C
for Y/Pb/Pr
note
for RGB
(default)
for Y/Pb/Pr
Note: When the VTV2-0 bits = “001”(source for TV = Encoder CVBS /RGB), TVG bit = “1” (TVG = active) and
VCLP1-0 bits = “11”(DC restore source = ENCG), the sync tip is selected even if the CLAMP2 bit = “0”.
Table 16. DC-restore control for Encoder Green/Y Input
VCLP2-0: DC restore source control
VCLP2
0
0
0
0
VCLP1
0
0
1
1
VCLP0
0
1
0
1
Sync Source of DC Restore
ENCV
ENCY
VCRVIN
ENCG
(default)
1
0
0
VCRG
1
0
1
(reserved)
1
1
0
(reserved)
1
1
1
(reserved)
Note: When the AUTO bit = “1”, the source is fixed to VCRVIN.
Table 17. DC-restore source control
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[AK4708]
4. Blanking Control
The AK4708 supports Fast Blanking signals and Slow Blanking (Function Switching) signals for TV/VCR SCART.
■ Input/Output Control for Fast/Slow Blanking
FB1-0: TV Fast Blanking output control (07H: D1-D0)
FB1 bit
FB0 bit
TVFB pin Output Level
0
0
0V
(default)
0
1
2V<, 4V(typ) at 150Ω load
1
0
Same as VCR FB input (4V/0V)
1
1
(Reserved)
Table 18. TV Fast Blanking output (Note: minimum load is 150Ω)
SBT1-0: TV Slow Blanking output control (07H: D3-D2)
SBT1 bit
SBT0 bit
TVSB pin Output Level
0
0
< 2V
(default)
0
1
5V <, < 7V
1
0
(Reserved)
1
1
10V <
Table 19. TV Slow Blanking output (Note: minimum load is 10kΩ)
FBV: VCR Fast Blanking output control (0CH: D7)
FBV bit
VCRFBO pin Output Level
0
0V
(default)
1
2V<, 4V(typ) at 150Ω load
Table 20. VCR Fast Blanking output (Note: minimum load is 150Ω)
SBV1-0: VCR Slow Blanking output control (07H: D5-D4)
SBV1 bit SBV0 bit
VCRSB pin Output Level
0
0
< 2V
(default)
0
1
5V <, < 7V
1
0
(Reserved)
1
1
10V <
Table 21. VCR Slow Blanking output (Note: minimum load is 10kΩ)
SBIO1-0: TV/VCR Slow Blanking I/O control (07H: D7-D6)
SBIO1 bit
SBIO0 bit
0
0
0
1
1
0
1
1
VCRSB pin Direction
TVSB pin Direction
Output
Output
(Controlled by SBV1-0 bits)
(Controlled by SBT1-0 bits)
(Reserved)
(Reserved)
Input
Output
(Stored in SVCR1-0 bits)
(Controlled by SBT1-0 bits)
Input
Output
(Stored in SVCR1-0 bits)
(Same output as VCR SB)
Table 22. TV/VCR Slow Blanking I/O control
MS0618-E-00
(default)
2007/04
- 26 -
[AK4708]
■ VCR Fast Blanking for VCR SCART (0CH: D7, D2)
The AK4708 supports the bi-directional VCR Fast Blanking signal on the VCR SCART.
#16 pin
(VCRFB bit)
6dB
2V
75
0V
VCRFBO
pin
(FBV bit)
VCRFB
pin
VCR SCART
(AK4708)
Figure 12. VCR Fast Blanking Bi-directional Control
FBV
0
0
1
1
VCRFB
0
1
0
1
State of VCRFBO pin
(default)
Hi-Z
Active / 0V(typ)
Hi-Z
Active / 2V<, 4V(typ) at 150Ω load
Table 23 VCR Fast Blanking Bi-directional Control
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2007/04
- 27 -
[AK4708]
5. Monitor Options and INT function
■ Monitor Options (08H: D4-D0)
The AK4708 has several detection functions. SVCR1-0 bits, FVCR bit, VCMON bit and TVMON bit reflect the input
DC level of VCR slow blanking, the input DC level of VCR fast blanking and signals input to TVVIN or VCRVIN pins.
SVCR1-0: VCR Slow blanking status monitor
SVCR1-0 bits reflect the voltage at VCRSB pin only when the VCRSB is in the input mode.
When the VCRSB is in the output mode, SVCR1-0 bits hold previous value.
VCRSB pin input level
SVCR1 bit
SVCR0 bit
< 2V
0
0
4.5 to 7V
0
1
(Reserved)
1
0
9.5 <
1
1
Table 24. VCR Slow Blanking monitor
FVCR: VCR Fast blanking input level monitor
This bit is enabled when TVFB bit = “1”.
VCRFB pin input level
FVCR bit
< 0.4V
0
1V <
1
Table 25. VCR Fast Blanking monitor (Typical threshold is 0.7V)
VCMON: VCRVIN pin video input monitor (MCOMN bit = “1”),
TVVIN pin or VCRVIN pin video input monitor (MCOMN bit = “0”)
0: No video signal detected.
1: Detects video signal.
TVMON: TVVIN pin video input monitor (active when MCOMN bit = “1”)
0: No video signal detected.
1: Detects video signal.
AUTO
(00H D3)
0
0
0
0
MCOMN
(09H D7)
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
TVMON
(08H D4)
0
0
0
0
VCMON
(08H D3)
0
1
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
0
0
0
1
1
1
TVVIN signal
VCRVIN signal
0
0
1
1
1
1
1
1
x
x
x
x
x:don’t care
Note 24. TVVIN/VCRVIN signal: signal 0 = No signal applied, signal 1 = signal applied
Table 26. TV/VCR Monitor Function
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2007/04
- 28 -
[AK4708]
■ INT Function and Mask Options (09H: D3-D1)
Changes of the 08H status can be monitored via the INT pin. The INT pin is the open drain output and goes “L” for 2μs
(typ.) when the status of 08H is changed. This pin should be connected to VD (typ. 5V) through 10kΩ resistor or lower
voltage through 10kΩ resistor. MTV bit, MVC bit, MCOMN bit, MFVCR bit and MSVCR bit control the reflection of the
status change of these monitors onto the INT pin from report to prevent to masks each monitor.
AK4708
5V
R=10kΩ
INT
uP
Figure 13. INT pin
MVC: VCMON Mask. Refer Table 28.
MTV: TVMON Mask. Refer Table 27.
MCOMN: Refer Table 26
AUTO
(00H D3)
0
0
0
0
TVMON
MTV
INT
(08H D4)
(09H D4)
No Change
0
Hi-Z
No Change
1
Hi-Z
Change
0
Generates “L” Pulse
Change
1
Hi-Z
No Change
0
Hi-Z
1
1
No Change
1
Hi-Z
Note 25. When the STBY bit = “0”, the TV Monitor Mask function is enabled.
Note 26. When AUTO bit = “1”, TVMON does not change
Table 27. TV Monitor Mask
AUTO
(00H D3)
0
0
0
0
VCMON
(08H D3)
No Change
No Change
Change
Change
MVC
(09H D3)
0
1
0
1
INT
Hi-Z
Hi-Z
Generates “L” Pulse
Hi-Z
1
No Change
0
Hi-Z
1
No Change
1
Hi-Z
1
Change
0
Generates “L” Pulse
1
Change
1
Generates “L” Pulse
Note 27. When the STBY bit = “0”, the VCR Monitor Mask function is enabled.
Table 28. VCR Monitor Mask
MFVCR: FVCR Monitor mask.
0: Change of FVCR is reflected to INT pin. (default)
1: Change of FVCR is NOT reflected to INT pin.
MSVCR: SVCR1-0 Monitor mask
0: Change of SVCR1-0 is reflected to INT pin. (default)
1: Change of SVCR1-0 is NOT reflected to INT pin.
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2007/04
- 29 -
[AK4708]
6. Control Interface
I2C-bus Control Mode
1. WRITE Operations
Figure 14 shows the data transfer sequence in I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 20). After the
START condition, a slave address is sent. This address is 7bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant seven bits of the slave address are fixed as “0010001”. If the slave address match that of the
AK4708, the AK4708 generates the acknowledge and the operation is executed. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 22). A
“1” for R/W bit indicates that the read operation is to be executed. A “0” indicates that the write operation is to be
executed. The second byte consists of the address for control registers of the AK4708. The format is MSB first, and those
most significant 3-bits are fixed to zeros (Figure 16). The data after the second byte contain control data. The format is
MSB first, 8bits (Figure 17). The AK4708 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 20).
The AK4708 can execute multiple one byte write operations in a sequence. After receipt of the third byte, the AK4708
generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal address
counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 0DH prior
to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 22) except for the START and the STOP
condition.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
Data(n)
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 14. Data transfer sequence at the I2C-bus mode
0
0
1
0
0
0
1
R/W
A2
A1
A0
D2
D1
D0
Figure 15. The first byte
0
0
0
A4
A3
Figure 16. The second byte
D7
D6
D5
D4
D3
Figure 17. Byte structure after the second byte
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[AK4708]
2. READ Operations
Set R/W bit = “1” for READ operations. After transmission of data, the master can read the next address’s data by
generating an acknowledge instead of terminating the write cycle after the receipt the first data word. After the receipt of
each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If
the address exceeds 09H prior to generating the stop condition, the address counter will “roll over” to 00H and the
previous data will be overwritten.
The AK4708 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
2-1. CURRENT ADDRESS READ
The AK4708 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4708 generates an
acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address
counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4708
discontinues transmission.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
Data(n+2)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 18. CURRENT ADDRESS READ
2-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start condition,
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledge, the master
immediately reissues the start condition and the slave address with the R/W bit set to “1”. Then the AK4708 generates an
acknowledge, 1-byte data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but generate the stop condition, the AK4708 discontinues transmission.
S
T
A
R
T
SDA
S
S
T
A
R
T
R/W= “0”
Sub
Address(n)
Slave
Address
A
C
K
S
A
C
K
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 19. RANDOM ADDRESS READ
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[AK4708]
SDA
SCL
S
P
start condition
stop condition
Figure 20. START and STOP conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 21. Acknowledge on the I2C-bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 22. Bit transfer on the I2C-bus
MS0618-E-00
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[AK4708]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
Register Name
Control
Switch
Main Volume
Zerocross
Video switch
Video output enable
Video volume/clamp
S/F Blanking control
S/F Blanking monitor
Monitor mask
DC restore
Reserve
VCR output
Volume
D7
0
VMUTE
0
0
0
CIO
CLAMPB
SBIO1
0
MCOMN
0
0
FVB
0
D6
0
0
0
VMONO
0
TVFB
VCLP1
SBIO0
0
0
0
0
0
0
D5
0
VCR1
L5
1
VVCR2
VCRC
VCLP0
SBV1
FVCR1
0
0
0
0
VOL2
D4
0
VCR0
L4
0
VVCR1
VCRV
CLAMP2
SBV0
TVMON
MTV
0
0
0
VOL1
D3
AUTO
MONO
L3
0
VVCR0
TVB
CLAMP1
SBT1
VCMON
MVC
VCLP2
0
0
VOL0
D2
0
1
L2
MOD
VTV2
TVG
CLAMP0
SBT0
FVCR0
MFVCR
0
0
VCRFB
1
D1
BIAS
TV1
L1
MDT1
VTV1
TVR
0
FB1
SVCR1
MSVCR
1
0
VCRB
1
D0
STBY
TV0
L0
MDT0
VTV0
TVV
0
FB0
SVCR0
0
1
0
VCRG
1
When the PDN pin goes “L”, the registers are initialized to their default values.
While the PDN pin = “H”, all registers can be accessed.
Do not write any data to the register over 0DH.
■ Register Definitions
Addr
00H
Register Name
Control
R/W
Default
D7
0
D6
0
D5
0
D4
0
0
0
0
0
D3
AUTO
D2
0
D1
BIAS
D0
STBY
1
0
1
1
R/W
STBY: Standby control
0: Normal Operation
1: Standby Mode (default). All registers are not initialized.
AMP: Powered down and timings are reset.
Source of TVOUT: fixed to VCRIN.
Source of VCROUT: fixed to TVIN.
Source of MONOOUT: fixed to VCRIN.
Source of TVVOUT: fixed to VCRVIN (or Hi-Z).
Source of TVRC: fixed to VCRRC (or Hi-Z).
Source of TVG: fixed to VCRG (or Hi-Z).
Source of TVB: fixed to VCRB (or Hi-Z).
Source of VCRVOUT: fixed to TVVIN (or Hi-Z).
Source of VCRC: fixed to Hi-Z.
Source of VCRGO: fixed to Hi-Z.
Source of VCRBO: fixed to Hi-Z.
BIAS: Audio output control
0: Normal operation
1: ALL Audio outputs to GND (default)
AUTO: Auto startup bit
0: Auto startup disable (Manual startup).
1: Auto startup enable (default).
Note: When the SBIO1 bit = “1”(default = “0”), the change of AUTO bit may cause a “L” pulse on INT pin.
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[AK4708]
Addr
01H
Register Name
Switch
R/W
Default
D7
VMUTE
D6
0
D5
VCR1
D4
VCR0
1
0
0
1
D3
MONO
R/W
0
D2
1
D1
TV1
D0
TV0
1
0
1
TV1-0: TVOUTL/R pins source switch
00: AMP
01: VCRINL/R pins (default)
10: MUTE
11: Reserved
MONO: Mono select for TVOUTL/R pins
0: Stereo. (default)
1: Mono. (L+R)/2
VCR1-0: VCROUTL/R pins source switch
00: AMP
01: TVINL/R pins (default)
10: MUTE
11: Volume#1 output
VMUTE: Mute switch for volume #1
0: Normal operation
1: Mute the volume #1 (default)
Addr
Register Name
02H
Main volume
D7
D6
D5
D4
D3
D2
D1
D0
0
0
L5
L4
L3
L2
L1
L0
1
1
1
1
R/W
Default
R/W
0
0
0
1
L5-0: Volume #1 control
Those registers control both Lch and Rch of Volume #1.
111111 to
100011: (Reserved)
100010: Volume gain = +6dB
100001: Volume gain = +4dB
100000: Volume gain = +2dB
011111: Volume gain = +0dB (default)
011110: Volume gain = -2dB
...
000011: Volume gain = -56dB
000010: Volume gain = -58dB
000001: Volume gain = -60dB
000000: Volume gain = Mute
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[AK4708]
Addr
03H
Register Name
Volume Control
R/W
Default
D7
0
VMONO
D6
D5
1
D4
0
0
0
1
0
D3
0
D2
MOD
D1
MDT1
D0
MDT0
0
1
1
1
R/W
MDT1-0: The time length control of volume transition time
00: typ. 5.3 ms
01: typ. 10.7 ms
10: typ. 21.3 ms
11: typ. 42.7 ms (default)
MOD: Soft transition enable for volume #1 control
0: Disable
The volume value changes immediately without soft transition.
1: Enable (default)
The volume value changes with soft transition.
This function is disabled when STBY bit = “1”.
VMONO: Mono select for VCROUTL/R pins
0: Stereo. (default)
1: Mono. (L+R)/2
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[AK4708]
Addr
04H
Register Name
Video switch
R/W
Default
D7
0
D6
0
D5
VVCR2
0
0
0
D4
D3
VVCR1 VVCR0
R/W
1
1
D2
VTV2
D1
VTV1
D0
VTV0
1
0
0
D4
D3
VCRV
TVB
R/W
0
0
D2
TVG
D1
TVR
D0
TVV
0
0
0
VTV2-0: Selector for TV video output
Refer Table 9.
VVCR2-0: Selector for VCR video output
Refer Table 10.
Addr
05H
Register Name
Output Enable
R/W
Default
D7
CIO
D6
TVFB
D5
VCRC
0
0
0
TVV: TVVOUT output control
TVR: TVRCOUT output control
TVG: TVGOUT output control
TVB: TVBOUT output control
VCRV: VCRVOUT output control
VCRC: VCRC output control
TVFB: TVFB output control
0: Hi-Z (default)
1: Active.
CIO: VCR RGB I/O control for VCR SCART
Refer Table 11, Table 12 and Table 13.
MS0618-E-00
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- 36 -
[AK4708]
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
06H
Video volume
CLAMPB
VCLP1
VCLP0
CLAMP2
CLAMP1
CLAMP0
0
0
0
1
0
0
D2
SBT0
D1
FB1
D0
FB0
0
0
0
R/W
Default
R/W
0
0
0
0
CLAMPB, CLAMP2-0: Clamp control.
Refer Table 14, Table 15 and Table 16.
VCLP1-0: DC restore source control
00: ENCV pin (default)
01: ENCY pin
10: VCRVIN pin
11: (Reserved)
When the AUTO bit = “1”, the source is fixed to VCRVIN pin.
Addr
07H
Register Name
S/F Blanking
R/W
Default
D7
SBIO1
D6
SBIO0
D5
SBV1
0
0
0
D4
D3
SBV0
SBT1
R/W
0
0
FB1-0: TV Fast Blanking output control (for TVFB pin)
00: 0V (default)
01: 2V<, 4V(typ) at 150Ω load
10: follow VCR FB input (4V/0V)
11: (Reserved)
SBT1-0: TV Slow Blanking output control (for TVSB pin. minimum load is 10kΩ.)
00: < 2V (default)
01: 5V <, < 7V
10: (Reserved)
11: 10V <
SBV1-0: VCR Slow Blanking output control (for VCRSB pin. minimum load is 10kΩ.)
00: < 2V (default)
01: 5V <, < 7V
10: (Reserved)
11: 10V <
SBIO1-0: TV/VCR Slow Blanking I/O control
Refer Table 22.
Addr
08H
Register Name
Monitor
R/W
Default
D7
D6
D5
D4
0
0
FVCR1
TVMON
D3
D2
D1
D0
VCMON
FVCR0
SVCR1
SVCR0
0
0
0
READ
0
0
0
0
0
SVCR1-0, FVCR1-0: VCR fast blanking/slow blanking monitor
Refer Table 24, Table 25.
VCMON, TVMON: VCR/TV video input monitor
Refer Table 26.
MS0618-E-00
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[AK4708]
Addr
09H
Register Name
Monitor mask
R/W
Default
D7
MCOMN
D6
0
D5
0
D4
MTV
0
0
0
0
D3
MVC
R/W
1
D2
MFVCR
D1
MSVCR
D0
0
0
0
0
MSVCR: SVCR1-0 bits Monitor mask
0: The INT pin reflects the change of SVCR1-0 bit. (default)
1: The INT pin does not reflect the change of SVCR1-0 bits.
MFVCR: FVCR Monitor mask
0: The INT pin reflects the change of MFVCR bit. (default)
1: The INT pin does not reflect the change of MFVCR bit.
MVC: VCR input monitor mask
Refer Table 28.
MTV: TV input monitor mask
Refer Table 27.
MCOMN: Monitor mask option
Refer Table 26.
Addr
Register Name
0AH
DC restore
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
VCLP2
0
1
1
0
1
1
R/W
0
0
0
0
0
VCLP2: DC restore source control
Refer Table 17
Addr
0CH
Register Name
VCR output
R/W
Default
D7
FBV
D6
0
D5
0
D4
0
0
0
0
0
D3
0
R/W
0
D2
VCRFB
D1
VCRB
D0
VCRG
0
0
0
VCRG: VCRGO output control
VCRB: VCRBO output control
VCRFB: VCRFBO output control
0: Hi-Z (default)
1: Active.
FBV: VCR Fast Blanking output control (for VCRFBO pin)
0: 0V (default)
0: 2V<, 4V(typ) at 150Ω load
MS0618-E-00
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[AK4708]
Addr
Register Name
0DH
Main volume
D7
D6
D5
D4
D3
D2
D1
D0
0
0
VOL2
VOL1
VOL0
1
1
1
1
1
1
1
R/W
Default
R/W
0
0
0
1
VOL2-0: Volume #0 control
Those registers control both Lch and Rch of Volume #0.
111: Volume gain = +12dB
110: Volume gain = +9dB
101: Volume gain = +6dB
100: Volume gain = +3dB
011: Volume gain = +0dB (default)
010: Volume gain = -3dB
001: Volume gain = -6dB
000: MUTE
MS0618-E-00
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[AK4708]
SYSTEM DESIGN
TVINL
27
11 ENCRC
TVINR
26
0.1u
0.1u
75
75
23 TVSB
24 VCRINR
300
0.1u
VCRINL 25
400
0.47u
0.1u
75
400
12 ENCC
22 VCRSB
10 ENCG
0.1u
0.1u
+ 10u
+ 10u
+ 10u
+ 10u
300
300
300
+ 10u
+
Audio 5V
0.1u
300
220k
220k
220k
220k
0.47u
0.47u
0.47u
10u
+
Analog
12V
300
300
300
TV SCART
VCROUTR 28
10u
0.1u + 10u
VCR SCART
0.47u
0.47u
AINR- 37
AINR+ 38
0.47u
0.47u
SCL 41
AINL+ 40
SDA 42
AINL- 39
75
PDN 43
9 ENCB
21 INT
0.1u
VCROUTL 29
20 VCRB
0.1u
75
8 VVD1
19 VCRG
75
TVOUTR 30
0.1u
0.1u
7 TVB
0.1u
75
TVOUTL 31
16 VCRVIN
0.1u
VP 32
6 TVG
13 ENCV
75
VCRBO 44
75
75
75
AK4708EQ
75
Micro
DACL DACR
encoder
controller
Video 5V
MPEG
decoder
DVCOM 33
15 TVVIN
75
VIDEO
4 VVD2
5 TVRC
75
Digital
Ground
PVCOM 34
18 VCRRC
75
36
3 TVVOUT
17 VCRFB
+
VD
VSS 35
0.1u
+
14 ENCY
75
2 VVSS
VCRGO 45
1 VCRC
10u 0.1u 10u 0.1u
VCRFBO 46
75
VCRVOUT 47
TVFB 48
75
Figure 23 shows the system connection diagram example. The evaluation board AKD4708 demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
Analog Ground
Figure 23. Typical Connection Diagram
MS0618-E-00
2007/04
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[AK4708]
■ Grounding and Power Supply Decoupling
VD, VP, VVD1, VVD2, VSS and VVSS should be supplied from analog supply unit with low impedance and be
separated from system digital supply. An electrolytic capacitor 10μF parallel with a 0.1μF ceramic capacitor should be
attached to these pins to eliminate the effects of high frequency noise. The 0.1μF ceramic capacitor should be placed as
near to VD (VP, VVD1, VVD2) as possible.
■ Voltage Reference
Each DVCOM/PVCOM are common voltage of this chip. An electrolytic capacitor 10μF parallel with a 0.1μF ceramic
capacitor should be attached to these VCOM pins to eliminate the effects of high frequency noise. No load current should
be drawn from these VCOM pins. All signals, especially clocks, should be kept away from these VCOM pins in order to
avoid unwanted coupling into the AK4708.
■ Analog Audio Outputs
The analog outputs are also single-ended and centered on 5.6V(typ.). The output signal range is typically 2Vrms .
MS0618-E-00
2007/04
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[AK4708]
■ External Circuit Example
Analog Audio Input pin
300Ω
TVINL/R
VCRINL/R
(Cable)
0.47μF
Analog Audio Input pin
AINR+
AINRAINL+
AINL-
0.47μF
Analog Audio Output pin
TVOUTL/R
VCROUTL/R
300Ω
10μF
(Cable)
Total > 4.5kΩ
Analog Video Input pin
75Ω
(Cable)
ENCV, ENCY, VCRVIN,
TVVIN, ENCRC, ENCC,
VCRRC, ENCG, VCRG,
ENCB, VCRB
0.1μF
75Ω
Analog Video Output pin
TVVOUT, TVRC
TVG, TVR, TVB,
VCRVOUT,VCRC,
VCRBO,VCRGO
75Ω
(Cable)
max
400pF
max
15pF
MS0618-E-00
75Ω
2007/04
- 42 -
[AK4708]
Slow Blanking pin
TVSB
VCRSB
(Cable)
400Ω
(max 500Ω)
max 3nF
(with 400Ω)
min: 10kΩ
Fast Blanking Input pin
VCRFB
75Ω
(Cable)
75Ω
Fast Blanking Output pin
75Ω
TVFB,
VCRFBO
(Cable)
75Ω
MS0618-E-00
2007/04
- 43 -
[AK4708]
PACKAGE
48pin LQFP(Unit:mm)
1.70Max
9.0 ± 0.2
0.13 ± 0.13
7.0
36
1.40 ± 0.05
24
48
13
7.0
37
1
9.0 ± 0.2
25
12
0.145 ± 0.05
0.5
0.22 ± 0.08
0.10 M
0° ∼ 10°
0.5 ± 0.2
0.10
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0618-E-00
2007/04
- 44 -
[AK4708]
MARKING
AK4708EQ
XXXXXXX
1
XXXXXXXX: Date code identifier
REVISION HISTORY
Date (YY/MM/DD)
07/04/25
Revision
00
Reason
First Edition
Page
MS0618-E-00
Contents
2007/04
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[AK4708]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
MS0618-E-00
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