A4983 DMOS Microstepping Driver with Translator Features and Benefits Description ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ The A4983 is a complete microstepping motor driver with built-in translator for easy operation. It is designed to operate bipolar stepper motors in full-, half-, quarter-, eighth, and sixteenth-step modes, with an output drive capacity of up to 35 V and ±2 A. The A4983 includes a fixed off-time current regulator which has the ability to operate in Slow or Mixed decay modes. Low RDS(ON) outputs Automatic current decay mode detection/selection Mixed and Slow current decay modes Synchronous rectification for low power dissipation Internal UVLO Crossover-current protection 3.3 and 5 V compatible logic supply Very thin profile QFN package Thermal shutdown circuitry The translator is the key to the easy implementation of the A4983. Simply inputting one pulse on the STEP input drives the motor one microstep. There are no phase sequence tables, high frequency control lines, or complex interfaces to program. The A4983 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. The chopping control in the A4983 automatically selects the current decay mode (Slow or Mixed). When a signal occurs at the STEP input pin, the A4983 determines if that step results in a higher or lower current in each of the motor phases. If the change is to a higher current, then the decay mode is set to Slow decay. If the change is to a lower current, then the current decay is set to Mixed (set initially to a fast decay for a period amounting to 31.25% of the fixed off-time, then to a Package: 28-pin QFN (suffix ET) Continued on the next page… Approximate size Typical Application Diagram VDD 0.22 μF 0.1 μF VREG VCP CP1 VDD Microcontroller or Controller Logic VBB VBB OUT1A MS1 OUT1B MS2 MS3 CP2 0.1 μF A4983 RS1 SLEEP STEP OUT2A DIR OUT2B RESET RS2 ENABLE REF 4983DS ROSC VBB A4983 DMOS Microstepping Driver with Translator Description (continued) slow decay for the remainder of the off-time). This current decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, undervoltage lockout (UVLO), and crossover-current protection. Special poweron sequencing is not required. The A4983 is supplied in a 5 mm × 5 mm × 0.90 nominal surface mount QFN package with exposed thermal pad (suffix ET). The package is lead (Pb) free (suffix –T), with 100% matte tin plated leadframe. Selection Guide Part Number Pb-free Package Packing A4983SET-T Yes 28-pin QFN with exposed thermal pad 73 pieces per tube A4983SETTR-T Yes 28-pin QFN with exposed thermal pad 1500 pieces per 7-in. reel Absolute Maximum Ratings Characteristic Symbol Load Supply Voltage VBB Output Current IOUT Logic Input Voltage Sense Voltage Reference Voltage Operating Ambient Temperature Maximum Junction Storage Temperature Notes Duty Cycle < 20% Rating Units 35 V ±2 A ±2.5 A VIN –0.3 to 7 V VSENSE 0.5 V 4 V –20 to 85 ºC TJ(max) 150 ºC Tstg –55 to 150 ºC VREF TA Range S Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A4983 DMOS Microstepping Driver with Translator Functional Block Diagram 0.1 MF 0.22 MF VREG VDD Current Regulator ROSC CP1 CP2 Charge Pump OSC VCP 0.1 MF DMOS Full Bridge REF DAC VBB1 OUT1A OUT1B PWM Latch Blanking Mixed Decay STEP Gate Drive DIR RESET MS1 SENSE1 Translator Control Logic MS2 DMOS Full Bridge VBB2 RS1 OUT2A OUT2B MS3 PWM Latch Blanking Mixed Decay ENABLE SLEEP DAC SENSE2 RS2 VREF Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A4983 DMOS Microstepping Driver with Translator ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted) Characteristics Output Drivers Min. Typ.2 Max. Units 8 0 3.0 – – – – – – – – – – – – – 0.350 0.300 – – – – – – – – 35 35 5.5 0.450 0.370 1.2 1.2 4 2 10 8 5 10 V V V Ω Ω V V mA mA μA mA mA μA VIN(1) VDD×0.7 – – V VIN(0) – – V μA Symbol Load Supply Voltage Range VBB Logic Supply Voltage Range VDD Output On Resistance RDSON Body Diode Forward Voltage VF Motor Supply Current IBB Logic Supply Current IDD Test Conditions Operating During Sleep Mode Operating Source Driver, IOUT = –1.5 A Sink Driver, IOUT = 1.5 A Source Diode, IF = –1.5 A Sink Diode, IF = 1.5 A fPWM < 50 kHz Operating, outputs disabled Sleep Mode fPWM < 50 kHz Outputs off Sleep Mode Control Logic Logic Input Voltage Logic Input Current Microstep Select 2 Microstep Select 3 Input Hysteresis Blank Time IIN(1) IIN(0) VIN = VDD×0.7 VIN = VDD×0.3 RMS2 RMS3 VHYS(IN) tBLANK Fixed Off-Time tOFF Reference Input Voltage Range Reference Input Current VREF IREF Current Trip-Level Error3 errI Crossover Dead Time Protection Thermal Shutdown Temperature Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis tDT OSC > 3 V ROSC = 25 kΩ VREF = 2 V, %ITripMAX = 38.27% VREF = 2 V, %ITripMAX = 70.71% VREF = 2 V, %ITripMAX = 100.00% TJ TJHYS UVLO UVHYS VDD rising –20 <1.0 VDD×0.3 20 –20 <1.0 20 μA – – 150 0.7 20 23 0 –3 – – – 100 100 100 300 1 30 30 – 0 – – – 475 – – 500 1.3 40 37 4 3 ±15 ±5 ±5 800 kΩ kΩ mV μs μs μs V μA % % % ns – – 2.35 0.05 165 15 2.7 0.10 – – 3 – °C °C V V 1Negative current is defined as coming out of (sourcing from) the specified device pin. 2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. I = (ITrip – IProg ) ⁄ IProg , where IProg = %ITripMAX ITripMAX. 3err × Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 A4983 DMOS Microstepping Driver with Translator THERMAL CHARACTERISTICS may require derating at maximum conditions Characteristic Symbol Package Thermal Resistance RθJA Test Conditions* Value Units Package ET; 4-layer PCB, based on JEDEC standard 32 ºC/W *In still air. Additional thermal information available on Allegro Web site. Maximum Power Dissipation, PD(max) 5.5 5.0 4.5 Power Dissipation, PD (W) 4.0 3.5 3.0 (R θJ 2.5 A = 2.0 32 ºC /W ) 1.5 1.0 0.5 0.0 20 40 60 80 100 120 Temperature (°C) 140 160 180 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 5 A4983 DMOS Microstepping Driver with Translator tA tB STEP tC tD MS1, MS2, MS3, RESET, or DIR Time Duration Symbol Typ. Unit STEP minimum, HIGH pulse width tA 1 μs STEP minimum, LOW pulse width tB 1 μs Setup time, input change to STEP tC 200 ns Hold time, input change to STEP tD 200 ns Figure 1. Logic Interface Timing Diagram Table 1. Microstep Resolution Truth Table MS1 MS2 MS3 Microstep Resolution Excitation Mode L L L Full Step 2 Phase H L L Half Step 1-2 Phase L H L Quarter Step W1-2 Phase H H L Eighth Step 2W1-2 Phase H H H Sixteenth Step 4W1-2 Phase Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 6 A4983 DMOS Microstepping Driver with Translator Functional Description Device Operation. The A4983 is a complete microstepping Step Input (STEP). A low-to-high transition on the STEP motor driver with a built-in translator for easy operation with minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and sixteenth-step modes. The currents in each of the two output full-bridges and all of the N-channel DMOS FETs are regulated with fixed off-time PWM (pulse width modulated) control circuitry. At each step, the current for each full-bridge is set by the value of its external current-sense resistor (RS1 and RS2), a reference voltage (VREF), and the output voltage of its DAC (which in turn is controlled by the output of the translator). At power-on or reset, the translator sets the DACs and the phase current polarity to the initial Home state (shown in figures 2 through 6), and the current regulator to Mixed Decay Mode for both phases. When a step command signal occurs on the STEP input, the translator automatically sequences the DACs to the next level and current polarity. (See table 2 for the current-level sequence.) The microstep resolution is set by the combined effect of inputs MS1, MS2, and MS3, as shown in table 1. When stepping, if the new output levels of the DACs are lower than their previous output levels, then the decay mode for the active full-bridge is set to Mixed. If the new output levels of the DACs are higher than or equal to their previous levels, then the decay mode for the active full-bridge is set to Slow. This automatic current decay selection improves microstepping performance by reducing the distortion of the current waveform that results from the back EMF of the motor. input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the combined state of inputs MS1, MS2, and MS3. Microstep Select (MS1, MS2, and MS3). Selects the microstepping format, as shown in table 1. MS2 and MS3 have a 100 kΩ pull-down resistance. Any changes made to these inputs do not take effect until the next STEP rising edge. If the MSx pins are pulled up to VDD, it is good practice to use a high value pull-up resistor in order to limit current to these pins, should an overvoltage event occur. Direction Input (DIR). This determines the direction of rotation of the motor. When low, the direction will be clockwise and when high, counterclockwise. Changes to this input do not take effect until the next STEP rising edge. Internal PWM Current Control. Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to a desired value, ITRIP . Initially, a diagonal pair of source and sink FET outputs are enabled and current flows through the motor winding and the current sense resistor, RSx. When the voltage across RSx equals the DAC output voltage, the current sense comparator resets the PWM latch. The latch then turns off either the source FETs (when in Slow Decay Mode) or the sink and source FETs (when in Mixed Decay Mode). The maximum value of current limiting is set by the selection of RSx and the voltage at the VREF pin. The transconductance function is approximated by the maximum value of current limiting, ITripMAX (A), which is set by If the logic circuits are pulled up to VDD, it is good practice to use a high value pull-up resistor in order to limit current to the logic inputs, should an overvoltage event occur. Logic inputs include: MSx, SLEEP, DIR, ENABLE, RESET, and STEP. where RS is the resistance of the sense resistor (Ω) and VREF is the input voltage on the REF pin (V). RESET Input (RESET). The RESET input sets the trans- The DAC output reduces the VREF output to the current sense comparator in precise steps, such that lator to a predefined Home state (shown in figures 2 through 6), and turns off all of the FET outputs. All STEP inputs are ignored until the RESET input is set to high. ITripMAX = VREF / ( 8 Itrip = (%ITripMAX / 100) × RS) × ITripMAX (See table 2 for %ITripMAX at each step.) Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 7 A4983 DMOS Microstepping Driver with Translator It is critical that the maximum rating (0.5 V) on the SENSE1 and SENSE2 pins is not exceeded. Fixed Off-Time. The internal PWM current control circuitry uses a one-shot circuit to control the duration of time that the DMOS FETs remain off. The one shot off-time, tOFF, is determined by the selection of an external resistor connected from the ROSC timing pin to ground. If the ROSC pin is tied to an external voltage > 3 V, then tOFF defaults to 30 μs. The ROSC pin can be safely connected to the VDD pin for this purpose. The value of tOFF (μs) is approximately tOFF ≈ ROSC ⁄ 825 Blanking. This function blanks the output of the current sense comparators when the outputs are switched by the internal current control circuitry. The comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and switching transients related to the capacitance of the load. The blank time, tBLANK (μs), is approximately Shutdown. In the event of a fault, overtemperature (excess TJ) or an undervoltage (on VCP), the FET outputs of the A4983 are disabled until the fault condition is removed. At power-on, the UVLO (undervoltage lockout) circuit disables the FET outputs and resets the translator to the Home state. Sleep Mode (SLEEP). To minimize power consumption when the motor is not in use, this input disables much of the internal circuitry including the output FETs, current regulator, and charge pump. A logic low on the SLEEP pin puts the A4983 into Sleep mode. A logic high allows normal operation, as well as start-up (at which time the A4983 drives the motor to the Home microstep position). When emerging from Sleep mode, in order to allow the charge pump to stabilize, provide a delay of 1 ms before issuing a Step command. If the SLEEP pin is pulled up to VDD, it is good practice to use a high value pull-up resistor in order to limit current to the pin, should an overvoltage event occur. tBLANK ≈ 1 μs Charge Pump (CP1 and CP2). The charge pump is used to generate a gate supply greater than that of VBB for driving the source-side FET gates. A 0.1 μF ceramic capacitor, should be connected between CP1 and CP2. In addition, a 0.1 μF ceramic capacitor is required between VCP and VBB, to act as a reservoir for operating the high-side FET gates. Mixed Decay Operation. The bridge can operate in Mixed Decay mode, depending on the step sequence, as shown in figures 3 through 6. As the trip point is reached, the A4983 initially goes into a fast decay mode for 31.25% of the off-time. tOFF. After that, it switches to Slow Decay mode for the remainder of tOFF. A timing dagram for this feature appears on the next page. Synchronous Rectification. When a PWM-off cycle is triggered by an internal fixed–off-time cycle, load current recirculates according to the decay mode selected by the control logic. This synchronous rectification feature turns on the appropriate FETs during current decay, and effectively shorts out the body diodes with the low FET RDS(ON). This reduces power dissipation Enable Input (ENABLE). This input turns on or off all of the significantly, and can eliminate the need for external Schottky FET outputs. When set to a logic high, the outputs are disabled. When set to a logic low, the internal control enables the outputs as diodes in many applications. Synchronous rectification turns off when the load current approaches zero (0 A), preventing reversal required. The translator inputs STEP, DIR, MS1, MS2, and MS3, as well as the internal sequencing logic, all remain active, indepen- of the load current. A timing dagram for this feature appears on dent of the ENABLE input state. the next page. VREG (VREG). This internally-generated voltage is used to operate the sink-side FET outputs. The VREG pin must be decoupled with a 0.22 μF ceramic capacitor to ground. VREG is internally monitored. In the case of a fault condition, the FET outputs of the A4983 are disabled. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 8 A4983 DMOS Microstepping Driver with Translator Current Decay Modes Timing Chart VPHASE + IOUT See Enlargement A 0 – Enlargement A toff IPEAK tFD tSD Slow Decay Mixed Decay IOUT Fa st De ca y t Symbol toff IPEAK Characteristic Device fixed off-time Maximum output current tSD Slow decay interval tFD Fast decay interval IOUT Device output current Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 9 A4983 DMOS Microstepping Driver with Translator Application Layout Solder A4983 Trace (2 oz.) Signal (1 oz.) Ground (1 oz.) PCB Thermal (2 oz.) Thermal Vias RS1 RS2 GND VBB1 NC SENSE1 NC DIR PAD CP1 GND STEP NC VDD C6 SLEEP VCP ROSC REF RESET CP2 MS2 C4 OUT1A A4983 ENABLE C3 VBB C2 OUT1B OUT2B MS3 1 OUT2A VBB2 C9 SENSE2 C7 MS1 Grounding In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance singlepoint ground, known as a star ground, located very close to the device. By making the connection between the exposed thermal pad and the groundplane directly under the A4983, that area becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. The recommended PCB layout shown in the diagram below, illustrates how to create a star ground under the device, to serve both as low impedance ground point and thermal path. VREG Layout The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A4983 must be soldered directly onto the board. On the underside of the A4983 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. Thermal vias should not have any thermal relief and should be connected to internal layers, if available, to maximize the dissipation area. R3 R2 VDD C1 C8 R6 R1 10 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A4983 DMOS Microstepping Driver with Translator STEP STEP 100.00 100.00 70.71 70.71 Slow Phase 1 IOUT1A Direction = H (%) –100.00 100.00 Phase 2 IOUT2A Direction = H (%) –100.00 100.00 70.71 Phase 2 IOUT2B Direction = H (%) 0.00 Slow Slow Slow Mixed Mixed Slow Slow Mixed 0.00 –70.71 –70.71 –100.00 –100.00 Figure 2. Decay Mode for Full-Step Increments Mixed 0.00 –70.71 70.71 Slow Mixed Home Microstep Position –70.71 Home Microstep Position 0.00 Slow Mixed Home Microstep Position Slow Home Microstep Position Phase 1 IOUT1A Direction = H (%) Figure 3. Decay Modes for Half-Step Increments STEP 100.00 92.39 70.71 38.27 Slow Mixed Slow Mixed Slow 0.00 Home Microstep Position Phase 1 IOUT1A Direction = H (%) –38.27 –70.71 –92.39 –100.00 100.00 92.39 70.71 Phase 2 IOUT2B Direction = H (%) 38.27 Slow Mixed Slow Mixed Slow Mixed 0.00 –38.27 –70.71 –92.39 –100.00 Figure 4. Decay Modes for Quarter-Step Increments 11 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A4983 DMOS Microstepping Driver with Translator STEP 100.00 92.39 83.15 70.71 55.56 38.27 19.51 0.00 Slow Mixed Mixed Slow –19.51 –38.27 –55.56 –70.71 –83.15 –92.39 –100.00 100.00 92.39 83.15 70.71 55.56 Phase 2 IOUT2B Direction = H (%) Slow Mixed Mixed Slow Home Microstep Position Phase 1 IOUT1A Direction = H (%) 38.27 19.51 0.00 –19.51 –38.27 –55.56 –70.71 –83.15 –92.39 –100.00 Figure 5. Decay Modes for Eighth-Step Increments 12 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A4983 DMOS Microstepping Driver with Translator STEP 100.00 95.69 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 Phase 1 IOUT1A Direction = H (%) 9.8 Slow 0.00 Mixed Slow Mixed –9.8 –19.51 –29.03 Home Microstep Position –38.27 –47.14 –55.56 –63.44 –70.71 –77.30 –83.15 –88.19 –95.69 –100.00 100.00 95.69 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 Phase 2 IOUT2B Direction = H (%) 9.8 0.00 Slow Mixed Slow Mixed Slow –9.8 –19.51 –29.03 –38.27 –47.14 –55.56 –63.44 –70.71 –77.30 –83.15 –88.19 –95.69 –100.00 Figure 6. Decay Modes for Sixteenth-Step Increments 13 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A4983 DMOS Microstepping Driver with Translator Table 2. Step Sequencing Settings Home microstep position at Step Angle 45º; DIR = H Full Step # Half Step # 1 1/4 Step # 1 2 1 2 3 3 5 6 2 4 7 8 Phase 2 Current [% ItripMax] [% ItripMax] (%) 100.00 (%) 0.00 1/16 Step # 1 2 99.52 9.80 5.6 2 3 98.08 19.51 11.3 4 95.69 29.03 16.9 5 92.39 38.27 22.5 6 88.19 47.14 28.1 4 7 83.15 55.56 33.8 8 77.30 63.44 39.4 5 9 70.71 70.71 45.0 3 Step Angle (º) 0.0 10 63.44 77.30 50.6 11 55.56 83.15 56.3 12 47.14 88.19 61.9 13 38.27 92.39 67.5 14 29.03 95.69 73.1 8 15 19.51 98.08 78.8 16 9.80 99.52 84.4 9 17 0.00 100.00 90.0 18 –9.80 99.52 95.6 10 19 –19.51 98.08 101.3 20 –29.03 95.69 106.9 21 –38.27 92.39 112.5 22 –47.14 88.19 118.1 12 23 –55.56 83.15 123.8 24 –63.44 77.30 129.4 13 25 –70.71 70.71 135.0 26 –77.30 63.44 140.6 14 27 –83.15 55.56 146.3 28 –88.19 47.14 151.9 29 –92.39 38.27 157.5 30 –95.69 29.03 163.1 31 –98.08 19.51 168.8 32 –99.52 9.80 174.4 6 4 Phase 1 Current 1/8 Step # 1 7 11 15 16 Full Step # Half Step # 5 1/4 Step # 9 10 3 6 11 12 7 13 14 4 8 15 16 Phase 1 Current Phase 2 Current [% ItripMax] [% ItripMax] Step Angle (%) 0.00 180.0 1/8 Step # 17 1/16 Step # 33 34 –99.52 –9.80 185.6 18 35 –98.08 –19.51 191.3 36 –95.69 –29.03 196.9 37 –92.39 –38.27 202.5 38 –88.19 –47.14 208.1 20 39 –83.15 –55.56 213.8 40 –77.30 –63.44 219.4 21 41 –70.71 –70.71 225.0 42 –63.44 –77.30 230.6 22 43 –55.56 –83.15 236.3 44 –47.14 –88.19 241.9 45 –38.27 –92.39 247.5 46 –29.03 –95.69 253.1 24 47 –19.51 –98.08 258.8 48 –9.80 –99.52 264.4 25 49 0.00 –100.00 270.0 50 9.80 –99.52 275.6 26 51 19.51 –98.08 281.3 52 29.03 –95.69 286.9 53 38.27 –92.39 292.5 54 47.14 –88.19 298.1 28 55 55.56 –83.15 303.8 56 63.44 –77.30 309.4 29 57 70.71 –70.71 315.0 58 77.30 –63.44 320.6 30 59 83.15 –55.56 326.3 60 88.19 –47.14 331.9 61 92.39 –38.27 337.5 62 95.69 –29.03 343.1 63 98.08 –19.51 348.8 64 99.52 –9.80 354.4 19 23 27 31 32 (%) –100.00 (º) 14 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A4983 DMOS Microstepping Driver with Translator 22 VBB1 23 SENSE1 24 OUT1A 25 NC 26 OUT2A 27 SENSE2 28 VBB2 Pin-out Diagram OUT2B 1 21 OUT1B ENABLE 2 20 NC GND 3 CP1 4 CP2 5 17 REF VCP 6 16 STEP NC 7 15 VDD 19 DIR SLEEP 14 ROSC 13 18 GND RESET 12 MS3 11 9 MS1 MS2 10 8 VREG PAD Terminal List Table Name Number Description CP1 4 Charge pump capacitor terminal CP2 5 Charge pump capacitor terminal VCP 6 Reservoir capacitor terminal VREG 8 Regulator decoupling terminal MS1 9 Logic input MS2 10 Logic input MS3 11 Logic input RESET 12 Logic input ROSC 13 Timing set SLEEP 14 Logic input VDD 15 Logic supply STEP 16 Logic input REF 17 Gm reference voltage input GND 3, 18 Ground* DIR 19 Logic input OUT1B 21 DMOS Full Bridge 1 Output B VBB1 22 Load supply SENSE1 23 Sense resistor terminal for Bridge 1 OUT1A 24 DMOS Full Bridge 1 Output A OUT2A 26 DMOS Full Bridge 2 Output A SENSE2 27 Sense resistor terminal for Bridge 2 VBB2 28 Load supply OUT2B 1 DMOS Full Bridge 2 Output B ENABLE 2 Logic input NC 7, 20, 25 PAD – No connection Exposed pad for enhanced thermal dissipation* *The GND pins must be tied together externally by connecting to the PAD ground plane under the device. 15 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A4983 DMOS Microstepping Driver with Translator ET Package, 28-Pin QFN with Exposed Thermal Pad 5.15 .203 4.85 .191 A B 28 All dimensions reference, not for tooling use (reference JEDEC MO-220VHHD except contact length and exposed pad length and width) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (terminal #1 identifier appearance at supplier discretion) 1 2 5.15 .203 4.85 .191 C Reference land pattern layout (reference IPC7351 QFN50P500X500X100-29V3M) except heel extended; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 28X 0.50 .020 NOM 4X0.20 .008 MIN 3.15 .124 NOM 4.96 .195 NOM 1.09 .043 REF 4.96 .195 NOM 0.20 .008 REF 0.05 .002 0.00 .000 0.56 .022 REF R0.25 REF .010 B 2 1 28 3.15 .124 NOM C 1.00 .039 0.80 .031 4X0.20 .008 MIN 1 2 C 0.30 .012 0.18 .007 0.10 [.004] M C A B 0.05 [.002] M C 0.50 .020 24X0.20 .008 MIN 28 SEATING PLANE 0.08 [.003] C 28X 0.30 .012 NOM A 3.15 .124 NOM 5.0 .197 NOM 3.15 .124 NOM 5.0 .197 NOM The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system.The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright ©2007, Allegro MicroSystems, Inc. For the latest version of this document, visit our website: www.allegromicro.com 16 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com